JP2011250459A - A/d converter and receiver using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample/hold circuit and a comparator with low power consumption that constitute an A/D converter.SOLUTION: A sample/hold circuit (SHC) that samples and holds an analog input signal in response to a clock signal and a comparator (COP) that discriminates a signal level of a hold output signal from the sample/hold circuit are included. The comparator comprises a preamplifier (AMP) that amplifies the hold output signal from the sample/hold circuit, a latch circuit (LCH) that latches differential output signals generated from the preamplifier, and a bias control circuit (BCC) that controls a current value of a bias current of the preamplifier in response to a level difference between the differential output signals generated from the preamplifier. When the level difference between the differential output signals is small, the bias control circuit controls the bias current of the preamplifier so as to be a large current value. When the level difference between the differential output signals is large, the bias control circuit controls the bias current of the preamplifier so as to be a small current value.

Description

  The present invention relates to an A / D converter for converting an analog signal into a digital signal and a receiving apparatus using the A / D converter, and more particularly to reducing power consumption of a sample / hold circuit and a comparator constituting the A / D converter. It relates to effective technology.

  In recent years, with the rapid development of computer technology, computers have been incorporated into various devices around us and various processes have been digitized. In the near future, it is thought that a ubiquitous society will be realized in which these devices are connected via a network, operate in an autonomous manner, and back up human life.

  In such a ubiquitous society, it is indispensable to incorporate real-world information into a computer. Real-world information such as temperature, color and intensity of light seen by humans, and radio waves used for wireless communication are analog information. On the other hand, what can be processed by a computer is a digital signal that is a discrete value in time and a quantized value. Therefore, in order to capture real-world information into a computer, a function of converting an analog signal into a digital signal, that is, an analog / digital converter (hereinafter referred to as an A / D converter) is essential. The A / D converter is incorporated in various devices, and examples thereof include a digital camera, a digital recorder, and a wireless communication receiver.

  Various types of A / D converter circuit configurations are known. As an example, a circuit including an initial stage sample / hold circuit and a subsequent stage comparator can be cited. When paying attention to the circuit operation of the A / D converter, a sample / hold circuit that samples an analog input signal that changes every time during processing in synchronization with the clock signal and temporarily holds it is used at the first stage. . The analog input signal sampled by the sample / hold circuit is compared with a reference value by a comparator for conversion to a digital signal, and a digital conversion output signal is obtained from the output of the comparator.

  For example, the following non-patent document 1 and the following non-patent document 2 describe sample / hold circuits using switched capacitors. Non-Patent Document 3 below describes that the input terminal of the operational amplifier is connected to the ground during the sample operation of the sample / hold circuit so that no band limitation is imposed on the operational amplifier.

  Non-Patent Document 4 below describes that, as a comparator of an A / D converter, two input signals to be compared are amplified by a preamplifier and then an output signal of the preamplifier is input to a latch circuit.

  Further, in Patent Document 1 below, as a method of reducing the consumption current of the comparator, when the difference between the input signals of the comparator is large, the consumption current of the high-speed switching comparator is reduced and the difference between the input signals is small. Describes a circuit for increasing the current consumption to maintain the required high switching speed.

  Furthermore, in Patent Document 2 below, a normal operating current is passed only when the comparator input enters the detection window to obtain a predetermined response speed, while when the input is outside the detection window, the consumption is very low. An adaptive control circuit operating with current is described.

  Further, the traditional sampling rate in A / D conversion is determined by the Nyquist sampling theorem that defines the sampling rate necessary for reproducing the original waveform. As is well known, according to the Nyquist sampling theorem, if the maximum frequency or frequency band of the original waveform is set to fmax, the Nyquist frequency of 2fmax is set so that the original waveform information is not lost. Sampling must be performed at equal or higher sampling frequency fs. If the Nyquist sampling theorem is violated and sampling is performed at a sampling frequency fs less than 2 fmax, an alias (false information) having a contour waveform completely different from the original waveform is generated.

  However, the following Non-Patent Document 5 and Non-Patent Document 6 describe a telecommunications receiver and software radio receiver using an undersampling A / D converter that can sufficiently convert an input signal having a frequency higher than the Nyquist frequency. ing. Thus, an undersampling technique with a rate of more than twice the signal bandwidth can completely reproduce the original information using in-band aliasing.

JP 2003-338735 A JP 2002-311063 A

BEHZAD RAZAVI, “PRINCIPLES OF DATA CONVERSION SYSTEM DESIGN,” IEEE PRESS, ISBN 0-7803-1093-4, PP. 40-42, 1995. BEHZAD RAZAVI, “A 200-MHz 15-mW BiCMOS Sample-and-Hold Amplifier with 3 V Supply,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 12, DECEMBER 1995, PP. 1326-1332. Gobert Geelen, et al. , A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipeline ADC with 0.5pJ / Conversion-Step, "2006 IEEE International Solid-State CIPE E. BEHZAD RAZAVI, “PRINCIPLES OF DATA CONVERSION SYSTEM DESIGN,” IEEE PRESS, ISBN 0-7803-1093-4, Section 7.2 COMPARATORS, PP. 177-194, 1995. Hooman Reyhani, “A 5 V, 6-b, 80 Ms / s BiCMOS Flash ADC,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, N.M. 8, AUGUST 1994, PP. 873-878. Akio Kiyono et al, "Jitter Effect on Digital Downconversion Receive with Undersampling Scheme," The 47th IEEE International Stipulation. II-677-II-680.

  Low power consumption is strongly required for A / D converters incorporated in various devices around us. In particular, in a ubiquitous society, since many battery-driven devices are used, the reduction of power consumption is a major issue.

  The problem to be solved by the present invention is to reduce the power consumption of an A / D converter and a receiving apparatus using the A / D converter. In particular, the A / D converter is used in the first stage of the A / D converter, and the sample / hold circuit that samples and holds the signal and the comparator, which is an essential function of the A / D converter, are reduced in power consumption. The overall power consumption is reduced.

  The details of the problems of the conventional A / D converter will be described below.

  When an analog signal is digitized by an A / D converter, as described above, according to the Nyquist theorem, if the maximum frequency or frequency band of the original analog signal waveform is fmax, information on the original analog signal waveform is obtained. In order not to be lost, it is necessary to sample at a sampling frequency fs equal to or higher than the Nyquist frequency of 2fmax. Therefore, after A / D conversion, information on frequency components equal to or higher than fmax, which is ½ of the sampling frequency fs, is lost, and aliasing occurs. For this reason, analog signals of the highest frequency or frequency band below the Nyquist frequency are often input to the A / D converter. However, it is also possible to A / D convert a signal having a frequency higher than the Nyquist frequency and restore the information using the resulting aliasing. A / D conversion of an analog input signal having a frequency higher than the Nyquist frequency is called undersampling A / D conversion. An A / D converter that performs undersampling A / D conversion is an undersampling A / D converter. be called.

  The undersampling A / D converter is a digital information from an impulse signal that is an intermittent analog signal in, for example, an ultra-wideband impulse radio (hereinafter referred to as UWB-IR) wireless communication device. Used to acquire In the software defined radio, the undersampling A / D converter functions as a down conversion. The undersampling A / D converter is also effective when a plurality of A / D converters are used in parallel to increase the effective conversion speed. In a wireless communication device such as a cellular phone, a received radio frequency signal is converted into an analog baseband signal by a receiving mixer, and the analog baseband signal is converted into a digital baseband signal by an A / D converter. Digital signal processing is performed in the signal processing unit. In order to reduce power consumption and improve the accuracy of digital signal processing for wireless communication devices such as mobile phones that operate on batteries or built-in power supplies with low drive capability, an A / D converter used in wireless communication devices It is necessary to reduce power consumption and improve performance.

  In order to realize A / D conversion, a sample / hold circuit is required at the first stage of the A / D converter. Particularly, a sample / hold circuit for undersampling operation at the first stage of the A / D converter plays an important role in realizing undersampling A / D conversion. The function required for this sample / hold circuit is to sample an input signal having a frequency equal to or higher than the Nyquist frequency, and hold the sampled signal at a frequency equal to the conversion frequency. This is called an undersampling sample / hold circuit.

  A simple way to implement this undersampling sample / hold circuit is to use a sample / hold circuit that can operate at a frequency greater than or equal to the frequency of the input signal. However, this method uses a high-performance circuit having a high operating frequency even during the hold operation, and thus has a problem that power consumption increases. Details thereof will be described with reference to FIGS.

  FIG. 1 is a circuit diagram showing a conventional sample / hold circuit SHC disclosed in Non-Patent Document 2. In FIG. This is a switched capacitor circuit comprising switches SW1a, SW1b, SW2a, SW2b, SW3a, SW3b, capacitors C1a, C1b, and an operational amplifier (OPA) 11. The subscripts a and b indicate a differential pair. In the following description, the subscripts a and b are omitted unless particularly necessary. In addition, in other reference symbols, when a suffix is omitted for a component having a plurality of the same component, the same component is indicated.

  The conventional sample / hold circuit SHC shown in FIG. 1 operates in two modes, a sample mode and a hold mode, by switching the switch SW. 2 shows an equivalent circuit in the sample mode of the conventional sample / hold circuit SHC shown in FIG. 1, and FIG. 3 shows an equivalent circuit in the hold mode of the conventional sample / hold circuit SHC shown in FIG. Yes.

  In the sample mode, the switches SW1 and SW3 are turned on and the switch SW2 is turned off. In other words, the input terminal Vin is connected to the capacitor C1, and the input and output of the operational amplifier 11 are short-circuited. By short-circuiting the input / output terminals of the operational amplifier 11 to form a feedback loop, the ON resistances of the switches SW1 and SW3 are so small that they can be ignored. Since the impedance is extremely high, the voltage V1a of the non-inverting input terminal (+) and the voltage V1b of the inverting input terminal (−) of the operational amplifier 11 are the output voltages of the inverting output terminal Vout1 (−) and the non-inverting output terminal Vout2 (+). Set to The input offset voltage between the non-inverting input terminal (+) and the inverting input terminal (−) of the operational amplifier 11 is so small as to be negligible, and the differential voltage between the differential input voltages Vin1 and Vin2 is a constant value during the sample mode period. Assume. Then, the voltage V1a of the non-inverting input terminal (+) of the operational amplifier 11 and the voltage V1b of the inverting input terminal (−) of the operational amplifier 11 become equal due to the characteristics of the operational amplifier 11, and as a result, the output voltage of the inverting output terminal Vout1 (−) of the operational amplifier 11 And the output voltage of the non-inverting output terminal Vout2 (+) are stably maintained at the same common mode voltage. This common mode voltage becomes Vdd / 2 which is substantially half of the power supply voltage Vdd supplied to the operational amplifier 11.

  As is well known, the electric charge accumulated in the capacitor is the product of the capacitance value and the voltage at both ends thereof. As described above, the input / output terminal of the operational amplifier 11 is short-circuited to form a feedback loop, and the voltage V1a of the non-inverting input terminal (+) and the voltage V1b of the inverting input terminal (−) of the operational amplifier 11 are kept at a constant potential. Thus, charges corresponding to the input signal Vin are accumulated in the capacitor C1. What is important here is that the voltages V1a and V1b are kept at a constant potential. If the voltages V1a and V1b are not maintained at a constant potential, the charge corresponding to the input signal Vin cannot be correctly stored in the capacitor C1. In the conventional sample / hold circuit SHC, the output drive capability of the inverting output terminal Vout1 (−) and the non-inverting output terminal Vout2 (+) of the operational amplifier 11 plays a role of maintaining the voltages V1a and V1b at a constant potential. That is, since the differential voltage between the differential input voltages Vin1 and Vin2 often changes instead of a constant value during the sample mode, the operational amplifier 11 changes the input signal Vin in order to keep the voltages V1a and V1b at a constant potential. Therefore, it is necessary to supply sufficient charges to the non-inverting input terminal (+) and the inverting input terminal (−) of the operational amplifier 11. Therefore, the operational amplifier 11 needs to operate at a frequency equal to or higher than the frequency of the input signal Vin.

  In the sample mode, the input signal Vin is stored in the capacitor C1, and at the same time, the input offset voltage of the operational amplifier 11 is stored in the capacitor C1. The input offset voltage between the non-inverting input terminal (+) and the inverting input terminal (−) of the operational amplifier 11 is so small that it can be ignored, and zero volts is ideal. However, the input offset voltage of the operational amplifier often becomes a value that cannot be ignored due to the influence of manufacturing variations. In the sample mode, since the input / output terminal of the operational amplifier 11 is short-circuited, the input offset voltage is accumulated in the capacitor C1. That is, in the sample mode, the input signal Vin and the input offset voltage of the operational amplifier 11 are accumulated in the capacitor C1.

  On the other hand, in the hold mode, the switches SW1 and SW3 are turned off and the switch SW2 is turned on. That is, as shown in FIG. 3, the feedback loop is formed by the capacitor C1 and the operational amplifier 11. This feedback loop operates to hold the charge accumulated in the sample mode in the capacitor C1. The terminal on the output side of the operational amplifier 11 in the hold mode of the capacitor C1 (that is, the input side terminals of the differential input voltages Vin1 and Vin2 in the sample mode of the capacitor C1) is switched to the hold mode from the sample mode. The electric charge is retained. Therefore, the difference voltage between the differential input voltages Vin1 and Vin2 at the time of switching from the sample mode to the hold mode is output as the output difference voltage between the inverting output terminal Vout1 (−) and the non-inverting output terminal Vout2 (+) of the operational amplifier 11. Is done. When the load impedances of the inverting output terminal Vout1 (−) and the non-inverting output terminal Vout2 (+) of the operational amplifier 11 are low, the output voltages of the inverting output terminal Vout1 (−) and the non-inverting output terminal Vout2 (+) of the operational amplifier 11 The level of will try to decrease. However, this decrease in the output voltage is compensated by the output drive capability of the inverting output terminal Vout1 (−) and the non-inverting output terminal Vout2 (+) of the operational amplifier 11, and the output differential voltage at the time of switching is between the hold mode. Can be stably maintained.

  Here, since the input offset voltage of the operational amplifier 11 is also stored in the capacitor C1 in the sample mode, the output signal Vout held in the hold mode is a voltage in which the input offset voltage of the operational amplifier 11 is canceled. Thus, by accumulating the input offset voltage in the capacitor C1 in the sample mode, the input offset voltage of the operational amplifier 11 can be canceled.

  In this way, in the hold mode, by forming a feedback loop with the capacitor C1 and the operational amplifier 11, it becomes possible to hold the input signal when the sample mode is switched to the hold mode. At this time, the operation speed necessary for the operational amplifier 11 is determined by the operation speed necessary for the hold mode, that is, the output drive capability of the operational amplifier 11 that compensates for the decrease in the output voltage difference, regardless of the frequency of the input signal.

  Focusing on the operating speed of the operational amplifier 11 of the sample / hold circuit SHC, the operational amplifier 11 needs to operate at a speed higher than the frequency of the input signal Vin in the sample mode. In the hold mode, the operation speed required for the operational amplifier 11 is determined by the output drive capability of the operational amplifier 11. Since the same operational amplifier 11 is used in the sample mode and the hold mode, the operational speed required for the operational amplifier 11 is either the frequency of the input signal Vin or the compensation speed of the output differential voltage decrease due to the output drive capability of the operational amplifier 11. It will be decided by the faster one.

  In a general A / D converter to which an analog signal having a Nyquist frequency or less is input, the input signal frequency of the analog signal is a relatively low frequency that is 1/2 or less of the A / D conversion frequency. Since the compensation speed of the output differential voltage decrease due to the output drive capability of the operational amplifier is faster than the analog input signal speed, the operation speed required for the operational amplifier of the sample / hold circuit needs to be determined from the compensation speed.

  On the other hand, in an undersampling A / D converter to which an analog input signal (for example, about 10 times) faster than the compensation speed is input, it is necessary to determine the operation speed of the operational amplifier of the sample / hold circuit from the frequency of the analog input signal. . That is, the operating speed required in the sample mode is higher than the operating speed required in the hold mode, and it is necessary to operate at a speed higher than the input signal speed.

  Generally, when the operation speed of an electronic circuit is increased, the power consumption of the electronic circuit increases. In the undersampling sample / hold circuit, the higher the input signal speed, the faster the operational amplifier must be operated, resulting in a problem of increased power consumption.

  If the technique described in Non-Patent Document 3 is adopted, band limitation will not be imposed on the operational amplifier, but with this, other problems arise, such as the input offset voltage of the operational amplifier cannot be canceled. End up. The details will be described below.

  FIG. 4 shows a sample / hold circuit SHC which the inventor has examined as a configuration of a differential input system and a differential output system prior to the present invention with reference to the sample / hold circuit described in Non-Patent Document 3. FIG. The sample / hold circuit SHC in FIG. 4 has a configuration in which a switch SW4 and an external potential Vcm are added to the sample / hold circuit SHC in FIG. As a result, the sample / hold circuit SHC shown in FIG. 4 includes switches SW1, SW2, SW3, SW4, a capacitor C1, an operational amplifier (OPA) 41, and an external potential Vcm. Here, the external potential Vcm is a constant potential substantially equal to the common mode potential of the operational amplifier 41, and is, for example, a voltage of Vdd / 2 that is half of the power supply voltage Vdd.

  In order to operate the sample / hold circuit SHC shown in FIG. 1 in the undersampling mode, charges are accumulated in the capacitor C1 using the operational amplifier 11 in the sample mode, so that the operational amplifier 11 is operated at a higher speed than the analog input signal. It was necessary to let them. For this reason, when the analog input signal becomes high speed, it is necessary to operate the operational amplifier 11 at a higher speed, resulting in an increase in power consumption.

  In the sample / hold circuit SHC shown in FIG. 4, the charge to the capacitor C1 is not supplied from the operational amplifier 41, but is supplied from the external potential Vcm via the switch SW4. 5 shows an equivalent circuit in the sample mode of the sample / hold circuit SHC shown in FIG. 4, and FIG. 6 shows an equivalent circuit in the hold mode of the sample / hold circuit SHC shown in FIG.

  As shown in FIG. 5, in the sample mode of the sample / hold circuit SHC shown in FIG. 4, the switches SW1, SW3, SW4 are turned on and the switch SW2 is turned off. By making the impedance of the switch SW4 lower than the output impedance of the operational amplifier 41, charge can be supplied from the external potential Vcm to the capacitor C1, and the operational amplifier 41 does not need to be operated at high speed. As shown in FIG. 6, in the sample mode of the sample / hold circuit SHC shown in FIG. 4, the switches SW1, SW3, SW4 are turned off and the switch SW2 is turned on.

  However, it has been clarified by the present inventors that the sample / hold circuit SHC shown in FIG. 4 has the following drawbacks. This requires the formation of a stable potential Vcm, and in order to generate this potential, power consumption and a certain chip occupation area in the semiconductor integrated circuit are required. Further, the potential Vcm needs to be a common potential of the operational amplifier 41 (for example, about half of the power supply voltage Vdd), and the switch SW4 needs to be operated near the potential Vcm. In order to reduce the impedance of the switch SW4, that is, the on-resistance, it is usually necessary to use a CMOS switch, and in order to reduce the impedance, it is necessary to increase the gate width, resulting in an increase in area. Further, a more serious drawback is that the non-inverting input terminal (+) and the inverting input terminal (−) of the operational amplifier 41 are connected to a common potential Vcm in the sample mode as shown in FIG. The voltage cannot be canceled.

  As described above, conventional sample / hold circuits prior to the present invention cannot achieve low power consumption and high performance when used in the first stage of an undersampling A / D converter.

  As an important circuit of the A / D converter, there is a next-stage comparator connected to the first-stage sample / hold circuit. The level of the analog input signal sampled by the sample / hold circuit is discriminated by a comparator for conversion into a digital signal. In the comparator, the level of the analog input signal is compared with, for example, a substantially constant reference value, and a digital conversion output signal is obtained from the output of the comparator. When a differential output hold signal is generated from the sample / hold circuit, the differential output hold signal is supplied to the differential input of the comparator, and the magnitude relationship of the differential voltage of the differential output hold signal is discriminated by the comparator. Is done. Thus, the comparator is a circuit that discriminates the magnitude relationship between the levels of the two analog input signals, and is an essential function for the A / D converter.

  FIG. 7 is a circuit diagram showing a comparator of a conventional A / D converter described in Non-Patent Document 4. This comparator includes a preamplifier (AMP) 181 and a latch circuit (LCH) 182. Two input signals Vsig and Vref to be compared are amplified by a preamplifier (AMP) 181, and then an output signal of the preamplifier (AMP) 181 is input to a latch circuit (LCH) 182. This comparator operates in synchronization with clock signals φ and φb having opposite phases. First, the difference between the analog input signal Vsig input to the comparator and the reference signal Vref during the period when the clock signal φ is at the high level is amplified by the preamplifier 181. Thereafter, the latch circuit 182 is activated during the high level period of the clock signal φb, and the digital signal Dout is output. The differential input terminal of the latch circuit 182 is also a differential output terminal, and the latch circuit 182 is formed by a positive feedback circuit in which the differential output terminals of the two inverters are directly connected to the differential input terminals in a cross-coupled form. It is configured. It is known that the threshold value at which the output of the inverter constituting the latch circuit 182 is inverted has variations due to the effects of manufacturing variations. Therefore, in order to correctly determine the magnitude of the signal input to the positive feedback latch circuit 182, it is necessary to input a voltage difference that exceeds the threshold voltage variation of the inverter. For this reason, it is necessary to amplify the difference between the two input signals Vsig and Vref to be compared using the preamplifier 181.

  FIG. 8 is a waveform diagram for explaining the operation of the comparator of the conventional A / D converter shown in FIG. FIG. 8 shows the difference voltage Vamp (broken line) between the output signals Va1 and Va2 of the preamplifier 181 in response to the input signal Vsig, the output voltage Dout (solid line) of the latch circuit 182 and the consumption current Icmp of the comparator. . For reference, the input signal Vsig is also indicated by a dotted line.

  The preamplifier 181 amplifies the difference between the input signal Vsig and the reference voltage Vref. The output difference voltage Vamp of the preamplifier 181 exhibits a substantially linear characteristic when the difference between the two signals Vsig and Vref is small, and gradually becomes saturated as the difference increases.

  FIG. 9 is a circuit diagram showing a preamplifier studied by the inventor prior to the present invention as the preamplifier 181 of the conventional comparator shown in FIG. In the figure, N-channel MOS transistors (hereinafter abbreviated as NMOS) NM1 and NM2 are differential pairs that amplify the difference between two signals Vsig and Vref, and NMOS NM3 is turned on by the high level of the anti-phase clock signal φb. The NM4 and NM5 which are equalizing switches and NMOSs are current mirrors as constant current sources for the differential pair NM1 and NM2. In the figure, P channel MOS transistors (hereinafter abbreviated as PMOS) PM1, PM2, PM3, PM4 are load transistors for the differential pair NM1, NM2, and PM5 of the PMOS is a current mirror NM4, with a constant bias voltage Vbp. This is a bias transistor for supplying a constant current mirror input current to NM5. In the figure, Vdd is a power supply voltage, and GND is a ground. Thus, the consumption current Ibias of the preamplifier 181 is determined by a constant bias current of the current mirrors NM4 and NM5 and does not depend on the difference between the input signals Vsig and Vref.

  As described above, in order to correctly determine the magnitude of the signal in the positive feedback latch circuit, a small difference voltage between the input signals Vsig and Vref is obtained by using the preamplifier 181 and the threshold value of the inverter of the latch circuit 182. It is necessary to amplify more than voltage variations. However, if the difference voltage between the input signals Vsig and Vref is sufficiently large, the difference voltage between the output signals Va1 and Va2 of the preamplifier 181 even if the bias current Ibias of the rent mirrors NM4 and NM5 of the preamplifier 181 shown in FIG. Vamp is sufficiently large, and the positive feedback latch circuit 182 can correctly determine the magnitude of the signal.

  In the case of a circuit type in which the differential output terminals of the two inverters of the positive feedback latch circuit 182 are indirectly connected to the differential input terminal via two input transistors driven by the input signal of the differential input terminal, The voltage difference amplified by the two input transistors is input to the positive feedback latch circuit 182. However, since there are manufacturing variations in the threshold voltages of the two input transistors, it is necessary for the preamplifier 181 to amplify a minute difference voltage between the input signals Vsig and Vref at a higher speed than the variations in the threshold voltages. Also, if the difference voltage between the input signals Vsig and Vref is sufficiently large, the difference voltage between the output signals Va1 and Va2 of the preamplifier 181 even if the bias current Ibias of the rent mirrors NM4 and NM5 of the preamplifier 181 shown in FIG. Vamp is sufficiently larger than the variation of the threshold voltage, and the magnitude of the input signal of the positive feedback latch circuit 182 can be easily determined.

  As is clear from the above description, the preamplifier 181 only needs to amplify with a large amplification factor only when the difference voltage between the input signal Vsig and the reference voltage Vref is small, and when the difference voltage between the input signal Vsig and the reference voltage Vref is sufficiently large. There is no need for amplification at a large amplification factor. However, in the comparator 181 examined by the inventor prior to the present invention shown in FIG. 9, the large difference due to the large bias current Ibias is large, even when the difference between the input signal Vsig and the reference voltage Vref is large. Since the amplification operation was performed at a high rate, the problem of wasting unnecessary power was clarified.

  The consumption current Icmp of the comparator is represented by the sum of the consumption current Ibias of the preamplifier 181 and the consumption current of the latch circuit 182, but generally the ratio of the consumption current Icmp of the comparator flows a steady bias current Ibias. The consumption current of the preamplifier 181 is larger.

  Therefore, if it is detected that the difference between the input signal Vsig and the reference voltage Vref is large and control is performed to reduce the bias current Ibias of the preamplifier 181, unnecessary power can be reduced. Patent Document 1 describes a configuration in which two input signals of a comparator are also supplied to a current mirroring circuit, and control is performed to increase the bias current only when the difference between the two input signals is small by this current mirroring circuit. . However, in this configuration, the input load capacitance of the current mirroring circuit is added to the input load capacitance of the comparator, and the problem that the operation speed becomes slow has been clarified. It has also been clarified that this configuration is not suitable for operation with a low power supply voltage because the number of MOS transistors connected in series in the current mirroring circuit is increased as compared with a normal bias current circuit.

  Patent Document 2 discloses a differential detection circuit that responds to a differential input signal, a voltage comparison output circuit that responds to a differential input signal, and a voltage comparison output circuit that responds to the output of the differential detection circuit. An adaptive control circuit for controlling the bias current is described. The differential detection circuit has a transfer characteristic in which the change in the differential output signal in response to the change in the differential input signal is asymmetric, and the plurality of transistors connected in series in the conversion circuit by the asymmetric differential output signal in the differential detection circuit. The bias current is controlled by the voltage comparison output circuit. Therefore, the plurality of transistors connected in series in the conversion circuit is not suitable for operation with a low power supply voltage. Further, since it is necessary to pass a bias current to the conversion circuit of the adaptive control circuit, the problem that the control circuit itself increases power consumption has been clarified. In addition, since the differential input signal supplied to the voltage comparison output circuit is also supplied to the differential detection circuit, the load capacity of the input terminal of the adaptive control circuit as a whole increases and the operation speed becomes slow. It was made clear.

  The present invention has been made on the basis of the results of the study conducted by the present inventors prior to the present invention, and the object thereof is to sample and hold an analog input signal in response to a clock signal. The power consumption of an A / D converter including a sample / hold circuit and a comparator for discriminating the signal level of a hold output signal from the sample / hold circuit is reduced.

  Another object of the present invention is to improve the performance of an A / D converter including a sample / hold circuit and a comparator.

  Still another object of the present invention is to operate with a battery or a built-in power source with low driving capability, reduce the power consumption of a wireless communication device including an A / D converter, and improve the accuracy of digital signal processing. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

≪Basic form of the present invention≫
An A / D converter (ADC) according to a first embodiment of the present invention includes a sample / hold circuit (SHC) that samples and holds an analog input signal (Vin) in response to a clock signal (φ), and the sample / A comparator (COP) for discriminating the signal level of the hold output signal (Vout) from the hold circuit (SHC).

  The sample / hold circuit (SHC) includes an operational amplifier (OPA, 61), a first switch (SW1), a second switch (SW2), a third switch (SW3), a fourth switch (SW8), A first capacitor (C2) and a second capacitor (C3) are included.

  The analog input signal (Vin) is supplied to one end of the first switch (SW1), and the other end of the first switch (SW1) is one end of the first capacitor (C2) and the second switch (SW2). Connected to one end. The other end of the first capacitor (C2) is connected to one end of the second capacitor (C3) and one end of the fourth switch (SW8), and the other end of the second capacitor (C3) is connected to the operational amplifier (OPA). 61) and one end of the third switch (SW3), and the other end of the second switch (SW2) and the other end of the third switch (SW3) are connected to the operational amplifier (OPA, 61). Connected to the output.

  In the sample mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), and the fourth switch (SW8) are controlled to be in an ON state, and the second switch (SW2) ) Is controlled to the off state.

  In the hold mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), and the fourth switch (SW8) are controlled to be in an OFF state, and the second switch (SW2) ) Is controlled to be on.

  The other end of the fourth switch (SW8) is connected to an operating potential (GND) maintained substantially stably in the system (see FIGS. 10 to 12).

  According to the means of the first aspect of the present invention, the other end of the fourth switch (SW8) is connected to the operating potential (GND) maintained substantially stably in the system. Accordingly, the sample / hold circuit (SHC) accurately samples the analog input signal (Vin) to the first capacitor (C2) and the operational amplifier (OPA) to the second capacitor (C3) during the sample mode. 61), the input offset voltage can be accurately sampled, and the power consumption and performance of the sample mode can be reduced. Therefore, it is possible to increase the speed and power consumption of the first stage sample / hold circuit (SHC) of the A / D converter (ADC).

  An A / D converter (ADC) according to a second embodiment of the present invention includes a sample / hold circuit (SHC) that samples and holds an analog input signal (Vin) in response to a clock signal (φ), and the sample. / A comparator (COP) for discriminating the signal level of the hold output signal (Vout) from the hold circuit (SHC).

  The comparator (COP) includes a preamplifier (AMP) for amplifying the hold output signal (Vout) from the sample / hold circuit (SHC), and differential output signals (Va1, Va2) generated from the preamplifier (AMP). ) And a bias current (Ibias) of the preamplifier (AMP) in response to a level difference between the differential output signals (Va1, Va2) generated from the preamplifier (AMP). And a bias control circuit (BCC) for controlling the value (see FIG. 10).

  When the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is small, the bias control circuit (BCC) sets the bias current (Ibias) of the preamplifier (AMP) to a large current value. When the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is large, the bias control circuit (BCC) causes the bias current (Ibias) of the preamplifier (AMP) to ) Is controlled to a small current value (see FIGS. 13 to 14).

  According to the means of the second aspect of the present invention, the preamplifier (AMP) in response to the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP). The current value of the bias current (Ibias) is controlled. When the level difference of the differential input signals (Vsig, Vref) of the preamplifier (AMP) is small, the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is also small. The bias current (Ibias) of the preamplifier (AMP) is controlled to a large current, and the preamplifier (AMP) amplifies the level difference of the differential input signals (Vsig, Vref) with a large amplification factor. Thereafter, when the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) increases, the bias current (Ibias) of the preamplifier (AMP) is controlled to a small current, and the preamplifier (AMP) amplifies the level difference of the differential input signals (Vsig, Vref) with a small amplification factor. In this way, it is possible to increase the speed and reduce the power consumption of the comparator (COP) at the subsequent stage of the A / D converter (ADC).

  An A / D converter (ADC) according to a third embodiment of the present invention includes a sample / hold circuit (SHC) that samples and holds an analog input signal (Vin) in response to a clock signal (φ), and the sample / A comparator (COP) for discriminating the signal level of the hold output signal (Vout) from the hold circuit (SHC).

  The sample / hold circuit (SHC) includes an operational amplifier (OPA, 61), a first switch (SW1), a second switch (SW2), a third switch (SW3), a fourth switch (SW8), A first capacitor (C2) and a second capacitor (C3) are included.

  The comparator (COP) includes a preamplifier (AMP) for amplifying the hold output signal (Vout) from the sample / hold circuit (SHC), and differential output signals (Va1, Va2) generated from the preamplifier (AMP). ) And a bias current (Ibias) of the preamplifier (AMP) in response to a level difference between the differential output signals (Va1, Va2) generated from the preamplifier (AMP). And a bias control circuit (BCC) for controlling the value (see FIG. 10).

  The analog input signal (Vin) is supplied to one end of the first switch (SW1), and the other end of the first switch (SW1) is one end of the first capacitor (C2) and the second switch (SW2). Connected to one end. The other end of the first capacitor (C2) is connected to one end of the second capacitor (C3) and one end of the fourth switch (SW8), and the other end of the second capacitor (C3) is connected to the operational amplifier (OPA). 61) and one end of the third switch (SW3), and the other end of the second switch (SW2) and the other end of the third switch (SW3) are connected to the operational amplifier (OPA, 61). Connected to the output.

  In the sample mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), and the fourth switch (SW8) are controlled to be in an ON state, and the second switch (SW2) ) Is controlled to the off state.

  In the hold mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), and the fourth switch (SW8) are controlled to be in an OFF state, and the second switch (SW2) ) Is controlled to be on.

  The other end of the fourth switch (SW8) is connected to an operating potential (GND) maintained substantially stably in the system (see FIGS. 10 to 12).

  When the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is small, the bias control circuit (BCC) sets the bias current (Ibias) of the preamplifier (AMP) to a large current value. When the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is large, the bias control circuit (BCC) causes the bias current (Ibias) of the preamplifier (AMP) to ) Is controlled to a small current value (see FIGS. 13 to 14).

  According to the means of the third aspect of the present invention, it is possible to increase the speed and power consumption of the sample / hold circuit (SHC) of the A / D converter (ADC), and the A / D converter (ADC) ) The subsequent stage comparator (COP) can be increased in speed and power consumption.

  According to a fourth aspect of the present invention, there is provided a receiving device that operates with a battery or a built-in power supply with low driving capability, a receiving mixer (MIX) that converts a received radio frequency signal into an analog baseband signal, and the receiving mixer (MIX). An analog / digital converter (ADC) that converts the analog baseband signal from the digital baseband signal, and a baseband signal processing that digitally processes the digital baseband signal from the A / D converter (ADC) Unit (BB) (see FIGS. 32 and 37).

  The A / D converter (ADC) that converts the analog baseband signal into the digital baseband signal is the A / D converter of any one of the first form, the second form, and the third form. It is comprised by D converter (ADC).

  According to the fourth aspect of the present invention, it is possible to operate a battery or a built-in power source with low driving capability, reduce the power consumption of a receiving device including an A / D converter, and improve the accuracy of digital signal processing. It becomes possible.

<< Preferred Form of the Present Invention >>
In the A / D converter (ADC) according to the preferred first embodiment of the present invention, the fourth switch (SW8) of the first embodiment includes a fifth switch (SW5), a sixth switch (SW6), and And a seventh switch (SW7).

  One end of the fifth switch (SW5) is connected to the other end of the first capacitor (C2) and one end of the sixth switch (SW6), and the other end of the fifth switch (SW5) is substantially connected to the other end. It is connected to the operating potential (GND) maintained stably. The other end of the sixth switch (SW6) is connected to the one end of the second capacitor (C3) and one end of the seventh switch (SW7), and the other end of the seventh switch (SW7) is substantially connected to the other end. It is connected to the operating potential (GND) maintained stably.

  In the sample mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), the fifth switch (SW5), and the seventh switch (SW7) are controlled to be in an ON state. Then, the second switch (SW2) and the sixth switch (SW6) are controlled to be turned off.

  In the hold mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), the fifth switch (SW5), and the seventh switch (SW7) are controlled to be in an OFF state. Then, the second switch (SW2) and the sixth switch (SW6) are controlled to be in an ON state (see FIGS. 22 to 24).

  According to the preferred first aspect of the present invention, in the sample mode, the sixth switch (SW6) is turned off, so that the operational amplifier (OPA, 61) is switched to the sample mode of the analog input signal (Vin). Is completely electrically isolated from the operation. Therefore, the operational amplifier (OPA, 61) is not used to store charges in the first capacitor (C2), and the operation speed of the operational amplifier (OPA, 61) is set to the analog input signal (Vin). No need to exceed speed.

  In an A / D converter (ADC) according to a preferred second embodiment of the present invention, the bias control circuit (BCC) of the second embodiment is configured such that the differential output signal generated from the preamplifier (AMP) ( Va1 and Va2) are supplied to one end and a predetermined bias potential (Vd) is supplied to the other end, and the other end of the pair of rectifying elements (PM8 and PM9) is one end. And the other end is composed of a capacitor (C1) connected to a bias circuit (PM5, NM4) for controlling the bias current (Ibias) of the preamplifier (AMP).

  When the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is large, it is connected to the capacitor (C1) via one rectifier of the pair of rectifiers (PM8, PM9). A current flows, the current of the bias circuit (PM5, NM4) decreases, and the bias current (Ibias) of the preamplifier (AMP) is controlled to a small current (see FIG. 17).

  According to the means according to the second preferred embodiment of the present invention, the bias control circuit (BCC) is composed of the pair of rectifying elements (PM8, PM9) and the capacitor (C1), and a power supply voltage (Vdd). ) And the ground (GND) do not have a path through which current consumption flows. Therefore, the bias control circuit (BCC) does not consume power consumption due to current consumption between the power supply voltage (Vdd) and the ground (GND).

  A receiving apparatus according to a fourth preferred embodiment of the present invention receives impulse signals (Impls) of ultra-wideband impulse radio (see FIGS. 32 and 37).

<< The more preferable form of the present invention >>
In the A / D converter (ADC) according to the more preferable first aspect of the present invention, the operating potential maintained substantially stably in the system of the first aspect is the A / D converter (ADC). ) Including a low impedance ground potential of a semiconductor integrated circuit, a low impedance ground potential of an electronic device equipped with the semiconductor integrated circuit, a low impedance power supply voltage stabilized by a voltage regulator, and a voltage regulator Or a low impedance reference voltage (see FIG. 10).

  In an A / D converter (ADC) according to another more preferable first embodiment of the present invention, the clock signal (φ) supplied to the sample / hold circuit (SHC) in the system of the first embodiment. The A / D converter (ADC) performs undersampling A / D conversion by setting the frequency to be less than the Nyquist frequency which is twice the maximum frequency or the frequency band of the analog input signal (Vin). Yes (see FIG. 10).

  In the A / D converter (ADC) according to the second embodiment of the present invention, the preamplifier (AMP) and the preamplifier (AMP) in a period of a predetermined level (high level) of the clock signal (φ) in the second embodiment. The bias control circuit (BCC) is activated while the latch circuit (LCH) is deactivated. While the clock signal (φ) is at a level (low level) different from the predetermined level, the preamplifier (AMP) and the bias control circuit (BCC) are inactivated, while the latch circuit (LCH) When activated, information is latched (see FIGS. 13 and 17).

  Other objects and other features of the present invention will become apparent from the following description.

  According to the present invention, an A / D conversion includes a sample / hold circuit that samples and holds an analog input signal in response to a clock signal, and a comparator that discriminates the signal level of the hold output signal from the sample / hold circuit. It is possible to reduce the power consumption of the device.

  Further, according to the present invention, it is possible to improve the performance of an A / D converter including a sample / hold circuit and a comparator.

  Furthermore, according to the present invention, it is possible to operate with a battery or a built-in power source with low driving capability, reduce the power consumption of a receiving device including an A / D converter, and improve the accuracy of digital signal processing.

FIG. 1 is a circuit diagram showing a conventional sample / hold circuit. FIG. 2 is an equivalent circuit in the sample mode of the conventional sample / hold circuit shown in FIG. FIG. 3 is an equivalent circuit in the hold mode of the conventional sample / hold circuit shown in FIG. FIG. 4 is a circuit diagram showing a sample / hold circuit examined by the inventor prior to the present invention. FIG. 5 is an equivalent circuit in the sample mode of the sample / hold circuit shown in FIG. FIG. 6 is an equivalent circuit in the hold mode of the sample / hold circuit shown in FIG. FIG. 7 is a circuit diagram showing a comparator of a conventional A / D converter. FIG. 8 is a waveform diagram for explaining the operation of the comparator of the conventional A / D converter shown in FIG. FIG. 9 is a circuit diagram showing a preamplifier studied by the present inventor prior to the present invention as the preamplifier of the conventional comparator shown in FIG. FIG. 10 is a circuit diagram showing an A / D converter according to the first embodiment of the present invention. FIG. 11 is an equivalent circuit in the sample mode of the first stage sample / hold circuit of the A / D converter shown in FIG. FIG. 12 is an equivalent circuit in the hold mode of the first stage sample / hold circuit of the A / D converter shown in FIG. FIG. 13 is a circuit diagram showing a comparator at the latter stage of the A / D converter shown in FIG. FIG. 14 is a waveform diagram for explaining the operation of the latter-stage comparator of the A / D converter shown in FIG. FIG. 15 is a circuit diagram showing an example of a bias current control circuit of a comparator at the latter stage of the A / D converter shown in FIG. FIG. 16 is a circuit diagram showing another example of the bias current control circuit of the comparator at the latter stage of the A / D converter shown in FIG. FIG. 17 is a circuit diagram showing a specific circuit configuration of the preamplifier and the bias current control circuit of the comparator at the rear stage of the A / D converter shown in FIG. FIG. 18 is a waveform diagram for explaining the operation of the preamplifier and the bias current control circuit of the comparator at the latter stage of the A / D converter shown in FIG. FIG. 19 is a circuit diagram showing another specific circuit configuration of the preamplifier and the bias current control circuit of the comparator at the latter stage of the A / D converter shown in FIG. FIG. 20 is a circuit diagram showing another configuration of the comparator at the subsequent stage of the A / D converter shown in FIG. FIG. 21 is a circuit diagram showing a specific circuit configuration of the first-stage amplifier, the second-stage amplifier, the bias current control circuit, and the latch circuit of the comparator at the rear stage of the A / D converter shown in FIG. FIG. 22 is a circuit diagram showing another configuration of the first stage sample / hold circuit of the A / D converter shown in FIG. FIG. 23 is an equivalent circuit in the sample mode of the sample / hold circuit SHC at the first stage of the A / D converter ADC shown in FIG. FIG. 24 is an equivalent circuit in the hold mode of the sample / hold circuit SHC of the first stage of the A / D converter ADC shown in FIG. FIG. 25 is a waveform diagram showing an example of a timing chart showing the on / off state of the switches of the sample / hold circuit SHC shown in FIG. FIG. 26 is a circuit diagram showing a clock generation circuit for forming three clock signals for controlling the on / off switching timing of the switch of the sample / hold circuit shown in FIG. 22 from a common original clock signal. FIG. 27 is a circuit diagram showing a specific circuit configuration of the operational amplifier and the switch of the first stage sample / hold circuit of the A / D converter shown in FIG. 28 is a circuit diagram showing another configuration of the first stage sample / hold circuit of the A / D converter shown in FIG. 10 and the sample / hold circuit shown in FIG. FIG. 29 is an equivalent circuit in the sample mode of the first stage sample / hold circuit of the A / D converter shown in FIG. FIG. 30 is an equivalent circuit in the hold mode of the first stage sample / hold circuit of the A / D converter shown in FIG. FIG. 31 is a circuit diagram showing a specific circuit configuration of the operational amplifier and the switch of the first stage sample / hold circuit of the A / D converter shown in FIG. FIG. 32 is a block diagram showing the configuration of the ultra-wideband impulse radio radio communication device according to the first embodiment of the present invention. FIG. 33 shows a flash type A / D conversion composed of a combination of the undersampling sample / hold circuits of the various embodiments described above and a plurality of comparators of the various embodiments described above. It is a circuit diagram which shows a container. FIG. 34 is a circuit diagram for explaining an A / D conversion operation by the flash A / D converter shown in FIG. FIG. 35 is a waveform diagram for explaining the operation for reducing the bias current in the A / D conversion by the flash A / D converter shown in FIGS. FIG. 36 is a circuit diagram showing a time interleaved A / D converter according to the second embodiment of the present invention. FIG. 37 is a block diagram showing a configuration of an ultra-wideband impulse radio radio communication device according to the second embodiment of the present invention. FIG. 38 is a diagram illustrating an example of a sensor network system that uses A / D converters according to various embodiments described above and ultra-wideband impulse radio radio communication devices according to various embodiments. FIG. 39 is a circuit diagram showing a more specific configuration of the variable gain amplifier and the undersampling A / D converter of the ultra-wideband impulse radio radio communication device shown in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
≪A / D converter ADC≫
FIG. 10 is a circuit diagram showing the A / D converter ADC according to the first embodiment of the present invention.

  As shown in the figure, the A / D converter ADC includes a first stage sample / hold circuit SHC and a rear stage comparator COP. The first-stage sample / hold circuit SHC includes switches SW1, SW2, SW3, SW8, capacitors C2, C3, and an operational amplifier (OPA) 61. The latter-stage comparator COP includes a preamplifier (AMP) 211, a latch circuit (LCH) 212, and a bias current control circuit (BCC) 213.

  The frequency of the clock signal φ supplied to the first stage sample / hold circuit SHC for the sample / hold operation is the maximum frequency or twice the frequency band of the analog input signal Vin to be A / D converted after being sampled / held. By setting the frequency below a certain Nyquist frequency, the A / D converter ADC performs undersampling A / D conversion.

  The A / D converter ADC in FIG. 10 is for explaining the principle of the present invention of the A / D converter, and the converted digital signal Dout from the comparator COP at the subsequent stage is 1 bit. One input signal Vsig of the differential input signal of the latter-stage comparator COP is one of the differential output signals Vout1 of the first-stage sample / hold circuit SHC, and the other input signal Vref of the differential input signal of the latter-stage comparator COP is The other Vout2 of the differential output signal of the sample / hold circuit SHC in the first stage may be used, or a substantially constant reference voltage VREF may be used. Therefore, if one input signal Vsig of the comparator COP at the subsequent stage is lower than the other input signal Vref, the 1-bit converted digital signal Dout becomes “0” level, and one input signal Vsig is higher than the other input signal Vref. For example, the 1-bit converted digital signal Dout is at the “1” level. However, since the 1-bit digital output A / D converter ADC has a large quantization error, the multi-bit digital output A / D converter ADC in which the quantization error is reduced in the embodiments shown in FIG. explain.

  The first feature of the first embodiment of the present invention shown in FIG. 10 is that the connection node between the two capacitors C2 and C3 is connected via the switch SW8 during the sample mode in the first stage sample / hold circuit SHC. Connected to an operating potential maintained substantially stable in the system. The system is a semiconductor integrated circuit including an A / D converter ADC or various electronic devices equipped with this semiconductor integrated circuit. The operating potential maintained substantially stably in the system is a low-impedance ground potential in a semiconductor integrated circuit or an electronic device, or a low-impedance power supply voltage or a reference voltage stabilized by a voltage regulator or the like. In FIG. 10, the operating potential maintained substantially stable in the system is the ground potential.

  By maintaining the ground potential, the power supply voltage, and the operating potential of the reference voltage at a low impedance and a substantially stable voltage, the first sample / hold circuit SHC is input to both ends of the capacitor C2 during the sample mode. The analog input voltage Vin at the terminal is sampled. Should the potential of the connection node between the two capacitors C2 and C3 fluctuate in an unstable manner, accurate sampling of the analog input voltage Vin at the input terminal into the capacitor C2 becomes impossible. Further, the input offset voltage of the operational amplifier (OPA) 61 is sampled across the capacitor C3 during the sample mode in the first stage sample / hold circuit SHC. Should the potential of the connection node between the two capacitors C2 and C3 fluctuate in an unstable manner, accurate sampling of the input offset voltage of the operational amplifier (OPA) 61 into the capacitor C3 becomes impossible. In this way, the first stage sample / hold circuit SHC can accurately sample the analog input voltage Vin to the capacitor C2 and accurately sample the input offset voltage of the operational amplifier (OPA) 61 to the capacitor C3 during the sample mode. Thus, low power consumption and high performance can be achieved during the sample mode. Therefore, the first stage sample / hold circuit SHC of the A / D converter can be increased in speed and reduced in power consumption.

  When the operating potential that is substantially stably maintained in the system is the ground potential, it is recommended to configure the switch SW8 with NMOS. When the operating potential maintained substantially stable in the system is a power supply voltage or a reference voltage, it is recommended that the switch SW8 be composed of a PMOS. In order to adapt to either case, it is recommended that the switch SW8 be composed of a CMOS analog switch including PMOS and NMOS.

  The second feature of the first embodiment of the present invention shown in FIG. 10 is that the preamplifier 211 of the comparator COP at the subsequent stage is configured such that the input signal Vsig supplied from the output of the sample / hold circuit SHC at the first stage and the reference voltage Vref. Amplification is performed with a large amplification factor only when the difference voltage is small, whereas amplification is performed with a small amplification factor when the difference voltage between the input signal Vsig and the reference voltage Vref is sufficiently large. The magnitude of the differential output signals Va1 and Va2 of the preamplifier 211 proportional to the magnitude of the difference voltage between the input signal Vsig supplied from the output of the first stage sample / hold circuit SHC and the reference voltage Vref is determined by a bias control circuit (BCC) 212. As a result, the bias current of the preamplifier 211 is controlled by the control output signal Vctl of the bias control circuit (BCC) 212. When the differential voltage between the input signal Vsig and the reference voltage Vref is small, the differential voltage between the differential output signals Va1 and Va2 of the preamplifier 211 is also small, the bias current of the preamplifier 211 is controlled to a large current, and the preamplifier of the comparator COP in the subsequent stage 211 amplifies the differential voltage between the input signal Vsig supplied from the output of the first stage sample / hold circuit SHC and the reference voltage Vref with a large amplification factor. Thereafter, when the differential voltage between the differential output signals Va1 and Va2 of the preamplifier 211 increases, the bias current of the preamplifier 211 is controlled to a small current, and the preamplifier 211 of the subsequent comparator COP is supplied from the output of the sample / hold circuit SHC of the first stage. The difference voltage between the input signal Vsig and the reference voltage Vref is amplified with a small amplification factor. In this way, it is possible to increase the speed and reduce the power consumption of the comparator COP at the subsequent stage of the A / D converter.

  Next, the first stage sample / hold circuit SHC of the A / D converter will be described in more detail. The sample / hold circuit SHC in the first stage operates in two modes, a sample mode and a hold mode, by switching the switches SW1, SW2, SW3, and SW8 according to the level change of the clock signal φ. 11 shows an equivalent circuit in the sample mode of the first stage sample / hold circuit SHC of the A / D converter ADC shown in FIG. 10, and FIG. 12 shows the first stage sample of the A / D converter ADC shown in FIG. An equivalent circuit in the hold mode of the / hold circuit SHC is shown.

  In the sample mode, the switches SW1, SW3, SW8 are turned on and the switch SW2 is turned off. Therefore, in the sample mode, as shown in FIG. 11, when the switch SW1 is turned on, the analog input voltage Vin of the input terminal is supplied to one end of the capacitor C2, and when the switch SW8 is turned on, the other end of the capacitor C2 and one end of the capacitor C3 are low. It is set to a ground potential that is an operating voltage that is stably maintained by impedance. Further, when the switch SW3 is turned on, the potential of the input / output terminal of the operational amplifier (OPA) 61 is set to a common mode potential of Vdd / 2 which is substantially half of the power supply voltage Vdd.

  Since the other end of the capacitor C2 is connected to the ground, it is kept at a constant potential, and charges corresponding to the analog input signal Vin can be accumulated at both ends of the capacitor C2. Simultaneously with the accumulation of the input signal in the capacitor C2, the input terminal and the output terminal of the operational amplifier (OPA) 61 are short-circuited by the switch SW3 to form a feedback loop. The other end of the capacitor C3 is kept at a constant ground potential, and a common mode potential including an input offset voltage of the operational amplifier (OPA) 61 is supplied to one end of the capacitor C3 by a feedback loop.

  In this way, the first stage sample / hold circuit SHC can accurately sample the analog input voltage Vin to the capacitor C2 and accurately sample the input offset voltage of the operational amplifier (OPA) 61 to the capacitor C3 during the sample mode. Thus, low power consumption and high performance can be achieved during the sample mode. Therefore, it is possible to increase the speed and power consumption of the sample / hold circuit SHC at the first stage of the A / D converter.

  Next, in the hold mode, the switches SW1, SW3, and SW8 are turned off and the switch SW2 is turned on. That is, in the hold mode, the capacitors C2 and C3 and the operational amplifier (OPA) 61 form a feedback loop when the switch SW2 is turned on as shown in FIG. This feedback loop operates so as to hold the charges accumulated in the capacitors C2 and C3. The other end of the capacitor C2, the one end of the capacitor C3, and the other end of the capacitor C3 hold charges when the sample mode is switched to the hold mode. When the sample mode is switched to the hold mode, the two input terminals of the operational amplifier (OPA) 61 are maintained at a common mode potential of Vdd / 2, which is approximately half of the power supply voltage Vdd, due to the characteristics of the operational amplifier (OPA) 61. The Accordingly, the output signal Vout becomes the input voltage Vin when the sample mode is switched to the hold mode, and is held during the hold mode.

  The output signal Vout held in the hold mode is a voltage in which the offset voltage of the operational amplifier (OPA) 61 is canceled because the offset voltage is accumulated in the capacitor C3. That is, the input offset voltage of the operational amplifier (OPA) 61 can be canceled by accumulating the input offset voltage in the capacitor C3 in the sample mode.

  In this manner, in the hold mode, by forming a feedback loop with the capacitors C2 and C3 and the operational amplifier (OPA) 61, it is possible to hold the input signal when the sample mode is switched to the hold mode.

  Next, the comparator COP at the subsequent stage of the A / D converter will be described in more detail.

  FIG. 13 is a circuit diagram showing a comparator COP at the latter stage of the A / D converter ADC shown in FIG. The comparator COP includes a preamplifier (AMP) 211, a latch circuit (LCH) 212, and a bias current control circuit (BCC) 213.

  During the high level period of the clock signal φ, the preamplifier 211 and the bias current control circuit 213 are activated, while the latch circuit 212 is deactivated by the low level of the anti-phase clock signal φb opposite in phase to the clock signal φ. ing. During the low level period of the clock signal φ, the preamplifier 211 and the bias current control circuit 213 are deactivated, while the latch circuit 212 is activated by the high level of the anti-phase clock signal φb opposite in phase to the clock signal φ. Latch information.

  The preamplifier 211 is supplied with the input signal Vsig and the reference voltage Vref from the output of the first-stage sample / hold circuit SHC of the A / D converter ADC, so that the output signals Va1 and Va2 are generated from the preamplifier 211. The bias current control circuit 213 receives the output signals Va1 and Va2 of the preamplifier 211 and monitors the magnitude of the signals. When the difference voltage between the input signal Vsig and the reference voltage Vref is very small, the preamplifier 211 amplifies the small difference voltage at a high speed and with a high amplification factor, which is sufficient for determining the magnitude of the signal in the latch circuit 212. Give potential difference. When the difference voltage between the input signal Vsig and the reference voltage Vref is very small, the difference voltage between the output signals Va1 and Va2 of the preamplifier 211 is also small, and the small difference voltage between the output signals Va1 and Va2 is determined by the bias current control circuit 213. The The preamplifier 211 is controlled to a large bias current by the control voltage Vctl of the bias current control circuit 213, and the preamplifier 211 amplifies a minute difference voltage between the input signal Vsig and the reference voltage Vref at a high speed and with a high amplification factor. When the difference voltage between the input signal Vsig and the reference voltage Vref becomes sufficiently large, it is not necessary for the preamplifier 211 to amplify the large difference voltage at a high speed and with a high amplification factor. When the difference voltage between the input signal Vsig and the reference voltage Vref becomes sufficiently large, the difference voltage between the output signals Va1 and Va2 of the preamplifier 211 also increases, and the large difference voltage between the output signals Va1 and Va2 is determined by the bias current control circuit 213. . The preamplifier 211 is controlled to a small bias current by the control voltage Vctl of the bias current control circuit 213, and the power consumption of the preamplifier 211 is reduced.

  FIG. 14 is a waveform diagram for explaining the operation of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. In the figure, the change in the consumption current Icmp of the comparator COP in response to the change in the input signal Vsig of the comparator COP in the subsequent stage of the A / D converter ADC shown in FIG. 10, the change in the output signal difference Vamp of the preamplifier 211, A change in the output voltage Dout of the latch circuit 212 is shown.

  In order to reduce the power consumption of the comparator COP at the subsequent stage of the A / D converter using the bias current control circuit 213, the following two requirements are necessary. First, the power consumption of the bias current control circuit 213 itself is sufficiently smaller than that of the preamplifier 211 and the latch circuit 212. The purpose of using the bias current control circuit 213 is not only to reduce the bias current of the preamplifier 211 but also to reduce the current consumption of the entire subsequent comparator COP. Next, the input capacity of the bias current control circuit 213 is sufficiently small. When the input capacity of the bias current control circuit 213 is large, the output load capacity of the preamplifier 211 is increased, and the speed performance of the preamplifier 211 is deteriorated. Therefore, the input capacity of the bias current control circuit 213 is required to be sufficiently small.

  FIG. 15 is a circuit diagram showing an example of the bias current control circuit 213 of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. The bias current control circuit 213 includes diodes (DIO) 231 and 232 and a control signal adjustment circuit (CSA) 233. The diode has a rectifying characteristic that current flows when a voltage applied to both ends of the diode exceeds a threshold voltage, and current does not flow unless the threshold voltage is exceeded. In the bias current control circuit 213, rectification characteristics of a diode are used.

  In the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. 13, the bias current control circuit 213 detects that the output signal difference Vamp of the preamplifier 211 is large. Since the output signal difference Vamp of the preamplifier 211 is the difference between the output signals Va1 and Va2 of the preamplifier 211, if the output signal Va1 or Va2 is large, the output signal difference Vamp of the preamplifier 211 is also large. Therefore, the bias current control circuit 213 detects that the output signal Va1 or Va2 of the preamplifier 211 is large.

  The large output signal Va1 or Va2 of the preamplifier is detected using the diodes 231 and 232. The voltage applied to the diode 231 is the difference between the bias voltage Vd and the output signal Va1 of the preamplifier. Therefore, when the output signal Va1 of the preamplifier 211 increases, the voltage between both ends of the diode 231 increases. Until the voltage exceeds the threshold voltage, no current flows through the diode 231, and when the voltage exceeds the threshold voltage, a current flows. Similarly to the diode 231, the output signal Va <b> 2 of the preamplifier 211 is increased with respect to the diode 232, and a current flows when the voltage between both ends of the diode 232 exceeds the threshold voltage. A current flowing through at least one of the diodes 231 and 232 is input to the control signal adjustment circuit (CSA) 233. A current flows into the control signal adjustment circuit 233 when at least one of the output signals Va1 and Va2 of the preamplifier is large, and no current flows when both are small. That is, by using the diodes 231 and 232, it is possible to detect that the output signal difference of the preamplifier is large.

  The control signal adjustment circuit 233 performs current-to-voltage conversion, voltage level shift, polarity inversion, and the like as necessary, and outputs a bias current control signal Vctl. The preamplifier 211 controls the bias current according to the value of the bias current control signal Vctl.

  FIG. 16 is a circuit diagram showing another example of the bias current control circuit 213 of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. The bias current control circuit 213 includes diodes (DIO) 241, 242, 243, 244 and a control signal adjustment circuit (CSA) 245. The diodes 241, 242, 243, and 244 constitute a bridge circuit, and rectify the output signal difference Vamp of the preamplifier 211. That is, it is possible to detect whether the output signal difference Vamp of the preamplifier is larger or smaller than a certain threshold voltage. When one output signal Va1 of the preamplifier is higher than the other output voltage Va2, the other output voltage is output from one output signal Va1 through the diode 244, the control signal adjustment circuit 245, and the diode 242, as shown by the arrow in FIG. A bridge current flows to Va2. Conversely, when one output signal Va1 of the preamplifier is lower than the other output voltage Va2, the bridge current is transferred from the other output voltage Va2 to one output signal Va1 via the diode 243, the control signal adjustment circuit 245, and the diode 241. Flows. The bridge current is converted from a differential signal to a single-end signal, converted from a current to a voltage, voltage level shift, polarity inversion, etc., as required, inside the control signal adjustment circuit 245, and a bias current control signal Vctl. Is output. In the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. 13, the preamplifier 211 controls the bias current according to the value of the bias current control signal Vctl.

  FIG. 17 is a circuit diagram showing a specific circuit configuration of the preamplifier 211 and the bias current control circuit 213 of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. The comparator COP includes a preamplifier (AMP) 211, a latch circuit (LCH) 212, and a bias current control circuit (BCC) 213.

  The comparator COP shown in FIG. 17 operates in synchronization with clock signals φ and φb having opposite phases. First, the preamplifier 211 includes an NMOS differential pair NM1, NM2, an NMOS equalize switch NM3, an NMOS constant current transistor NM5, and PMOS load transistors PM1, PM2, PM3, PM4, which are loads of the differential pair NM1, NM2. An NMOS bias transistor NM4 that biases the constant current transistor NM5, a PMOS bias current supply transistor PM5 that supplies a bias current to the bias transistor NM4, a PMOS that generates a bias voltage Vbn, and NMOS bias transistors PM6 and NM6. Yes. The bias current control circuit 213 includes a PMOS switch transistor PM7 that supplies a bias voltage Vbp to the gate of the bias current supply transistor PM5 of the preamplifier 211 during a period when the clock signal φ is at a low level (a high level period of the reverse phase clock signal φb). A bias potential Vd based on the bias voltage Vbn generated by the PMOS rectifier transistors PM8 and PM9, the capacitor C1 and the preamplifier 211 for detecting the levels of the output signals Va1 and Va2 of the preamplifier 211 is in a period (in reverse phase). The NMOS switch transistor NM7 is supplied to the rectifying transistors PM8 and PM9 and the capacitor C1 during the high level period of the clock signal φb. The bias current control signal Vctl is generated by the rectifying transistors PM8 and PM9 and the capacitor C1, and the value of the bias current is controlled by the constant current transistor NM5 of the preamplifier 211.

  A bias current flows through the constant current transistor NM5 of the preamplifier 211 while the clock signal φ is at a high level, and the difference between the analog input signal Vsig and the reference voltage Vref is amplified by the preamplifier (AMP) 211. Thereafter, the latch circuit (LCH) 212 is operated during the period when the reverse phase clock signal φb is at the high level, and the digital signal Dout is output. The preamplifier 211 and the bias current control circuit 213 are reset during the period when the negative phase clock signal φb is at the high level. The equalize switch NM3 of the preamplifier 211 is turned on, and the differential output terminal of the preamplifier 211 is short-circuited. Further, the switch transistor PM7 is turned on, the bias voltage Vbp is supplied to the gate of the bias current supply transistor PM5, an appropriate bias current is supplied to the preamplifier 211, and the next clock signal φ is amplified during the high level period. Prepare. At the same time, the switch transistor NM7 is turned on, a bias potential Vd based on the bias voltage Vbn is generated, and the voltage applied to both ends of the rectifier transistors PM8 and PM9 is biased to be equal to or lower than the threshold voltage of the diode.

  During the period when the next clock signal φ is at a high level, the preamplifier 211 operates to amplify the difference between the input signal Vsig and the reference voltage Vref. The preamplifier output signals Va1 and Va2 are supplied to the rectifying transistors PM8 and PM9 of the bias current control circuit 213. When the output signals Va1 and Va2 of the preamplifier are small, the voltage applied to the rectifying transistors PM8 and PM9 does not exceed the threshold voltage of the diode, and no current flows through the bias current control circuit 213. Therefore, the bias current control signal Vctl remains in a state in which the reverse phase clock signal φb is biased during the high level period. For this reason, the preamplifier 211 can perform amplification while maintaining a sufficient bias current for amplification.

  On the other hand, when the output signal Va1 or Va2 of the preamplifier is large and the voltage applied to one of the rectifying transistors PM8 and PM9 exceeds the threshold voltage of the diode, a current flows on the side exceeding the threshold voltage. Since this current flows into the bias potential Vd, the potential of the bias potential Vd increases. As a result, the potential of the gate of the bias current supply transistor PM5 also rises via the capacitor C1, so that the current flowing through PM5 and NM4 in the preamplifier 211 decreases. Since NM4 and NM5 that determines the bias current Ibias of the preamplifier 211 have a current mirror configuration, the preamplifier bias current Ibias can be reduced. Further, the common mode change of the preamplifier 211 can be reduced by reducing the load currents of the load transistors PM1 and PM2 of the preamplifier 211 by the bias current control signal Vctl.

  The threshold voltage at which the rectifying transistors PM8 and PM9 are turned on can be adjusted by the value of the bias voltage Vbn.

  FIG. 18 is a waveform diagram for explaining operations of the preamplifier 211 and the bias current control circuit 213 of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. The figure shows the clock signal φ input to the comparator COP, the difference between the input signal Vsig of the comparator COP and the reference voltage Vref, the difference between the output signals Va1 and Va2 of the preamplifier 211, and the bias current Ibias flowing through the preamplifier 211. Yes.

  When the difference between the input signal Vsig and the reference voltage Vref is small and therefore the difference between the output signals Va1 and Va2 of the preamplifier 251 is small, the bias current control circuit 213 does not reduce the bias current Ibias of the preamplifier 211. Accordingly, the preamplifier 211 performs an amplification operation with a bias current Ibias sufficient to amplify a minute difference voltage between the input signal Vsig and the reference voltage Vref at a high speed and with a high amplification factor. On the other hand, when the difference between the input signal Vsig and the reference voltage Vref is large, and thus the difference between the output signals Va1 and Va2 of the preamplifier 211 is large, the bias current control circuit 213 operates to reduce the bias current Ibias of the preamplifier 211. Since the bias current Ibias of the preamplifier 211 is reduced, the difference Va1−Va2 between the output signals is smaller than when the bias current Ibias is not reduced, but the voltage level at which the latch circuit 212 can determine the magnitude of the signal. Since the above-mentioned amplification is performed, there is no performance deterioration as the comparator COP.

  In the figure, for reference, when the difference between the input signal Vsig and the reference voltage Vref is large, and therefore the difference between the output signals Va1 and Va2 of the preamplifier 211 is large, the bias current Ibias of the preamplifier 211 is not reduced. The difference between the output signals Va1 and Va2 of the preamplifier 211 and the bias current Ibias flowing through the preamplifier 211 are indicated by broken lines. In this case, the difference Va1-Va2 between the output signals of the preamplifier 211 becomes large, but there is a problem that the bias current Ibias of the preamplifier 211 is too large.

  The bias current control circuit 213 described above satisfies two conditions necessary for the control circuit: (1) sufficiently low current consumption and (2) sufficiently small input capacitance. The bias current control circuit 213 includes only rectification transistors PM8 and PM9, a capacitor C1, and switch transistors PM7 and NM7, and does not have a path for current consumption to flow between the power supply voltage Vdd and the ground GND. Therefore, the control circuit 212 itself does not consume power consumption due to current consumption between the power supply voltage Vdd and the ground GND. The input capacitance of the control circuit 212 is dominated by the diffusion capacitance of the source of the MOS transistor and the capacitance between the gate and the source, and is normally negligible compared to the input capacitance of the latch circuit 212. Therefore, if this bias current control circuit 213 is used, it is possible to reduce the power consumption of the comparator without increasing the power consumption by the control circuit or increasing the load capacity of the preamplifier.

  FIG. 19 is a circuit diagram showing another specific circuit configuration of the preamplifier 211 and the bias current control circuit 213 of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. The comparator COP includes a preamplifier (AMP) 211, a latch circuit (LCH) 212, and a bias current control circuit (BCC) 213. In particular, the bias current control circuit 213 includes PN junction diodes 274 and 275, a capacitor C276, and a switch.

  The preamplifier 211 and the bias current control circuit 213 are reset during the high level period of the negative phase clock signal φb. During the high level period of the next clock signal φ, the preamplifier 211 amplifies the difference between the input signal Vsig and the reference voltage Vref. The bias current control circuit 213 receives preamplifier output signals Va1 and Va2, and controls the bias current of the preamplifier 211 in accordance with the magnitudes of the output signals Va1 and Va2. When the output signals Va1 and Va2 of the preamplifier have not changed much from the reset state and the voltage across the diodes 274 and 275 does not exceed the threshold voltage, current flows in the bias current control circuit 213. Absent. Therefore, the bias current control signal Vctl remains biased during the high level period of the reverse phase clock signal φb. For this reason, the preamplifier 211 can perform amplification while maintaining a bias current Ibias sufficient for amplification.

  On the other hand, when the difference between the input signal Vsig and the reference voltage Vref increases, the output signal difference of the preamplifier 211 also increases, so that the potential of one of the output signals Va1 and Va2 decreases. When the potential of the output signal Va1 or Va2 of the preamplifier 211 decreases and the voltage between both ends of the diodes 274 and 275 exceeds the threshold voltage, a current flows out from the bias current control circuit 213, and the bias current flows through the capacitor C276. The potential of the control signal Vctl decreases. As a result, the gate voltage of NM5 decreases, and the bias current Ibias of the preamplifier 211 is reduced. Thus, by detecting the case where the output voltage difference of the preamplifier 211 is large by the diodes 274 and 275 and reducing the bias current Ibias of the preamplifier 211, the power consumption of the comparator COP can be reduced.

  FIG. 20 is a circuit diagram showing another configuration of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. The comparator COP includes a first-stage amplifier (FAMP) 211_A, a second-stage amplifier (SAMP) 211_B, a latch circuit (LCH) 212, a bias current control circuit (BCC) 213, switches 285a, 285b, 286a, and 286b, and capacitors 287a and 287b. Composed. The subscripts a and b indicate a differential pair, and in the following description, the subscripts a and b are omitted unless particularly necessary. Vsig, Vref, and Dout indicate the input signal, reference voltage, and output signal of the comparator, respectively. The subscripts p and n indicate differential signal components. In the following description, the description regarding the subscripts of p and n is omitted unless particularly necessary.

  The input signal Vsig and the reference voltage Vref are input as differential signals to the comparator COP shown in FIG. The difference between the input signal Vsig and the reference voltage Vref is formed using the switches 285a, 285b, 286a, 286b and the capacitors 287a, 287b, and is input to the first stage amplifier 211_A. In the first stage amplifier 211_A, the difference between the input signal Vsig and the reference voltage Vref is amplified, and further amplified by the second stage amplifier 211_B. The output signal of the second-stage amplifier 211_B is converted into a digital signal Dout by the latch circuit 212.

  In order to reduce the power consumption of the comparator COP, a bias current control circuit 213 is used. The bias current control circuit 213 monitors the output signal of the first stage amplifier 211_A. A case where the difference between the differential output signals of the first-stage amplifier 211_A is large is detected, and the bias current of the first-stage amplifier 211_A and the second-stage amplifier 211_B is reduced to reduce power consumption.

  FIG. 21 is a circuit diagram showing specific circuit configurations of the first-stage amplifier 211_A, the second-stage amplifier 211_B, the bias current control circuit 213, and the latch circuit 212 of the comparator COP at the subsequent stage of the A / D converter ADC shown in FIG. FIG.

  The first stage amplifier 211_A and the bias current control circuit 213 of the comparator COP shown in FIG. 21 are configured in substantially the same manner as the preamplifier 211 and the bias current control circuit 213 of the comparator COP shown in FIG. However, an NMOS switch transistor that is turned on by a reverse phase clock signal φb is connected between the drain and gate of the differential pair NM1, NM2 of the first stage amplifier 211_A of the comparator COP shown in FIG. The second stage amplifier 211_B of the comparator COP shown in FIG. 21 includes a constant current transistor NM8, NMOS differential pairs NM9 and NM10 that amplify the differential output signal of the first stage amplifier 211_A, and a switch transistor NM11 controlled by the clock signal φ. NM12, a switch transistor PM10 controlled by a reverse phase clock signal φb, and load transistors PM11 and PM12. The latch circuit 212 of the comparator COP shown in FIG. 21 is a switch transistor controlled by two CMOS inverters NM12, PM14, NM13, PM15, and a negative phase clock signal φb that latch the differential output signal of the second-stage amplifier 211_B. The switch transistor PM13 is controlled by the NM11 and the clock signal φ.

  In the comparator COP shown in FIG. 21, the first-stage amplifier 211_A and the second-stage amplifier 211_B operate during the high-level period of the clock signal φ, and the difference between the input signal Vsig and the reference voltage Vref is amplified. The latch circuit 212 operates during the high level period of φb, and the comparison result between the input signal Vsig and the reference voltage Vref is latched. Further, the first stage amplifier 211_A and the bias current control circuit 213 are also reset during the high level period of the reverse phase clock signal φb.

  The bias current control circuit (BCC) 213 includes rectifying transistors PM8 and PM9, a capacitor C1, and switch transistors PM7 and NM7. The first stage amplifier 211_A and the second stage amplifier 211_B are large as long as the output signal difference of the first stage amplifier 211_A is small and the voltage across the rectification transistors PM8 and PM9 does not exceed the threshold voltage of the rectification transistors PM8 and PM9. An amplification operation is performed while maintaining a bias current sufficient for amplification at the amplification factor.

  On the other hand, when the output signal difference of the first stage amplifier 211_A is large and the voltage between both ends of the rectifying transistors PM8 and PM9 exceeds the threshold voltage of the diode, a current flows through one of the rectifying transistors PM8 and PM9. With this current, the potential of the bias terminal Vd rises, and the gate potential of the bias transistor PM5 also rises via the capacitor C1. For this reason, the current flowing through PM5 and NM4 decreases. Since NM5 and NM4 are current mirrors, the current flowing through NM5, that is, the bias current value of the first-stage amplifier 211_A is reduced. At the same time, the gate voltages of the load transistors PM1 and PM2 are controlled, and the load current values of the load transistors PM1 and PM2 are also reduced. Further, the bias current value of the second-stage amplifier 211_B is also reduced. It is the gate voltage of the constant current transistor NM8 that determines the bias current of the second-stage amplifier 211_B. The gate of the constant current transistor NM8 is connected to the gate of the constant current transistor NM5 of the first stage amplifier 211_A. Therefore, since the current value flowing through the bias transistor NM4 is reduced by the control signal of the bias current control circuit 213, the bias current value flowing through the constant current transistor NM8 is also reduced at the same time. With this configuration, the bias current value of the second-stage amplifier 211_B is reduced. The differential output signal of the second-stage amplifier 211_B is input to a positive feedback latch composed of two CMOS inverters NM12, PM14, NM13, and PM15 of the latch circuit 212, and the digital signal Dout is output from the latch circuit 212. The

  FIG. 22 is a circuit diagram showing another configuration of the first stage sample / hold circuit SHC of the A / D converter ADC shown in FIG.

  The sample / hold circuit SHC shown in FIG. 22 differs from the sample / hold circuit SHC shown in FIG. 10 in that the connection node between the two capacitors C2 and C3 and the ground potential (substantially in the system). In FIG. 22, the switch SW8 connected to the stable operating potential is replaced with three switches SW5, SW6, and SW7.

  23 shows an equivalent circuit in the sample mode of the first stage sample / hold circuit SHC of the A / D converter ADC shown in FIG. 22, and FIG. 24 shows the first stage sample of the A / D converter ADC shown in FIG. An equivalent circuit in the hold mode of the / hold circuit SHC is shown.

  In the sample mode, the switches SW1, SW3, SW5, SW7 are turned on, and the switches SW2, SW6 are turned off. As shown in FIG. 23, in the sample mode, the analog input signal Vin is supplied to one end of the capacitor C2 through the switch SW1, and the other end of the capacitor C2 is connected to the ground through the switch SW5. Corresponding charges are accumulated in the capacitor C2. At this time, the switches SW2 and SW6 are controlled to be off, and the switches SW3 and SW7 are controlled to be on. Accordingly, one end of the capacitor C3 is connected to the ground via the switch SW7, and a common mode potential including the input offset voltage of the operational amplifier (OPA) 61 is supplied to the other end of the capacitor C3. Charge corresponding to the input offset voltage is accumulated in the capacitor C3. In addition, the operational amplifier (OPA) 61 is completely electrically separated from the operation of the sample mode of the analog input signal Vin by turning off the SW6. For this reason, the operational amplifier (OPA) 61 is not used to accumulate charges in the capacitor C2, and the operational speed of the operational amplifier (OPA) 61 does not need to be higher than the speed of the analog input signal Vin.

  In the hold mode, the switches SW1, SW3, SW5, SW7 are turned off, and the switches SW2, SW6 are turned on. That is, in the hold mode, a feedback loop is formed by the capacitors C2 and C3 and the operational amplifier (OPA) 61 when the switch SW2 is turned on as shown in FIG. This feedback loop operates so as to hold the charges accumulated in the capacitors C2 and C3. The other end of the capacitor C2, the one end of the capacitor C3, and the other end of the capacitor C3 hold charges when the sample mode is switched to the hold mode. When the sample mode is switched to the hold mode, the two input terminals of the operational amplifier (OPA) 61 are maintained at a common mode potential of Vdd / 2, which is approximately half of the power supply voltage Vdd, due to the characteristics of the operational amplifier (OPA) 61. The Accordingly, the output signal Vout becomes the input voltage Vin when the sample mode is switched to the hold mode, and is held during the hold mode.

  The output signal Vout held in the hold mode is a voltage in which the offset voltage of the operational amplifier (OPA) 61 is canceled because the offset voltage is accumulated in the capacitor C3. That is, the input offset voltage of the operational amplifier (OPA) 61 can be canceled by accumulating the input offset voltage in the capacitor C3 in the sample mode.

  In this manner, in the hold mode, by forming a feedback loop with the capacitors C2 and C3 and the operational amplifier (OPA) 61, it is possible to hold the input signal when the sample mode is switched to the hold mode.

  When the sample / hold circuit SHC shown in FIG. 22 is switched from the sample mode to the hold mode, the relationship between the on / off time differences of the switches SW1, SW2, SW3, SW5, SW6, and SW7 is important.

  FIG. 25 is a waveform diagram showing an example of a timing chart showing the on / off states of the switches SW1, SW2, SW3, SW5, SW6, and SW7 of the sample / hold circuit SHC shown in FIG. Here, when the signal is at a high level, the switch is on, and when the signal is at a low level, the switch is off. The sampled analog input signal Vin is held at the timing when the switch SW5 switches from on to off. Therefore, the switch SW1 needs to be turned off after the switch SW5 is turned off. The input offset voltage of the operational amplifier (OPA) 61 is stored at the timing when the switch SW3 is switched from on to off. Therefore, the timing for turning off the switch SW7 for fixing one end of the capacitor C3 to the ground needs to be performed after the switch 3 is turned off. Further, the switch SW2 and SW6 must be turned on after the analog input signal Vin is held and the input offset voltage is accumulated.

  That is, the switch SW5 is turned off after the switch SW5 is turned off, and the switches SW1 and SW7 are turned off after the switch SW3 is turned off. The switches SW2 and SW6 are turned on after the switches SW1 and SW7 are turned off. At this time, the three clock signals for controlling the on / off switching timing of the switches SW3 and SW5, the switches SW1 and SW7, and the switches SW2 and SW6 can be formed from a common original clock signal.

  FIG. 26 shows a common original clock signal CLK0 with three clock signals for controlling the on / off switching timing of the switches SW3 and SW5, the switches SW1 and SW7, and the switches SW2 and SW6 of the sample / hold circuit SHC shown in FIG. It is a circuit diagram which shows the clock generation circuit for forming from.

  This clock generation circuit includes a buffer 331, NAND circuits 332 and 333, and an inverter 334. In response to the original clock signal CLK0, an output clock signal CLK35 is generated from the NAND circuit 333, an output clock signal CLK17 is generated from the NAND circuit 332, and an output clock signal CLK26 is generated from the inverter 334. The output clock signal CLK35 determines the on / off switching timing of the switches SW3 and SW5, the output clock signal clock CLK17 determines the on / off switching timing of the switches SW1 and SW7, and the output clock signal CLK26 determines the switch SW2 And the switching timing of ON / OFF of SW6 can be determined.

  FIG. 27 shows a specific circuit configuration of the operational amplifier (OPA) 61 and the switches SW1, SW2, SW3, SW5, SW6, and SW7 of the first stage sample / hold circuit SHC of the A / D converter ADC shown in FIG. FIG.

  The switch SW1a is composed of a NM20 and PM20 CMOS analog switch, and the switch SW1b is composed of a NM21 and PM21 CMOS analog switch. The switch SW5a is composed of an NMOS NM22, and the switch SW5b is composed of an NMOS NM25. The switch SW6a is composed of an NMOS NM23, and the switch SW6b is composed of an NMOS NM26. The switch SW7a is composed of an NMOS NM24, and the switch SW7b is composed of an NMOS NM27. The switch SW2a is composed of a NM38 and PM32 CMOS analog switch, and the switch SW2b is composed of a NM39 and PM33 CMOS analog switch. The switch SW3a is composed of a CMOS analog switch of NM40 and PM34, and the switch SW3b is composed of a CMOS analog switch of NM41 and PM35.

  The gate of the NMOS NM29 and the gate of the NM30 of the differential pair function as a non-inverting input terminal + and an inverting input terminal − of the operational amplifier (OPA) 61, respectively, and a bias voltage is applied to the gate of the source of NM29 and the source of NM30. A constant current transistor NM28 to which Vbn is supplied is connected, and PMOS load transistors PM22 and PM23 are connected to the drain of NM29 and the drain of NM30. The drain amplification signal of NM29 and the drain amplification signal of NM30 are amplified by PM24 and PM26, which are PMOS amplification transistors, respectively, and the output signal Vout1 (inverted output signal −) of the operational amplifier (OPA) 61 from the drain of PM24 and the drain of PM26. ) And the output signal Vout2 (non-inverted output signal +) are generated. NM31 and NM32, which are NMOS constant current load transistors, are connected to the drain of PM24 and PM26, respectively, and a phase compensation circuit composed of a PM25 of PMOS and a capacitor C4 is connected between the drain and gate of PM24. A phase compensation circuit composed of a PMOS PM27 and a capacitor C5 is connected between the drain and the gate of the PM26. The bias voltage Vb is supplied to the gates of the PMOS PM25 and PM27 of the phase compensation circuit, and the resistance value between the drain and source of the PM25 and PM27 is set.

  The differential pair NMOS NM36 and NM37, the constant current transistor NM35, the load transistors PM30 and PM31, the PMOS PM28 and PM29, the NMOS NM33 and NM34, and the capacitors C6 and C7 are the operational amplifiers of the sample / hold circuit SHC ( This constitutes a negative feedback control circuit for setting the common mode voltage of the output signal Vout1 (inverted output signal −) and the output signal Vout2 (non-inverted output signal +) of the OPA 61. During the sample mode period of the sample / hold circuit SHC, the PMOS PM28 and PM29, the NMOS NM33 and NM34 are turned on, and the potential of the output signal Vout1 (inverted output signal −) is set by the averaging circuit using the on-resistance. An intermediate potential intermediate to the potential of the output signal Vout2 (non-inverted output signal +) is formed. Further, during the hold mode period of the sample / hold circuit SHC, the PMOS PM28 and PM29 and the NMOS NM33 and NM34 are turned off, and the output signal Vout1 (inverted output signal −) is output by the averaging circuit including the capacitors C6 and C7. An intermediate potential intermediate between the potential and the potential of the output signal Vout2 (non-inverted output signal +) is formed. The intermediate potential is supplied to the gate of the NM 36, and the target common mode voltage Vcm is supplied to the gate of the NM 37 for voltage comparison. For example, if the intermediate potential is higher than the target common mode voltage Vcm, the drain voltage of the NM 36 decreases. Then, the drain voltages of the PMOS load transistors PM22 and PM23 increase, so that the drain voltages of the PMOS amplification transistors PM24 and PM26 decrease, and finally the intermediate potential becomes equal to the target common mode voltage Vcm. Thus, negative feedback control is executed.

  FIG. 28 is a circuit diagram showing another configuration of the sample / hold circuit SHC at the first stage of the A / D converter ADC shown in FIG. 10 and the sample / hold circuit SHC shown in FIG.

  The sample / hold circuit SHC shown in FIG. 28 is different from the sample / hold circuit SHC shown in FIG. 22 in that a switch SW9 and a capacitor C4 are added between the analog input Vin and the switch SW6 in FIG. The switch SW10 is connected between the capacitor C4 and the common mode voltage Vcm. The added capacitance value of the capacitor C4 is set substantially equal to the capacitance values of the capacitors C2 and C3.

  29 shows an equivalent circuit in the sample mode of the first stage sample / hold circuit SHC of the A / D converter ADC shown in FIG. 28, and FIG. 30 shows the first stage sample of the A / D converter ADC shown in FIG. An equivalent circuit in the hold mode of the / hold circuit SHC is shown.

  In the sample mode, the switches SW1, SW3, SW5, SW7, and SW9 are turned on, and SW2, SW6, and SW10 are turned off. Therefore, as shown in FIG. 29, in the sample mode, the two capacitors C2 and C4 are connected in parallel between the analog input Vin and the ground, and an equal charge Q is accumulated in each of the two capacitors C2 and C4. Therefore, + 2Q total charge is accumulated in the electrodes on the analog input Vin side of the two capacitors C2 and C4, and -2Q total charge is accumulated in the ground side electrodes of the two capacitors C2 and C4. Since the input / output terminal of the operational amplifier 121 is connected by turning on SW3, the common mode potential including the input offset voltage of the operational amplifier (OPA) 61 is supplied to the capacitor C3. In this sample mode, since SW6 is turned off, the operational amplifier (OPA) 61 is completely electrically separated from the input side capacitors C2 and C4. Therefore, since the operational amplifier (OPA) 61 is not related to the charge accumulation in the capacitors C2 and C4 in the sample mode, the operation speed of the operational amplifier (OPA) 61 does not need to be higher than the speed of the analog input signal Vin.

  In the hold mode, the switches SW1, SW3, SW5, SW7, and SW9 are turned off, and the switches SW2, SW6, and SW10 are turned on. Therefore, as shown in FIG. 30, in the hold mode, the capacitors C2 and C3 and the operational amplifier 121 form a feedback loop. Further, when the switch SW10 is turned on, the charge accumulated in the electrodes on the analog input Vin side of the capacitors C4a and C4b is discharged to the common mode voltage Vcm, so that the voltage difference between both ends of the capacitors C4a and C4b is approximately zero volts. It becomes. At this time, since the total charge of −2Q stored in the electrodes on the ground side of the two capacitors C2 and C4 is held by the charge conservation law, the electrode on the analog input Vin side (hold) in the sample mode of the capacitor C2 The charge on the output side electrode of the operational amplifier (OPA) 61 in the mode increases from the initial value + Q in the sample mode to the final value + 2Q in the hold mode by driving the output of the operational amplifier (OPA) 61. Therefore, in this operation, the initial charge + Q accumulated in the capacitor C4 in the sample mode moves in the hold mode to the capacitor C2 that accumulated the initial charge + Q in the sample mode, and the final charge of the capacitor C2 in the hold mode becomes Equivalent to increasing to + 2Q. Therefore, the feedback loop of the capacitors C2 and C3 and the operational amplifier 121 operates so that the voltage accumulated in the capacitor C2 in the sample mode is amplified twice in the hold mode. Therefore, the output signal Vout of the operational amplifier (OPA) 61 is twice the analog input voltage Vin at the time when the sample mode is switched to the hold mode, and twice the voltage is held in the hold mode period. In the output signal Vout held during the hold mode, the input offset voltage of the operational amplifier (OPA) 61 is accumulated in the capacitor C3 during the sample mode, so that the input offset voltage of the operational amplifier (OPA) 61 is canceled. Has been.

  That is, by using the sample / hold circuit SHC shown in FIG. 28, a low power consumption undersampling sample / hold circuit capable of canceling the input offset voltage of the operational amplifier while having a voltage gain of double is realized. It becomes possible.

  In the sample / hold circuit SHC shown in FIG. 28, the case where the capacitance values of the capacitors C2 and C4 are the same has been described. However, the present invention is not limited to this. It is also possible to obtain a large voltage gain by changing the ratio of the capacitance values of the capacitors C2 and C4 to an integral multiple, for example. In the sample / hold circuit SHC shown in FIG. 28, the example in which the common mode potential Vcm is supplied to the terminals on the input side of the capacitors C4a and C4b in the hold mode has been described. However, the present invention is not limited to this. For example, in the hold mode, it is possible to output a difference between the sampled signal and the potential difference by applying a potential difference between the input terminals of the capacitors C4a and C4b.

  FIG. 31 shows a specific example of the operational amplifier (OPA) 61 and the switches SW1, SW2, SW3, SW5, SW6, SW7, SW9, SW10 of the first stage sample / hold circuit SHC of the A / D converter ADC shown in FIG. It is a circuit diagram which shows the structure of a simple circuit.

  In the first stage sample / hold circuit SHC of the A / D converter ADC shown in FIG. 31, the switches SW1, SW2, and SW3 are composed of CMOS analog switches like the switches SW1, SW2, and SW3 of FIG. SW9a, SW9b, SW10a, and SW10b are also composed of CMOS analog switches. Further, the switches SW5, SW6, and SW7 in FIG. 31 are configured with NMOS switches in the same manner as the switches SW5, SW6, and SW7 in FIG. Further, the operational amplifier (OPA) 61 in FIG. 31 is configured by a CMOS analog circuit exactly the same as the operational amplifier (OPA) 61 in FIG.

≪Application of A / D converter ADC≫
Embodiments by application of an undersampling A / D converter ADC configured by combining the undersampling sample / hold circuit SHC of the various embodiments described above and the comparator COP of the various embodiments will be described below. To do.

  FIG. 32 is a block diagram showing a configuration of an ultra-wideband impulse radio (hereinafter, abbreviated as UWB-IR) wireless communication apparatus according to the first embodiment of the present invention.

  The A / D converters (ADC) 166i, 166q inside the UWB-IR wireless communication apparatus shown in FIG. 6 are the undersampling sample / hold circuits SHC of the various embodiments described above and the various embodiments. This is an undersampling A / D converter ADC composed of a combination with the comparator COP.

  32 includes an antenna (ANT) 161, a low noise amplifier (LNA) 162, reception mixers (MIX) 163i and 163q, low pass filters (LPF) 164i and 164q, and variable gain. Amplifiers (VGA) 165i and 165q, A / D converters (ADC) 166i and 166q, a baseband signal processing unit (BB) 167, a π / 2 phase shifter (QPS) 168, and a clock generator (CLK) 169. The subscripts i and q indicate the relationship between the I signal (in-phase signal: In Phase) and the Q signal (quadrature signal: Quadrature), respectively. A description of the subscript is omitted.

  As shown in the figure, the UWB-IR radio receiver intermittently receives UWB impulse signals Impls at a long reception interval Ti. The UWB impulse signal Impls is a signal having an ultra-wide bandwidth (for example, a center frequency of about 4 GHz and a bandwidth of about 500 MHz) transmitted intermittently (for example, at intervals of several tens of MHz). The impulse signal Impls is received by the antenna 161, amplified by the low noise amplifier 162, and then supplied to the reception mixer 163. Since the clock signal of about 4 GHz generated from the clock generator 169 is supplied to the mixer 163, the RF carrier wave component of 4 GHz band and the analog baseband signal component of the frequency bandwidth of about 500 MHz are generated from the output of the receiving mixer 163. Is done. Since the RF carrier component is removed by the low-pass filter 164 connected to the output of the reception mixer 163, the analog baseband signal in the frequency band of about 500 MHz is amplified by the variable gain amplifier 165 and then sent to the A / D converter 166. Supplied. Therefore, an analog baseband signal having a wide frequency bandwidth of, for example, about 500 MHz is intermittently supplied to the A / D converter 166, for example, at intervals of several tens of MHz. The analog baseband signal supplied intermittently is A / D converted by the A / D converter 166 at the long reception interval Ti of the impulse signal Impls, and the digital baseband signals of “1” and “0” are baseband. The signal processing unit 167 is supplied. In order to improve the signal accuracy of the digital baseband signal, the undersampling A / D converter 166 is required to have high undersampling A / D conversion performance. That is, in order to realize A / D conversion by the undersampling A / D converter 166 with low power consumption and high signal accuracy, the undersampling sample / hold circuit SHC of the various embodiments described above and various implementations are described. The undersampling A / D converter ADC configured in combination with the comparator COP in the form is used as an A / D converter (ADC) 166i, 166q inside the UWB-IR wireless communication device shown in FIG. . The two receiving mixers 163i and 163q are supplied with clock signals having different π / 2 (90 °) phases generated by the π / 2 phase shifter 169 based on the clock signal from the clock generator 169. Yes. Accordingly, an I-phase analog baseband signal component that is an in-phase output signal is generated from the reception mixer 163i, and a Q-phase analog baseband signal component that is a quadrature component is generated from the reception mixer 163q.

  FIG. 33 shows a flash type A / A circuit comprising a combination of the undersampling sample / hold circuit SHC of the various embodiments described above and a plurality of comparators COP of the various embodiments described above. It is a circuit diagram which shows D converter ADC.

  The undersampling sample / hold circuit SHC of the various embodiments described above is arranged in the first stage of the flash type A / D converter ADC shown in the figure. The undersampling sample / hold circuit SHC is an analog input signal. Sample / hold Vin. At the output of the undersampling sample / hold circuit SHC, a plurality of the comparators COP described above are arranged in parallel. A plurality of differential voltages between the hold output signal Vsig of the undersampling sample / hold circuit SHC and the plurality of reference voltages Vref_1, Vref_2,... Vref_N are amplified in parallel by the plurality of preamplifiers 211_1, 211_2,. A plurality of reference voltages Vref_1, Vref_2,... Vref_N are generated from interconnection nodes of a plurality of resistors R connected in series between a high level reference voltage VH and a low level reference voltage VL.

  FIG. 34 is a circuit diagram for explaining an A / D conversion operation by the flash A / D converter ADC shown in FIG.

  The flash type A / D converter ADC includes an undersampling sample / hold circuit USSHC and a plurality of comparators COP1, COP2,..., COP5. The input signal Vin is sampled and held by the undersampling sample / hold circuit USSHC. A plurality of difference voltages between the hold output signal Vsig and a plurality of reference voltages Vref_1, Vref_2,... Vref_5 are amplified in parallel by a plurality of comparators COP1, COP2,. Converted to a digital output signal. The digital signal is encoded by the digital encoder ENC, and a final multi-bit A / D converted digital output signal is generated from the output of the digital encoder ENC.

  By adopting the undersampling sample / hold circuit SHC of the various embodiments described above as the first stage undersampling sample / hold circuit USSHC of the flash type A / D converter ADC shown in FIG. It is possible to sample and hold an analog input signal that changes at a high speed with respect to the / D conversion speed with low power consumption and high accuracy.

  Further, the comparators COP of the various embodiments described above are adopted as the plurality of comparators COP1, COP2,..., COP5 in the next stage of the flash type A / D converter ADC shown in FIG. Thus, an unnecessarily large bias current can be reduced for a plurality of preamplifiers of a plurality of comparators, and power consumption can be reduced.

  FIG. 35 is a waveform diagram for explaining the operation of reducing the bias current in the A / D conversion by the flash type A / D converter ADC shown in FIGS.

  In FIG. 35, changes in the consumption currents Icmp1, Icmp2,... Icmp5 of the plurality of comparators are shown with respect to changes in the input voltage Vsig common to the plurality of comparators. In each of the plurality of preamplifiers of the plurality of comparators, the current consumption increases when the level difference between the common input voltage Vsig and the reference signals Vref_1, Vref_2,... Vref_5 having different levels is large, but when the level difference is large. The current consumption is reduced. Therefore, the total total current consumption Isum of the current consumptions Icmp1, Icmp2,... Icmp5 of the plurality of comparators is less dependent on the change in the common input voltage Vsig, and becomes the total current consumption Isum having a substantially constant value.

  FIG. 33 and FIG. 34 illustrate a flash type A / D converter that uses a plurality of comparators in parallel and performs A / D conversion in parallel with a common analog input voltage on a multi-bit digital signal. However, the present invention is not limited to this. The low power consumption and high accuracy undersampling sample / hold circuit SHC and the low power consumption comparator COP that dynamically suppresses the bias current of the preamplifier according to the present invention are not only a successive approximation type, but also a pipeline type. It can also be applied to A / D converters and oversampling ΣΔ type A / D converters, and can be widely applied to low power consumption and high accuracy of various types of A / D converters. .

  As is well known, the successive approximation type A / D converter includes a successive approximation register, a sub D / A converter DAC, and a comparator, and one input terminal and the other input terminal of the comparator are connected to each other. An analog input voltage and a converted analog output signal from the sub D / A converter SUBDAC are supplied. The level of the converted analog output signal from the sub D / A converter SUBDAC is set by multi-bit data in the successive approximation register. Therefore, a negative comparison including the successive approximation in the comparator, the comparator, the successive approximation register, and the sub D / A converter SUBDAC is performed so that the converted analog output signal from the sub D / A converter SUBDAC follows the level of the analog input voltage. By the feedback operation, the multi-bit data of the successive approximation register finally becomes a digital conversion output. As the comparator of the successive approximation type A / D converter, the comparator COP according to the various embodiments of the present invention described above can be used.

  As is well known, a pipeline type A / D converter includes a plurality of unit conversion circuits connected in series. Each unit conversion circuit includes a sample / hold circuit SHC, a sub A / D converter SUBADC, and The sub D / A converter SUBDAC, the difference circuit Diff, and a post-amplifier PTAMP whose voltage gain is set to a constant value (for example, 2). In each unit conversion circuit, the analog input signal from the previous stage is first sampled / held by the sample / hold circuit SHC, the hold voltage is A / D converted by the sub A / D converter SUBADC, and a digital output is output. The digital output is converted into an internal analog signal by the sub D / A converter and then subtracted from the hold voltage of the sample / hold circuit SHC by the difference circuit Diff. The quantization error due to the subtraction is amplified by the post-amplifier PTAM and supplied to the sample / hold circuit SHC of the next stage unit conversion circuit, whereby the same operation as described above is executed. As a result, a multi-bit digital conversion output signal can be obtained from a plurality of unit conversion circuits connected in series. The sample / hold circuit SHC and the sub A / D converter SUBADC of the pipeline type A / D converter include the sample / hold circuit SHC according to the various embodiments of the present invention described above and the various types of the present invention. It is possible to use the comparator COP according to the embodiment.

  As is well known, the oversampling ΣΔ A / D converter includes an oversampling sample / hold circuit SHC, a difference circuit Diff, an integrator Int, and a 1-bit output comparator COP as a quantizer. And a 1-bit sub D / A converter. The difference between the hold voltage of the oversampling sample / hold circuit SHC and the analog conversion output of the sub D / A converter is formed by the difference circuit Diff, integrated by the integrator Int, and then supplied to the 1-bit output comparator COP. The The level of the analog input signal is converted by the oversampling ΣΔ A / D converter from the output of the comparator COP into a 1-bit pulse, and further processed by a digital filter in the subsequent stage. The oversampling sample / hold circuit SHC and the 1-bit output comparator COP of this oversampling ΣΔ A / D converter include the sample / hold circuit SHC according to various embodiments of the present invention described above, and It is possible to use a comparator COP according to various embodiments of the present invention. Even when the output of the quantizer is not 1-bit but multi-bit, it is possible to use the comparator COP according to various embodiments of the present invention.

(Second Embodiment)
≪A / D converter ADC≫
FIG. 36 is a circuit diagram showing a time interleaved A / D converter ADC according to the second embodiment of the present invention.

  In the time interleaved A / D converter ADC shown in the figure, a plurality of sub A / D converters are used in parallel, and the effective A / D conversion speed can be remarkably improved. This time-interleaved A / D converter ADC is composed of n sub A / D converters (SADC) 1511, 1512, 1513,... 151n and a digital multiplexer (MUX) 152. . Each of the n sub A / D converters (SADC) includes an undersampling sample / hold circuit (USSH) and a comparator (COP). Further, as each of the n sub A / D converters (SADC), the undersampling sample / hold circuit (USSH) has a low power consumption of the various embodiments described in the first embodiment of the present invention. A power-accurate undersampling sample / hold circuit SHC can be employed. Further, as each comparator (COP) of the n sub A / D converters (SADC), the bias currents of the preamplifiers of various embodiments described in the first embodiment of the present invention are reduced. A comparator COP can be employed.

  In the time interleaved A / D converter ADC shown in FIG. 36, the analog input signal Vin supplied to the sub A / D converter (SADC) is sampled / held by the undersampling sample / hold circuit (USSH). The hold signal is converted into a digital output signal by a comparator (COP). The n sub A / D converters 1511, 1512, 1513,... 151n are supplied with n multiphase clock signals φ1, φ2, φ3,. Then, A / D conversion is performed. These n multiphase clock signals φ1, φ2, φ3,... Φn have the same frequency fs1, but are different in phase from 2π / n, for example. Therefore, n digitally converted output data of a plurality of bits obtained by A / D converting the analog input signal Vin are sequentially output in time series from the sub A / D converters 1511, 1512, 1513,. The n digital conversion output data of plural bits is converted into one continuous bit stream data of plural bits by the digital multiplexer 152. In this way, the time interleaved A / D converter ADC uses n sub A / D converters in parallel, so that the total A / D as the time interleaved A / D converter ADC is obtained. The conversion throughput is n times the A / D conversion frequency fs1 of each sub A / D converter, and the effective A / D conversion speed can be significantly improved.

  As described above, in the time interleaved A / D converter, the total effective A / D conversion frequency is n × fs1, so that half the frequency (Nyquist frequency) is assumed to be the highest frequency of the analog input signal. Is recommended. That is, the maximum frequency of the analog input signal is assumed to be n × fs1 / 2, and particularly when the parallel number n is large, each of the sub A / D converters 1511, 1512, 1513,. The performance of a high performance undersampling A / D converter is required. In order to realize this, each of the sub A / D converters 1511, 1512, 1513,... 151n has the low power consumption of the various embodiments described in the first embodiment of the present invention. It is recommended to use a highly accurate undersampling sample / hold circuit SHC.

  FIG. 37 is a block diagram showing a configuration of a UWB-IR wireless communication device according to the second embodiment of the present invention.

  A plurality of A / D converters (ADCs) 166i1, 166i2, 166i3, 166q1, 166q2, and 166q3 in the UWB-IR wireless communication apparatus shown in the figure are the second embodiment of the present invention described in FIG. Is a time interleaved A / D converter ADC. The UWB-IR radio communication apparatus shown in FIG. 37 has substantially the same configuration as that of the UWB-IR radio communication apparatus shown in FIG. 32 except for the time interleaved A / D converter ADC. .

  In order to receive the impulse signal Impls used for UWB-IR wireless communication and to track the synchronization between the impulse signal Impls and the multiphase clock pulse, a method of sampling and A / D conversion at a plurality of timings is effective. is there. The monopulse signal amplified by the variable gain amplifier 165 is sampled at a plurality of timings and A / D converted using a plurality of A / D converters 166i1, 166i2, 166i3, 166q1, 166q2, and 166q3 arranged in parallel. . Multiphase clock pulses 1721, 1722 and 1723 supplied to these A / D converters are generated by a multiphase clock control circuit 171. A first clock 1721 is supplied to the first A / D converters 166i1, 166q1, a second clock 1722 is supplied to the second A / D converters 166i2, 166q2, and a third A / D converter is supplied. A third clock 1723 is supplied to the converters 166i3 and 166q3. By making the difference between the timings of these multiphase clocks 1721, 1722, and 1723 sufficiently smaller than the pulse width of the monopulse signal output from the variable gain amplifier 165, the monopulse signal is sampled at a plurality of timings and A / D Can be converted. For example, while the pulse width of the monopulse signal is 2 ns or more, the difference in timing between the multiphase clocks 1721, 1722, and 1723 is set to about 1 ns or less. The digital output data after A / D conversion by the time interleaved A / D converter ADC is supplied to the baseband processing unit 167, and digital signal processing such as filtering and demodulation is executed. Further, in the baseband processing unit 167, the synchronization deviation or the synchronization deviation between the impulse signal Impls and the multiphase clock pulse is lost due to the magnitude relationship of the digital output signals at a plurality of timings of the output of the time interleaved A / D converter ADC. Is detected. The multi-phase clock control circuit 171 is controlled based on the detection result, and the phases of the multi-phase clocks 1721, 1722, and 17 are adjusted, thereby obtaining synchronization between the impulse signal Impls and the multi-phase clock pulse. The individual A / D converters 166i1, 166i2, 166i3, 166q1, 166q2, and 166q3 constituting the time interleaved A / D converter ADC of the UWB-IR wireless communication device are also provided with high performance undersampling A / D. The performance of the D converter is required. In order to realize this, each sub A / D converter has a low power consumption and high accuracy undersampling sample / hold circuit SHC according to the various embodiments described in the first embodiment of the present invention. And a comparator COP that reduces the bias current of the preamplifiers of the various embodiments described in the first embodiment of the present invention above is recommended. FIG. 37 shows an example in which a time interleaved A / D converter ADC is configured with three sub A / D converters for each of the I signal and the Q signal. However, the present invention is not limited to this, and it goes without saying that the time interleaved A / D converter ADC may be constituted by four or more sub A / D converters.

  The A / D converter ADC according to the various embodiments described above and the UWB-IR wireless communication device according to the various embodiments can be applied to various systems. One example is a wireless sensor network (hereinafter abbreviated as sensor network) technology. The sensor network wirelessly transmits various situations and environmental data, such as the human condition, the status of articles such as electronic devices, and their surrounding environment, over a wireless network, thereby improving the efficiency of daily life and work. It is intended to realize. Furthermore, new applications are also expected, especially for security and healthcare.

  FIG. 38 is a diagram showing an example of a sensor network system that uses the A / D converter ADC according to various embodiments described above and the UWB-IR wireless communication device according to various embodiments.

  This sensor network system is attached to a service infrastructure including the Internet (INT), a server (SRV), a terminal (TRM), and a base station (BAS), and a large number of articles such as humans and mobile devices that enjoy the service. It is composed of a large number of terminal nodes (NOD). The server SRV also includes various databases (DBS). A large number of terminal nodes NOD are distributed in various environments, and a large amount of information collected by each terminal node NOD is aggregated in the server SRV via the base station BAS, and is used for various services on a network such as the Internet INT. It is used effectively.

  In such a sensor network, when a large number of terminal nodes NOD are distributed and arranged, in order to improve the degree of freedom of the terminal nodes NOD, it is necessary to eliminate the need for power supply lines and data lines in the terminal node NOD. That is, the terminal node NOD needs to have a built-in power source and perform wireless communication. Since the life of the power supply affects the maintenance cost, the power consumption of the terminal node NOD is preferably as small as possible. As shown in FIG. 37, each terminal node NOD includes a sensor (SEN), a controller (CPU), a memory (nonvolatile memory ROM / volatile memory RAM), a wireless communication unit (transmission subunit TX / reception subunit RX). ), And a power supply unit (PWR) and the like. A component that consumes a large amount of power in the terminal node NOD is a wireless communication unit (TX / RX). That is, a wireless communication method with low power consumption in the wireless communication unit (TX / RX) is important. Therefore, as shown in the lower part of FIG. 38, the receiving circuit of the UWB-IR radio communication apparatus according to the second embodiment of the present invention shown in FIG. 37 is used as the receiving subunit RX constituting the terminal node NOD. As a result, power consumption can be reduced. Therefore, it is possible to extend the life of the power supply of the terminal node NOD, and further reduce the maintenance cost of the system. Note that the sensor SEN constituting the terminal node NOD shown in FIG. 37 is for grasping various situations such as temperature and vibration of humans and various articles. If this sensor SEN is an acceleration sensor, it is possible to convert the kinetic energy of the movement and movement of humans and various articles into the power supply voltage of the power supply unit PWR.

  FIG. 39 is a circuit diagram showing a more specific configuration of the variable gain amplifier (VGA) and the undersampling A / D converter (ADC) of the UWB-IR wireless communication device shown in FIG.

  The analog baseband signal from the low pass filter LPF connected to the reception mixer MIX of the UWB-IR wireless communication device shown in FIG. 32 is amplified by the variable gain amplifier VGA. At this time, the gain of the variable gain amplifier VGA is controlled by the gain control signal Vgctl. The analog baseband amplified signal from the output of the variable gain amplifier VGA is compared with the sampling and holding speed of the undersampling sample / hold circuit USSHC (same configuration as the undersampling sample / hold circuit shown in FIG. 27). It contains high-speed signal components. The undersampling sample / hold circuit USSHC samples the output signal of the variable gain amplifier VGA that changes at high speed, and holds the signal sampled for a long time compared to the speed of the fast change signal. By using the undersampling sample / hold circuit USSHC, it is possible to sample / hold a high-speed input signal with low power consumption and high performance.

  The analog signal held by the undersampling sample / hold circuit USSHC is supplied to the next-stage sample / hold circuit SHC and the comparators COP1 and COP2. The sample / hold circuit SHC is configured in substantially the same manner as the sample / hold circuit SHC shown in FIG. 31, and is a sample / hold circuit having a double voltage gain. The sample / hold circuit SHC samples the input signal and doubles it. Holds after voltage amplification. The next-stage comparators COP1 and COP2 are configured in substantially the same manner as the comparator COP shown in FIG. 21, and compare the output signal of the previous-stage undersampling sample / hold circuit USSHC with the reference voltage. The reference voltages Vref_1 and Vref_2 are generated by the voltage dividing resistor R. In each of the next-stage comparators COP1 and COP2, the difference between the input signal and the reference voltage is amplified by the first-stage amplifier (FAMP) 211_A and the second-stage amplifier (SAMP) 211_B, and the discrimination result is sent to the latch circuit (LCH) 212. Is latched. At this time, the bias currents of the first stage amplifier (FAMP) 211_A and the second stage amplifier (SAMP) 211_B are controlled by the output of the bias current control circuit (BCC) 213 responding to the output voltage difference of the first stage amplifier (FAMP) 211_A. Yes. That is, when the output voltage difference of the first stage amplifier (FAMP) 211_A is large, the bias currents of the first stage amplifier (FAMP) 211_A and the second stage amplifier (SAMP) 211_B are reduced by the output of the bias current control circuit (BCC) 213. Therefore, low power consumption is achieved.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  As described above, the present invention is limited to an undersampling A / D converter including a low power consumption and high accuracy undersampling sample / hold circuit and a low power consumption comparator that dynamically suppresses the bias current of the preamplifier. It is applicable not only to the pipeline type but also to the successive approximation type as well as the oversampling ΣΔ type A / D converter, and it is possible to reduce the power consumption of various types of A / D converters. Some can be applied to a wide range of precision.

  The present invention also provides an A / D conversion including a sample / hold circuit that samples and holds an analog input signal in response to a clock signal, and a comparator that discriminates the signal level of the hold output signal from the sample / hold circuit. The present invention is not limited to a device, but can be applied to a sample / hold circuit used in a wide range, and can also be applied to a comparator used in a wide range.

  Considering that the claim for the sample / hold circuit to be used widely and the claim for the comparator to be used widely will be filed as necessary in the future, the features of the invention having the possibility of this divisional application will be described below. It describes.

  A basic sample / hold circuit (SHC) that is widely used includes an operational amplifier (OPA, 61), a first switch (SW1), a second switch (SW2), a third switch (SW3), 4 switch (SW8), 1st capacity | capacitance (C2), and 2nd capacity | capacitance (C3) are included.

  An input signal (Vin) is supplied to one end of the first switch (SW1), and the other end of the first switch (SW1) is one end of the first capacitor (C2) and one end of the second switch (SW2). It is connected to the. The other end of the first capacitor (C2) is connected to one end of the second capacitor (C3) and one end of the fourth switch (SW8), and the other end of the second capacitor (C3) is connected to the operational amplifier (OPA). 61) and one end of the third switch (SW3), and the other end of the second switch (SW2) and the other end of the third switch (SW3) are connected to the operational amplifier (OPA, 61). Connected to the output.

  In the sample mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), and the fourth switch (SW8) are controlled to be in an ON state, and the second switch (SW2) ) Is controlled to the off state.

  In the hold mode of the sample / hold circuit (SHC), the first switch (SW1), the third switch (SW3), and the fourth switch (SW8) are controlled to be in an OFF state, and the second switch (SW2) ) Is controlled to be on.

  The other end of the fourth switch (SW8) is connected to an operating potential (GND) maintained substantially stably in the system (see FIGS. 10 to 12).

  A more suitable sample / hold circuit (SHC), which is widely used, will be apparent from the foregoing description.

  A basic comparator (COP) widely used includes a preamplifier (AMP) for amplifying a differential input signal (Vsig, Vref) and a differential output signal (Va1, Va2) generated from the preamplifier (AMP). ) And a bias current (Ibias) of the preamplifier (AMP) in response to a level difference between the differential output signals (Va1, Va2) generated from the preamplifier (AMP). And a bias control circuit (BCC) for controlling the value.

  When the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is small, the bias control circuit (BCC) sets the bias current (Ibias) of the preamplifier (AMP) to a large current value. When the level difference of the differential output signals (Va1, Va2) generated from the preamplifier (AMP) is large, the bias control circuit (BCC) causes the bias current (Ibias) of the preamplifier (AMP) to ) Is controlled to a small current value (see FIGS. 13 to 14).

  A suitable comparator (COP) from the preferred comparator (COP) used extensively will be apparent from the foregoing description.

SHC sample hold circuit SW1 switch C1a, C1b, C2a, C2b, C3a, C3b Capacity ADC A / D converter COP comparator 11, 41, 61, 91 Operational amplifier (OPA)
181, 211 Preamplifier (AMP)
182, 212 Latch (LCH)
213 Bias control circuit (BCC)
161 Antenna (ANT)
162 Low noise amplifier (LNA)
163i, 163q Mixer (MIX)
164i, 164q Low-pass filter (LPF)
165i, 165q Variable gain amplifier (VGA)
166i, 166q A / D converter (ADC)
167 Baseband processing unit (BB)
168 π / 2 phase shifter (QPS)
169 ... Clock generator (CLK)
USSH Undersampling sample / hold circuit 1511, 1512, 151n Sub A / D converter (SADC)
152 Digital multiplexer (MUX)

Claims (5)

A sample / hold circuit that samples and holds an analog input signal in response to a clock signal; and a comparator that discriminates the signal level of the hold output signal from the sample / hold circuit;
The comparator includes a preamplifier that amplifies the hold output signal from the sample / hold circuit, a latch circuit that latches a differential output signal generated from the preamplifier, and a differential output signal generated from the preamplifier. A bias control circuit that controls a current value of the bias current of the preamplifier in response to a level difference,
When the level difference of the differential output signal generated from the preamplifier is small, the bias control circuit controls the bias current of the preamplifier to a large current value, and the differential output signal generated from the preamplifier When the level difference is large, the bias control circuit controls the bias current of the preamplifier to a small current value. In claim 1,
The bias control circuit includes a pair of rectifying elements in which the differential output signal generated from the preamplifier is supplied to one end and a predetermined bias potential is supplied to the other end, and one end is the other end of the pair of rectifying elements. And an other end of the A / D converter having a capacitor connected to a bias circuit for controlling the bias current of the preamplifier. In claim 1,
The preamplifier and the bias control circuit are activated during a predetermined level period of the clock signal, while the latch circuit is deactivated, and the preamplifier during a period when the clock signal is different from the predetermined level. The A / D converter is characterized in that the bias control circuit is deactivated while the latch circuit is activated to latch information. A reception mixer that converts a received radio frequency signal into an analog baseband signal, an A / D converter that converts the analog baseband signal from the reception mixer into a digital baseband signal, and the A / D converter A baseband signal processing unit that digitally processes the digital baseband signal of
A receiving apparatus, wherein the A / D converter is operated by a battery constituted by the A / D converter according to claim 1 or a built-in power source having a low driving capability. In claim 4,
An apparatus for receiving an impulse signal of an ultra-wide band impulse radio.

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