JP5676155B2 - Radiation detector manufacturing method and radiation detector - Google Patents

Radiation detector manufacturing method and radiation detector Download PDF

Info

Publication number
JP5676155B2
JP5676155B2 JP2010142387A JP2010142387A JP5676155B2 JP 5676155 B2 JP5676155 B2 JP 5676155B2 JP 2010142387 A JP2010142387 A JP 2010142387A JP 2010142387 A JP2010142387 A JP 2010142387A JP 5676155 B2 JP5676155 B2 JP 5676155B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
radiation detector
connection member
connecting member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010142387A
Other languages
Japanese (ja)
Other versions
JP2012007926A (en
Inventor
主鉉 柳
主鉉 柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Aloka Medical Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Aloka Medical Ltd filed Critical Hitachi Aloka Medical Ltd
Priority to JP2010142387A priority Critical patent/JP5676155B2/en
Priority to PCT/JP2011/064221 priority patent/WO2011162282A1/en
Publication of JP2012007926A publication Critical patent/JP2012007926A/en
Application granted granted Critical
Publication of JP5676155B2 publication Critical patent/JP5676155B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11318—Manufacturing methods by local deposition of the material of the bump connector in liquid form by dispensing droplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/13191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14179—Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145—Material
    • H01L2224/14505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/175—Material
    • H01L2224/17505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8184—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9205—Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Description

本発明は、放射線検出器の製造方法、及び放射線検出器に関する。特に、本発明は、γ線、Ｘ線等の放射線を検出する放射線検出器の製造方法、及び放射線検出器に関する。   The present invention relates to a method for manufacturing a radiation detector and a radiation detector. In particular, the present invention relates to a method for manufacturing a radiation detector that detects radiation such as γ-rays and X-rays, and a radiation detector.

従来、熱膨張係数が８．０×１０−６［１／℃］以上の基板と、基板上に配置された半導体検出素子とから構成される半導体検出部を備え、半導体検出素子が略平板状の半導体結晶体からなり、半導体結晶体の下面にＡｕからなる素子電極が設けられ、素子電極と配線基板に設けられたパッド電極とを半導体結晶のヤング率より小さいずれ弾性を有するバンプで固定する放射線検出器が知られている（例えば、特許文献１参照）。特許文献１に記載の放射線検出器は、半導体結晶体との間で熱膨張係数差が大きな配線基板でも半導体結晶体の検出特性の劣化を抑制することができる。 2. Description of the Related Art Conventionally, a semiconductor detection unit including a substrate having a thermal expansion coefficient of 8.0 × 10 −6 [1 / ° C.] or more and a semiconductor detection element disposed on the substrate is provided. An element electrode made of Au is provided on the lower surface of the semiconductor crystal, and the element electrode and the pad electrode provided on the wiring substrate are fixed by a bump having a displacement elasticity smaller than the Young's modulus of the semiconductor crystal. A radiation detector is known (see, for example, Patent Document 1). The radiation detector described in Patent Document 1 can suppress deterioration in detection characteristics of a semiconductor crystal even in a wiring board having a large difference in thermal expansion coefficient with the semiconductor crystal.

特開２００７−２１４１９１号公報JP 2007-214191 A

しかし、特許文献１に係る放射線検出器は、基板に半導体検出素子を配置し、半導体検出素子を基板に固定する工程において基板の反り等に起因する放射線検出器の製造歩留りについて考慮していない。   However, the radiation detector according to Patent Document 1 does not consider the manufacturing yield of the radiation detector due to warpage of the substrate or the like in the process of arranging the semiconductor detection element on the substrate and fixing the semiconductor detection element to the substrate.

したがって、本発明の目的は、製造工程において製品の歩留りを向上させることのできる放射線検出器の製造方法、及び放射線検出器を提供することにある。   Therefore, the objective of this invention is providing the manufacturing method of a radiation detector which can improve the yield of a product in a manufacturing process, and a radiation detector.

本発明は、上記目的を達成するため、配線パターンと、配線パターンの表面に設けられる第１接続部材とを有する基板を準備する基板準備工程と、第２接続部材を基板上に部分的に塗布する塗布工程と、第２接続部材を介して放射線を検出可能な半導体素子を基板上に配置し、第２接続部材を硬化させることにより半導体素子を基板に一時的に固定する仮固定工程とを備える放射線検出器の製造方法が提供される。   In order to achieve the above object, the present invention provides a substrate preparation step of preparing a substrate having a wiring pattern and a first connection member provided on the surface of the wiring pattern, and partially applying the second connection member on the substrate. And a temporary fixing step in which a semiconductor element capable of detecting radiation is disposed on the substrate via the second connection member, and the semiconductor element is temporarily fixed to the substrate by curing the second connection member. A method of manufacturing a radiation detector is provided.

また、上記放射線検出器の製造方法においては、仮固定工程の後に、第１接続部材を硬化させ、配線パターンと半導体素子とを電気的に接続させる硬化工程を更に備えることもできる。   Moreover, in the manufacturing method of the said radiation detector, the hardening process which hardens a 1st connection member and electrically connects a wiring pattern and a semiconductor element after a temporary fixing process can also be further provided.

また、上記放射線検出器の製造方法においては、半導体素子が、平面視にて略四角形状を有し、塗布工程が、半導体素子の四隅近傍に対応する基板上の複数の位置に第２接続部材を塗布することもできる。   Moreover, in the manufacturing method of the radiation detector, the semiconductor element has a substantially square shape in a plan view, and the coating process is performed at the second connection member at a plurality of positions on the substrate corresponding to the vicinity of the four corners of the semiconductor element. Can also be applied.

また、上記放射線検出器の製造方法においては、第１接続部材が、銀ペースト又ははんだであり、第２接続部材が、ＵＶ硬化樹脂であり、仮固定工程が、第２接続部材に紫外線を照射することにより第２接続部材を硬化させ、硬化工程が、第１接続部材を加熱することにより第１接続部材を硬化させることもできる。   Moreover, in the said manufacturing method of a radiation detector, a 1st connection member is a silver paste or solder, a 2nd connection member is UV hardening resin, and a temporary fixing process irradiates a 2nd connection member with an ultraviolet-ray. By doing so, the second connecting member can be cured, and in the curing step, the first connecting member can be cured by heating the first connecting member.

また、上記放射線検出器の製造方法においては、基板準備工程が、一方の面及び他方の面のそれぞれに配線パターンと第１接続部材とを有する基板を準備し、塗布工程が、一方の面及び他方の面のそれぞれの複数個所に部分的に第２接続部材を塗布し、仮固定工程が、一方の面及び他方の面のそれぞれに複数の半導体素子を配置し、一方の面及び他方の面のそれぞれに複数の半導体素子それぞれを一時的に固定することもできる。   Moreover, in the manufacturing method of the said radiation detector, a board | substrate preparatory process prepares the board | substrate which has a wiring pattern and a 1st connection member in each of one side and the other side, and an application | coating process consists of one side and The second connecting member is partially applied to each of a plurality of locations on the other surface, and the temporary fixing step places a plurality of semiconductor elements on each of the one surface and the other surface, and the one surface and the other surface. Each of the plurality of semiconductor elements can be temporarily fixed to each.

また、上記放射線検出器の製造方法においては、基板準備工程が、一方の面及び他方の面のそれぞれに配線パターンと第１接続部材とを有する基板を準備し、塗布工程が、一方の面及び他方の面のそれぞれの複数個所に部分的に第２接続部材を塗布し、仮固定工程が、一方の面に複数の半導体素子を配置し、配置した複数の半導体素子を一時的に固定した後、他方の面に複数の半導体素子を配置すると共に、他方の面に複数の半導体素子を一時的に固定することもできる。   Moreover, in the manufacturing method of the said radiation detector, a board | substrate preparatory process prepares the board | substrate which has a wiring pattern and a 1st connection member in each of one side and the other side, and an application | coating process consists of one side and After the second connecting member is partially applied to each of a plurality of locations on the other surface, and the temporary fixing process places a plurality of semiconductor elements on one surface and temporarily fixes the plurality of arranged semiconductor elements A plurality of semiconductor elements can be disposed on the other surface, and a plurality of semiconductor elements can be temporarily fixed on the other surface.

また、本発明は、上記目的を達成するため、配線パターンと、配線パターンの表面に設けられる第１接続部材とを有する基板と、第１接続部材を介し配線パターンに電気的に接続され、放射線を検出可能な半導体素子と、半導体素子と基板との間に部分的に設けられ、半導体素子を基板に固定させる複数の第２接続部材とを備える放射線検出器が提供される。   In order to achieve the above object, the present invention provides a substrate having a wiring pattern and a first connection member provided on the surface of the wiring pattern, and is electrically connected to the wiring pattern via the first connection member, and radiation. There is provided a radiation detector comprising: a semiconductor element capable of detecting the semiconductor element; and a plurality of second connection members that are partially provided between the semiconductor element and the substrate and fix the semiconductor element to the substrate.

また、上記放射線検出器は、第２接続部材が、第１接続部材の接着力より弱い接着力を有することが好ましい。   In the radiation detector, it is preferable that the second connection member has an adhesive force weaker than that of the first connection member.

また、上記放射線検出器は、前記基板が、０．４ｍｍ以下の厚さを有していてもよい。   In the radiation detector, the substrate may have a thickness of 0.4 mm or less.

また、上記放射線検出器は、半導体素子が、平面視にて略四角状に形成され、第２接続部材が、半導体素子の四隅近傍に位置させてもよい。   In the radiation detector, the semiconductor element may be formed in a substantially square shape in a plan view, and the second connection member may be positioned near the four corners of the semiconductor element.

また、上記放射線検出器は、第１接続部材が、銀ペースト又ははんだであり、第２接続部材が、ＵＶ硬化樹脂であってもよい。   In the radiation detector, the first connecting member may be a silver paste or solder, and the second connecting member may be a UV curable resin.

本発明に係る放射線検出器の製造方法、及び放射線検出器によれば、製造工程において製品の歩留りを向上させることのできる放射線検出器の製造方法、及び放射線検出器を提供することができる。   According to the radiation detector manufacturing method and the radiation detector according to the present invention, it is possible to provide a radiation detector manufacturing method and a radiation detector capable of improving the yield of products in the manufacturing process.

本発明の第１の実施の形態に係る放射線検出器の斜視図である。1 is a perspective view of a radiation detector according to a first embodiment of the present invention. 本発明の第１の実施の形態に係る放射線検出器の一部を放射線が入射する方向から見た場合における部分拡大図である。It is the elements on larger scale in the case of seeing a part of radiation detector concerning a 1st embodiment of the present invention from the direction which radiation enters. 本発明の第１の実施の形態に係る放射線検出器の製造工程の流れの一部の模式図である。It is a partial schematic diagram of the flow of the manufacturing process of the radiation detector which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る放射線検出器の製造工程の一部の模式図である。It is a partial schematic diagram of the manufacturing process of the radiation detector which concerns on the 1st Embodiment of this invention. 本発明の第２の実施の形態に係る放射線検出器の製造工程の一部の模式図である。It is a partial schematic diagram of the manufacturing process of the radiation detector which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る放射線検出器の製造工程の一部の模式図である。It is a partial schematic diagram of the manufacturing process of the radiation detector which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施の形態に係る放射線検出器の製造工程の一部の模式図である。It is a partial schematic diagram of the manufacturing process of the radiation detector which concerns on the 3rd Embodiment of this invention.

［第１の実施の形態］
図１は、本発明の第１の実施の形態に係る放射線検出器の斜視図の概要を示す。図２は、本発明の第１の実施の形態に係る放射線検出器の一部を放射線が入射する方向から見た場合における部分拡大図の概要を示す。 [First Embodiment]
FIG. 1 shows an outline of a perspective view of a radiation detector according to a first embodiment of the present invention. FIG. 2 shows an outline of a partially enlarged view when a part of the radiation detector according to the first embodiment of the present invention is viewed from the direction in which the radiation is incident.

（放射線検出器１の構成の概要）
本実施の形態に係る放射線検出器１は、カード形状を呈し、γ線、Ｘ線等の放射線を検出する放射線検出器である。図１において放射線１００は、紙面の上方から下方に沿って入射してくる。すなわち、放射線１００は、放射線検出器１の半導体素子１０からカードホルダ３０及びカードホルダ３１に向かう方向に沿って入射して放射線検出器１に到達する。そして、放射線検出器１は、半導体素子１０の側面（つまり、図１の上方に面している面）に放射線１００が入射する。したがって、半導体素子１０の側面が放射線１００の入射面となっている。このように、半導体素子１０の側面を放射線１００の入射面とする放射線検出器１を、本実施の形態ではエッジオン型の放射線検出器１と称する。 (Outline of configuration of radiation detector 1)
The radiation detector 1 according to the present embodiment is a radiation detector that has a card shape and detects radiation such as γ rays and X rays. In FIG. 1, the radiation 100 enters from the upper side to the lower side of the page. That is, the radiation 100 is incident along the direction from the semiconductor element 10 of the radiation detector 1 toward the card holder 30 and the card holder 31 and reaches the radiation detector 1. In the radiation detector 1, the radiation 100 is incident on the side surface of the semiconductor element 10 (that is, the surface facing upward in FIG. 1). Therefore, the side surface of the semiconductor element 10 is an incident surface for the radiation 100. Thus, the radiation detector 1 having the side surface of the semiconductor element 10 as the incident surface of the radiation 100 is referred to as an edge-on type radiation detector 1 in the present embodiment.

なお、放射線検出器１は、特定の方向（例えば、放射線検出器１に向かう方向）に沿って入射してくる放射線１００が通過する複数の開口を有するコリメータ（例えば、マッチドコリメータ、ピンホールコリメータ等）を介して放射線１００を検出する複数の放射線検出器１が並べられて構成されるエッジオン型の放射線検出器用の放射線検出器１として構成することもできる。   The radiation detector 1 includes a collimator (for example, a matched collimator, a pinhole collimator, etc.) having a plurality of openings through which the incident radiation 100 passes along a specific direction (for example, a direction toward the radiation detector 1). The radiation detector 1 can be configured as an edge-on type radiation detector configured by arranging a plurality of radiation detectors 1 that detect the radiation 100 via the above.

具体的に、放射線検出器１は、放射線１００を検出可能な一対の半導体素子１０と、薄い基板２０と、一対の半導体素子１０の隣接部分にて基板２０を挟み込むことにより基板２０を支持するカードホルダ３０及びカードホルダ３１とを備える。そして、本実施の形態においては、一例として、一対の半導体素子１０が４組、基板２０を挟み込む位置において基板２０に固定される。すなわち、各組の一対の半導体素子１０は、基板２０の一方の面と他方の面とのそれぞれに基板２０を対称面として対称の位置に固定される。   Specifically, the radiation detector 1 includes a pair of semiconductor elements 10 capable of detecting the radiation 100, a thin substrate 20, and a card that supports the substrate 20 by sandwiching the substrate 20 between adjacent portions of the pair of semiconductor elements 10. A holder 30 and a card holder 31 are provided. In the present embodiment, as an example, four pairs of the semiconductor elements 10 are fixed to the substrate 20 at positions where the substrate 20 is sandwiched. That is, the pair of semiconductor elements 10 in each set is fixed to a symmetric position with the substrate 20 as a symmetry plane on each of one surface and the other surface of the substrate 20.

また、基板２０はカードホルダ３０とカードホルダ３１とに挟み込まれて支持される。カードホルダ３０とカードホルダ３１とはそれぞれ同一形状を有して形成され、カードホルダ３０が有する溝付穴３４にカードホルダ３１が有する突起部３６が嵌め合うと共に、カードホルダ３１が有する溝付穴３４（図示しない）にカードホルダ３０が有する突起部３６（図示しない）が嵌め合うことにより基板２０を支持する。   The substrate 20 is supported by being sandwiched between a card holder 30 and a card holder 31. The card holder 30 and the card holder 31 are formed to have the same shape, and the protruding portion 36 of the card holder 31 is fitted into the grooved hole 34 of the card holder 30 and the grooved hole of the card holder 31 is fitted. The board | substrate 20 is supported by the projection part 36 (not shown) which the card holder 30 has fitting to 34 (not shown).

また、板ばね等から構成される弾性部材３２は、複数の放射線検出器１を支持する放射線検出器立てに放射線検出器１が挿入された場合に、放射線検出器１を放射線検出器立てに押し付ける。なお、放射線検出器立てはカードエッジ部２９が挿入されるコネクタを有しており、放射線検出器１は、カードエッジ部２９がコネクタに挿入され、コネクタとパターン２９ａとが電気的に接続することにより外部の電気回路としての制御回路、外部からの電源線、グランド線等に電気的に接続される。   Further, the elastic member 32 constituted by a leaf spring or the like presses the radiation detector 1 against the radiation detector stand when the radiation detector 1 is inserted into the radiation detector stand that supports the plurality of radiation detectors 1. . The radiation detector stand has a connector into which the card edge portion 29 is inserted. In the radiation detector 1, the card edge portion 29 is inserted into the connector, and the connector and the pattern 29a are electrically connected. Thus, the circuit is electrically connected to a control circuit as an external electric circuit, an external power supply line, a ground line, and the like.

なお、放射線検出器１は、一対の半導体素子１０の基板２０の反対側に、各半導体素子１０の電極パターンと基板２０に設けられている複数の基板端子２２とのそれぞれを電気的に接続する配線パターンを有するフレキシブル基板を更に備えることができる（なお、半導体素子１０の電極パターン、フレキシブル基板、フレキシブル基板の配線パターンは図示しない）。フレキシブル基板は、一対の半導体素子１０の一方の半導体素子１０側、及び他方の半導体素子１０側の双方に設けることができる。例えば、４組の一対の半導体素子１０の一方の半導体素子１０側のそれぞれと、他方の半導体素子１０側のそれぞれとの双方に、フレキシブル基板をそれぞれ設けることができる。   The radiation detector 1 electrically connects the electrode pattern of each semiconductor element 10 and the plurality of substrate terminals 22 provided on the substrate 20 to the opposite side of the substrate 20 of the pair of semiconductor elements 10. A flexible substrate having a wiring pattern can be further provided (note that the electrode pattern of the semiconductor element 10, the flexible substrate, and the wiring pattern of the flexible substrate are not shown). The flexible substrate can be provided on both the one semiconductor element 10 side and the other semiconductor element 10 side of the pair of semiconductor elements 10. For example, a flexible substrate can be provided on each of one semiconductor element 10 side of each of the four pairs of semiconductor elements 10 and each of the other semiconductor element 10 side.

（基板２０の詳細）
基板２０は、金属導体等の導電性材料からなる導電性薄膜（例えば、銅箔）が表面に形成された薄肉基板（例えば、ＦＲ４等のガラスエポキシ基板）を、ソルダーレジスト等の絶縁材料からなる絶縁層で挟んで可撓性を有して形成される。また、基板２０は、半導体素子１０の電極パターンに電気的に接続する配線パターン２００を有する。配線パターン２００の表面の一部の領域には導電性を有する第１接続部材としての銀ペースト５０が設けられ、半導体素子１０の電極パターンは銀ペースト５０を介して配線パターン２００に電気的に接続する。 (Details of substrate 20)
The substrate 20 is a thin substrate (for example, a glass epoxy substrate such as FR4) on which a conductive thin film (for example, copper foil) made of a conductive material such as a metal conductor is formed, and is made of an insulating material such as a solder resist. It is formed with flexibility by being sandwiched between insulating layers. The substrate 20 has a wiring pattern 200 that is electrically connected to the electrode pattern of the semiconductor element 10. A silver paste 50 as a conductive first connection member is provided in a partial region of the surface of the wiring pattern 200, and the electrode pattern of the semiconductor element 10 is electrically connected to the wiring pattern 200 through the silver paste 50. To do.

また、半導体素子１０の電極パターンに電気的に接続する基板２０の配線パターンは、カードエッジ部２９のパターン２９ａに電気的に接続するように形成される。また、基板２０は、基板端子２２とカードエッジ部２９のパターン２９ａとを電気的に接続する配線パターンを有する。これにより、基板２０において、半導体素子１０の基板２０側の面の電極は、基板２０の配線パターンによりカードエッジ部２９のパターン２９ａに電気的に接続される。また、半導体素子１０の基板２０側の反対側の面の電極は、フレキシブル基板の配線パターンと、基板端子２２と、基板２０の配線パターンとを経由してカードエッジ部２９のパターン２９ａに電気的に接続される。ここで、例えば、半導体素子１０の基板２０側の電極をアノード電極とし、半導体素子１０の基板２０側の反対側の面の電極をカソード電極とする。この場合、アノード電極からの信号とカソード電極からの信号とはそれぞれ、カードエッジ部２９のパターン２９ａに導かれ、パターン２９ａを介して外部の電気回路へ出力される。   In addition, the wiring pattern of the substrate 20 that is electrically connected to the electrode pattern of the semiconductor element 10 is formed so as to be electrically connected to the pattern 29 a of the card edge portion 29. The substrate 20 has a wiring pattern that electrically connects the substrate terminal 22 and the pattern 29 a of the card edge portion 29. Thereby, in the substrate 20, the electrode on the surface of the semiconductor element 10 on the substrate 20 side is electrically connected to the pattern 29 a of the card edge portion 29 by the wiring pattern of the substrate 20. Further, the electrode on the surface opposite to the substrate 20 side of the semiconductor element 10 is electrically connected to the pattern 29a of the card edge portion 29 via the wiring pattern of the flexible substrate, the substrate terminal 22, and the wiring pattern of the substrate 20. Connected to. Here, for example, an electrode on the substrate 20 side of the semiconductor element 10 is an anode electrode, and an electrode on the opposite side of the substrate 20 side of the semiconductor element 10 is a cathode electrode. In this case, the signal from the anode electrode and the signal from the cathode electrode are respectively guided to the pattern 29a of the card edge portion 29 and output to an external electric circuit via the pattern 29a.

なお、基板２０は、一例として、幅広の方向、すなわち長手方向は４０ｍｍ程度の長さを有して形成される。そして、基板２０は、幅広の部分の端部から幅が狭くなっている部分の端部までの短手方向において、２０ｍｍ程度の長さを有して形成される。また、銀ペースト５０の代わりに低温で溶融するはんだを用いることもできる。更に、基板２０は放射線を検出することができない領域であるので、一対の半導体素子１０によって挟まれる基板２０の厚さ分の領域は不感領域となる。したがって、基板２０の厚さは薄いことが好ましい。基板２０は、０．４ｍｍ以下の厚さであることが好ましい。本実施の形態では、一例として、０．２ｍｍの厚さを有して形成される。なお、基板２０の厚さの下限は特に限定されないが、製造可能性の観点から、基板２０としてフレキシブル基板を用いることにより０．０４ｍｍまで薄くすることができる。   As an example, the substrate 20 is formed to have a length of about 40 mm in the wide direction, that is, the longitudinal direction. The substrate 20 is formed to have a length of about 20 mm in the short direction from the end of the wide portion to the end of the narrow portion. Further, instead of the silver paste 50, a solder that melts at a low temperature can be used. Furthermore, since the substrate 20 is a region where radiation cannot be detected, a region corresponding to the thickness of the substrate 20 sandwiched between the pair of semiconductor elements 10 is a dead region. Therefore, the thickness of the substrate 20 is preferably thin. The substrate 20 preferably has a thickness of 0.4 mm or less. In the present embodiment, as an example, it is formed with a thickness of 0.2 mm. In addition, although the minimum of the thickness of the board | substrate 20 is not specifically limited, From a viewpoint of manufacturability, it can be made thin to 0.04 mm by using a flexible substrate as the board | substrate 20. FIG.

（半導体素子１０の詳細）
半導体素子１０は、略直方体状に形成され（つまり、平面視にて略四角状に形成され）、素子表面１０ｂと、素子表面１０ｂの反対側の面である素子表面１０ｃとのそれぞれに電極パターンが設けられる（図示しない）。放射線は各半導体素子１０の端部から入射して、カードエッジ部２９側に向かって半導体素子１０中を走行する。また、本実施の形態に係る半導体素子１０は、放射線が入射する面に垂直な一の面である素子表面１０ｃに複数の溝１０ａが設けられる。溝１０ａの幅は、一例として、０．２ｍｍである。なお、一例として、半導体素子１０の素子表面１０ｂの電極パターンをアノード電極、半導体素子１０の素子表面１０ｃの電極パターンをカソード電極とする。この場合、一例として、半導体素子１０のカソード電極に負の高電圧（例えば、−３００〜−８００Ｖ）を印加する。 (Details of semiconductor element 10)
The semiconductor element 10 is formed in a substantially rectangular parallelepiped shape (that is, formed in a substantially square shape in plan view), and an electrode pattern is formed on each of the element surface 10b and the element surface 10c that is a surface opposite to the element surface 10b. Is provided (not shown). Radiation enters from the end of each semiconductor element 10 and travels through the semiconductor element 10 toward the card edge portion 29 side. In addition, the semiconductor element 10 according to the present embodiment is provided with a plurality of grooves 10a on the element surface 10c, which is one surface perpendicular to the surface on which the radiation is incident. As an example, the width of the groove 10a is 0.2 mm. As an example, an electrode pattern on the element surface 10b of the semiconductor element 10 is an anode electrode, and an electrode pattern on the element surface 10c of the semiconductor element 10 is a cathode electrode. In this case, as an example, a negative high voltage (for example, −300 to −800 V) is applied to the cathode electrode of the semiconductor element 10.

そして、放射線が入射する半導体素子１０の面であって、各溝１０ａから、溝１０ａが設けられている面の反対側の面（つまり、素子表面１０ｃ）への仮想的な垂線により区切られる領域、及び当該仮想的な垂線と半導体素子１０の端部とで区切られる領域を、素子内ピクセル領域と称する。半導体素子１０が、（ｎ−１）個の溝１０ａを有すると共に、複数の溝１０ａ間、及び素子表面１０ｃにそれぞれ電極を有することにより、ｎ個の素子内ピクセル領域が構成される。複数の素子内ピクセル領域のそれぞれが、放射線を検出する１つの画素（ピクセル）に対応する。これにより、一の半導体素子１０は、複数の画素を有することになる。   And the area | region of the semiconductor element 10 into which radiation injects, Comprising: The area | region divided by the virtual perpendicular | vertical from each groove | channel 10a to the surface (namely, element surface 10c) on the opposite side to the surface in which the groove | channel 10a is provided. , And a region divided by the virtual perpendicular and the end of the semiconductor element 10 is referred to as an in-element pixel region. The semiconductor element 10 has (n−1) grooves 10a, and electrodes are provided between the plurality of grooves 10a and on the element surface 10c, so that n element pixel regions are formed. Each of the plurality of in-element pixel regions corresponds to one picture element (pixel) that detects radiation. Thereby, one semiconductor element 10 has a plurality of pixels.

一例として、１つの放射線検出器１が８つの半導体素子１０（４組の一対の半導体素子１０）を備え、１つの半導体素子１０がそれぞれ８つの素子内ピクセル領域を有する場合、１つの放射線検出器１は、６４ピクセルの解像度を有することになる。溝１０ａの数を増減させることにより、一の半導体素子１０のピクセル数を増減させることができる。なお、一例として、半導体素子１０の幅は１．２ｍｍ程度、長さは１１．２ｍｍ程度、高さは５ｍｍ程度である。   As an example, when one radiation detector 1 includes eight semiconductor elements 10 (four pairs of semiconductor elements 10) and one semiconductor element 10 has eight in-element pixel regions, one radiation detector. 1 will have a resolution of 64 pixels. By increasing or decreasing the number of grooves 10a, the number of pixels of one semiconductor element 10 can be increased or decreased. As an example, the width of the semiconductor element 10 is about 1.2 mm, the length is about 11.2 mm, and the height is about 5 mm.

半導体素子１０を構成する材料としては、ＣｄＴｅを用いることができる。また、γ線等の放射線を検出できる限り、半導体素子１０はＣｄＴｅ素子に限られない。例えば、半導体素子１０として、ＣｄＺｎＴｅ（ＣＺＴ）素子、ＨｇＩ２素子等の化合物半導体素子を用いることもできる。 As a material constituting the semiconductor element 10, CdTe can be used. Further, the semiconductor element 10 is not limited to a CdTe element as long as radiation such as γ rays can be detected. For example, a compound semiconductor element such as a CdZnTe (CZT) element or an HgI 2 element can also be used as the semiconductor element 10.

ここで、図２に示すように半導体素子１０は、半導体素子１０と基板２０との間に部分的に設けられ、半導体素子１０を基板２０に仮に固定させる複数の第２接続部材としてのＵＶ硬化樹脂４０を備える。具体的に、ＵＶ硬化樹脂４０は、半導体素子１０の四隅近傍のそれぞれに位置し、半導体素子１０と基板２０とを仮に固定している。本実施形態において「仮に固定」とは、半導体素子１０がＡｇペースト５０を介して基板２０に固定されており、ＵＶ硬化樹脂４０は、後述する放射線検出器１の製造工程において半導体素子１０を基板２０に一時的に固定することを目的として用いられていることを意味する。また、「四隅近傍」とは、基板２０の四隅から予め定められた距離だけ離れた位置であることを含む。なお、ＵＶ硬化樹脂４０の代わりにゴム又は粘土を用いることもできる。   Here, as shown in FIG. 2, the semiconductor element 10 is partially provided between the semiconductor element 10 and the substrate 20, and is UV cured as a plurality of second connection members that temporarily fix the semiconductor element 10 to the substrate 20. A resin 40 is provided. Specifically, the UV curable resin 40 is located near each of the four corners of the semiconductor element 10, and temporarily fixes the semiconductor element 10 and the substrate 20. In this embodiment, “temporarily fixed” means that the semiconductor element 10 is fixed to the substrate 20 via the Ag paste 50, and the UV curable resin 40 is used for the substrate of the semiconductor element 10 in the manufacturing process of the radiation detector 1 described later. It is used for the purpose of temporarily fixing to 20. Further, “near the four corners” includes a position that is separated from the four corners of the substrate 20 by a predetermined distance. In place of the UV curable resin 40, rubber or clay may be used.

なお、第２接続部材は、第１接続部材の接着力より弱い接着力を有することが好ましい。これにより、第１接続部材と第２接続部材の熱膨張差によって発生する応力によって第１接続部材の接着箇所にクラックが生じることを抑制できる。また、第２接続部材としてのＵＶ硬化樹脂は、紫外線を照射することにより短時間で硬化させることができるという利点と、基板２０に反りを発生させるような熱を加えることなく硬化させることができる利点とを有する。   In addition, it is preferable that a 2nd connection member has an adhesive force weaker than the adhesive force of a 1st connection member. Thereby, it can suppress that a crack generate | occur | produces in the adhesion location of a 1st connection member by the stress which generate | occur | produces by the thermal expansion difference of a 1st connection member and a 2nd connection member. Further, the UV curable resin as the second connecting member can be cured without applying heat that causes the substrate 20 to warp and the advantage that it can be cured in a short time by irradiating ultraviolet rays. With advantages.

（放射線検出器１の製造方法）
図３Ａ及び図３Ｂは、本発明の第１の実施の形態に係る放射線検出器の製造工程の一部を模式的に示す。 (Manufacturing method of radiation detector 1)
3A and 3B schematically show a part of the manufacturing process of the radiation detector according to the first exemplary embodiment of the present invention.

まず、表面及び裏面のそれぞれに複数の配線パターン２００と、複数の配線パターン２００それぞれの表面の一部の領域に設けられるＡｇペースト５０とを有する基板２０を準備する（図３Ａの（ａ）、基板準備工程）。なお、Ａｇペースト５０は、例えば、メタルマスク塗布、又はディスペンサ塗布により配線パターン２００の表面の一部の領域に塗布することができる。   First, a substrate 20 having a plurality of wiring patterns 200 on each of the front and back surfaces and an Ag paste 50 provided in a partial region of each surface of the plurality of wiring patterns 200 is prepared ((a) in FIG. 3A). Substrate preparation step). Note that the Ag paste 50 can be applied to a partial region of the surface of the wiring pattern 200 by, for example, metal mask application or dispenser application.

次に、Ａｇペースト５０の接着力より弱い接着力を有するＵＶ硬化樹脂４０を、基板２０上の複数個所に部分的に塗布する（図３Ａの（ｂ）、塗布工程）。例えば、基板２０の表面及び裏面それぞれの半導体素子１０が固定されるべき領域であって、半導体素子１０の四隅近傍に対応する位置にＵＶ硬化樹脂４０を塗布する。ＵＶ硬化樹脂４０の塗布は、ディスペンサ塗布により実施することができる。   Next, the UV curable resin 40 having an adhesive strength weaker than that of the Ag paste 50 is partially applied to a plurality of locations on the substrate 20 (FIG. 3A (b), application step). For example, the UV curable resin 40 is applied to the regions corresponding to the vicinity of the four corners of the semiconductor element 10 in the regions where the semiconductor elements 10 on the front surface and the back surface of the substrate 20 should be fixed. The application of the UV curable resin 40 can be performed by dispenser application.

続いて、ＵＶ硬化樹脂４０を介して半導体素子１０を基板２０上に配置すると共にＵＶ硬化樹脂４０を硬化させる（図３Ｂの（ｃ）、仮固定工程）。   Subsequently, the semiconductor element 10 is placed on the substrate 20 via the UV curable resin 40 and the UV curable resin 40 is cured ((c) in FIG. 3B, temporary fixing step).

具体的に、第１の実施の形態では、基板２０の表面側及び裏面側のそれぞれに一対の半導体素子１０を対称に配置する。例えば、半導体素子１０の基板２０への配置は、自動マウント装置を用いて実施できる。まず、自動マウント装置が備えるコレット６０で半導体素子１０を吸着する。そして、コレット６０は、吸着した半導体素子１０を基板２０上の予め定められた位置に配置し、一定の力（例えば、５０〜１００ｇ）で半導体素子１０を基板２０側へ押しつける。第１の実施の形態では、基板２０を挟んで対称の位置において、一方のコレット６０が吸着している半導体素子１０と、他方のコレット６０が吸着している半導体素子１０とが基板２０に略同時に押しつけられる。これにより、一対の半導体素子１０が基板２０の表面及び裏面の予め定められた位置に配置される。   Specifically, in the first embodiment, a pair of semiconductor elements 10 are arranged symmetrically on the front surface side and the back surface side of the substrate 20. For example, the semiconductor element 10 can be arranged on the substrate 20 using an automatic mounting apparatus. First, the semiconductor element 10 is adsorbed by the collet 60 provided in the automatic mounting apparatus. And the collet 60 arrange | positions the adsorbed semiconductor element 10 in the predetermined position on the board | substrate 20, and presses the semiconductor element 10 to the board | substrate 20 side with fixed force (for example, 50-100g). In the first embodiment, the semiconductor element 10 on which one collet 60 is adsorbed and the semiconductor element 10 on which the other collet 60 is adsorbed are substantially on the substrate 20 at symmetrical positions with the substrate 20 in between. Pressed at the same time. Thereby, the pair of semiconductor elements 10 are arranged at predetermined positions on the front surface and the back surface of the substrate 20.

そして、半導体素子１０と基板２０とに挟まれた複数のＵＶ硬化樹脂４０それぞれに紫外線を照射することによりＵＶ硬化樹脂４０を硬化させ、一対の半導体素子１０のそれぞれを基板２０に一時的に固定する。続いて、固定した一対の半導体素子１０の隣に、新たに一対の半導体素子１０を配置すると共に一時的に基板２０に固定する（図３Ｂの（ｄ））。なお、基板２０の表面側及び裏面側のそれぞれに複数対の半導体素子１０を配置し、複数対の半導体素子１０を基板２０の対称の位置に実質的に同時に、かつ、一時的に固定することもできる。   Then, the UV curable resin 40 is cured by irradiating each of the plurality of UV curable resins 40 sandwiched between the semiconductor element 10 and the substrate 20, and each of the pair of semiconductor elements 10 is temporarily fixed to the substrate 20. To do. Subsequently, a pair of semiconductor elements 10 is newly arranged next to the fixed pair of semiconductor elements 10 and temporarily fixed to the substrate 20 ((d) in FIG. 3B). In addition, a plurality of pairs of semiconductor elements 10 are arranged on each of the front surface side and the back surface side of the substrate 20, and the plurality of pairs of semiconductor elements 10 are fixed to the symmetrical position of the substrate 20 substantially simultaneously and temporarily. You can also.

次に、Ａｇペースト５０を硬化させ、配線パターン２００と半導体素子１０とを電気的に接続させる（硬化工程）。硬化工程は、例えば、高温槽内においてＡｇペースト５０を加熱することにより実施する。一例として、７５℃、２〜３．５時間程度の加熱により硬化するＡｇペースト５０を用いることができる。硬化工程後、フレキシブル基板、カードホルダ３０及びカードホルダ３１、弾性部材３２等を複数の半導体素子１０及び基板２０の定められた位置に取り付ける（組み立て工程）。これにより、第１の実施の形態に係る放射線検出器１が製造される。   Next, the Ag paste 50 is cured, and the wiring pattern 200 and the semiconductor element 10 are electrically connected (curing process). The curing step is performed, for example, by heating the Ag paste 50 in a high temperature bath. As an example, an Ag paste 50 that is cured by heating at 75 ° C. for about 2 to 3.5 hours can be used. After the curing process, the flexible substrate, the card holder 30, the card holder 31, the elastic member 32, and the like are attached to the predetermined positions of the plurality of semiconductor elements 10 and the substrate 20 (assembly process). Thereby, the radiation detector 1 which concerns on 1st Embodiment is manufactured.

（第１の実施の形態の効果）
本発明の第１の実施の形態に係る放射線検出器１の製造方法は、基板２０への半導体素子１０の固定において、まずＵＶ硬化樹脂４０で半導体素子１０を基板２０に仮に固定するので、硬化工程で基板２０に発生しうる反りをＡｇペースト５０が硬化するまで抑制することができる。また、ＵＶ硬化樹脂４０は、半導体素子１０の四隅近傍に設けられるので、基板２０に対する半導体素子１０の傾きを抑制することができる。これにより、第１の実施の形態に係る放射線検出器１の製造方法においては、半導体素子１０の電極パターンと基板２０の配線パターンとの電気的な断線を抑制でき、歩留りを向上させることができる。 (Effects of the first embodiment)
In the method of manufacturing the radiation detector 1 according to the first exemplary embodiment of the present invention, in fixing the semiconductor element 10 to the substrate 20, first, the semiconductor element 10 is temporarily fixed to the substrate 20 with the UV curable resin 40. Warpage that may occur in the substrate 20 in the process can be suppressed until the Ag paste 50 is cured. Moreover, since the UV curable resin 40 is provided in the vicinity of the four corners of the semiconductor element 10, the inclination of the semiconductor element 10 with respect to the substrate 20 can be suppressed. Thereby, in the manufacturing method of the radiation detector 1 which concerns on 1st Embodiment, the electrical disconnection with the electrode pattern of the semiconductor element 10 and the wiring pattern of the board | substrate 20 can be suppressed, and a yield can be improved. .

また、第１の実施の形態においては、基板２０を挟み、基板２０の対称な位置で一対の半導体素子１０を基板２０の上下方向から押さえつけるので、基板２０に反りが存在している場合であっても、基板２０を平坦にすることができる。したがって、基板２０の反りを抑制することができるので、Ａｇペースト５０が硬化した後のＡｇペースト５０の厚さのばらつきを低減できる。これにより、半導体素子１０内に発生する応力分布差を低減できる。   Further, in the first embodiment, the pair of semiconductor elements 10 are pressed from the vertical direction of the substrate 20 at the symmetrical position of the substrate 20 with the substrate 20 interposed therebetween, and thus the substrate 20 is warped. However, the substrate 20 can be flattened. Therefore, since the curvature of the board | substrate 20 can be suppressed, the dispersion | variation in the thickness of the Ag paste 50 after the Ag paste 50 hardens | cures can be reduced. Thereby, the stress distribution difference generated in the semiconductor element 10 can be reduced.

また、本実施の形態においては、第２接続部材として、熱により硬化する接着剤を用いることができる。一対の半導体素子１０を基板２０の上下方向から押さえつけているため、第２接続部材を硬化する際に熱を加えても、基板２０の熱による反りを抑制できるからである。ただし、第２接続部材を硬化させる温度は、第１接続部材が硬化する温度よりも低くする。   Moreover, in this Embodiment, the adhesive agent hardened | cured with a heat | fever can be used as a 2nd connection member. This is because the pair of semiconductor elements 10 are pressed from above and below the substrate 20, so that even when heat is applied when the second connection member is cured, warpage due to heat of the substrate 20 can be suppressed. However, the temperature at which the second connecting member is cured is lower than the temperature at which the first connecting member is cured.

また、自動マウント装置を用いる場合、±０．０２ｍｍの位置精度で半導体素子１０を基板２０に配置することができる。これにより、高精度で半導体素子１０を基板２０に配置することができると共に、配置スピードを向上させることができる   Further, when the automatic mounting apparatus is used, the semiconductor element 10 can be arranged on the substrate 20 with a positional accuracy of ± 0.02 mm. Thereby, the semiconductor element 10 can be arranged on the substrate 20 with high accuracy, and the arrangement speed can be improved.

更に、Ａｇペースト５０が硬化するまでの間、ＵＶ硬化樹脂４０が半導体素子１０を基板２０に一時的に固定する仮固定部材として機能するので、半導体素子１０を基板２０の予め定められた位置に一時的に保持することができる。これにより、複数の半導体素子１０のそれぞれを基板２０の予め定められた位置に配置する複雑な冶具を要さないので、放射線検出器１の量産コストを低減できる。   Furthermore, until the Ag paste 50 is cured, the UV curable resin 40 functions as a temporary fixing member that temporarily fixes the semiconductor element 10 to the substrate 20, so that the semiconductor element 10 is placed at a predetermined position on the substrate 20. Can be held temporarily. Thereby, since the complicated jig which arrange | positions each of the several semiconductor element 10 in the predetermined position of the board | substrate 20 is not required, the mass production cost of the radiation detector 1 can be reduced.

また、ＵＶ硬化樹脂４０を短時間で硬化させることができるので、仮固定工程後の工程（例えば、硬化工程）において基板２０の反りに起因する半導体素子１０の基板２０の予め定められた位置からの位置ずれを抑制できる。更に、ＵＶ硬化樹脂４０としてＡｇペースト５０と同程度のヤング率（２０〜２００ＭＰａ）のＵＶ硬化樹脂４０を用いることにより、線膨張差によって半導体素子１０内に発生する応力を緩和することができる。   In addition, since the UV curable resin 40 can be cured in a short time, from a predetermined position of the substrate 20 of the semiconductor element 10 due to warpage of the substrate 20 in a process after the temporary fixing process (for example, a curing process). Can be suppressed. Furthermore, by using a UV curable resin 40 having a Young's modulus (20 to 200 MPa) similar to that of the Ag paste 50 as the UV curable resin 40, it is possible to relieve stress generated in the semiconductor element 10 due to a difference in linear expansion.

また、本実施の形態は、厚さが薄く、撓みやすく、反りが発生しやすい基板を用いる場合に、特に有効である。薄い基板、好ましくは０．４ｍｍ以下の厚さを有する薄い基板を用いることにより、不感領域を低減できる。   In addition, this embodiment is particularly effective when using a substrate that is thin, easily bent, and easily warps. By using a thin substrate, preferably a thin substrate having a thickness of 0.4 mm or less, the dead area can be reduced.

［第２の実施の形態］
図４Ａ及び図４Ｂは、本発明の第２の実施の形態に係る放射線検出器の製造工程の一部の模式的に示す。 [Second Embodiment]
4A and 4B schematically show a part of the manufacturing process of the radiation detector according to the second exemplary embodiment of the present invention.

第２の実施の形態に係る放射線検出器の製造方法は、第１の実施の形態に係る放射線検出器１の製造方法とは一部異なる点を除き、第１の実施の形態に係る放射線検出器１と略同一の製造方法である。したがって、相違点を除き詳細な説明は省略する。   The method for manufacturing a radiation detector according to the second embodiment is different from the method for manufacturing the radiation detector 1 according to the first embodiment, except that the radiation detection according to the first embodiment is performed. The manufacturing method is substantially the same as that of the container 1. Therefore, a detailed description is omitted except for differences.

まず、第１の実施の形態と同様に、基板準備工程、塗布工程を経ることにより、基板２０の表面及び裏面のそれぞれに複数の配線パターン２００が形成され、複数の配線パターン２００それぞれの表面の一部にＡｇペースト５０が設けられ、更に予め定められた位置にＵＶ硬化樹脂４０が設けられた基板２０を作製する。そして、第１の実施の形態と同様に、ＵＶ硬化樹脂４０を介して半導体素子１０を基板２０上に配置すると共にＵＶ硬化樹脂４０を硬化させる（図４Ａの（ａ））。   First, similarly to the first embodiment, a plurality of wiring patterns 200 are formed on each of the front surface and the back surface of the substrate 20 by performing a substrate preparation process and a coating process. A substrate 20 in which an Ag paste 50 is provided in part and the UV curable resin 40 is provided in a predetermined position is manufactured. Then, as in the first embodiment, the semiconductor element 10 is disposed on the substrate 20 via the UV curable resin 40 and the UV curable resin 40 is cured (FIG. 4A (a)).

具体的に、第２の実施の形態においては、基板２０の表面又は裏面のいずれか一方に半導体素子１０を配置し、一時的に固定する。例えば、基板２０の表面側に半導体素子１０を一つずつ配置し、配置された半導体素子１０と基板２０とに挟まれたＵＶ硬化樹脂４０にＵＶ光を照射して当該半導体素子１０を一時的に固定する。そして、まず基板２０の表面側だけに複数の半導体素子１０を一時的に固定する（図４Ａの（ｂ））。   Specifically, in the second embodiment, the semiconductor element 10 is disposed on either the front surface or the back surface of the substrate 20 and temporarily fixed. For example, the semiconductor elements 10 are arranged one by one on the surface side of the substrate 20, and the UV curable resin 40 sandwiched between the arranged semiconductor elements 10 and the substrate 20 is irradiated with UV light to temporarily dispose the semiconductor elements 10. Secure to. First, a plurality of semiconductor elements 10 are temporarily fixed only on the surface side of the substrate 20 ((b) in FIG. 4A).

次に、基板２０の一方の面（例えば、表面）へ複数の半導体素子１０を一時的に固定した後、基板２０の他方の面（例えば、裏面）に半導体素子１０を配置し、一時的に固定する。例えば、基板２０の裏面側に半導体素子１０を一つずつ配置し、配置された半導体素子１０と基板２０とに挟まれたＵＶ硬化樹脂４０にＵＶ光を照射して当該半導体素子１０を一時的に固定する（図４Ｂの（ｃ））。そして、基板２０の裏面側に複数の半導体素子１０を一時的に固定する（図４Ｂの（ｄ））。   Next, after temporarily fixing the plurality of semiconductor elements 10 to one surface (for example, the front surface) of the substrate 20, the semiconductor element 10 is disposed on the other surface (for example, the back surface) of the substrate 20, and temporarily Fix it. For example, the semiconductor elements 10 are arranged one by one on the back side of the substrate 20, and the UV curable resin 40 sandwiched between the arranged semiconductor elements 10 and the substrate 20 is irradiated with UV light to temporarily dispose the semiconductor elements 10. (Fig. 4B (c)). Then, the plurality of semiconductor elements 10 are temporarily fixed to the back side of the substrate 20 ((d) in FIG. 4B).

次に、硬化工程及び組み立て工程を経て、第２の実施の形態に係る放射線検出器１が製造される。   Next, the radiation detector 1 according to the second embodiment is manufactured through a curing process and an assembly process.

本実施の形態においては、基板２０に反りが発生しないように、仮固定工程で熱を加えないことが好ましい。例えば、第２接続部材としては、ＵＶ硬化樹脂の他に、常温（２０℃〜４０℃）で硬化する接着剤を用いることができる。   In the present embodiment, it is preferable not to apply heat in the temporary fixing step so that the substrate 20 is not warped. For example, as the second connection member, an adhesive that cures at room temperature (20 ° C. to 40 ° C.) can be used in addition to the UV curable resin.

［第３の実施の形態］
図５は、本発明の第３の実施の形態に係る放射線検出器の製造工程の一部を模式的に示す。 [Third Embodiment]
FIG. 5 schematically shows a part of the manufacturing process of the radiation detector according to the third exemplary embodiment of the present invention.

第３の実施の形態に係る放射線検出器の製造方法は、第１の実施の形態に係る放射線検出器１の製造方法とは一部異なる点を除き、第１の実施の形態に係る放射線検出器１と略同一の製造方法である。したがって、相違点を除き詳細な説明は省略する。   The method for manufacturing a radiation detector according to the third embodiment is different from the method for manufacturing the radiation detector 1 according to the first embodiment, except that the radiation detection according to the first embodiment is performed. The manufacturing method is substantially the same as that of the container 1. Therefore, a detailed description is omitted except for differences.

まず、第１の実施の形態と同様に、基板準備工程、塗布工程を経ることにより、基板２０の表面及び裏面のそれぞれに複数の配線パターン２００が形成され、複数の配線パターン２００それぞれの表面の一部にＡｇペースト５０が設けられ、更に予め定められた位置にＵＶ硬化樹脂４０が設けられた基板２０を作製する。そして、第１の実施の形態と同様に、ＵＶ硬化樹脂４０を介して半導体素子１０を基板２０上に配置すると共にＵＶ硬化樹脂４０を硬化させる。   First, similarly to the first embodiment, a plurality of wiring patterns 200 are formed on each of the front surface and the back surface of the substrate 20 by performing a substrate preparation process and a coating process. A substrate 20 in which an Ag paste 50 is provided in part and the UV curable resin 40 is provided in a predetermined position is manufactured. Then, as in the first embodiment, the semiconductor element 10 is disposed on the substrate 20 via the UV curable resin 40 and the UV curable resin 40 is cured.

具体的に、第３の実施の形態においては、基板２０の表面又は裏面のいずれか一方に複数の半導体素子１０を配置し、一時的に固定する。例えば、基板２０の表面側であって、半導体素子１０を搭載すべき部分の全てのそれぞれに半導体素子１０を配置し、配置された半導体素子１０と基板２０とに挟まれたＵＶ硬化樹脂４０にＵＶ光を照射して複数の半導体素子１０それぞれを一時的に固定する（図５の（ａ））。   Specifically, in the third embodiment, a plurality of semiconductor elements 10 are arranged on either the front surface or the back surface of the substrate 20 and temporarily fixed. For example, the semiconductor element 10 is disposed on each of the portions on the surface side of the substrate 20 where the semiconductor element 10 is to be mounted, and the UV curable resin 40 sandwiched between the disposed semiconductor element 10 and the substrate 20 is provided. UV light is irradiated to temporarily fix each of the plurality of semiconductor elements 10 ((a) of FIG. 5).

次に、基板２０の一方の面（例えば、表面）へ複数の半導体素子１０を一時的に固定した後、基板２０の他方の面（例えば、裏面）に半導体素子１０を配置し、一時的に固定する。例えば、基板２０の裏面側であって、半導体素子１０を搭載すべき部分の全てのそれぞれに半導体素子１０を配置し、配置された半導体素子１０と基板２０とに挟まれたＵＶ硬化樹脂４０にＵＶ光を照射して複数の半導体素子１０それぞれを一時的に固定する（図５の（ｂ））。   Next, after temporarily fixing the plurality of semiconductor elements 10 to one surface (for example, the front surface) of the substrate 20, the semiconductor element 10 is disposed on the other surface (for example, the back surface) of the substrate 20, and temporarily Fix it. For example, the semiconductor element 10 is disposed on each of the portions on the back surface side of the substrate 20 where the semiconductor element 10 is to be mounted, and the UV curable resin 40 sandwiched between the disposed semiconductor element 10 and the substrate 20 is provided. UV light is irradiated to temporarily fix each of the plurality of semiconductor elements 10 ((b) of FIG. 5).

次に、硬化工程及び組み立て工程を経て、第３の実施の形態に係る放射線検出器１が製造される。   Next, the radiation detector 1 according to the third embodiment is manufactured through a curing process and an assembly process.

本実施の形態においては、基板２０に反りが発生しないように、仮固定工程で熱を加えないことが好ましい。例えば、第２接続部材としては、ＵＶ硬化樹脂の他に、常温（２０℃〜４０℃）で硬化する接着剤を用いることができる。   In the present embodiment, it is preferable not to apply heat in the temporary fixing step so that the substrate 20 is not warped. For example, as the second connection member, an adhesive that cures at room temperature (20 ° C. to 40 ° C.) can be used in addition to the UV curable resin.

以上、本発明の実施の形態を説明したが、上記に記載した実施の形態は特許請求の範囲に係る発明を限定するものではない。また、実施の形態の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。   While the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

１ 放射線検出器
１０ 半導体素子
１０ａ 溝
１０ｂ 素子表面
１０ｃ 素子表面
２０ 基板
２２ 基板端子
２９ カードエッジ部
２９ａ パターン
３０、３１ カードホルダ
３２ 弾性部材
３４ 溝付穴
３６ 突起部
４０ ＵＶ接着剤
５０ 銀ペースト
６０ コレット
１００ 放射線
２００ 配線パターン DESCRIPTION OF SYMBOLS 1 Radiation detector 10 Semiconductor element 10a Groove 10b Element surface 10c Element surface 20 Substrate 22 Substrate terminal 29 Card edge part 29a Pattern 30, 31 Card holder 32 Elastic member 34 Grooved hole 36 Projection part 40 UV adhesive 50 Silver paste 60 Collet 100 radiation 200 wiring pattern

Claims (9)

配線パターンと、前記配線パターンの表面に設けられる第１接続部材とを有する基板を準備する基板準備工程と、
第２接続部材を前記基板上に部分的に塗布する塗布工程と、
前記第２接続部材を介して放射線を検出可能な半導体素子を前記基板上に配置し、前記第２接続部材を硬化させることにより前記半導体素子を前記基板に一時的に固定する仮固定工程と
を備える放射線検出器の製造方法。 A substrate preparation step of preparing a substrate having a wiring pattern and a first connecting member provided on a surface of the wiring pattern;
A coating step of partially coating the second connecting member on the substrate;
Placing a semiconductor element capable of detecting radiation via the second connecting member on the substrate, and temporarily fixing the semiconductor element to the substrate by curing the second connecting member; A method for manufacturing a radiation detector. 前記仮固定工程の後に、前記第１接続部材を硬化させ、前記配線パターンと前記半導体素子とを電気的に接続させる硬化工程
を更に備える請求項１に記載の放射線検出器の製造方法。 The method of manufacturing a radiation detector according to claim 1, further comprising a curing step of curing the first connection member and electrically connecting the wiring pattern and the semiconductor element after the temporary fixing step. 前記半導体素子が、平面視にて略四角形状を有し、
前記塗布工程が、前記半導体素子の四隅近傍に対応する前記基板上の複数の位置に前記第２接続部材を塗布する請求項２に記載の放射線検出器の製造方法。 The semiconductor element has a substantially square shape in plan view,
The method of manufacturing a radiation detector according to claim 2, wherein the applying step applies the second connection member to a plurality of positions on the substrate corresponding to the vicinity of the four corners of the semiconductor element. 前記第１接続部材が、銀ペースト又は半田であり、
前記第２接続部材が、ＵＶ硬化樹脂であり、
前記仮固定工程が、前記第２接続部材に紫外線を照射することにより前記第２接続部材を硬化させ、
前記硬化工程が、前記第１接続部材を加熱することにより前記第１接続部材を硬化させる請求項３に記載の放射線検出器の製造方法。 The first connecting member is silver paste or solder;
The second connecting member is a UV curable resin;
The temporary fixing step cures the second connecting member by irradiating the second connecting member with ultraviolet rays,
The method of manufacturing a radiation detector according to claim 3, wherein the curing step cures the first connection member by heating the first connection member. 前記基板準備工程が、一方の面及び他方の面のそれぞれに前記配線パターンと前記第１接続部材とを有する前記基板を準備し、
前記塗布工程が、前記一方の面及び前記他方の面のそれぞれの複数個所に部分的に前記第２接続部材を塗布し、
前記仮固定工程が、前記一方の面及び前記他方の面のそれぞれに複数の前記半導体素子を配置し、前記一方の面及び前記他方の面のそれぞれに複数の前記半導体素子それぞれを一時的に固定する請求項１に記載の放射線検出器の製造方法。 The substrate preparation step prepares the substrate having the wiring pattern and the first connection member on each of one surface and the other surface;
The application step, the second connection member is partially applied to each of a plurality of locations on the one surface and the other surface;
In the temporary fixing step, a plurality of the semiconductor elements are arranged on each of the one surface and the other surface, and each of the plurality of semiconductor elements is temporarily fixed on each of the one surface and the other surface. The manufacturing method of the radiation detector of Claim 1 to do. 前記基板準備工程が、一方の面及び他方の面のそれぞれに前記配線パターンと前記第１接続部材とを有する前記基板を準備し、
前記塗布工程が、前記一方の面及び前記他方の面のそれぞれの複数個所に部分的に前記第２接続部材を塗布し、
前記仮固定工程が、前記一方の面に複数の前記半導体素子を配置し、配置した複数の前記半導体素子を一時的に固定した後、前記他方の面に複数の前記半導体素子を配置すると共に、前記他方の面に複数の前記半導体素子を一時的に固定する請求項１に記載の放射線検出器の製造方法。 The substrate preparation step prepares the substrate having the wiring pattern and the first connection member on each of one surface and the other surface;
The application step, the second connection member is partially applied to each of a plurality of locations on the one surface and the other surface;
The temporary fixing step arranges the plurality of semiconductor elements on the one surface, temporarily fixes the plurality of arranged semiconductor elements, and then arranges the plurality of semiconductor elements on the other surface, The method of manufacturing a radiation detector according to claim 1, wherein the plurality of semiconductor elements are temporarily fixed to the other surface. 配線パターンと、前記配線パターンの表面に設けられる第１接続部材とを有する基板と、
前記第１接続部材を介し前記配線パターンに電気的に接続され、放射線を検出可能な半導体素子と、
前記半導体素子と前記基板との間に部分的に設けられ、前記半導体素子を前記基板に接着により固定させる複数の第２接続部材とを備え、
前記第２接続部材が、前記第１接続部材の接着力より弱い接着力を有し、
前記基板が、０．４ｍｍ以下の厚さを有する放射線検出器。 A substrate having a wiring pattern and a first connecting member provided on a surface of the wiring pattern;
A semiconductor element electrically connected to the wiring pattern via the first connection member and capable of detecting radiation;
The semiconductor element and partially disposed between the substrate, e Bei a plurality of second connecting members for fixing by bonding the semiconductor element to the substrate,
The second connecting member has an adhesive force weaker than an adhesive force of the first connecting member;
A radiation detector in which the substrate has a thickness of 0.4 mm or less . 前記半導体素子が、平面視にて略四角状に形成され、
前記第２接続部材が、前記半導体素子の四隅近傍に位置する請求項７に記載の放射線検出器。 The semiconductor element is formed in a substantially square shape in plan view,
The radiation detector according to claim 7, wherein the second connection member is positioned near four corners of the semiconductor element . 前記第１接続部材が、銀ペースト又ははんだであり、
前記第２接続部材が、ＵＶ硬化樹脂である請求項７または８に記載の放射線検出器。 The first connecting member is silver paste or solder;
The radiation detector according to claim 7 or 8, wherein the second connection member is a UV curable resin .
JP2010142387A 2010-06-23 2010-06-23 Radiation detector manufacturing method and radiation detector Expired - Fee Related JP5676155B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010142387A JP5676155B2 (en) 2010-06-23 2010-06-23 Radiation detector manufacturing method and radiation detector
PCT/JP2011/064221 WO2011162282A1 (en) 2010-06-23 2011-06-22 Manufacturing method for radiation detectors, and radiation detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010142387A JP5676155B2 (en) 2010-06-23 2010-06-23 Radiation detector manufacturing method and radiation detector

Publications (2)

Publication Number Publication Date
JP2012007926A JP2012007926A (en) 2012-01-12
JP5676155B2 true JP5676155B2 (en) 2015-02-25

Family

ID=45371459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010142387A Expired - Fee Related JP5676155B2 (en) 2010-06-23 2010-06-23 Radiation detector manufacturing method and radiation detector

Country Status (2)

Country Link
JP (1) JP5676155B2 (en)
WO (1) WO2011162282A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015107724B4 (en) * 2015-04-02 2016-12-01 Heraeus Deutschland GmbH & Co. KG Method for producing a substrate arrangement, substrate arrangement, method for connecting an electronic component to a substrate arrangement and electronic component
EP3276652A3 (en) * 2015-04-02 2018-04-25 Heraeus Deutschland GmbH & Co. KG Method for producing a substrate arrangement with a glue prefixing means, corresponding substrate arrangement, method for connecting an electronic component with a substrate arrangement using a glue prefixing means formed on the electronic component and/or the substrate arrangement and an electronic component bonded with a substrate arrangement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3649907B2 (en) * 1998-01-20 2005-05-18 シャープ株式会社 Two-dimensional image detector and manufacturing method thereof
JP2001091656A (en) * 1999-09-22 2001-04-06 Sharp Corp Two-dimensional image detector
JP2003303946A (en) * 2002-04-12 2003-10-24 Sony Corp Solid-state image pickup device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2012007926A (en) 2012-01-12
WO2011162282A1 (en) 2011-12-29

Similar Documents

Publication Publication Date Title
US9887222B2 (en) Method of manufacturing optical apparatus
US9220172B2 (en) Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus
US9978675B2 (en) Package, electronic component, and electronic apparatus
US8222609B2 (en) Image pickup apparatus, radiation image pickup apparatus, and method for manufacturing same
BR102013010101A2 (en) Electronic component and device
RU2013147397A (en) SPECTRAL IMAGE DETECTOR
KR20180074660A (en) METHOD AND APPARATUS WITH TILE IMAGE SENSOR
KR101369987B1 (en) film type Probe unit for inspecting display panel
US10381314B2 (en) Method of manufacturing mounting member and method of manufacturing electronic component
JP5676155B2 (en) Radiation detector manufacturing method and radiation detector
US5744379A (en) Semiconductor device composed of plural semiconductor chips and coupling means which couple the semiconductor chips together
JP2015084378A (en) Electronic component, electronic apparatus, manufacturing method of mounting member, and manufacturing method of electronic component
JP5610520B2 (en) Radiation detector
JP2010185752A (en) Radiation detector
JP5725747B2 (en) Radiation detector and method for manufacturing radiation detector
TW201333485A (en) Examination method of LED light bar
JP5436880B2 (en) Radiation detector
JP2012138390A (en) Semiconductor device and manufacturing method of the same
RU2726905C1 (en) X-ray detector and method of its manufacturing
JP5320309B2 (en) Probe card
JP2006128713A (en) Solid state imaging device and manufacturing method of solid state imaging device
US8203121B2 (en) Radiation detector stand
JP2010243229A (en) Probe card, and method for manufacturing the same
JP6654116B2 (en) Linear image sensor and method of manufacturing the same
JP2006174492A (en) Solid-state imaging device and manufacturing method therefor

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20111017

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120912

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140128

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140328

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20140609

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140819

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141024

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20141031

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141202

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141225

R150 Certificate of patent or registration of utility model

Ref document number: 5676155

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees