JP5673463B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a lateral high voltage element and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, in an SOI (Silicon on Insulator) substrate in which a semiconductor substrate (drift layer) is formed on a support substrate through a buried insulating film, a semiconductor device in which a lateral high voltage element is formed on the semiconductor substrate is known. . When an SOI substrate is used in this way, a breakdown voltage in the depth direction of the substrate can be secured. On the other hand, with the miniaturization of semiconductor devices and their manufacturing processes for the purpose of power saving and high yield, the distance between the electrodes formed on the surface of the semiconductor substrate is also shortened, and the horizontal breakdown voltage of the substrate is reduced. That is, it has become difficult to ensure the withstand voltage between the electrodes in the lateral device.

  A semiconductor device in which a field plate is formed on the surface of an insulating film between electrodes is known as a means for preventing such a decrease in horizontal breakdown voltage. The field plate exhibits a function of equalizing equipotential lines in the semiconductor substrate between the electrodes. That is, local electric field concentration can be prevented in the semiconductor substrate between the electrodes, and the withstand voltage between the electrodes formed on the surface of the element can be improved.

  Patent Document 1 discloses a semiconductor device having a super junction structure on the surface of a buried insulating film. In this semiconductor device, a ring-shaped P-type region and an N-type region are alternately and repeatedly formed on a surface layer portion adjacent to a buried insulating film in an N-type semiconductor substrate to form a super junction structure. Yes. In this configuration, when one of the support substrate and the electrode is grounded and a high voltage is applied to the other electrode so that a reverse bias is applied between the electrodes, the P-type region is positioned adjacent to the buried insulating film. An inversion layer is generated and a positive charge is induced. On the other hand, no charge is induced because an inversion layer does not occur at a position adjacent to the buried insulating film in the N-type region. For this reason, the ring-shaped P-type and N-type regions function as pseudo field plates. Therefore, the withstand voltage between the electrodes formed on the surface of the element can be improved.

JP 2011-97021 A

  However, in the case where ring-shaped P-type regions and N-type regions are alternately and repeatedly formed, at least two masks and two ion implantations are necessary to divide each region. Further, when the width of the impurity ion implantation region is changed in each region in accordance with the use of the semiconductor device, a predetermined number of masks and ion implantations are required, which increases the number of processes.

  Also, in the thermal diffusion process after the implantation of impurity ions, if the impurities diffuse into the semiconductor substrate and the P-type region is formed above the N-type region, the role as a pseudo field plate may not be expected. There is. Furthermore, this impurity diffusion may affect the characteristics of the device.

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve the breakdown voltage in the horizontal direction while preventing adverse effects due to implantation of impurity ions.

In order to achieve the above object, the invention described in claim 1
A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
The first impurity region formed in the surface layer of the first main surface in the semiconductor substrate and the surface layer of the first main surface formed in a position not overlapping with the first impurity region, and a current between the first impurity region An element having a second impurity region through which
An insulating film formed on a surface including a region between the first impurity region and the second impurity region in the first main surface of the semiconductor substrate;
A field plate formed between a first impurity region and a second impurity region on an insulating film,
The same component and inertness as the semiconductor substrate at least in a region between the first impurity region and the second impurity region at a predetermined depth deeper than the first impurity region and the second impurity region from the first main surface of the semiconductor substrate An amorphous layer containing an element, the amorphous layer is formed by ion implantation of an inert element, functions as a pseudo field plate, and captures a metal impurity present in a semiconductor substrate It is characterized by functioning as

  Thus, in the present invention, the semiconductor substrate has an amorphous layer. This amorphous layer behaves as a high resistance layer having higher electrical resistance than the single crystal state or the polycrystalline state. For this reason, when a potential difference occurs between the first impurity region and the second impurity region, the function of correcting so that equipotential lines between the two regions are as evenly spaced as possible is exhibited. That is, it functions as a pseudo field plate. Therefore, the interval between the equipotential lines in the semiconductor substrate corrected so as to be as evenly spaced as possible by the field plate formed on the surface of the insulating film can be corrected so as to be closer to the equal interval. Thereby, the breakdown voltage in the horizontal direction of the element can be improved.

In addition, the above amorphous layer is configured to include the same components and inert elements as the semiconductor substrate. Such an amorphous layer is formed by ion implantation of an inert element as will be described later. For this reason, the number of processes can be reduced and the influence on the semiconductor device due to the diffusion of the dopant can be suppressed as compared with the case where a plurality of ion species as dopants are ion-implanted to have a pseudo field plate function. You can also.

  Further, this amorphous layer also functions as a gettering layer for metal impurities. For this reason, high quality of elements formed on the surface layer of the semiconductor substrate, for example, a gate insulating film such as a MOS transistor can be expected. In addition, it can also be used as a layer for controlling the lifetime of the element.

  By having the field plate and the amorphous layer, the equipotential lines between the first impurity region and the second impurity region become uniform, while the electric field concentrates directly under the amorphous layer. In order to suppress a decrease in breakdown voltage due to this electric field concentration, as described in claim 2, the semiconductor substrate has an SOI in which the second main surface is supported by the support substrate through a buried insulating film having a predetermined thickness. It is good to have a structure.

  According to this, the buried insulating film having pressure resistance is disposed between the semiconductor substrate having the amorphous layer and the support substrate. Therefore, the withstand voltage in the depth direction between the impurity region formed on the first main surface of the semiconductor substrate and the support substrate can be improved.

  More preferably, as described in claim 3, the amorphous layer is formed adjacent to the buried insulating film.

  With reference to the first main surface of the semiconductor substrate, the electric field in a layer deeper than the amorphous layer is the largest directly under the amorphous layer. For this reason, the structure in which the buried insulating film is adjacent to the amorphous layer can more effectively suppress a decrease in breakdown voltage due to electric field concentration.

  In addition, as described in claim 4, the semiconductor substrate may be a bulk single crystal substrate.

  In this configuration, the amorphous layer is formed by performing ion implantation of an inert element on the semiconductor substrate and functions as a pseudo field plate. Therefore, even when the semiconductor substrate is a bulk single crystal substrate, the horizontal breakdown voltage of the element can be improved.

  In addition, the semiconductor substrate may be an epitaxial substrate formed by epitaxial growth on a bulk single crystal substrate.

  An epitaxial substrate as a semiconductor substrate is superior in crystallinity and purity as compared with a bulk single crystal substrate. In addition, an extremely thin crystal film or a complicated multilayer crystal structure can be manufactured. In this configuration, the amorphous layer is formed by performing ion implantation of an inert element on the semiconductor substrate and functions as a pseudo field plate. Therefore, even when the semiconductor substrate is an epitaxial substrate, the horizontal breakdown voltage of the element can be improved.

  In the structure of Claims 2-5, it can improve the horizontal withstand pressure | voltage of an element by having a field plate and an amorphous layer. Therefore, it is suitable as a power semiconductor device. Therefore, as an element having the first impurity region and the second impurity region, for example, the lateral diode according to claim 6, the lateral insulated gate bipolar transistor according to claim 7, and the lateral type according to claim 8. The MOS transistor can be employed.

  These are suitable as elements constituting an inverter circuit for driving an inductive load such as a motor, for example. Further, the MOS transistor has an amorphous layer as a pseudo field plate in addition to the lateral MOS structure configured to relax the electric field between the drain and the gate. For this reason, for example, it is also suitable as a power amplifier circuit.

A method of manufacturing a semiconductor device having an SOI structure according to claim 2 is as follows.
A step of ion-implanting an inert element from the second main surface side of the semiconductor substrate to form an amorphous layer at a predetermined depth from the first main surface;
Bonding a second main surface of the semiconductor substrate and a support substrate having a buried insulating film on a surface facing the second main surface of the semiconductor substrate via the buried insulating film;
Forming an insulating film on the first main surface so that a part of the first main surface is exposed;
Forming a first impurity region and a second impurity region in a surface layer of the first main surface with a depth not reaching the amorphous layer by ion implantation from the first main surface side using the insulating film as a mask; ,
And a step of forming a field plate on the insulating film between the first impurity region and the second impurity region.

  Since the operational effects of the present invention are the same as the operational effects of the inventions described in claims 1 and 2, the description thereof is omitted.

  By the way, the amorphous layer as the high resistance layer (pseudo field plate) can be substituted with a buried insulating film if the thickness of the semiconductor substrate is reduced. However, in this case, it is necessary to increase the thickness of the buried insulating film in order to ensure the withstand voltage in the depth direction. The buried insulating film can be obtained as an oxide film by heating the support substrate in an oxygen atmosphere. However, in order to increase the thickness of the buried insulating film, the time required for oxidation becomes long, which is not practical.

  In contrast, the method according to claim 9 is to obtain an amorphous layer by ion implantation of an inert element, and does not require long-time heating for forming a buried insulating film. For this reason, according to this method, the time required for manufacturing the semiconductor device can be greatly reduced.

  According to a tenth aspect of the present invention, in the step of forming the amorphous layer, the amorphous layer may be formed on the surface layer of the second main surface of the semiconductor substrate.

  Since the effect of this invention is the same as the effect of the invention of Claim 3, the description is abbreviate | omitted.

On the other hand, the manufacturing method of the semiconductor device according to claim 4 is as described in claim 11.
A step of ion-implanting an inert element from a first main surface side to a bulk single crystal substrate as a semiconductor substrate to form an amorphous layer at a predetermined depth from the first main surface;
Grinding the semiconductor substrate from the second main surface side to a predetermined thickness;
Forming an insulating film on the first main surface so that a part of the first main surface is exposed;
Forming a first impurity region and a second impurity region in a surface layer of the first main surface with a depth not reaching the amorphous layer by ion implantation from the first main surface side using the insulating film as a mask; ,
And a step of forming a field plate on the insulating film between the first impurity region and the second impurity region.

  Since the operational effects of the present invention are the same as the operational effects described in claims 1 and 4, description thereof is omitted.

Further, according to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device as described in the twelfth aspect,
Forming an epitaxial substrate as a semiconductor substrate by epitaxial growth on one surface of a bulk single crystal substrate;
A step of ion-implanting an inert element from the first main surface side of the semiconductor substrate to the formed semiconductor substrate to form an amorphous layer at a predetermined depth from the first main surface;
Forming an insulating film on the first main surface so that a part of the first main surface is exposed;
A step of forming the first impurity region and the second impurity region in a surface layer of the first main surface with a depth not reaching the amorphous layer by ion implantation from the first main surface side using the insulating film as a mask. When,
And a step of forming a field plate on the insulating film between the first impurity region and the second impurity region.

  Since the operational effects of the present invention are the same as the operational effects described in claims 1 and 5, description thereof is omitted.

  In general, an SOI structure is a structure in which a silicon semiconductor layer is provided on a buried insulating film. However, in this specification and the like, a structure in which a semiconductor layer made of a material other than silicon is provided on the buried insulating film is used. It is used as a concept including a substrate. That is, the semiconductor layer included in the SOI substrate is not limited to the silicon semiconductor layer.

  In this specification and the like, a single crystal refers to a crystal in which the direction of the crystal axis is the same in any part of the sample when attention is paid to a certain crystal axis. That is, even if crystal defects, dangling bonds, and the like are included, those having the same crystal axis direction as described above are treated as single crystals. In this specification and the like, amorphous means a solid substance having no three-dimensional long-range order like a single crystal. In the present specification and the like, polycrystal means a solid substance composed of a large number of minute single crystals.

1 is a circuit diagram of a general-purpose inverter according to a first embodiment. 1 is a top view illustrating a schematic configuration of a semiconductor device according to a first embodiment. It is sectional drawing which follows the III-III line of FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment, (a) is a semiconductor substrate preparation process, (b) is an amorphous layer formation process, (c) is a support substrate preparation process, ( d) shows a buried insulating film forming step, (e) shows a bonding step, and (f) shows a grinding or polishing step. 4A and 4B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment, where FIG. 5A illustrates an element isolation process, FIG. 5B illustrates an impurity region formation process, and FIG. It is a simulation result of the equipotential line in a semiconductor substrate, (a) is a non-amorphous condition, (b) is an amorphous layer presence condition. It is sectional drawing which shows a modification. It is a top view which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which follows the IX-IX line of FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment, (a) is a bulk single crystal substrate preparation process, (b) is an amorphous layer formation process, (c) is a grinding or polishing process. Indicates. 9A and 9B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment, where FIG. 5A illustrates a LOCOS oxidation process, FIG. 5B illustrates an impurity region formation process, and FIG. 5C illustrates an electrode and field plate formation process. It is a top view which shows schematic structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which follows the XIII-XIII line | wire of FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment, (a) is a preparation process of a bulk single crystal substrate, (b) is an epitaxial substrate formation process, (c) is an amorphous layer formation process, (D) shows a grinding or polishing step.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same reference numerals are given to the same or equivalent parts. Moreover, the dimension of each site | part in each figure is arbitrary, and is not limited to the dimension shown by each figure.

  The number of turns of the field plate shown in FIGS. 2, 3, 5 to 9, and 11 to 13 is arbitrary, and is not limited to the number of turns shown in each figure.

(First embodiment)
The semiconductor device according to the present embodiment will be described with reference to FIGS. This semiconductor device is characterized in that an element is formed on the surface layer of a semiconductor substrate having an SOI structure and an amorphous layer is formed in the semiconductor substrate. In the present embodiment, as an example of the element, an example in which an insulated gate bipolar transistor (hereinafter referred to as IGBT) and a free-wheeling diode constituting an inverter unit described later is provided.

  A general-purpose inverter circuit 10 shown in FIG. 1 includes a converter unit 11 that rectifies an alternating voltage into a direct current, and an inverter unit 12 that converts the direct voltage into an arbitrary frequency and voltage.

  The converter unit 11 includes a diode 13 and a capacitor 14, and rectifies the AC voltage supplied from the AC power supply 15 by a circuit in which the diode 13 is arranged as shown in FIG. Create a DC voltage.

  The inverter unit 12 includes an IGBT 16, a freewheeling diode 17, a driver IC 18, and an input logic IC (not shown). A driver IC 18 controlled by an input logic IC is connected to the gate electrode of each IGBT 16, and ON / OFF of the IGBT 16 is controlled by applying a predetermined voltage to the gate electrode. In the inverter unit 12, two IGBTs 16 are connected in series to the capacitor 14, and a diode 17 is connected in parallel to each IGBT 16. Three circuit configurations having two IGBTs 16 and two diodes 17 are connected in parallel to the capacitor 14. Each midpoint of the two IGBTs 16 connected in series is connected to a motor 19 that is an inductive load, and this general-purpose inverter circuit 10 constitutes a three-phase AC circuit. The semiconductor device 20 according to the present embodiment is integrally provided with an IGBT 16 and a diode 17 connected to the IGBT 16 in antiparallel.

  Next, the semiconductor device 20 will be described. As shown in FIG. 2, the semiconductor device 20 includes an IGBT 16 and a diode 17 connected in parallel to the IGBT 16 on the same semiconductor substrate 21.

  In the present embodiment, as the semiconductor substrate 21, as shown in FIG. 3, an N− type silicon disposed on a support substrate 22 made of silicon via a buried insulating film 23 made of an oxide film or the like. The semiconductor layer which consists of etc. is adopted. An amorphous layer 24 having the same component as that of the semiconductor substrate 21 is formed in a region adjacent to the buried insulating film 23 in the semiconductor substrate 21. In the present embodiment, the amorphous layer 24 is formed adjacent to the buried insulating film 23 as shown in FIG. That is, it is formed on the surface layer of the second main surface 25 in the semiconductor substrate 21. The semiconductor substrate 21 and the amorphous layer 24 are divided into a plurality of element regions by an insulating isolation trench 26 in which an oxide film is embedded in the trench in order to insulate and isolate the element. The IGBT 16 is formed in one surrounded element region. A diode 17 is formed in another element region. That is, the IGBT 16 and the diode 17 are electrically isolated by the insulating isolation trench 26.

  In the element region of the IGBT 16 in the semiconductor substrate 21, the amorphous layer 24 is formed over the entire element region. In addition to the above-described amorphous layer 24, a conductive impurity region different from the semiconductor substrate 21 is formed in the element region of the IGBT 16. Specifically, a collector region 27 as a first impurity region, a buffer region 28, an emitter region 29 as a second impurity region, and a channel region 30 are formed. The IGBT 16 includes the collector region 27, the emitter region 29, the channel region 30 in which a channel is formed, and the semiconductor substrate 21 that functions as a drift layer between the collector region 27 and the emitter region 29.

  An insulating film having an opening corresponding to the impurity region on the surface of the semiconductor substrate 21 opposite to the buried insulating film 23 (hereinafter referred to as a first main surface 31) and on the element region of the IGBT 16. 32 is formed, and a field plate 33 is formed on the insulating film 32. Further, a collector electrode 34, an emitter electrode 35 and a gate electrode 36 are formed on the first main surface 31.

  In this embodiment, as shown in FIGS. 2 and 3, the P + type semiconductor region as the collector region 27 and the N type as the buffer region 28 extend in one direction parallel to the first main surface 31 of the semiconductor substrate 21. A semiconductor region is formed on the surface layer of the first major surface 31. The junction surfaces of the collector region 27 and the buffer region 28 are terminated at the first main surface 31. That is, the P-type collector region 27 is exposed at the first main surface 31, and the N-type buffer region 28 is formed surrounding the P-type collector region 27.

  Further, in a direction parallel to the first main surface 31 of the semiconductor substrate 21, an N + type semiconductor as the emitter region 29 is formed in a ring shape surrounding the regions 27 and 28 while being separated from the collector region 27 and the buffer region 28. A P-type semiconductor region as the region and the channel region 30 is formed in the surface layer of the first main surface 31. The junction surface between the emitter region 29 and the channel region 30 is terminated at the first main surface 31. That is, the emitter region 29 and the channel region 30 are exposed at the first main surface 31, and the P-type channel region 30 is formed surrounding the N-type emitter region 29. The channel region 30 has a shape surrounding the two emitter regions 29.

  The insulating film 32 is formed on a portion of the first main surface 31 of the semiconductor substrate 21 excluding a portion where the collector region 27, the buffer region 28, the emitter region 29, and the channel region 30 are exposed. In the present embodiment, the insulating film 32 is made of a LOCOS oxide film. On the insulating film 32, a resistance type field plate 33 made of polycrystalline silicon is formed in a portion (opposing portion) between the collector region 27 and the buffer region 28, and the emitter region 29 and the channel region 30. Yes. In the present embodiment, the field plate 33 is formed along the emitter region 29 and the channel region 30 having a ring shape. That is, the field plate 33 has a spiral structure. The both ends of the field plate 33 are connected to the collector electrode 34 and the gate electrode 36, respectively, via an aluminum wiring (not shown).

  The collector electrode 34 is connected to the collector region 27 on the first main surface 31. Emitter electrode 35 is connected to emitter region 29 and channel region 30 on first main surface 31. A part of the gate electrode 36 is located on the emitter region 29 and the channel region 30 via a gate oxide film (not shown).

  On the other hand, in the element region of the diode 17 in the semiconductor substrate 21, the amorphous layer 24 is formed over the entire element region. Further, in the element region of the diode 17, a conductive impurity region different from the semiconductor substrate 21 is formed in addition to the amorphous layer 24 described above. Specifically, a cathode region 37 as a first impurity region and an anode region 38 as a second impurity region are formed. The diode 17 includes the cathode region 37, the anode region 38, and the semiconductor substrate 21.

  An insulating film 32 having openings corresponding to the cathode region 37 and the anode region 38 is formed on the first main surface 31 of the semiconductor substrate 21 and on the element region of the diode 17. A field plate 33 is formed. Further, a cathode electrode 39 and an anode electrode 40 are formed on the first main surface 31.

  In the present embodiment, as shown in FIGS. 2 and 3, the N + type semiconductor region as the cathode region 37 extending in one direction parallel to the first main surface 31 of the semiconductor substrate 21 is formed on the first main surface 31. It is formed on the surface layer. On the other hand, in a direction parallel to the first main surface 31 of the semiconductor substrate 21, a P + type semiconductor region as the anode region 38 is formed in a ring shape surrounding the cathode region 37 while being separated from the cathode region 37. It is formed on the surface layer of the surface 31.

  The insulating film 32 is formed on a portion of the first main surface 31 of the semiconductor substrate 21 excluding a portion where the cathode region 37 and the anode region 38 are exposed. In the present embodiment, the insulating film 32 is made of a LOCOS oxide film. On the insulating film 32, a resistance type field plate 33 made of polycrystalline silicon is formed in a portion (opposing portion) between the cathode region 37 and the anode region 38. In the present embodiment, the field plate 33 is formed along the anode region 38 having a ring shape. That is, the field plate 33 has a spiral structure. Then, both ends of the field plate 33 are connected to the cathode electrode 39 and the anode electrode 40, respectively, via an aluminum wiring (not shown).

  The cathode electrode 39 is connected to the cathode region 37 on the first main surface 31. The anode electrode 40 is connected to the anode region 38 on the first main surface 31.

  Next, a method for manufacturing the semiconductor device 20 will be described with reference to FIGS.

  First, a manufacturing process of the semiconductor substrate 21 having the amorphous layer 24 will be described with reference to FIG.

  First, as shown in FIG. 4A, a semiconductor substrate 21 made of single crystal silicon having a first main surface 31 and a second main surface 25 is prepared. As the semiconductor substrate 21, for example, an MCZ substrate that is N-type (the doping material is phosphorus), a first main surface 31 having a plane orientation <100>, and a resistivity of 30 to 60 Ωcm can be used.

Next, as shown in FIG. 4B, argon ions are implanted from the second main surface 25 side of the semiconductor substrate 21 to form the amorphous layer 24. Argon ions are preferably accelerated with energy required to cause distortion in the crystal lattice of silicon in the vicinity of the surface layer of the second main surface 25 of the semiconductor substrate 21. The dose of argon ions is also preferably set to a sufficient amount to cause distortion in the silicon crystal lattice. For example, as ion implantation conditions, the acceleration energy of argon ions is set to 100 keV or less (for example, 40 keV), and the dose is set to 3 × 10 ¹⁴ ions / cm ² to 1 × 10 ¹⁶ ions / cm ² (for example, 2 × 10 ^15). ions / cm ² ). As a result, the silicon crystal lattice is distorted near the surface layer of the second main surface 25 of the semiconductor substrate 21 to make it amorphous.

  By the above method, a semiconductor substrate having the amorphous layer 24 on the surface layer of the second main surface 25 can be obtained.

  Next, a manufacturing process of the support substrate 22 that supports the semiconductor substrate 21 will be described with reference to FIGS.

  First, as shown in FIG. 4C, a bulk substrate made of silicon is prepared. As the support substrate 22, for example, an MCZ substrate that is P-type (a doping material is boron) can be used.

  Next, as shown in FIG. 4D, the support substrate 22 is thermally oxidized in an oxygen atmosphere to form an oxide film that becomes the buried insulating film 23 on the surface of the support substrate 22.

  By the above method, the support substrate 22 having the buried insulating film 23 on the surface can be obtained.

  Next, a step of bonding the semiconductor substrate 21 and the support substrate 22 obtained by the above method is performed.

  As shown in FIG. 4E, the second main surface 25 of the semiconductor substrate 21 and the support substrate 22 are bonded to each other via a buried insulating film 23 formed on the support substrate 22 to increase the strength. Annealing is performed. As annealing conditions, for example, heating at 900 ° C. to 1200 ° C. is performed in a nitrogen atmosphere for about 0.5 hours to 5 hours. Due to this annealing treatment, recrystallization of a part of the amorphous layer 24 formed on the second main surface 25 of the semiconductor substrate 21 proceeds. However, if the annealing condition is particularly 1150 ° C. for about 2 hours, the second main surface 25 of the semiconductor substrate 21 and the support substrate 22 are bonded together while leaving the amorphous layer 24 as a high resistance layer. Can do.

  Next, as shown in FIG. 4F, the semiconductor substrate 21 is ground or polished from the first main surface 31 side so that the semiconductor substrate 21 has a predetermined thickness. In the present embodiment, the carrier path of the IGBT 16 and the diode 17 is more than the distance between the impurity regions 27, 28, 29, and 30 of the IGBT 16 and the impurity regions 37 and 38 of the diode 17 and the amorphous layer 24. Grind or polish so that a certain drift length becomes longer.

  Through the above steps, a substrate having an SOI structure can be obtained.

  Next, a method of forming elements formed on the first main surface 31 side of the semiconductor substrate 21 will be described with reference to FIG.

  First, as shown in FIG. 5A, an element isolation process is performed by trench isolation that electrically partitions the IGBT 16 and the diode 17. Element isolation by trench isolation is performed by generally known trench etching, and in this embodiment, the insulating film formed in the insulating isolation trench 26 is an oxide film formed by a CVD method. The insulating isolation trench 26 is formed so as to penetrate the semiconductor substrate 21 and reach the buried insulating film 23, thereby electrically isolating the IGBT 16 and the diode 17.

  Next, as shown in FIG. 5B, an insulating film 32 is formed by LOCOS oxidation on the surface layer of the first main surface 31 of the semiconductor substrate 21 excluding the region constituting the element. In other words, the insulating film 32 having openings in the portions where the collector region 27, the buffer region 28, the emitter region 29 and the channel region 30 of the IGBT 16 and the cathode region 37 and the anode region 38 of the diode 17 are formed is formed. Then, the IGBT 16 and the diode 17 are formed by performing ion implantation using the insulating film 32 formed by LOCOS oxidation as a mask. The IGBT 16 and the diode 17 in the present embodiment are lateral elements, and the manufacturing method thereof conforms to a generally known method, and therefore details are omitted here.

  Next, as shown in FIG. 5C, a process of forming the collector electrode 34, the emitter electrode 35, and the gate electrode 36 of the IGBT 16, and the cathode electrode 39 and the anode electrode 40 of the diode 17 is performed. Further, a step of forming a resistance type field plate 33 made of polycrystalline silicon on the insulating film 32 formed by LOCOS oxidation is also performed. Since these steps also conform to generally known steps, details are omitted. The field plate 33 is formed in each of the IGBT 16 and the diode 17 as shown in FIG. In the IGBT 16, the field plate 33 has a spiral shape whose both ends are connected to the collector electrode 34 and the gate electrode 36, and is arranged so as to surround the collector electrode 34. In the diode 17, the field plate 33 has a spiral shape whose both ends are connected to the cathode electrode 39 and the anode electrode 40, and is arranged so as to surround the cathode electrode 39.

  Finally, although not shown, the semiconductor device 20 can be obtained through an interlayer insulating film forming process, a protective film forming process, and an aluminum wiring process.

  Subsequently, the operation and effect of the amorphous layer 24 which is a characteristic part in the semiconductor device 20 according to the present embodiment will be described with reference to the results (FIG. 6) based on the process / device simulation. In the present embodiment, a structure in which the IGBT 16 and the diode 17 are formed on the same semiconductor substrate 21 is shown, but the effect of the amorphous layer 24 is that the IGBT 16 functions as a pseudo field plate. Therefore, the diode 17 will be described as an example.

  When a predetermined voltage is applied to the cathode electrode 39 of the diode 17 and the anode electrode 40 and the support substrate 22 are set to GND, that is, a reverse bias is applied, the semiconductor substrate 21 is induced in a portion adjacent to the buried insulating film 23. An inversion layer is formed by the added + charges. For this reason, as shown in FIG. 6A, the interval between the equipotential lines between the cathode region 37 and the buried insulating film 23 is narrowed. Therefore, the electric field concentrates at this portion, and the breakdown voltage in the horizontal direction decreases.

  On the other hand, in the present embodiment, the amorphous layer 24 is provided in a portion adjacent to the buried insulating film 23 in the semiconductor substrate 21. The amorphous layer 24 behaves as a high resistance layer having higher electric resistance than the single crystal state and the polycrystalline state. For this reason, when a reverse bias is applied between the cathode region 37 and the anode region 38, the function of correcting so that equipotential lines between both regions are as evenly spaced as possible is exhibited. That is, it functions as a pseudo field plate. Therefore, as shown in FIG. 6B, the intervals of the equipotential lines in the semiconductor substrate 21 corrected to be as evenly spaced as possible by the field plate 33 formed on the surface of the insulating film 32 are made more evenly spaced. It can be corrected to a close shape. Thereby, the horizontal breakdown voltage of the diode 17 (IGBT 16) can be improved.

  The amorphous layer 24 has the same component as the semiconductor substrate 21. Such an amorphous layer 24 is formed by ion implantation of an inert element. For this reason, the number of processes can be reduced and the influence of the diffusion of the dopant on the diode 17 (IGBT 16) can be reduced as compared with the case where a plurality of ion species as dopants are ion-implanted to have a function of a pseudo field plate. It can also be suppressed.

  Further, the amorphous layer 24 also functions as a metal impurity gettering layer. For this reason, the quality improvement of the element formed in the surface layer of the semiconductor substrate 21, for example, the gate insulating film of IGBT16, can be expected. In addition, it can also be used as a layer for controlling the lifetime of the diode 17 (IGBT 16).

  The amorphous layer 24 as a high resistance layer (pseudo field plate) can be substituted by the buried insulating film 23 if the thickness of the semiconductor substrate 21 is reduced. However, in this case, it is necessary to increase the thickness of the buried insulating film 23 in order to ensure the withstand voltage in the depth direction. The buried insulating film 23 is obtained as an oxide film by heating the support substrate 22 in an oxygen atmosphere. However, in order to increase the thickness of the buried insulating film 23, the time required for the oxidation becomes long and realistic. is not.

  On the other hand, in the present embodiment, the amorphous layer 24 is obtained by argon ion implantation, which requires long-time heating to form the buried insulating film 23 as a pseudo field plate. do not do. For this reason, the time required for manufacturing the semiconductor device can be greatly reduced.

  In this embodiment, the amorphous layer 24 is adjacent to the buried insulating film 23. However, the formation region of the amorphous layer 24 is not limited to the above example. As shown in FIG. 7, the amorphous layer 24 is formed in the semiconductor substrate 21 at a position deeper than the impurity region (corresponding to the reference numerals 23 to 26, 28, and 29) with respect to the first main surface 31. Just do it. The formation position of the amorphous layer 24 can be arbitrarily determined by adjusting the acceleration energy at the time of argon ion implantation in the formation process of the amorphous layer 24.

  In the present embodiment, the horizontal position where the amorphous layer 24 is formed is formed in the entire element region. However, the present invention is not limited to the above example. The amorphous layer 24 functions as a pseudo field plate if it is formed at least in a region between the first impurity region and the second impurity region.

  In this embodiment, the IGBT 16 and the diode 17 are formed on the same semiconductor substrate 21, but the IGBT 16 and the diode 17 may be formed independently. The elements formed on the surface layer of the semiconductor substrate 21 are not limited to the IGBT 16 and the diode 17, and any horizontal element such as a horizontal MOS transistor can be formed. Further, the shape of the element is not limited.

(Second Embodiment)
In the first embodiment, an example in which a semiconductor layer having an SOI structure is used as the semiconductor substrate 21 has been described. In contrast, in this embodiment, an example in which a bulk single crystal substrate is used as the semiconductor substrate 21 is shown.

  The semiconductor device 20 according to this embodiment will be described with reference to FIGS. The semiconductor device 20 shown in FIGS. 8 and 9 has only a diode 17 as a lateral element on a bulk single crystal substrate as the semiconductor substrate 21.

  As the bulk single crystal substrate, for example, an MCZ substrate made of N-type silicon or the like can be used. As shown in FIG. 9, in this embodiment, an amorphous layer 24 having the same component as the bulk single crystal substrate is formed in the bulk single crystal substrate as the semiconductor substrate 21. The diode 17 having the same configuration as that of the first embodiment is formed on the semiconductor substrate 21. Further, the amorphous layer 24 is formed over the entire element region at a position deeper than the impurity regions 37 and 38 with respect to the first main surface 31 of the semiconductor substrate 21.

  Next, a method for manufacturing the diode 17 formed on the semiconductor substrate 21 (bulk single crystal substrate) as described above will be described with reference to FIGS.

  First, a manufacturing process of the amorphous layer 24 will be described with reference to FIG.

  First, as shown in FIG. 10A, a bulk single crystal substrate made of a silicon single crystal having a first main surface 31 and a second main surface 25 on the back surface thereof is prepared as the semiconductor substrate 21. As this bulk single crystal substrate, for example, an MCZ substrate that is N-type (the doping material is phosphorus), a surface orientation <100> of the first main surface 31 and a resistivity of 30 to 60 Ωcm can be used.

Next, as shown in FIG. 10B, argon ions are implanted from the first main surface 31 side of the semiconductor substrate 21 (bulk single crystal substrate) to form the amorphous layer 24. Argon ions are implanted by adjusting the acceleration energy so that the amorphous layer 24 is formed at a position deeper than the diffusion layer of the element to be formed, that is, the cathode region 37 and the anode region 38 of the diode 17. Specifically, it is preferable to set the dose to 100 keV to 200 keV (for example, 150 keV) and the dose amount to 3 × 10 ¹⁴ ions / cm ² to 1 × 10 ¹⁶ ions / cm ² (for example, 2 × 10 ¹⁵ ions / cm ² ). . As a result, the silicon crystal lattice is distorted at a predetermined depth of the semiconductor substrate 21 (bulk single crystal substrate) to make it amorphous.

  Next, as shown in FIG. 10C, by grinding or polishing from the second main surface 25 side of the semiconductor substrate 21 (bulk single crystal substrate), the semiconductor substrate 21 (bulk single crystal substrate) is predetermined. Thickness.

  By the above method, a bulk single crystal substrate having the amorphous layer 24 is manufactured as the semiconductor substrate 21.

  Note that the order of the step of forming the amorphous layer 24 shown in FIG. 10B and the step of grinding or polishing shown in FIG. 10C may be reversed.

  Next, a method for forming the diode 17 will be described with reference to FIG.

  First, as shown in FIG. 11A, an insulating film 32 is formed by LOCOS oxidation on the surface layer of the first main surface 31 of the semiconductor substrate 21 except for the region constituting the element. In other words, the insulating film 32 having an opening is formed in a portion where the cathode region 37 and the anode region 38 of the diode 17 are formed.

  Next, as shown in FIG. 11B, the cathode region 37 and the anode region 38 are formed by performing ion implantation using the insulating film 32 formed by LOCOS oxidation as a mask. That is, the diode 17 is formed. The diode 17 in the present embodiment is a lateral element, and the manufacturing method thereof conforms to a generally known method, and therefore the details are omitted here.

  Next, as shown in FIG. 11C, a step of forming the cathode electrode 39 and the anode electrode 40 of the diode 17 is performed. Further, a step of forming a resistance type field plate 33 made of polycrystalline silicon on the insulating film 32 formed by LOCOS oxidation is performed. Since these steps also conform to generally known steps, details of the forming method are omitted. The field plate 33 has a spiral shape with both ends connected to the cathode electrode 39 and the anode electrode 40, and is disposed so as to surround the cathode electrode 39.

  Finally, although not shown, the semiconductor device 20 can be obtained through an interlayer insulating film forming process, a protective film forming process, an aluminum wiring process, and the like.

  Next, functions and effects of the semiconductor device 20 and the manufacturing method thereof according to the present embodiment will be described. In addition to the effects described in the first embodiment, the following effects can be expected.

  In the present embodiment, unlike the SOI structure described in the first embodiment, a bonding process is not performed. For this reason, since the heating process for increasing the bonding strength is not necessary, the amorphous layer 24 can be prevented from being polycrystallized by heating. That is, the amorphous layer 24 having a higher resistance can be formed as compared with the case where the amorphous layer 24 is provided in the SOI structure. Therefore, the breakdown voltage in the horizontal direction of the element can be improved more effectively.

  In the present embodiment, an example in which only the diode 17 is formed on the semiconductor substrate 21 (bulk single crystal substrate) has been shown. However, an element formed on the surface layer of the semiconductor substrate 21 is not limited to the diode 17. In addition, any lateral element such as an IGBT or a lateral MOS transistor can be formed. Further, the shape of the element is not limited.

(Third embodiment)
In 2nd Embodiment, the example which has the amorphous layer 24 in the bulk single crystal substrate as the semiconductor substrate 21 was shown. On the other hand, in this embodiment, an example in which an epitaxial substrate is used as the semiconductor substrate 21 is shown. This epitaxial substrate is formed by epitaxial growth using a bulk single crystal substrate as the support substrate 22. An example of the semiconductor device 20 in which a lateral MOS transistor 41 is formed on an epitaxial substrate as the semiconductor substrate 21 will be described with reference to FIGS.

  As shown in FIGS. 12 and 13, in this embodiment, an epitaxial substrate epitaxially grown on a supporting substrate 22 is used as the semiconductor substrate 21. As the bulk single crystal substrate as the support substrate 22, an MCZ substrate or the like can be used. In addition, the semiconductor substrate 21 (epitaxial substrate) in the present embodiment is formed as an N− type. A lateral MOS transistor 41 is formed on the surface layer of the semiconductor substrate 21 (epitaxial substrate). An amorphous layer 24 having the same component as the epitaxial substrate is formed in the semiconductor substrate 21 (epitaxial substrate). The amorphous layer 24 has an impurity region constituting the MOS transistor 41 with respect to the first main surface 31, that is, a drain region 42 as a first impurity region, a source region 43 as a second impurity region, and a channel region. 44 and the channel contact region 45 at a deeper position than the entire device region.

  An insulating film 32 having an opening corresponding to the impurity region is formed on the first main surface 31 of the semiconductor substrate 21 and on the element region of the MOS transistor 41. A field plate is formed on the insulating film 32. 33 is formed. Further, a drain electrode 46, a source electrode 47, a gate electrode 48, and a channel contact electrode 49 are formed on the first main surface 31.

  In the present embodiment, as shown in FIGS. 12 and 13, the N + type semiconductor region as the drain region 42 extending in one direction parallel to the first main surface 31 of the semiconductor substrate 21 is formed on the first main surface 31. It is formed on the surface layer.

  Further, in a direction parallel to the first main surface 31 of the semiconductor substrate 21, a ring shape surrounding the drain region 42 while being separated from the drain region 42 is formed, and an N + type semiconductor region as the source region 43 and a channel region 44 are formed. The P + type semiconductor region and the P + type semiconductor region as the channel contact region 5 are formed on the surface layer of the first main surface 31. The junction surface between the channel region 44 and the source region 43 and the junction surface between the channel region 44 and the channel contact region 45 are terminated at the first main surface 31. That is, the source region 43, the channel region 44, and the channel contact region 45 are exposed at the first main surface 31, and the P-type channel region 44 connects the N + -type source region 43 and the P + -type channel contact region 45. Surrounding is formed.

  The insulating film 32 is formed in a portion of the first main surface 31 of the semiconductor substrate 21 excluding a portion where the drain region 42, the source region 43, the channel region 44 and the channel contact region 45 are exposed. In the present embodiment, the insulating film 32 is made of a LOCOS oxide film. On the insulating film 32, a resistance type field plate 33 made of polycrystalline silicon is formed in a portion (opposing portion) between the drain region 42, the source region 43, the channel region 44, and the channel contact region 45. ing. In the present embodiment, the field plate 33 is formed along the source region 43, the channel region 44, and the channel contact region 45 having a ring shape. That is, the field plate 33 has a spiral structure. The both ends of the field plate 33 are connected to the drain electrode 46 and the gate electrode 48, respectively, via aluminum wiring (not shown).

  On the first main surface 31, the drain electrode 46 is connected to the drain region 42. The source electrode 47 is connected to the source region 43, and the channel contact electrode 49 is connected to the channel contact region 45. A part of the gate electrode 48 is located on the channel region 44 through a gate oxide film (not shown).

  Next, a method for manufacturing the MOS transistor 41 formed on the epitaxial substrate as the semiconductor substrate 21 will be described with reference to FIG.

  First, a manufacturing process of the semiconductor substrate 21 (epitaxial substrate) will be described.

  First, as shown in FIG. 14A, a bulk single crystal substrate made of single crystal silicon having a main surface 50 is prepared as a support substrate 22 for growing crystals. As this bulk single crystal substrate, for example, an MCZ substrate that is N-type (the doping material is phosphorus), a surface orientation <100> of the principal surface 50, and a resistivity of 30 to 60 Ωcm can be used.

  Next, as shown in FIG. 14B, an N− type semiconductor substrate 21 (epitaxial substrate) is grown on the main surface 50 of the bulk single crystal substrate as the support substrate 22 by metal organic vapor phase epitaxy. The growth of the epitaxial substrate is not limited to the metal organic chemical vapor deposition method, and a molecular beam epitaxy method can also be used.

Next, as shown in FIG. 14C, argon ions are implanted from the first main surface 31 of the semiconductor substrate 21 (epitaxial substrate) to form the amorphous layer 24. Argon ion implantation is performed so that the amorphous layer 24 is formed at a position deeper than the impurity region of the element, that is, the drain region 42, the source region 43, the channel region 44, and the channel contact region 45 of the MOS transistor 41. This is done by adjusting the acceleration energy. Specifically, it is preferable to set the dose to 100 keV to 200 keV (for example, 150 keV) and the dose amount to 3 × 10 ¹⁴ ions / cm ² to 1 × 10 ¹⁶ ions / cm ² (for example, 2 × 10 ¹⁵ ions / cm ² ). . As a result, the silicon crystal lattice is distorted to a predetermined depth of the semiconductor substrate 21 (epitaxial substrate) to make it amorphous.

  By the above method, an epitaxial substrate as the semiconductor substrate 21 having the amorphous layer 24 can be manufactured.

  Next, although not shown, a method for forming the MOS transistor 41 formed on the first main surface 31 of the semiconductor substrate 21 (epitaxial substrate) having the amorphous layer 24 will be described. The element formation flow is the same as the element formation flow described in the second embodiment except that the element to be formed is a diode.

  First, in the first main surface 31 of the semiconductor substrate 21 (epitaxial substrate) manufactured by the above method, the LOCOS is formed on the surface layer excluding the portion where the drain region 42, the source region 43, the channel region 44 and the channel contact region 45 are formed. An insulating film 32 is formed by oxidation.

  Next, the MOS transistor 41 is formed by performing ion implantation using the insulating film 32 formed by LOCOS oxidation as a mask. The MOS transistor 41 in the present embodiment is a lateral element, and its structure and manufacturing method conform to a generally known structure and method, and therefore details are omitted here.

  Next, a step of forming the drain electrode 46, the source electrode 47, the gate electrode 48, and the channel contact electrode 49 of the MOS transistor 41 is performed. Further, a step of forming a resistance type field plate 33 made of polycrystalline silicon on the insulating film 32 formed by LOCOS oxidation is performed. Since these steps also conform to generally known steps, details are omitted. The field plate 33 has a spiral shape whose both ends are connected to the drain electrode 46 and the gate electrode 48, and is disposed so as to surround the drain electrode 46.

  Finally, the semiconductor device 20 can be obtained through processes such as an interlayer insulating film forming process, a protective film forming process, and aluminum wiring.

  Next, functions and effects of the amorphous layer 24 that is a characteristic part of the semiconductor device 20 according to the present embodiment will be described.

  In addition to the operational effects described in the second embodiment, when an epitaxial substrate is used as the semiconductor substrate 21, an effect resulting from superior crystallinity and purity as compared with a bulk single crystal substrate can be expected. That is, the horizontal direction is also applied to a substrate that needs to be formed by epitaxial growth, such as an element that requires high crystallinity or high purity as the semiconductor substrate 21 or an element formed for many types of compound semiconductors. The breakdown voltage can be improved.

  In the present embodiment, an example in which the MOS transistor 41 is formed on the epitaxial substrate as the semiconductor substrate 21 is shown, but the element formed on the surface layer of the epitaxial substrate is not limited to the MOS transistor 41. Any horizontal element can be formed. Further, the shape of the element is not limited.

(Other embodiments)
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In the second embodiment and the third embodiment, an example in which one element is formed on the semiconductor substrate 21 has been described. However, a plurality of elements can be formed on the same semiconductor substrate 21. In this case, element isolation is performed by trench isolation or PN junction isolation. In particular, when a bulk single crystal substrate is used as the semiconductor substrate 21 as in the second embodiment, trench isolation can be performed as described below.

  First, the insulating film 32 is formed by LOCOS oxidation on the surface layer of the first main surface 31 of the semiconductor substrate 21 excluding the region constituting the element. Next, a desired impurity region is formed by ion implantation. Next, ion implantation of an inert element is performed from the second main surface 25 side of the semiconductor substrate 21 to form an amorphous layer 24 at a predetermined depth from the first main surface. Next, a trench is formed at an element isolation location by trench etching from the second main surface 25 side of the semiconductor substrate 21, and an insulating layer is formed in the trench to electrically isolate a plurality of elements. Finally, as in the above embodiments, the semiconductor device 20 is obtained through the steps of forming electrodes, field plates 33, interlayer insulating films, protective films, aluminum wirings, and the like. Note that the order of forming the amorphous layer 24 and the step of performing trench isolation may be reversed.

  In each of the above-described embodiments, the example in which the amorphous layer 24 is used as the high resistance layer formed in the semiconductor substrate 21 has been described. However, the present invention is not limited to the above example. For example, a polycrystalline layer may be used.

  In each of the embodiments described above, an example in which a resistance type field plate is used as the field plate has been described. However, the present invention is not limited to the above example, and a capacitive type field plate may be used.

  Further, in each of the above-described embodiments, the example using the semiconductor substrate mainly composed of silicon is shown, but the present invention is not limited to the above example, and a compound semiconductor such as GaAs may be used.

  In each of the above-described embodiments, argon is used as the ion species implanted to form the amorphous layer 24. However, the embodiment is not limited to the above example. Any element that is inert to the semiconductor substrate 21 (does not act as a dopant) may be used, and carbon, oxygen, silicon, krypton, and xenon ions may be used.

16 ... IGBT
17 ... Diode 21 ... Semiconductor substrate 22 ... Support substrate 23 ... Embedded insulating film 24 ... Amorphous layer 26 ... Insulation isolation trench 27 ... Collector region 28 ... Buffer region 29 ... Emitter region 30 ... Channel region 32 ... Insulating film 33 ... Field plate 37 ... Cathode region 38 ... Anode region

Claims (12)

A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
A first impurity region formed in a surface layer of the first main surface of the semiconductor substrate; and a surface layer of the first main surface formed at a position not overlapping with the first impurity region; A device having a second impurity region through which a current flows,
An insulating film formed on a surface including a region between the first impurity region and the second impurity region in the first main surface of the semiconductor substrate;
A field plate formed between the first impurity region and the second impurity region on the insulating film,
The semiconductor substrate at least in a region between the first impurity region and the second impurity region at a predetermined depth deeper than the first impurity region and the second impurity region from the first main surface of the semiconductor substrate. Having an amorphous layer containing the same components and inert elements,
The amorphous layer is formed by ion implantation of the inert element, functions as a pseudo field plate, and functions as a gettering layer that captures metal impurities present in the semiconductor substrate. Semiconductor device.   The semiconductor device according to claim 1, wherein the semiconductor substrate has an SOI structure in which the second main surface is supported by a support substrate via a buried insulating film having a predetermined thickness.   The semiconductor device according to claim 2, wherein the amorphous layer is formed adjacent to the buried insulating film.   The semiconductor device according to claim 1, wherein the semiconductor substrate is a bulk single crystal substrate.   The semiconductor device according to claim 1, wherein the semiconductor substrate is an epitaxial substrate formed by epitaxial growth on a bulk single crystal substrate.   6. The device according to claim 1, wherein the element includes a lateral diode, and the diode includes a cathode region as the first impurity region and an anode region as the second impurity region. 2. A semiconductor device according to item 1.   The device includes a lateral insulated gate bipolar transistor, and the insulated gate bipolar transistor includes a collector region as the first impurity region and an emitter region as the second impurity region. Item 7. The semiconductor device according to any one of Items 1 to 6.   The element includes a lateral MOS transistor, and the MOS transistor has a drain region as the first impurity region and a source region as the second impurity region. The semiconductor device according to any one of the above. A method of manufacturing a semiconductor device according to claim 2,
Injecting an inert element from the second main surface side of the semiconductor substrate to form an amorphous layer at a predetermined depth from the first main surface;
Bonding a second main surface of the semiconductor substrate and a support substrate having a buried insulating film on a surface facing the second main surface of the semiconductor substrate via the buried insulating film;
Forming the insulating film on the first main surface so that a part of the first main surface is exposed;
By ion-implanting into the surface layer of the first main surface from the first main surface side using the insulating film as a mask, the first impurity region and the second impurity have a depth that does not reach the amorphous layer. Forming a region;
And a step of forming a field plate on the insulating film between the first impurity region and the second impurity region.   The method for manufacturing a semiconductor device according to claim 9, wherein in the step of forming the amorphous layer, the amorphous layer is formed on a surface layer of the second main surface of the semiconductor substrate. A method of manufacturing a semiconductor device according to claim 4,
A step of ion-implanting an inert element from the first main surface side to the bulk single crystal substrate as the semiconductor substrate to form an amorphous layer at a predetermined depth from the first main surface; ,
Grinding the semiconductor substrate from the second main surface side to a predetermined thickness;
Forming an insulating film on the first main surface so that a part of the first main surface is exposed;
By ion-implanting into the surface layer of the first main surface from the first main surface side using the insulating film as a mask, the first impurity region and the second impurity have a depth that does not reach the amorphous layer. Forming a region;
And a step of forming a field plate on the insulating film between the first impurity region and the second impurity region. A method of manufacturing a semiconductor device according to claim 5,
Forming an epitaxial substrate as the semiconductor substrate by epitaxial growth on one surface of a bulk single crystal substrate;
A step of ion-implanting an inert element from the first main surface side of the semiconductor substrate to the formed semiconductor substrate to form an amorphous layer at a predetermined depth from the first main surface;
Forming an insulating film on the first main surface so that a part of the first main surface is exposed;
By ion-implanting into the surface layer of the first main surface from the first main surface side using the insulating film as a mask, the first impurity region and the second impurity have a depth that does not reach the amorphous layer. Forming a region;
And a step of forming a field plate on the insulating film between the first impurity region and the second impurity region.

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