JP5665902B2 - Image processing apparatus, image processing method, and program - Google Patents

Description

  The present invention relates to vector graphics processing.

  In image processing for processing vector graphics or two-dimensional computer graphics, when an image processing apparatus draws overlapping figures, it draws in order from the lowest overlapping figure to the upper figure.

JP 2006-221418 A

  In the conventional technology, since it is unclear which part is hidden by the upper figure at the time of drawing the lower figure by this method, the image processing apparatus applies the pixel (pixel) of the figure to be hidden. Also performs processing for drawing. An object of the present invention is to improve the efficiency of drawing overlapping graphics in image processing for processing vector graphics or two-dimensional computer graphics.

  One aspect of embodiments of the present invention is illustrated by an image processing device. The image processing apparatus generates an intersection generation unit that generates intersection information including a position of an intersection between a boundary line of a graphic and an arrangement of pixels in the scanning line direction of the image, and layer information indicating a hierarchical relationship between the graphic and another graphic. And the other boundary line of the figure and the scanning line from the intersection (starting point) of one boundary line and the scanning line of the figure that intersects the scanning line of the image, excluding the existence range of the upper layer figure in the hierarchical relationship A span generation unit that generates a span, which is a set of pixels included up to the intersection (end point).

  According to this image processing apparatus, it is possible to improve the efficiency of drawing overlapping graphics in image processing for processing vector graphics or two-dimensional computer graphics.

It is an example of a process of the image processing apparatus of a comparative example. It is a figure which illustrates the structure of the information processing apparatus containing the image processing apparatus which concerns on a comparative example. It is a figure which illustrates the composition of edge information. It is a figure which illustrates the structure of span information. It is a figure which illustrates the processing target by an image processing device. It is a format example of the intersection buffer which concerns on a comparative example. It is a figure which illustrates the cover value at the time of dividing one pixel into 4x4 subpixels. It is a figure which illustrates the structure of an intersection buffer. It is a figure which illustrates the process which adds cover value information. 6 is a diagram illustrating calculation of cover value information of a pixel at coordinates (X + 1) adjacent to the right side of an intersection point X. FIG. It is a figure which illustrates the process which subtracts cover value information. It is an example of cover value information. It is a figure which illustrates a span production | generation process. It is a figure which illustrates the format on the intersection buffer of intersection information with a layer. It is a figure which illustrates the structure of the information processing apparatus containing the image processing apparatus which concerns on an Example. It is a figure which illustrates the flowchart of the span production | generation process which concerns on an Example. It is a figure which illustrates the detail of an intersection process. It is a figure which illustrates the detail of span calculation. It is a figure which illustrates the detail of the span calculation which concerns on a modification.

  Hereinafter, an image processing apparatus according to an embodiment will be described with reference to the drawings. The configuration of the following embodiment is an exemplification, and the present apparatus is not limited to the configuration of the embodiment.

[Comparative example]
An image processing apparatus according to a comparative example will be described with reference to FIGS. FIG. 1 is a processing example of the image processing apparatus 101 of the comparative example. FIG. 1A is an example of a graphic displayed on a display device of a computer including the image processing device 101. In FIG. 1A, the upper layer graphic and the lower layer graphic are partially overlapped and displayed.

  FIG. 1B is an example of pixel generation by the image processing apparatus 101. The image processing apparatus 101 generates pixels of each figure in order to display the image of FIG. When generating pixels for the lower layer graphic, the image processing apparatus 101 does not recognize that the upper layer graphic partially overlaps with the lower layer graphic, and generates graphic pixels in order from the lower layer graphic. For this reason, the image processing apparatus 101 generates pixels even in the hidden surface hidden by the upper layer graphic in the lower layer graphic.

  FIG. 2 is a diagram illustrating a configuration of an information processing apparatus including the image processing apparatus 101. The information processing apparatus includes, for example, a CPU 102 in addition to the image processing apparatus 101. For example, the CPU 102 executes an image processing program and delivers graphic information to the image processing apparatus 101. The graphic information is, for example, a polygon, a line including width information, or the like.

  The image processing apparatus 101 includes an edge generation unit 112, a sequencer 113, an intersection generation unit 114, a sorter 115, a span generation unit 116, an intersection buffer 117, a rasterizer 118, and a pixel processing unit 119.

  The edge generation unit 112 receives graphic information from the CPU 102 and generates edge information. The edge generation unit 112 outputs the generated edge information to a buffer (not shown). Since the buffer is controlled by the sequencer 113, the edge information is handed over from the edge generation unit 112 to the sequencer 113 in FIG. The edge generation unit 112 may be, for example, a DSP that executes a program or a dedicated hardware circuit.

The sequencer 113 controls the intersection generation unit 114, the sorter 115, and the span generation unit 116. The sequencer 113 may be, for example, a DSP that executes a program or a dedicated hardware circuit. When the edge information is handed over, the sequencer 113 activates the intersection generation unit 114. However, the edge generation unit 112 and the intersection generation unit 114 only need to be able to exchange edge information through, for example, a buffer that stores edge information. Accordingly, the edge information may be delivered to the intersection generation unit 114 every time one piece of edge information in one figure, for example, a polygon is generated. That is, in the processing of one figure, the edge generation unit 112 and the intersection generation unit 114 may execute processing in parallel.

  The intersection generation unit 114 generates intersection information based on the edge information output from the edge generation unit 112. Here, the intersection information is an intersection of the edge information output from the edge generation unit 112 and the horizontal line of the image. The horizontal line of the image is a horizontal arrangement of pixels in the image, and is also called a scanning line.

  That is, the intersection information is information on the intersection between the boundary line of the graphic output by the CPU 102 and the scanning line. The intersection generation unit 114 outputs the generated intersection information to the intersection buffer 117. For example, when the intersection generation unit 114 outputs the intersection information for a single figure to the intersection buffer 117, the sequencer 113 activates the sorter 115.

  The sorter 115 rearranges the intersection information on the intersection buffer using the scanning line (for example, the Y coordinate of the displayed graphic) and the X coordinate as the key. The sorter 115 may be, for example, a DSP that executes a program or a dedicated hardware circuit. When the sorting by the sorter 115 is completed, the sequencer 113 activates the span generator 116.

  The span generator 116 generates span information from the intersection information of the intersection buffer 117 that has been rearranged. The span generator 116 delivers the generated span information to the rasterizer 118. The span generator 116 may be, for example, a DSP that executes a program or a dedicated hardware circuit.

  The rasterizer 118 generates pixel information from the span information. The rasterizer 118 delivers the generated pixel information to the pixel processing unit 119. The rasterizer 118 may be a DSP that executes a program, or may be a dedicated hardware circuit. The pixel processing unit 119 generates control information for a display device that controls a display device (not shown) from the pixel information, and outputs the control information to the display device.

  In the description of FIG. 2, the sequencer 113 has been described as starting the sorter 115 after the processing of the intersection generation unit 114 is completed and starting the span generation unit 116 after the processing of the sorter 115 is completed. However, the intersection generation unit 114 may activate the sorter 115 after the processing of the intersection generation unit 114 ends, and the sorter 115 may activate the span generation unit 116 after the processing of the sorter 115 ends.

(Edge information and span information)
FIG. 3 illustrates the configuration of edge information. As shown in FIG. 3, the edge information includes, for example, the Y coordinate (YTOP) of the upper edge of the edge, the Y coordinate (YBottom) of the lower edge of the edge, the X coordinate (XTOP) of the upper edge of the edge, and the X coordinate when the Y coordinate changes by one line. Increase (decrease) amount (DeltaX) and edge direction (Dir). Here, the direction of the edge (Dir) indicates whether the edge is upward or downward. However, the inside of the figure is defined on the right side (or left side) of the traveling direction when moving along the edge in the direction of the edge. Therefore, it can be said that the direction of the edge defines whether the inside of the figure is on the right side or the right side of the edge.

FIG. 4 illustrates the configuration of span information. A span corresponds to, for example, a portion where a scanning line intersects one figure in a scanning line of an image, for example, a horizontal pixel array. The span information defines both ends of the span. As shown in FIG. 4, the span information includes the Y coordinate (Y) of the span,
The X coordinate (XLeft) of the left end of the span, the X coordinate (XRight) of the right end of the span, and the cover value (Cover) of the span are included. The cover value refers to a ratio of a portion through which an edge passes to a pixel through which the edge passes. For example, a cover value of 0 means that no edge passes through the pixel. On the other hand, a cover value of 1 means that the edge passes through the entire pixel. On the other hand, when the cover value is a value between 0 and 1, it means that the edge passes covering a part of the pixel. The span information is output for each cover value, for example.

(Processing of intersection generation unit 114)
The process of the intersection generation unit 114 is illustrated with reference to FIGS. FIG. 5 illustrates a processing target by the image processing apparatus 101. FIG. 5 illustrates a circular annular pattern. Moreover, the horizontal line which cross | intersects a circular annular pattern is illustrated. Four intersection points are formed between the boundary line of the circular annular pattern and the horizontal line.

  As illustrated in FIG. 2, the application program on the CPU 102 delivers, for example, a graphic as illustrated in FIG. 5 to the edge generation unit 112. The edge generation unit 112 generates a minute straight line (edge) obtained by linear approximation of a figure boundary line exemplified by a circular annular pattern, and passes it to the intersection generation unit 114. The intersection generation unit 114 stores, in the intersection buffer 117, intersection information at which the edge and the horizontal line intersect. Note that, in the case of a polygonal figure whose outer shape includes a straight side instead of a curved shape as shown in FIG. 5, the straight side becomes an edge as it is.

  The intersection generation unit 114 obtains the X coordinate of the intersected pixel, the information indicating how much the edge has covered the pixel (cover value information), and the direction of the edge (Dir) at the location where the edge of the figure intersects the horizontal line. Save as one intersection information.

  FIG. 6 is an example of a format of an intersection buffer that stores intersection information per intersection when one pixel is divided into 4 × 4 subpixels. In FIG. 6, the intersection information includes cover value information (Mark1 [0: 3], Mark2 [0: 3], Mark3 [0: 3], Mark4 [0: 3]), direction (Dir), and reserved (Reserved). , And X coordinates.

  FIG. 7 is an example of the cover value information when one pixel is divided into 4 × 4 subpixels when the intersection information is extracted at the intersection of the pixel and the edge. Mark1 [0: 3], Mark2 [0: 3], Mark3 [0: 3], Mark4 [0: 3] each have 4 bits, and whether or not each subpixel is covered by an edge, that is, , Indicates whether each sub-pixel is included in the figure. The intersection generation unit 114 sets 0 to the bit of the cover value information corresponding to the subpixel outside the graphic with respect to the edge at each intersection, and the bit of the cover value information corresponding to the subpixel inside the graphic with respect to the edge Set 1 to.

  The span generator 116 calculates the cover value of the entire pixel based on the cover value information when generating the span. A cover value of 1 indicates that the pixel is completely covered inside the edge. That is, a pixel with a cover value of 1 indicates a pixel that is completely contained within the figure. In the example of FIG. 7, since the edge is upward, 1 is set to each bit corresponding to the sub-pixel existing on the right side of the edge. Further, when there is an overlap in the same figure, an edge overlap occurs. The span generator 116 has a counter for calculating cover value information when edges overlap at the same coordinates. For example, when the span generator 116 uses a 16-bit counter with the number of subpixels, the degree of overlap of 65535 edges can be calculated for each subpixel at the same coordinate.

In FIG. 6, the direction (Dir) on the intersection buffer indicates whether the edge passes upward or downward through the intersection. In the present embodiment, for example, when the edge passes upward through the intersection, it is defined that the inside of the graphic exists on the right side of the intersection. However, as long as it is unified within the information processing apparatus including the CPU 102 and the graphic processing apparatus 101, the definition of the direction may be reversed. That is, when the edge passes upward through the intersection, it may be defined that the inside of the figure exists on the left side of the intersection. Further, in FIG. 6, the X coordinate is information indicating a position on the horizontal line. The X coordinate can be exemplified by, for example, serial numbers of pixels arranged from left to right.

  FIG. 8 is a diagram illustrating the configuration of the intersection buffer. In the present embodiment, it is an array of intersection information prepared for each horizontal line. Intersection information is stored in each rectangle of FIG. 8 in the format of the intersection buffer of FIG.

  The vertical arrangement (0 to H-1) in FIG. 8 indicates the number of the horizontal line, that is, the scanning line. On the other hand, the horizontal arrangement (0 to k−1) illustrates a set of intersection buffers for each horizontal line. In the example of FIG. 8, an entry of an array of k intersection buffers is prepared for each horizontal line. The intersection generation unit 114 adds intersection information in the format of FIG. 6 in order from the left of the array to the empty entry of the intersection array of each horizontal line every time the location where the horizontal line and the edge intersect as shown in FIG. 6 is specified.

  The sorter 115 illustrated in FIG. 2 rearranges the array of intersection information on the intersection buffer illustrated in FIGS. 6 and 8 by the X coordinate on each horizontal line (1 to H−1) and again intersects the buffer 117. Save to.

Hereinafter, the processing of the span generator 116 will be exemplified with reference to FIGS. 9 to 13.
(Calculation of cover value information by the span generator 116)
FIGS. 9 to 11 are diagrams illustrating an example of the procedure for calculating the cover value information by the span generator 116. The span generator 116 extracts intersection information from the head of the array of intersection information on each horizontal line after sorting. Then, the span generation unit 116 adds or subtracts the current cover value information and the cover value information of the extracted intersection information to obtain the intersection cover value. The span generator 116 determines whether to add or subtract based on the edge direction (Dir). In this embodiment, the upward direction is addition and the downward direction is subtraction. This is because, in the present embodiment, it is defined that the inside of the graphic exists on the right side of the edge when the edge is upward. FIG. 9 illustrates a process of adding cover value information. The cover value is added for each word entry (Marki [j], i = 1, 4, j = 0, 3) corresponding to the sub-pixel in the pixel.

FIG. 10 illustrates calculation of cover value information of a pixel at coordinates (X + 1) adjacent to the right side of the intersection X. In the example of FIG. 10, the cover value information of the pixel at the coordinate X + 1 next to the intersection is the vertical one column (4 subpixels) adjacent to the left side of the pixel at the coordinate X + 1 among the subpixels at the intersection. A column copy. When there are further intersections at the next coordinate X + 1 of the intersection X (when the intersections are continuous), the span generator 116 further adds the value calculated from the cover value information of the intersection X in the above procedure. Cover value information calculated from the intersection of the X + 1 coordinates is added.

  FIG. 11 illustrates processing for subtracting cover value information. The cover value is subtracted for each bit entry (Marki [j], i = 1, 4, j = 0, 3) corresponding to the sub-pixel in the pixel.

The span generator 116 calculates a span cover value according to a predetermined rule based on the cover value information obtained by the processes of FIGS. 9 to 11. For example, the cover value calculation result is illustrated by taking the cover value information of FIG. 12 as an example. As a calculation method, a method of counting the number of non-zero subpixels among the subpixels included in the cover value information (Non-zero rule) can be exemplified. According to the non-zero rule, the cover value is 13/16 = 0.8125 in the example of FIG. Further, for example, in the method (ODD rule) of counting an odd number of sub-pixel cover value information (ODD rule), in the case of the cover value information in FIG.

(Span generation)
FIG. 13 exemplifies span generation processing by the span generator 116. Span generator 116
Uses the X coordinate of a pixel whose cover value is not 0.0 as the start point of the span. Then, the span generator 116 sets the pixel at the X coordinate −1 (adjacent to the left) of the pixel whose cover value appears next to 0.0 as the end point. The span generator 116 generates span information including the start point and the end point, and outputs the generated span information to the rasterizer 118.

  For example, in FIG. 13, when the cover value is 1 at the intersection A and the cover value is 0 at the intersection B + 1, the span generator 116 generates span information starting from the intersection A and ending at the intersection B. The span from the intersection point A to the intersection point B is the span of the cover value 1.

(problem)
As illustrated in FIG. 6, the intersection information on the intersection buffer 117 has no depth information. For example, when a plurality of spans as shown in FIG. 13 are generated, the vertical relationship between the spans is unknown. In such a case, when drawing a plurality of overlapping figures, the image processing apparatus 101 is required to draw in order from the bottom figure. Therefore, in the later stage, the image processing apparatus 101 generates a span and further a pixel for a lower-layer graphic portion hidden by a graphic drawn on the upper layer, and executes a useless process. .

  The image processing apparatus 1 according to the embodiment will be described with reference to FIGS. In order to solve the problem of the comparative example, the image processing apparatus 1 according to the embodiment adds a layer number to the intersection information and saves it. The layer number is an integer starting from 0 given for each figure, for example. In the embodiment, the higher the layer number, the higher the figure in the superposition of the figures, that is, the hierarchical relationship between the figures. The layer number may be given by software processing on the CPU, for example.

  FIG. 14 illustrates the format of the intersection information with layers on the intersection buffer. As shown in FIG. 14, in the intersection information of the embodiment, the reserved area (Reserved) is the layer number (Layer [3: 0]) in FIG. 16 of the comparative example. In the example of FIG. 14, the layer number is set with 4 words.

  FIG. 15 illustrates a configuration of an information processing apparatus including the image processing apparatus 1 according to the embodiment and a CPU 102. The image processing apparatus 1 includes an edge generation unit 12, a sequencer 13, an intersection generation unit 14, a sorter 15, a span generation unit 16, an intersection buffer 17, a rasterizer 18, and a pixel processing unit 19. The edge generation unit 12, the sequencer 13, the intersection generation unit 14, the sorter 15, the span generation unit 16, the intersection buffer 17, the rasterizer 18, the pixel processing unit 19, and the like may be, for example, a DSP that executes a computer program. Further, for example, the processing of each component included in the image processing apparatus 1 may be described in a hardware description language, and the processing of each component may be executed by a hardware circuit. Further, part of the processing of each component included in the image processing apparatus 1 may be executed by the DSP using a computer program, and part of the processing may be executed by a hardware circuit.

  In the embodiment, for example, the CPU 102 executes an image processing program and delivers information including a layer number to the image processing apparatus 1 together with graphic information. On the other hand, the sequencer 13 has a register and holds the layer number of the graphic currently being processed. For example, the sequencer 13 may pass the layer number to the intersection generation unit 14 every time the graphic information is switched. The intersection generation unit 14 assigns the layer number passed from the sequencer 13 to the generated intersection information. The intersection information given the layer number is held in the intersection buffer 17. The span generation unit 16 generates a span while determining the vertical relationship of the span based on the layer number attached to the intersection information.

  On the other hand, the processing of the edge generation unit 12, sorter 15, rasterizer 18, and pixel processing unit 19 of the embodiment is the same as the processing of the edge generation unit 112, sorter 115, rasterizer 118, and pixel processing unit 119 of the comparative example, respectively. is there.

  The processing of the span generator 16 is illustrated with reference to FIGS. FIG. 16 illustrates a flowchart of span generation processing executed by the span generation unit 16. In the process of FIG. 16, first, the span generation unit 16 sets an initial value for the attention layer number (S1). The attention layer number means the layer number currently being processed. The initial value of the attention layer number is, for example, 0 indicating the lowest layer.

  Next, the span generator 16 sets an initial value for the horizontal line position (S2). The horizontal line position is, for example, a raster number in the image, and is exemplified by a vertical number (0 to H-1) of the intersection buffer 117 in FIG. In the embodiment, the configuration of the intersection buffer is the same as that in FIG. 8 of the comparative example. Further, along with the process of S2, the span generator 16 clears the cover value information of each layer to zero. That is, an initial value indicating a state where there is no overlap with the edge is set for each layer.

  Next, the span generator 16 sets the intersection buffer read initial position on the horizontal line currently being processed (S3). The intersection buffer reading position is exemplified by the horizontal number (0 to k−1) of the intersection buffer 117 in FIG. 8, for example. The intersection buffer read initial position is 0, for example.

  And the span production | generation part 16 performs an intersection process (S4). The intersection process is a process of calculating a cover value indicating the relationship between the edge and the pixel at the intersection coordinates of the horizontal line and the graphic edge, and calculating a span indicating the existence range on the horizontal line of the graphic with higher layer priority. Details of S4 will be described later with reference to FIGS.

  After executing the processing at one intersection point coordinate in S4, the span generator 16 determines whether or not there is a next intersection point on the current horizontal line (S5). If there is a next intersection on the current horizontal line, the span generator 16 returns the control to S4. On the other hand, when there is no next intersection on the current horizontal line, the span generator 16 updates the horizontal line and clears the cover value information of each layer to 0 (S6). Then, the span generator 16 determines whether or not the processing for all the horizontal lines has been completed (S7). If the processing for all horizontal lines has not been completed, the span generator 16 returns the control to S3. That is, the span generation unit 16 executes processing from the intersection buffer read initial position on the next horizontal line.

  On the other hand, if it is determined in S7 that all horizontal lines have been processed, the span generator 16 updates the target layer number (S8). Then, the span generator 16 determines whether or not the processing of all layer numbers has been completed (S9). Note that the maximum value of the layer number is transferred from the CPU 102 to the span generation unit 16 through the sequencer 13, for example. If the processing of all layer numbers has not been completed for the current horizontal line, the span generator 16 returns the control to S2. That is, the process is executed from the initial position of the horizontal line at the new attention layer number.

  On the other hand, when all the layers have been processed, the span generation unit 16 ends the span generation processing. In the process of FIG. 16, the attention layer number is updated in the outer loop, and the horizontal line is updated in the inner loop. However, the processing of the span generator 16 is not limited to FIG. For example, the span generation unit 16 may update the horizontal line in the outer loop and update the attention layer number of the inner loop.

  FIG. 17 illustrates details of the intersection process (S4 in FIG. 16). In the process of FIG. 17, the span generator 16 calculates a cover value and a span at one intersection coordinate on the horizontal line.

  In the example of FIG. 17, first, the span generator 16 reads the intersection information from the intersection buffer (S40). And the span production | generation part 16 determines whether the layer number of the read intersection information is a lower layer than an attention layer number (S41). If the layer number of the read intersection information is greater than or equal to the target layer number, the span generation unit 16 calculates span cover value information for each layer based on the cover value information of the read intersection information (S42).

  In the process of S42, the span generator 16 first executes a process similar to the process shown in FIGS. 9 and 11 of the comparative example. That is, the span generator 16 determines whether the edge is upward or downward on the intersection. Then, when the intersection information indicates an upward edge, the span generator 16 adds each word of the cover value information of the intersection read in S41 to each word of the current cover value information of the span in the layer indicated by the intersection information. Is added. On the other hand, when the intersection information indicates a downward edge, the span generation unit 16 selects each word of the cover value information of the intersection read in S41 from each word of the current cover value information of the span in the layer indicated by the intersection information. Is subtracted.

  Then, the span generator 16 calculates the cover value of the intersection in each span based on the cover value information of the subpixel at each intersection coordinate. The process of calculating the cover value at the intersection in each span based on the sub-pixel cover value information is the same as the process illustrated according to FIG. 12 in the comparative example. That is, the span generation unit 16 may obtain a ratio between the number of subpixels other than 0 and the total number of subpixels included in the pixel. In addition, the span generation unit 16 adds sub-pixel cover value information (Mark1 [0: 3], Mark2 [0: 3], Mark3 [0: 3], Mark4 [0: 3]) added values for each bit) The ratio of the odd number of subpixels to the total number of subpixels included in the pixel may be obtained. If the layer number of the read intersection information is lower than the target layer number, the span generation unit 16 proceeds to S43 as it is without executing the process of S42. Then, the span generator 16 determines whether or not the coordinates of the intersection of the next intersection information on the intersection buffer are the same as the coordinates of the intersection of the intersection information currently being processed (S43). Here, the same coordinate of the intersection means that the two intersections overlap. If the coordinates of the next intersection are the same as the coordinates of the intersection currently being processed, the span generator 16 returns the control to S40. That is, the span generation unit 16 performs the intersection process of FIG. 17 on all intersection information having overlapping intersection coordinates.

  On the other hand, when the coordinate of the next intersection is different from the coordinate of the intersection currently being processed, the span generator 16 temporarily stores the next intersection information in a register or the like (S44). Hereinafter, the intersection coordinate of the intersection information temporarily stored in the register is X2. Note that the intersection coordinates of the current intersection information read in S40 are set to X1 in the following processing.

  And the span production | generation part 16 performs a span calculation (S45). In the span calculation, the start of the span, the end of the span, or the continuation of the span is determined based on a plurality of pieces of intersection information having the same intersection coordinates or single intersection information.

  FIG. 18 illustrates details of span calculation (S45 in FIG. 17). That is, when the cover value at the intersection coordinate X1 of the upper layer is larger than 0.0 and the span of the upper layer is not continued, the span generation unit 16 sets the pixel of the intersection coordinate X1 as the start point of the upper layer span. Here, the span non-continuation means a state where the span start point is not set. Further, the span generator 16 calculates the cover value of the pixel immediately adjacent to the start point, and sets the cover value up to the next intersection (S451).

  Further, when the cover value of the next intersection X2 of the upper layer is 0.0 and the span of the upper layer is continuing, the span generation unit 16 sets the pixel of the coordinate X2-1 next to the left of the next intersection X2 to the upper layer. Is set to the end point of the span (S452). Next, the span generator 16 determines whether or not there is an upper layer with a cover value of 1 at the intersection coordinate X1 (S453). When there is an upper layer with the cover value 1 at the intersection coordinate X1, and the span of the target layer is continuing, the span generator 16 determines the pixel at the coordinate X1-1 on the left side of the intersection coordinate X1 as the end point of the span of the target layer (S454). Further, in the present embodiment, the span generator 16 calculates the cover value at the current intersection coordinate X1 and the cover value at the coordinate X1 + 1 of the target layer. Then, the span generator 16 sets the cover value at the coordinate X1 + 1 as the cover value up to the next intersection. That is, in this embodiment, even when there is an upper layer having a cover value of 1, the cover value of the target layer is calculated until the cover value of the target layer becomes zero.

  Furthermore, in S454, when the target layer is not continuing and the target layer cover value is greater than 0, the span generator 16 sets the current intersection coordinate X1 as the start point of the span of the target layer. Further, the span generator 16 calculates a cover value at the current intersection coordinate X1 and a cover value at the coordinate X1 + 1 of the target layer. Then, the span generator 16 sets the cover value at the coordinate X1 + 1 as the cover value up to the next intersection. As described above, if the span of the attention layer continues at the current intersection coordinate X1 and the intersection of the upper layer changes to less than 1, the attention layer even if there is no intersection of the attention layer at the current intersection coordinate X1 It is necessary to be the start point of the span. For this reason, even when there is an upper layer with a cover value of 1, the start point is set and the cover value is calculated for the target layer.

  Thereafter, the span generator 16 ends the span calculation 1 process. On the other hand, when there is no upper layer with the cover value 1 at the intersection coordinate X, the span generation unit 16 executes the processing from S455 to S457. That is, when the cover value at the intersection coordinate X1 of the target layer is greater than 0.0 and the span of the target layer is not continued, the span generation unit 16 sets the pixel of the intersection coordinate X1 as the start point of the span of the target layer. Further, the span generator 16 calculates the cover value of the pixel immediately adjacent to the start point, and sets the cover value up to the next intersection. The cover value up to the next intersection coordinate X2 of the target layer is referred to as the current cover value. Further, the span generator 16 sends span information from the intersection point coordinate X1 to the next intersection point coordinate X2-1 to the rasterizer 18 (S455). Therefore, in the process of the present embodiment, the span is once ended even if the cover value of the next intersection X2 is not zero. However, instead of the processing of S455, the span generation unit 16 continues the span until the cover value of the next intersection X2 becomes 0, and when the cover value of the next intersection X2 becomes 0, the span information is displayed. It may be sent to the rasterizer 18.

  Further, the span generator 16 has no attention layer at the current intersection X1, the current cover value of the attention layer is greater than 0.0, and the cover value of the upper layer is less than 1.0 at the current intersection X1. If changed, the current intersection point X1 is set as the start point of the span (S456). The process of S456 corresponds to the appearance of the attention layer that is hidden in the upper layer and is continuing the span. In this case, the span of the target layer hidden in the upper layer starts.

  Furthermore, when the cover value of the next intersection point X2 of the attention layer is 0.0 and the span of the attention layer is continuing, the span generation unit 16 determines the pixel at the coordinate X2-1 next to the left of the next intersection point X2 coordinate. The end point of the span of the target layer is set (S457).

If the upper layer does not exist by repeating the procedure of FIG. 18 for each intersection coordinate, the start point of the span of the target layer is set in S455. On the other hand, even when an upper layer having a cover value of 1 exists at the intersection coordinates, as described in the description of S454, the current cover value from the start point of the span of the target layer to the next intersection point is set. That is, in this embodiment, even when the cover value of the upper layer is 1 or more, the start point and the cover value of the target layer are calculated temporarily.

  However, when the upper layer cover value is 1, the determination in S453 is YES, and the processing from S455 to S457 is omitted. As a result, when an upper layer having a cover value of 1 exists at the intersection, output of span information for the target layer is omitted. Therefore, in the range hidden by the graphic of the upper layer, the pixel of the span is not generated, and the graphic processing device 1 can efficiently create the pixel in vector graphics.

  Further, in the repetition of the span calculation 1 process (FIG. 18) for a plurality of intersection coordinates, when the intersection of the upper layer is reached on the horizontal line, the end point of the span of the target layer is set by the process of S452. When the right edge of the figure of the target layer is reached on the horizontal line, the end point of the span of the target layer is set by the processing in S457.

(Modification)
In FIGS. 17 and 18, the cover value at the intersection is calculated as a value between 0 and 1 obtained from the cover value information of the subpixel. However, instead of such a procedure, the cover value of the intersection may be limited to 0 or 1. For example, the graphic processing apparatus 1 stores the presence / absence of an intersection by a 1-bit flag indicating the presence / absence of an intersection in place of Mark1 [3: 0] to Mark4 [3: 0] in the intersection information of FIG. Good. In that case, as the cover value calculation of the intersection point in S43 of FIG.

  FIG. 19 illustrates details of span calculation (S45 in FIG. 17) when the cover value is limited to 0 or 1. That is, when the cover value at the intersection coordinate X1 of the upper layer is 1 and the span of the upper layer is not continued, the span generator 16 sets the pixel of the intersection coordinate X1 as the start point of the upper layer span ( T451).

  Further, when the cover value of the next intersection coordinate X2 of the upper layer is 0 and the span of the upper layer is continuing, the span generation unit 16 sets the pixel of the coordinate X2-1 next to the left of the next intersection coordinate X2 to the upper layer Is set to the end point of the span (T452).

  Next, the span generator 16 determines whether or not there is an upper layer with a cover value of 1 at the intersection coordinate X1 (T453). When there is an upper layer of the cover value 1 at the intersection coordinate X1, and the span of the target layer is continuing, the span generator 16 sets the pixel of the coordinate X1-1 next to the left of the intersection coordinate X1 to the span of the target layer. The end point is set (T454). Further, in T454, when the target layer is not continuing and the target layer cover value is 1, the span generation unit 16 sets the current intersection coordinate X1 as the start point of the span of the target layer. Further, the cover value at the current intersection coordinate X1 and the cover value at the coordinate X1 + 1 of the target layer are calculated. Then, the span generator 16 sets the cover value at the coordinate X1 + 1 as the cover value up to the next intersection. This process is the same as S454.

  On the other hand, when there is no upper layer with the cover value 1 at the intersection coordinate X1, the span generation unit 16 executes the processing from T455 to T457. That is, when the cover value at the intersection coordinate X1 of the attention layer is 1 and the span of the attention layer is not continued, the span generation unit 16 sets the pixel of the intersection coordinate X1 as the start point of the span of the attention layer. Further, the cover value from the right adjacent to the current intersection coordinate X1 to the next intersection coordinate X2 is set to 1. Then, the span generator 16 sends span information from the current intersection point X1 to the next intersection point X2-1 to the rasterizer 1 (T455).

Further, the span generation unit 16 does not have the attention layer at the current intersection X1, the current cover value of the attention layer is 1, and the cover value of the upper layer changes to 0 at the current intersection X1, Is set as the span start point (T456). The process of T456 is the same as that of S456. Furthermore, when the cover value of the next intersection coordinate X2 of the target layer is 0 and the span of the target layer is continuing, the span generator 16 pays attention to the pixel of the next adjacent coordinate X2-1 on the left side of the next intersection coordinate X2. The end point of the span of the layer is set (T457).

  As described above, even when the cover value is limited to 0 or 1 and the cover value is not calculated by sub-pixels, it is efficient from the relationship between the upper layer and the lower layer of the figure as in FIGS. Pixel generation is possible.

  That is, when the cover value of the upper layer is 1, the determination at T453 is YES, and the processing from T455 to T457 is omitted. As a result, when an upper layer having a cover value of 1 exists at the intersection, output of span information for the target layer is omitted. Therefore, in the range hidden by the graphic of the upper layer, the pixel of the span is not generated, and the graphic processing device 1 can efficiently create the pixel in vector graphics.

  Further, in the repetition of the span calculation 2 process (FIG. 19) for a plurality of intersection coordinates, when the intersection of the upper layer is reached on the horizontal line, the end point of the span of the target layer is set by the process of T452. When the right edge of the figure of the attention layer is reached on the horizontal line, the end point of the span of the attention layer is set by the process of T456.

  When the processing of FIG. 19 is compared with FIG. 18, in FIG. 18, the cover value of the intersection can take a value in the range of 0 to 1, so that the graphic of the upper layer becomes translucent and the graphic of the lower layer In some cases, the span generation unit 16 maintains the cover value from the start point to the next intersection (S455 in FIG. 18). On the other hand, in FIG. 19, since the cover value is either 0 or 1, the cover value is fixed from the start point to the end point, and the span generator 16 maintains the cover value from the start point to the next intersection. There is no need to do this (T455 in FIG. 19).

(Other)
Hereinafter, a difference between the pixel processing in the vector graphics described in the present embodiment and the Z buffer method in the three-dimensional graphics will be described. In the Z buffer method used for hidden surface processing in three-dimensional graphics, the graphic processing apparatus has depth information (Z value) in pixel units and compares Z values in pixel units. On the other hand, since the graphic processing apparatus 1 according to the present embodiment performs processing in units of spans, which are sets of pixels, it can perform hidden surface processing more efficiently.

<Computer-readable recording medium>
A program for causing a computer or other machine or device (hereinafter, a computer or the like) to realize any of the above functions can be recorded on a recording medium that can be read by the computer or the like. The function can be provided by causing a computer or the like to read and execute the program of the recording medium.

  Here, a computer-readable recording medium is a recording medium that stores information such as data and programs by electrical, magnetic, optical, mechanical, or chemical action and can be read from a computer or the like. Say. Examples of such a recording medium that can be removed from a computer or the like include a flexible disk, a magneto-optical disk, a CD-ROM, a CD-R / W, a DVD, a Blu-ray disk, a DAT, an 8 mm tape, a flash memory, and the like. There are cards. In addition, as a recording medium fixed to a computer or the like, there are a hard disk, a ROM (read only memory), and the like.

1 Graphic Processing Device 12 Edge Generation Unit 13 Sequencer 14 Intersection Generation Unit 15 Sorter 16 Span Generation Unit 17 Intersection Buffer 18 Rasterizer 19 Pixel Processing Unit

Claims (6)

An intersection generation unit for generating intersection information including the position of the intersection between the boundary line of the graphic and the arrangement of pixels in the scanning line direction of the image, and layer information indicating a hierarchical relationship between the graphic and the other graphic;
Excluding the existence range of the graphic of the upper layer in the hierarchical relationship, the intersection (starting point) of one boundary line of the graphic intersecting the scanning line of the image and the scanning line, and the other boundary line and the scanning line of the graphic span generation section for generating a span that will be defined by the intersection (end point) and,
An image processing apparatus comprising: a rasterizer that generates a set of pixels included in the span . The intersection generation unit divides the pixel at the intersection position into a plurality of subpixels, sets cover information indicating a range covered by the boundary of the figure for each subpixel,
The span generation unit calculates a cover value indicating a ratio of a portion where a boundary line passes through the pixel to the pixel based on the cover information of the sub-pixel, and the presence of the graphic of the upper layer according to the cover value The image processing apparatus according to claim 1, wherein a range and each intersection point are determined. An intersection generation step in which the computer generates intersection information including the position of the intersection between the boundary line of the graphic and the arrangement of pixels in the scanning line direction, and layer information indicating a hierarchical relationship between the graphic and the other graphic;
Excluding the existence range of the graphic of the upper layer in the hierarchical relationship, the intersection (starting point) of one boundary line of the graphic intersecting the scanning line of the image and the scanning line, and the other boundary line and the scanning line of the graphic and span generation step of generating a span that will be defined by the intersection (end point) and,
Generating a set of pixels included in the span . The intersection generation step has a step of dividing the pixel at the intersection position into a plurality of subpixels and setting cover information indicating a range covered by the boundary of the figure for each subpixel,
The span generation step calculates a cover value indicating a ratio of a portion through which a boundary line passes in the pixel to the pixel based on the cover information of the sub-pixel, and the presence of the graphic of the upper layer according to the cover value The image processing method according to claim 3, further comprising a step of determining a range and each intersection point. An intersection generation step for generating intersection information including, on a computer, a position of an intersection between the boundary line of the figure and the arrangement of pixels in the scanning line direction, and layer information indicating a hierarchical relationship between the figure and another figure;
Excluding the existence range of the graphic of the upper layer in the hierarchical relationship, the intersection (starting point) of one boundary line of the graphic intersecting the scanning line of the image and the scanning line, and the other boundary line and the scanning line of the graphic and span generation step of generating a span that will be defined by the intersection (end point) and,
Generating a set of pixels included in the span . The intersection generation step has a step of dividing the pixel at the intersection position into a plurality of subpixels and setting cover information indicating a range covered by the boundary of the figure for each subpixel,
The span generation step calculates a cover value indicating a ratio of a portion through which a boundary line passes in the pixel to the pixel based on the cover information of the sub-pixel, and the presence of the graphic of the upper layer according to the cover value The program according to claim 5, further comprising a step of determining a range and each of the intersections.

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