JP5656229B2 - Variable resistance nonvolatile memory element - Google Patents
Variable resistance nonvolatile memory element Download PDFInfo
- Publication number
- JP5656229B2 JP5656229B2 JP2011141308A JP2011141308A JP5656229B2 JP 5656229 B2 JP5656229 B2 JP 5656229B2 JP 2011141308 A JP2011141308 A JP 2011141308A JP 2011141308 A JP2011141308 A JP 2011141308A JP 5656229 B2 JP5656229 B2 JP 5656229B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- voltage
- resistance state
- memory element
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000008859 change Effects 0.000 claims description 35
- 230000010287 polarization Effects 0.000 claims description 12
- 230000007812 deficiency Effects 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 230000002950 deficient Effects 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 description 14
- 239000001301 oxygen Substances 0.000 description 14
- 229910004121 SrRuO Inorganic materials 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 239000000126 substance Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- -1 oxygen ions Chemical class 0.000 description 6
- 230000003446 memory effect Effects 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 230000004075 alteration Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 230000003252 repetitive effect Effects 0.000 description 4
- 229910000314 transition metal oxide Inorganic materials 0.000 description 4
- 229910002367 SrTiO Inorganic materials 0.000 description 3
- 229910052797 bismuth Inorganic materials 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000004993 emission spectroscopy Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Description
本発明は、不揮発性メモリに関し、特に遷移金属酸化物半導体を用いた不揮発性メモリ素子に関する。 The present invention relates to a nonvolatile memory, and more particularly to a nonvolatile memory element using a transition metal oxide semiconductor.
絶縁体または半導体の遷移金属酸化物を金属電極間に挟み込んだ素子に外部電圧を印加すると電気抵抗の巨大変化が発現することが知られている。
この抵抗スイッチング現象を利用した抵抗変化型メモリＲｅｓｉｓｔａｎｃｅ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ（以下ＲeＲＡＭと記す）は、巨大抵抗変化率に加えて小消費電力、高密度化、高速動作などの利点が望まれて、次世代不揮発性メモリとして有望視されて精力的な研究が行われている。
It is known that when an external voltage is applied to an element in which an insulator or a semiconductor transition metal oxide is sandwiched between metal electrodes, a huge change in electrical resistance appears.
A resistance random access memory (hereinafter referred to as “ReRAM”) using this resistance switching phenomenon is expected to have advantages such as small power consumption, high density, and high speed operation in addition to a large resistance change rate. It is considered promising as a non-volatile memory, and intensive research is being conducted.
抵抗スイッチング動作原理の起源としてはこれまでに、導電性フィラメントの形成とその導電性フィラメントの酸化還元反応（非特許文献１）や、酸素イオン・酸素欠陥の移動による界面接触抵抗の変化等の機構（非特許文献２）が報告されている。 The origin of the resistive switching operation principle is the formation of conductive filaments and the oxidation-reduction reaction of the conductive filaments (Non-Patent Document 1) and the mechanism of changes in interface contact resistance due to the movement of oxygen ions and oxygen defects. (Non-Patent Document 2) has been reported.
例えば、酸素イオンの移動による界面接触抵抗の変化を利用したＲeＲＡＭとしては、Ｐｒ1-xＣａxＭｎＯ3やＳｒＴｉＯ3などペロブスカイト型酸化物と金属材料を積層したキャパシタンス型の薄膜素子があり、導電性フィラメントの形成を利用したＲeＲＡＭとしては、ＮｉＯやＴｉＯ2などの二元系酸化物と金属材料を積層したキャパシタンス型の薄膜素子がある（非特許文献２）。
界面接触抵抗の変化を利用したＲeＲＡＭに極性の異なったパルス電圧を印加することにより、素子抵抗が可逆的に変化することを利用した不揮発性メモリ素子が報告されている（特許文献１）。
For example, as a ReRAM using a change in interfacial contact resistance due to the movement of oxygen ions, there is a capacitance type thin film element in which a perovskite type oxide such as Pr 1-x Ca x MnO 3 or SrTiO 3 and a metal material are laminated, As a ReRAM utilizing the formation of a conductive filament, there is a capacitance-type thin film element in which a binary oxide such as NiO or TiO 2 and a metal material are stacked (Non-patent Document 2).
There has been reported a non-volatile memory element utilizing the fact that the element resistance is reversibly changed by applying a pulse voltage having a different polarity to the ReRAM utilizing the change in interface contact resistance (Patent Document 1).
また、電圧を印加することでＢｉＦｅＯ3中の酸素欠陥が移動するモデルとしては、Ｂｉの一部をＣａで置換したＢｉＦｅＯ3をＳｒＲｕＯ3電極で挟んだ構造を有する素子が報告されている（非特許文献３）。
しかしこれらの動作原理によるメモリ抵抗変化の発現は、メモリ素子の化学的な変質に由来するものと言え、従ってメモリ素子の動作原理としては破壊的であったり、またメモリ抵抗状態の安定的な制御が困難であったりする。
In addition, as a model in which oxygen defects in BiFeO 3 move when a voltage is applied, an element having a structure in which BiFeO 3 in which part of Bi is replaced by Ca is sandwiched between SrRuO 3 electrodes has been reported (non-native). Patent Document 3).
However, the change in memory resistance due to these operating principles can be attributed to chemical alteration of the memory element. Therefore, the operating principle of the memory element is destructive, and the memory resistance state is stably controlled. Is difficult.
上述したようにＲｅＲＡＭと呼ばれる遷移金属酸化物を用いた不揮発性メモリでは、メモリ抵抗の可逆的な変化は、電場による酸素欠陥または酸素イオンの移動により引き起こされる化学的変質のため、メモリ抵抗変化が繰り返し行われると材料の劣化が起こり、メモリ抵抗変化の繰り返し特性またメモリ抵抗状態の安定した保持特性に問題があった。
本発明は、遷移金属酸化物を用いた不揮発性メモリにおいて、メモリ抵抗の可逆的な変化を化学的変質にたよらない、従って、メモリ抵抗変化の繰り返しによる材料の劣化が起きにくい、メモリ抵抗変化の繰り返し特性に優れ、メモリ抵抗状態の安定した保持特性を有する抵抗変化型不揮発性メモリ素子を提供することを目的とする。
As described above, in a non-volatile memory using a transition metal oxide called ReRAM, a reversible change in memory resistance is caused by a chemical alteration caused by oxygen defects or movement of oxygen ions due to an electric field. When repeated, the material deteriorates, and there is a problem in the repeated characteristics of the memory resistance change and the stable retention characteristics of the memory resistance state.
In the nonvolatile memory using the transition metal oxide, the reversible change of the memory resistance does not depend on the chemical alteration. Therefore, the deterioration of the material due to the repeated change of the memory resistance hardly occurs. An object of the present invention is to provide a variable resistance nonvolatile memory element that has excellent repetitive characteristics and has stable memory resistance holding characteristics.
本発明は、上述の課題解決のため、基板上に少なくとも第一電極と第二電極とが配置されている抵抗変化型不揮発性メモリ素子であって、前記第一電極は金属からなり、前記第一電極と前記第二電極との間にＢｉが欠損することにより（Ｂｉ欠損量ｘ）導電性を有する強誘電酸化物Ｂｉ1-xＦｅＯ3 （０.１６＝＜ｘ＝＜０.１９）が形成されていて、前記第一電極と前記導電性の強誘電酸化物とは整流性接合されていて、前記第二電極と前記導電性の強誘電酸化物とはオーミック接合されていて、前記第一電極と第二電極との間に正電圧を正方向に漸次印加し続けると該メモリ素子の抵抗値は第一の閾値（極大電流が流れる電圧）を越えた前記正電圧の一定範囲で減少し、該メモリ素子は安定的に低抵抗状態となり、その後前記正電圧を除去しても前記低抵抗状態は保持されていて、前記第一電極と第二電極との間に負電圧を負方向に漸次印加し続けると該メモリ素子の抵抗値は第二の閾値（極小電流が流れる電圧）を越えた前記負電圧の一定範囲で増加し、該メモリ素子は安定的に高抵抗状態となり、その後前記負電圧を除去しても高抵抗状態は保持されていて、前記第一電極と前記導電性の強誘電酸化物との界面において、分極反転によるショットキー的障壁の変化により素子の抵抗状態が変化し、低抵抗状態だけでなく高抵抗状態においても整流特性を有することを特徴とする抵抗変化型不揮発性メモリ素子を提供する。
本発明により、該不揮発性メモリ素子は、安定的にメモリ抵抗状態が保持されて、保持されたメモリ抵抗状態は第一の閾値と第二の閾値の間にある任意の電圧を印加して非破壊的に検知することが可能となった。
さらに、該不揮発性メモリ素子の保持されたメモリ抵抗状態は、電圧の印加により生じる電気分極の反転作用により、第一の閾値より高い正電圧を印加して、または、第二の閾値より低い負電圧を印加して非破壊的にメモリ抵抗状態を更新できて、安定的に制御することが可能となった。
The present invention provides a variable resistance nonvolatile memory element in which at least a first electrode and a second electrode are disposed on a substrate in order to solve the above-described problem, wherein the first electrode is made of metal, and the first electrode Bi is deficient between one electrode and the second electrode (Bi deficiency x), and the ferroelectric oxide Bi 1-x FeO 3 having conductivity (0.16 = <x = <0.19) Is formed, the first electrode and the conductive ferroelectric oxide are rectifying bonded, the second electrode and the conductive ferroelectric oxide are ohmic bonded, When a positive voltage is gradually applied in the positive direction between the first electrode and the second electrode, the resistance value of the memory element is within a certain range of the positive voltage exceeding the first threshold (voltage through which the maximum current flows). The memory device is stably in a low resistance state, and then the positive voltage is removed. However, the low resistance state is maintained, and when a negative voltage is gradually applied in the negative direction between the first electrode and the second electrode, the resistance value of the memory element becomes the second threshold value (the minimum current is The negative voltage exceeding the flowing voltage) increases in a certain range, and the memory element is stably in a high resistance state, and the high resistance state is maintained even after the negative voltage is removed, and the first electrode The resistance state of the element changes due to the change of the Schottky barrier due to polarization inversion at the interface between the conductive ferroelectric oxide and the conductive ferroelectric oxide, and has a rectifying characteristic not only in the low resistance state but also in the high resistance state. A variable resistance nonvolatile memory element is provided.
According to the present invention, the memory resistance state of the nonvolatile memory element is stably held, and the held memory resistance state is not applied by applying an arbitrary voltage between the first threshold value and the second threshold value. It became possible to detect destructively.
Further, the retained memory resistance state of the non-volatile memory element is applied by applying a positive voltage higher than the first threshold or negative lower than the second threshold due to the inversion action of electric polarization caused by the application of voltage. The memory resistance state can be updated non-destructively by applying a voltage, and stable control can be achieved.
本発明により、Ｂｉ欠損があり導電性を有するペロブスカイト型の金属酸化物Ｂｉ 1-x ＦｅＯ 3 の有用性が明らかとなった。 According to the present invention, the usefulness of a perovskite metal oxide Bi 1-x FeO 3 having Bi deficiency and conductivity is revealed.
さらに本発明は、前記金属は、Ｐｔである前記載の抵抗変化型不揮発性メモリ素子を提供する。
本発明により、第一電極に使用するＰｔの有用性が明らかとなった。
Furthermore, the present invention provides the variable resistance nonvolatile memory element according to the above, wherein the metal is Pt.
The usefulness of Pt used for the first electrode has been clarified by the present invention.
本発明により提供される抵抗変化型不揮発性メモリ素子の抵抗変化動作原理は、化学的変質を招く電場による酸素欠陥または酸素イオンの移動を原理とせず、電子的な機構に基づき導電性の強誘電酸化物Ｂｉ1-xＦｅＯ3層の電気分極反転を原理としているため、材料の劣化を防止でき、抵抗変化の高い繰り返し特性が得られ、抵抗状態を安定的に制御して保持でき、変化した抵抗状態を非破壊的に検知できる等の改善点がある。 The resistance change operation principle of the resistance change type nonvolatile memory device provided by the present invention is not based on the principle of oxygen defect or oxygen ion movement due to an electric field that causes chemical alteration, and is based on an electronic mechanism and is a conductive ferroelectric. Since the principle of reversal of the electric polarization of the oxide Bi 1-x FeO 3 layer is used, it is possible to prevent deterioration of the material, to obtain a repetitive characteristic with a high resistance change, and to control and maintain the resistance state stably. There are improvements such as non-destructive detection of the resistance state.
以下、図１乃至図７を参照して本発明の実施形態を詳細に説明する。
図１では、基板から見て相対的に上部に位置する電極を上部電極、下部に位置する電極を下部電極とした。
以下の説明には上部電極と下部電極との用語を使用する。
請求項に記載した第一電極と第二電極はそれぞれ図１の上部電極と下部電極とに対応している。
図１の（ａ）は、本発明に係る導電性の強誘電酸化物を使用した不揮発性メモリ素子の概念的断面図であり、その作製方法は次のとおりである。
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.
In FIG. 1, the upper electrode is the upper electrode relative to the substrate and the lower electrode is the lower electrode.
In the following description, the terms upper electrode and lower electrode are used.
The first electrode and the second electrode described in the claims correspond to the upper electrode and the lower electrode in FIG. 1, respectively.
FIG. 1A is a conceptual cross-sectional view of a nonvolatile memory element using a conductive ferroelectric oxide according to the present invention, and the manufacturing method thereof is as follows.
まず絶縁体であるＳｒＴｉＯ3酸化物単結晶基板上に、オーミック電極となるＳｒＲｕＯ3のような高い導電性を有する酸化物を、基板温度７００℃、酸素圧力１００ｍＴｏｒｒの作製条件で、パルスレーザーデポジションにより５０ｎｍ厚に形成する。
続いてその上に、基板温度７００℃、酸素圧力３０ｍＴｏｒｒの作製条件で導電性の強誘電体となる、Ｂｉ1-xＦｅＯ3を１００ｎｍ厚に形成した。
First, on a SrTiO 3 oxide single crystal substrate that is an insulator, an oxide having high conductivity such as SrRuO 3 that becomes an ohmic electrode is subjected to pulsed laser deposition under the conditions of a substrate temperature of 700 ° C. and an oxygen pressure of 100 mTorr. To a thickness of 50 nm.
Subsequently, Bi 1-x FeO 3 , which becomes a conductive ferroelectric material under a production condition of a substrate temperature of 700 ° C. and an oxygen pressure of 30 mTorr, was formed thereon with a thickness of 100 nm.
その後、室温で電子線蒸着によりＢｉ1-xＦｅＯ3上に金属Ｐｔを１０ｎｍ厚形成し、さらに金属Ａｕを１００ｎｍ厚形成し、Ａｕ/Ｐｔ/Ｂｉ1-xＦｅＯ3/ＳｒＲｕＯ3積層構造を作製した。
作製した積層構造は、フォトリソグラフィーとＡｒイオンミリングにより素子面積１００μｍ×１００μｍに加工し、Ａｕ/Ｐｔ/Ｂｉ1-xＦｅＯ3/ＳｒＲｕＯ3接合からなるメモリ素子とした。
Then, 10 nm thick metal Pt is formed on Bi 1-x FeO 3 by electron beam evaporation at room temperature, and 100 nm thick metal Au is further formed to produce an Au / Pt / Bi 1-x FeO 3 / SrRuO 3 laminated structure. did.
The fabricated laminated structure was processed into a device area of 100 μm × 100 μm by photolithography and Ar ion milling to obtain a memory device composed of an Au / Pt / Bi 1-x FeO 3 / SrRuO 3 junction.
Ｂｉ1-xＦｅＯ3膜にＢｉ欠損を導入するため、パルスレーザーデポジションの原料であるセラミックターゲットに含まれるＢｉとＦｅの組成比率を調整した。
作製したＢｉ1-xＦｅＯ3膜のＢｉ欠損量ｘは、誘導結合プラズマ発光分析により測定した。
Ｂｉが欠損すると、Ｂｉ1-xＦｅＯ3に導電性を担う正孔が生成され、Ｂｉ1-xＦｅＯ3はいわゆるｐ型半導体的特性を示す。
In order to introduce Bi deficiency into the Bi 1-x FeO 3 film, the composition ratio of Bi and Fe contained in the ceramic target, which is a raw material for pulse laser deposition, was adjusted.
The amount of Bi deficiency x in the produced Bi 1-x FeO 3 film was measured by inductively coupled plasma emission spectrometry.
When Bi is deficient, Bi 1-x FeO 3 generates holes responsible for conductivity, and Bi 1-x FeO 3 exhibits so-called p-type semiconductor characteristics.
図２は、上述したＢｉ欠損量ｘがあり、導電性を有しているＢｉ1-xＦｅＯ3が強誘電体の特性を有していることを確認するために、Ｂｉ欠損量ｘが０．１９の導電性のＢｉ1-xＦｅＯ3で作製したＢｉ1-xＦｅＯ3／ＳｒＲｕＯ3積層構造の表面を、ピエゾ応答フォース顕微鏡で観測した結果を示す図である。
最初にピエゾ応答フォース顕微鏡の探針に−８Ｖを印加して外側の点線で囲んだ１μｍ×１μｍの領域を走査し、その後、ピエゾ応答フォース顕微鏡の探針に＋８Ｖを印加して内側の点線で囲んだ０．５μｍ×０．５μｍの領域を走査し、最後にピエゾ応答フォース顕微鏡の探針に＋３Ｖを印加して表面全体を走査して、Ｂｉ1-xＦｅＯ3の電気分極の方向を評価した。
FIG. 2 shows that the Bi deficiency amount x is 0 and the Bi deficiency amount x is 0 in order to confirm that Bi 1-x FeO 3 having conductivity has ferroelectric characteristics. . 19 is a diagram showing a result of observing the surface of a Bi 1-x FeO 3 / SrRuO 3 stacked structure made of 19 conductive Bi 1-x FeO 3 with a piezoelectric response force microscope.
First, -8V is applied to the probe of the piezo response force microscope to scan the 1 μm × 1 μm region surrounded by the outer dotted line, and then +8 V is applied to the probe of the piezo response force microscope with the inner dotted line. Scan the enclosed 0.5 μm × 0.5 μm area, and finally apply +3 V to the probe of a piezo response force microscope to scan the entire surface to evaluate the direction of electrical polarization of Bi 1-x FeO 3 did.
その結果、−８Ｖを印加して走査した外側の点線で囲んだ１μｍ×１μｍの領域ではＢｉ1-xＦｅＯ3の電気分極は表面からＳｒＲｕＯ３電極方向を向き、＋８Ｖを印加して走査した内側の点線で囲んだ０．５μｍ×０．５μｍの領域では電気分極はＳｒＲｕＯ3電極から表面方向を向いている。
したがって、Ｂｉ1-xＦｅＯ3はＢｉ欠損量ｘがあり導電性を有しても強誘電体としての特性も有していることがわかる。
すなわち、Ｂｉ欠損量ｘがあるＢｉ1-xＦｅＯ3は導電性の強誘電体であることがわかる。
As a result, in the region of 1 μm × 1 μm surrounded by the outer dotted line scanned by applying −8V, the electrical polarization of Bi 1-x FeO 3 faces the SrRuO 3 electrode direction from the surface and is scanned by applying + 8V. In the region of 0.5 μm × 0.5 μm surrounded by the dotted line, the electric polarization faces the surface direction from the SrRuO 3 electrode.
Therefore, it can be seen that Bi 1-x FeO 3 has a Bi deficiency x and has a property as a ferroelectric substance even if it has conductivity.
That is, it can be seen that Bi 1-x FeO 3 having the Bi deficiency x is a conductive ferroelectric substance.
図３の（ａ）は、本発明のメモリ素子の電流−電圧特性の室温における測定結果を示す図である。
この素子のＢｉ1-xＦｅＯ3のＢｉ欠損量ｘは０．１６であり、導電性を有している。
図３において、プラス方向は、図１に示すメモリ素子の下部から上部に電流を流す方向である。
FIG. 3A is a diagram showing the measurement results at room temperature of the current-voltage characteristics of the memory element of the present invention.
The Bi d -x amount of Bi 1-x FeO 3 of this element is 0.16, and it has conductivity.
In FIG. 3, the plus direction is a direction in which current flows from the lower part to the upper part of the memory element shown in FIG.
図３の（ａ）によれば、素子にプラス方向の電圧を印加すると、ある閾値電圧（図３の（ａ）では約＋６．５Ｖ）以上の電圧で素子に流れる電流値が急激に変化して電流極大が現れた後、低抵抗状態へと転移する。
その後電圧を下げてもその低抵抗状態は維持される。
さらに素子に印加する電圧の極性をマイナスにすると、ある閾値電圧（図３の（ａ）では約−２．５Ｖ）以下の電圧で電流値は急激に変化して電流極小が現れた後、高抵抗状態へと転移する。
その後電圧を戻しても高抵抗状態は維持される。
According to FIG. 3A, when a positive voltage is applied to the element, the value of the current flowing through the element at a certain threshold voltage (about +6.5 V in FIG. 3A) suddenly changes. After the current maximum appears, the state transitions to a low resistance state.
Even if the voltage is lowered thereafter, the low resistance state is maintained.
Further, if the polarity of the voltage applied to the element is negative, the current value suddenly changes at a voltage below a certain threshold voltage (about −2.5 V in FIG. 3A), and a current minimum appears. Transition to a resistance state.
After that, even if the voltage is returned, the high resistance state is maintained.
すなわち、素子に印加する電圧の極性を変えて閾値電圧以上の電圧を印加することにより、素子の抵抗状態を低抵抗状態と高抵抗状態の間で可逆に変化する、電界・電流誘起抵抗変化メモリ効果が実現されている。
素子の低抵抗状態をセット“１”、高抵抗状態をリセット“０”と定義した時、素子の抵抗状態を読み出すための電圧をプラス方向及びマイナス方向の閾値電圧の間の任意の電圧に設定することで、素子の抵抗状態を非破壊で読み出すことが可能である。
That is, by changing the polarity of the voltage applied to the element and applying a voltage higher than the threshold voltage, the resistance state of the element reversibly changes between a low resistance state and a high resistance state, and an electric field / current induced resistance change memory. The effect is realized.
When the low resistance state of the element is defined as “1” and the high resistance state is defined as “0”, the voltage for reading the resistance state of the element is set to any voltage between the threshold voltages in the positive and negative directions. By doing so, it is possible to read the resistance state of the element nondestructively.
図３の（ｂ）は、比較のため、図１に示すメモリ素子において、上部電極の金属のＰｔに代えて酸化物のＳｒＲｕＯ3を電極としたものである。
この場合には電流−電圧特性はヒステリシスを有さないオーミックな特性であることから、抵抗変化メモリ効果は発現しない。
したがって、本発明に係る導電性の強誘電酸化物を使用した不揮発性メモリ素子において、ＰｔとＢｉ1-xＦｅＯ3界面の電気的特性は非オーミックコンタクトであり、図３の（ａ）に示すヒステリシスを有する電流−電圧特性は、この界面で発現していることがわかる。
For comparison, FIG. 3B shows an oxide SrRuO 3 electrode instead of the upper electrode metal Pt in the memory element shown in FIG.
In this case, since the current-voltage characteristics are ohmic characteristics having no hysteresis, the resistance change memory effect does not appear.
Therefore, in the nonvolatile memory element using the conductive ferroelectric oxide according to the present invention, the electrical characteristic of the interface between Pt and Bi 1-x FeO 3 is a non-ohmic contact, and is shown in FIG. It can be seen that the current-voltage characteristics having hysteresis are manifested at this interface.
図４は、Ｐｔ電極とＢｉ1-xＦｅＯ3の界面のバンド構造の模式図（高抵抗状態、低抵抗状態）である。
Ｐｔの仕事関数は約５．７ｅＶであるのに対して、ｐ型の導電性を有するＢｉ1-xＦｅＯ3の価電子帯のトップは約６ｅＶであることから、Ｂｉ1-xＦｅＯ3の価電子帯のトップ（ＥＶ）はＰｔのフェルミ面（ＥＦ）よりも深いエネルギーに位置し、界面にショットキー的な障壁が形成される。
このようなショットキー的な障壁が形成されるため、図３の（ａ）のような電圧の極性に対して非対称な電流‐電圧特性、すなわち、整流特性が観測される。
FIG. 4 is a schematic diagram (high resistance state, low resistance state) of the band structure at the interface between the Pt electrode and Bi 1-x FeO 3 .
The work function of Pt is about 5.7 eV, whereas the top of the valence band of Bi 1-x FeO 3 having p-type conductivity is about 6 eV, so that Bi 1-x FeO 3 The top (E V ) of the valence band is located at a deeper energy than the Fermi surface (E F ) of Pt, and a Schottky barrier is formed at the interface.
Since such a Schottky barrier is formed, a current-voltage characteristic that is asymmetric with respect to the voltage polarity as shown in FIG.
電気分極は、Ｂｉ1-xＦｅＯ3のバンド構造に電場の勾配を与えるため、電気分極の向きに依存してＢｉ1-xＦｅＯ3の正孔に対するショットキー的な障壁の高さと厚さ（ＷＤ）が変化する。
電気分極の反転により界面に形成されたショットキー的な障壁の高さと厚さが変化することが、界面における正孔の導電特性の変化、すなわち抵抗変化の動作機構である。
Electric polarization, Bi 1-x to give the band structure of FeO 3 the gradient of the electric field, the Schottky barriers depending on the electric polarization orientation for a hole in the Bi 1-x FeO 3 height and thickness ( W D ) changes.
The change in the height and thickness of the Schottky barrier formed at the interface due to the reversal of the electric polarization is the operating mechanism of the change in the conductive property of holes at the interface, that is, the resistance change.
図５は、本発明に係る不揮発性メモリ素子構造にパルス電圧を印加した場合の抵抗変化の室温における測定結果を示す図である。
図５において、プラス方向は、図１に示すメモリ素子の下部から上部に電流を流す方向である。
この測定結果では、素子抵抗は＋１Ｖの電圧印加した状態で素子に流れる電流値を測定することで得られる値である。
FIG. 5 is a diagram showing a measurement result of a resistance change at room temperature when a pulse voltage is applied to the nonvolatile memory element structure according to the present invention.
In FIG. 5, the plus direction is a direction in which current flows from the lower part to the upper part of the memory element shown in FIG.
In this measurement result, the element resistance is a value obtained by measuring a current value flowing through the element in a state where a voltage of +1 V is applied.
素子にプラスのパルス電圧（図５では＋７Ｖ）を印加することにより素子の抵抗状態が低抵抗状態（ＲＬ）へと変化し、マイナスの電圧パルス（図５では−７Ｖ）を印加することで、素子の抵抗状態が高抵抗状態（ＲＨ）へと変化する。
すなわち、素子に印加するパルス電圧の極性を変えることにより、素子の抵抗状態を低抵抗状態と高抵抗状態の間で可逆に変化する、抵抗変化メモリ効果が実現されている。パルス電圧幅（時間）が増加すると抵抗変化比（ＲＨ／ＲＬ）は増加する。
By applying a positive pulse voltage (+7 V in FIG. 5) to the element, the resistance state of the element is changed to a low resistance state (R L ), and by applying a negative voltage pulse (−7 V in FIG. 5). The resistance state of the element changes to the high resistance state (R H ).
That is, a resistance change memory effect is realized in which the resistance state of the element is reversibly changed between the low resistance state and the high resistance state by changing the polarity of the pulse voltage applied to the element. As the pulse voltage width (time) increases, the resistance change ratio (R H / R L ) increases.
図６の（ａ）は、本発明に係る不揮発性メモリ素子構造に、時間幅１μｓ、電圧＋７Ｖと−７Ｖのパルス電圧を交互に１００万回ずつ印加した場合の抵抗変化の繰り返し書き換え特性を測定した結果を示す図である。
１桁以上の抵抗変化が１０万回以上の繰り返しまで維持されている。
FIG. 6A shows the repetitive rewriting characteristics of resistance change when a time width of 1 μs and voltage pulses of +7 V and −7 V are alternately applied 1 million times to the nonvolatile memory element structure according to the present invention. It is a figure which shows the result.
The resistance change of one digit or more is maintained until the repetition of 100,000 times or more.
図６の（ｂ）は、Ｂｉ1-xＦｅＯ3に代わって強誘電体ではない導電性の常誘電体であるＳｍ0.7Ｃａ0.3ＭｎＯ3を用い、Ｐｔに代わって上部電極にＴｉを用いた従来構造の素子の抵抗変化の繰り返し書き換え特性を測定した結果を示す図である。
この従来構造素子では、抵抗変化メモリ効果が酸素イオンまたは酸素欠陥の移動により発現している。
この素子では、１０００回以上の繰り返し書き換えで動作しなくなった。
In FIG. 6B, Sm 0.7 Ca 0.3 MnO 3 , which is a conductive paraelectric material that is not a ferroelectric material, is used instead of Bi 1-x FeO 3 , and Ti is used for the upper electrode instead of Pt. It is a figure which shows the result of having measured the repeated rewriting characteristic of the resistance change of the element of conventional structure.
In this conventional structure element, the resistance change memory effect is manifested by the movement of oxygen ions or oxygen defects.
With this element, it stopped operating after 1000 times or more of rewrites.
図６の測定結果からわかるように、導電性の強誘電体であるＢｉが欠損したＢｉ1-xＦｅＯ3とＰｔ電極を用いることで、従来のものに比べて、データの繰り返し書き換え特性が大きく改善されていることがわかる。
これは、抵抗変化メモリ効果の動作機構として、従来型の酸素イオンまたは酸素欠陥の移動に代わり、強誘電分極の反転を用いることにより特性が改善されたものである。
As can be seen from the measurement results of FIG. 6, the use of Bi 1-x FeO 3 lacking Bi, which is a conductive ferroelectric substance, and a Pt electrode has a larger data rewrite characteristic than the conventional one. You can see that it has improved.
This is an improvement in characteristics by using the inversion of ferroelectric polarization instead of the conventional movement of oxygen ions or oxygen defects as the operation mechanism of the resistance change memory effect.
図７は、本発明に係る不揮発性メモリ素子構造の室温における低抵抗状態と高抵抗状態の保持特性の測定結果である。この測定結果では、素子抵抗は＋１Ｖの電圧印加した状態で素子に流れる電流値を測定することで得られる値である。
低抵抗状態、高抵抗状態ともに１０万秒まで抵抗変化の時間変化はほとんど見られず、１桁以上の抵抗変化比を保持し、メモリ機能を有していることがわかる。
FIG. 7 shows measurement results of retention characteristics in a low resistance state and a high resistance state at room temperature of the nonvolatile memory element structure according to the present invention. In this measurement result, the element resistance is a value obtained by measuring a current value flowing through the element in a state where a voltage of +1 V is applied.
It can be seen that in both the low resistance state and the high resistance state, the time change of the resistance change is hardly seen up to 100,000 seconds, and the resistance change ratio of one digit or more is maintained and the memory function is provided.
本実施例では、金属電極としてＰｔを使用したが、これに代えて、仕事関数が６ｅＶよりも小さく、酸化しにくいＡｕ、Ａｇ等又はそれらの合金若しくは化合物であってもよい。 In this embodiment, Pt is used as the metal electrode. Alternatively, Au, Ag, or the like, or an alloy or compound thereof having a work function smaller than 6 eV and difficult to oxidize may be used.
本発明は、高速動作、低消費電力、非破壊読出し等の特徴を有する不揮発性メモリ素子である。
よって、小電力、高速のスイッチング特性を有し耐久性のある不揮発性メモリセルアレイ、メモリ装置を製造することができ、高密度実装によりハードディスクやフラッシュメモリなどのストレージメモリの代替として利用できる。
The present invention is a nonvolatile memory device having features such as high-speed operation, low power consumption, and nondestructive reading.
Therefore, a durable non-volatile memory cell array and memory device having low power and high-speed switching characteristics can be manufactured, and can be used as an alternative to a storage memory such as a hard disk or a flash memory by high-density mounting.
１ Ａｕ
２ Ｐｔ（上部電極）
３ Ｂｉ1-xＦｅＯ3
４ ＳｒＲｕＯ3（下部電極）
５ ＳｒＴｉＯ3
６ Ｔｉ（上部電極）
７ Ｓｍ0.7Ｃａ0.3ＭｎＯ3
1 Au
2 Pt (upper electrode)
3 Bi 1-x FeO 3
4 SrRuO 3 (lower electrode)
5 SrTiO 3
6 Ti (upper electrode)
7 Sm 0.7 Ca 0.3 MnO 3
Claims (2)
前記第一電極は金属からなり、
前記第一電極と前記第二電極との間にＢｉが欠損することにより（Ｂｉ欠損量ｘ）導電性を有する強誘電酸化物Ｂｉ1-xＦｅＯ3 （０.１６＝＜ｘ＝＜０.１９）が形成されていて、
前記第一電極と前記導電性の強誘電酸化物とは整流性接合されていて、
前記第二電極と前記導電性の強誘電酸化物とはオーミック接合されていて、
前記第一電極と第二電極との間に正電圧を正方向に漸次印加し続けると該メモリ素子の抵抗値は第一の閾値（極大電流が流れる電圧）を越えた前記正電圧の一定範囲で減少し、該メモリ素子は安定的に低抵抗状態となり、その後前記正電圧を除去しても前記低抵抗状態は保持されていて、
前記第一電極と第二電極との間に負電圧を負方向に漸次印加し続けると該メモリ素子の抵抗値は第二の閾値（極小電流が流れる電圧）を越えた前記負電圧の一定範囲で増加し、該メモリ素子は安定的に高抵抗状態となり、その後前記負電圧を除去しても高抵抗状態は保持されていて、
前記第一電極と前記導電性の強誘電酸化物との界面において、分極反転によるショットキー的障壁の変化により素子の抵抗状態が変化し、低抵抗状態だけでなく高抵抗状態においても整流特性を有することを特徴とする抵抗変化型不揮発性メモリ素子。 A variable resistance nonvolatile memory element in which at least a first electrode and a second electrode are disposed on a substrate,
The first electrode is made of metal,
Bi is deficient between the first electrode and the second electrode (Bi deficiency x), and the ferroelectric oxide Bi 1-x FeO 3 (0.16 = <x = <0.0. 19) is formed,
The first electrode and the conductive ferroelectric oxide are rectifying bonded,
The second electrode and the conductive ferroelectric oxide are in ohmic contact,
When a positive voltage is gradually applied in the positive direction between the first electrode and the second electrode, the resistance value of the memory element exceeds a first threshold value (voltage at which a maximum current flows), and is within a certain range of the positive voltage. The memory element is stably in a low resistance state, and the low resistance state is maintained even after the positive voltage is removed.
When a negative voltage is gradually applied in the negative direction between the first electrode and the second electrode, the resistance value of the memory element exceeds a second threshold value (voltage at which a minimum current flows), and is within a certain range of the negative voltage. The memory element is stably in a high resistance state, and the high resistance state is maintained even after the negative voltage is removed,
At the interface between the first electrode and the conductive ferroelectric oxide, the resistance state of the element changes due to the change of the Schottky barrier due to polarization inversion, and the rectification characteristic is exhibited not only in the low resistance state but also in the high resistance state. A variable resistance nonvolatile memory element characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011141308A JP5656229B2 (en) | 2011-06-27 | 2011-06-27 | Variable resistance nonvolatile memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011141308A JP5656229B2 (en) | 2011-06-27 | 2011-06-27 | Variable resistance nonvolatile memory element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013008884A JP2013008884A (en) | 2013-01-10 |
| JP5656229B2 true JP5656229B2 (en) | 2015-01-21 |
Family
ID=47675971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011141308A Expired - Fee Related JP5656229B2 (en) | 2011-06-27 | 2011-06-27 | Variable resistance nonvolatile memory element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5656229B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6367035B2 (en) * | 2014-07-23 | 2018-08-01 | 国立研究開発法人産業技術総合研究所 | Nonvolatile memory device and manufacturing method thereof |
| JP2019012711A (en) * | 2015-11-19 | 2019-01-24 | 国立大学法人 東京大学 | Nonvolatile memory element, nonvolatile memory, and control method of nonvolatile memory |
| JP6978775B2 (en) * | 2018-01-05 | 2021-12-08 | 国立研究開発法人理化学研究所 | Photoelectric conversion element, optical sensor, power generation device, and photoelectric conversion method |
| CN113257996A (en) * | 2020-02-12 | 2021-08-13 | 中国科学院物理研究所 | Two-end neuromorphic device based on ferroelectric domain inversion |
| KR102326601B1 (en) * | 2020-04-22 | 2021-11-17 | 브이메모리 주식회사 | Electronic device and method of controlling electronic device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304880B2 (en) * | 2003-05-08 | 2007-12-04 | Matsushita Electric Industrial Co., Ltd. | Electric switch and memory device using the same |
| JP5459515B2 (en) * | 2009-02-20 | 2014-04-02 | 株式会社村田製作所 | Resistance memory element and method of using the same |
| JP2011114191A (en) * | 2009-11-27 | 2011-06-09 | Panasonic Corp | Capacitive element and method of manufacturing the same |
-
2011
- 2011-06-27 JP JP2011141308A patent/JP5656229B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013008884A (en) | 2013-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100718155B1 (en) | Non-volatile memory device using two oxide layer | |
| KR101275800B1 (en) | Non-volatile memory device comprising variable resistance material | |
| JP4822287B2 (en) | Nonvolatile memory device | |
| KR100723420B1 (en) | Non volatile memory device comprising amorphous alloy metal oxide layer | |
| Jin Hu et al. | Optically controlled electroresistance and electrically controlled photovoltage in ferroelectric tunnel junctions | |
| Sawa | Resistive switching in transition metal oxides | |
| JP5154138B2 (en) | Variable resistance random access memory device with n + interface layer | |
| KR101176542B1 (en) | Nonvolatile memory device and memory array | |
| Tsurumaki et al. | Impact of Bi deficiencies on ferroelectric resistive switching characteristics observed at p‐type Schottky‐like Pt/Bi1–δFeO3 interfaces | |
| Fujisaki | Current status of nonvolatile semiconductor memory technology | |
| JP4698630B2 (en) | Variable resistance memory device having buffer layer formed on lower electrode | |
| Panda et al. | Nonvolatile Memristive Switching Characteristics of TiO $ _ {\bm 2} $ Films Embedded With Nickel Nanocrystals | |
| JP5656229B2 (en) | Variable resistance nonvolatile memory element | |
| Hou et al. | A ferroelectric memristor based on the migration of oxygen vacancies | |
| JP6356486B2 (en) | Resistance change memory and method of manufacturing resistance change memory | |
| Tian et al. | New opportunity of ferroelectric tunnel junction memory with ultrathin HfO 2-based oxides | |
| US7932505B2 (en) | Perovskite transition metal oxide nonvolatile memory element | |
| Liu et al. | Interfacial resistive switching properties in Ti/La0. 7Ca0. 3MnO3/Pt sandwich structures | |
| Chen | Electronic effect resistive switching memories | |
| Scherff et al. | Polarity reversal in bipolar resistive switching in Pr0. 7Ca0. 3MnO3 noble metal sandwich structures | |
| JP6813844B2 (en) | Tunnel junction element and non-volatile memory element | |
| JP2014022660A (en) | Variable resistance element, and nonvolatile semiconductor memory device provided with variable resistance element | |
| Duan et al. | Switchable Cu 2 O/WO xp–n junction for high density crossbar arrays | |
| JP5215741B2 (en) | Variable resistance element | |
| Lashkare et al. | Understanding the Location of Resistance Change in the Pr0. 7Ca0. 3MnO3 RRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131118 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131203 |
|
| A072 | Dismissal of procedure [no reply to invitation to correct request for examination] |
Free format text: JAPANESE INTERMEDIATE CODE: A072 Effective date: 20140401 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140731 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140805 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140916 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141007 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141029 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141118 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141119 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5656229 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |