JP5656074B2 - Branch prediction apparatus, processor, and branch prediction method - Google Patents

Description

The present invention relates to a branch prediction apparatus and a branch prediction method for a processor that performs branch prediction and pipeline operations in a computer architecture.

  Some processors have a pipeline processing mechanism in order to improve throughput in the processor. In a processor that performs a pipeline operation, instructions are continuously executed in a plurality of pipelines, so that throughput is improved. However, when a state requiring determination based on a processing result such as a conditional branch instruction occurs in the pipeline, a state (control hazard) in which the instruction cannot be continuously executed in the pipeline occurs. Branch prediction and speculative execution of instructions are used to reduce such hazards. For example, Japanese Patent Laid-Open No. 2001-243069 introduces a branch prediction device that feeds back a branch prediction result that has been implemented in the past to one branch prediction unit to improve branch prediction accuracy as the latest branch prediction state. Has been.

JP 2001-243069 A

  Branch prediction and speculative execution of instructions are important techniques for pipelined processors that achieve high-speed operation. However, (a) the branch prediction method with high accuracy of the branch prediction result takes a long time to obtain the prediction result from the input. Subsequent fetches cannot be performed until a branch prediction result is obtained, and so-called bubbles are generated in the pipeline. (b) The branch prediction method with a short time from input to obtaining the prediction result has low accuracy of the prediction result. Since the accuracy of branch prediction results is low, many speculative executions fail and high performance cannot be obtained.

Therefore, an object of the present invention is to provide a branch prediction apparatus and a branch prediction method that can shorten the time (prediction latency) from the input of branch prediction to the output of the result of branch prediction (prediction latency).

  In order to achieve the above object, one aspect of the branch prediction apparatus according to the reference example includes a plurality of branch prediction means and a contradiction detection means for determining a fetch line to be executed next from an instruction fetch history, and includes a plurality of branch prediction means. The instruction fetch address is tentatively determined by the prediction address output by the high-speed branch prediction means, and the prediction address output by the high-precision and low-speed branch prediction means and the prediction output by the high-speed branch prediction means among the plurality of branch prediction means When the address is the same, the instruction at the provisional instruction fetch address is executed in the pipeline. When the address is different, the prediction address of the low-speed branch prediction unit is used as the instruction fetch address, and the preceding provisional instruction on the time axis is used. The instruction at the instruction fetch address is not executed (discarded) in the pipeline.

  With this configuration, it is possible to obtain a branch prediction device with a short prediction time (low prediction latency) and high prediction accuracy.

Another aspect of the branch prediction apparatus of the present invention is a branch prediction apparatus for a processor having a multi-stage pipeline processing structure, in which an instruction fetch for designating an address of an instruction to be executed next from among a plurality of instructions is provided. An address part; a first branch prediction unit connected to the instruction fetch address part for outputting a first prediction address of an instruction to be executed next from a history of the address of the designated instruction; and the instruction fetch address is connected to the section, the first branch prediction means for outputting a second predicted address of the next instruction to be executed from a history of the addresses of the designated instruction predetermined time delay from the output of the first predicted address A second branch predicting means having a higher prediction accuracy than the above-mentioned instruction fetch address section, and the instruction to be executed next is predicted from the history of the address of the designated instruction. A third branch prediction means for outputting the address in low response speed and high prediction accuracy than the second branch prediction unit, when the output of the first to third branch prediction unit are all the same, the first The output of one branch prediction means is designated as the instruction address to be fetched in the instruction fetch address section, and when the outputs of the second and third branch prediction means are different, the output of the third branch prediction means is fetched. When the instruction fetch address part is designated as the instruction address to be fetched and the outputs of the first and second branch prediction means are different, the output of the second branch prediction means is taken as the instruction address to be fetched. And a prediction result selection means for designating to the section.
Further, one aspect of the branch prediction apparatus of the reference example is a branch prediction apparatus for a processor having a multi-stage pipeline processing structure, a storage means for storing a plurality of instructions in association with addresses, and among the plurality of instructions. An instruction fetch address portion for designating the address of the next instruction to be executed, an execution unit for executing the designated instruction, and a first predicted address of the instruction to be executed next from the history of the designated instruction address The first branch prediction means for outputting the second prediction address of the instruction to be executed next from the history of the address of the designated instruction, and outputting the second prediction address delayed for a predetermined time from the output of the first prediction address A second branch prediction unit having a higher prediction accuracy than that of the first branch prediction unit; and the first prediction address preceding the second prediction address is provided to the instruction fetch unit. And a prediction result selection means for giving the second prediction address to the instruction fetch unit when the first prediction address and the second prediction address subsequent to the first prediction address are different from each other, and And a contradiction detecting means for instructing the execution unit to discard the execution of the instruction at the first predicted address when the predicted address is given to the instruction fetch address section.

  By adopting such a configuration, it is possible to obtain a branch prediction device with a short branch prediction time and high prediction accuracy.

  According to another aspect of the branch prediction apparatus of the present invention, in a branch prediction apparatus for a processor having a multi-stage pipeline processing structure, a storage means for storing a plurality of instructions in association with addresses, An instruction fetch address portion for designating the address of the next instruction to be executed, an execution unit for executing the designated instruction, and a first predicted address of the instruction to be executed next from the history of the designated instruction address The first branch prediction means for outputting the sequence of the second instruction and the second prediction address sequence of the instruction to be executed next from the history of the address of the designated instruction are delayed by a predetermined time from the output of the first prediction address. A second branch predicting unit having a higher prediction accuracy than the first branch predicting unit to be output; a column of the first predicted address; When the first predicted address column and the second predicted address column are compared and the corresponding predicted addresses are different, the first predicted address column is the same as the second predicted address column address. A prediction result selecting means for correcting the instruction, and discarding the execution of the instruction at the corrected address in the first predicted address column when the address of the second predicted address column is given to the instruction fetch address portion. Contradiction detection means for instructing the execution unit.

  By adopting such a configuration, it is possible to obtain a branch prediction device with a short branch prediction time and high prediction accuracy.

  Preferably, there is a time difference corresponding to one stage or a plurality of stages in the pipeline structure between the output of the first branch prediction unit and the output of the second branch prediction unit.

  Further, one aspect of the branch prediction apparatus of the reference example is a branch prediction apparatus for a processor having a multi-stage pipeline processing structure, a storage means for storing a plurality of instructions in association with addresses, and among the plurality of instructions. An instruction fetch address portion for designating the address of the next instruction to be executed, an execution unit for executing the designated instruction, and a first predicted address of the instruction to be executed next from the history of the designated instruction address The first branch prediction means for outputting the sequence of the second instruction and the second prediction address sequence of the instruction to be executed next from the history of the address of the designated instruction are delayed by a predetermined time from the output of the first prediction address. A second branch predicting unit having a higher prediction accuracy than the first branch predicting unit to be output; a column of the first predicted address; When the first predicted address column and the second predicted address column are compared and the corresponding predicted addresses are different, the first predicted address column is the same as the second predicted address column address. A prediction result selecting means for correcting the instruction, and discarding the execution of the instruction at the corrected address in the first predicted address column when the address of the second predicted address column is given to the instruction fetch address portion. Contradiction detection means for instructing the execution unit.

  By adopting such a configuration, it is possible to obtain a branch prediction device with a short branch prediction time and high prediction accuracy.

  Further, one aspect of the branch prediction method of the reference example is that in a branch prediction method of a processor having a multi-stage pipeline processing structure, a high-speed and low-precision branch prediction unit and a low-speed and high-precision branch prediction unit are provided in parallel. When the instruction fetch is executed using the previously obtained low-precision prediction address as the temporary address and the prediction result is different by comparing the temporary address and the high-precision prediction address obtained later, the high-precision obtained later The instruction fetch is executed at the predicted address, and the instruction fetched at the temporary address is discarded or the execution result of the instruction fetched at the temporary address is discarded.

  By adopting such a configuration, it is possible to obtain a branch prediction device with a short branch prediction time and high prediction accuracy.

One aspect of the branch prediction method of the present invention is a branch prediction method for a processor having a multi-stage pipeline processing structure, wherein a predicted address of an instruction to be executed next is determined from a history of addresses of designated instructions. A first branch prediction step that outputs with a predetermined response speed and a predetermined prediction accuracy, and a predicted address of an instruction to be executed next is lower than the first branch prediction step from the history of the address of the designated instruction. A second branch prediction step for outputting with a response speed and high prediction accuracy, and a predicted address of an instruction to be executed next from the history of the address of the designated instruction is lower than the second branch prediction step. A third branch prediction step that outputs with high prediction accuracy, and when the outputs of the first to third branch prediction steps are the same, the first branch prediction step When the output is specified as an instruction address to be fetched and the outputs of the second and third branch prediction steps are different, the output of the third branch prediction step is specified as an instruction address to be fetched and is later in the pipeline. When the output by the fetch based on the instruction address of each output of the first and second branch prediction steps is discarded and the outputs of the first and second branch prediction steps are different, The output is designated as an instruction address to be fetched , and the processing based on the fetch based on the instruction address of the output of the first branch prediction step is discarded at the later stage of the pipeline.
Also, one aspect of the branch prediction method of the reference example is that in a branch prediction method of a processor having a multi-stage pipeline processing structure, a predicted address of an instruction to be executed next is determined from a specified instruction address history. A first branch prediction unit that outputs a response speed and a predetermined prediction accuracy; and a predicted address of an instruction to be executed next from the history of the address of the designated instruction is lower than the first branch prediction unit. The second branch predicting means for outputting with high prediction accuracy, and the predicted address of the next instruction to be executed from the history of the address of the designated instruction with lower response speed and higher prediction accuracy than the second branch prediction means. Third branch prediction means for outputting, and when the outputs of the first to third branch prediction means are the same, the output of the first branch prediction means is used as an instruction address to be fetched. When the outputs of the second and third branch predicting means are different from each other, the output of the third branch predicting means is specified as an instruction address to be fetched, and the first and second outputs are executed in the subsequent stage of the pipeline. When the outputs of the branch prediction means are discarded by the fetched instruction address and the outputs of the first and second branch prediction means are different, the output of the second branch prediction means is designated as the instruction address to be fetched. At the same time, the processing by the instruction address fetched from the output of the first branch predicting means is discarded at the latter stage of the pipeline.

  By adopting such a configuration, it is possible to obtain a branch prediction device with a short branch prediction time and high prediction accuracy.

  According to the present invention, it is possible to obtain a branch prediction device and a branch prediction method capable of performing highly accurate branch prediction with a short time from the branch prediction input to the branch prediction result output.

It is explanatory drawing explaining the branch prediction apparatus of this invention. It is a flowchart explaining the example of the algorithm of the operation | movement in a branch prediction apparatus. It is a timing diagram explaining operation | movement (when prediction is in agreement) of a branch prediction apparatus. It is a timing diagram explaining operation | movement (when prediction does not correspond) of a branch prediction apparatus. It is a figure explaining reduction of the prediction latency (execution time) by the branch prediction apparatus of this invention.

  Hereinafter, the present invention will be described through embodiments of the present invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

(Device configuration)
The branch prediction device incorporated in the processor according to the present invention operates a relatively low speed and high accuracy branch prediction device and a relatively high speed and low accuracy branch prediction device in cooperation with each other in the instruction fetch pipeline. Realizes high-speed and high-precision branch prediction.

  In this embodiment, the processor has three pipeline stages, the branch prediction device performs prediction using three (plural) branch prediction units as branch prediction means, and an instruction fetch mechanism based on the prediction result A case where the pipeline is controlled will be described as an example. The first branch prediction unit 100 is a branch prediction unit that realizes the fastest and low-accuracy operation, and the second branch prediction unit 101 realizes an operation that is slower and more accurate than the first branch prediction unit. It is a branch prediction means. The third branch prediction unit 102 is a branch prediction unit that realizes the slowest and most accurate operation.

  The branch prediction unit includes, for example, simple prediction, static prediction, next line prediction, two-level branch prediction, local branch prediction, high-frequency branch prediction, integrated branch prediction, consensus prediction, branch prediction unit overwriting, neural branch prediction, A prediction mechanism having an algorithm of L-Tage branch prediction and other branch prediction is appropriately configured.

  As shown in FIG. 1, the branch prediction apparatus of the present invention includes a prediction result selection unit 120, an instruction fetch address unit 130, an instruction cache unit 140, an instruction decoding unit 150, and instruction fetch line valid bit units 160 and 161. An instruction execution unit 170, three (plural) branch prediction units 100, 101, and 102, a contradiction detection unit 110 that determines whether to discard subsequent fetch information by referring to the prediction information result, and 111, including logic gates.

  Here, the instruction fetch unit 130 (stage 0), the instruction cache unit 140 (stage 1), the instruction decode unit 150, and the instruction execution unit unit 170 (stage 2) form a pipeline. Further, three stages (stage 0, stage 1 and stage 2) of the pipeline are shown in the vertical direction of FIG. Data movement between each stage is synchronized by a register or a data latch.

The instruction fetch address unit 130 holds the instruction address to be executed next, which is output from the prediction result selection unit 120, and gives an instruction fetch instruction to the instruction cache unit 140. The instruction fetch address unit 130 simultaneously issues a branch prediction request to the branch prediction units 100, 101, and 102.

  Instruction fetch line valid bit sections 160 and 161 indicate whether or not the instruction fetch data of each stage is valid. For example, in stage 0, “1” is set in the instruction fetch valid bit unit 160 by the instruction fetch instruction. It is propagated to the instruction fetch line effective bit portion 161 (a plurality of pipelines) in the subsequent stage in synchronization with the clock. If there is a mismatch between the outputs of the branch prediction units during the process, the instruction fetch line valid bit part is reset.

  The instruction cache unit 140 performs instruction fetch processing of the corresponding address in accordance with the instruction fetch instruction given from the instruction fetch address unit 130, and gives instruction information to the instruction unit decoding unit 150.

The instruction decode unit 150 decodes the instruction fetch line information output from the instruction cache unit 140 to form a control signal group for operating the instruction execution unit unit 170 and supplies the control signal group to the instruction execution unit unit 170. Same pipe instruction fetch line valid bit 161 of line stage "1" (set) instruction execution of the instruction is given to the instruction execution unit 170 in the case of "0" (reset) instruction execution unit in the case of Razz given instruction to execute the instruction section 170 (the instruction execution unit 170 does not operate instruction), the instruction is discarded.

  Each of the plurality of branch prediction units 100 to 102 outputs the prediction result to the branch prediction result selection unit 120 and the contradiction detection units 110 and 111 that perform the subsequent fetch line discard determination.

The prediction result selection unit 120 determines an appropriate one of the obtained branch prediction results and outputs it to the instruction fetch address unit 130. The operation of the prediction result selection unit 120 will be described later with reference to FIG.
According to the value specified in the instruction fetch address unit 130, the instruction fetch pipeline continues the fetch processing from the next cycle.

  The contradiction detection means (110 and 111) for determining the subsequent fetch line discarding detection detects inconsistencies between the branch prediction units. Output (see FIG. 2 described later). That is, the contradiction detection unit 110 detects inconsistency between the branch prediction units 100 and 101, and outputs an instruction discard instruction to the instruction fetch line valid bit unit 160 when a contradiction is detected. The contradiction detecting unit 111 detects inconsistency between the branch prediction units 101 and 102, and outputs an instruction discard instruction to the instruction fetch line valid bit units 160 and 161 when the contradiction is detected. The instruction discard instruction resets the instruction fetch line valid bits 160 and 161 of the subsequent fetch line to “0”. When the instruction fetch line valid bit portion 161 is reset to “0”, the discarded instruction is not executed. Note that the initial values of the instruction fetch line valid bit units 160 and 161 are set to “1”.

(Explanation of device operation)
Next, the operation of a processor including the above branch prediction apparatus will be described.
First, the instruction fetch address unit 130 outputs an instruction fetch request to the instruction cache 140 in each cycle of the pipeline operation. The instruction fetch address unit 130 outputs a branch prediction request. When an instruction fetch request and a branch prediction request are output, the following processes (a) and (b) are executed in parallel.

  (A) The instruction cache unit 140 performs an instruction fetch based on the value of the instruction fetch address unit 130 in response to the instruction fetch request, and outputs the obtained instruction information to the instruction decoding unit 150. The operation of the instruction cache unit 140 uses a well-known technique as the operation of the instruction cache memory, and a description thereof will be omitted.

(A) Upon receiving a branch prediction request, the branch prediction units 100, 101, and 102 output prediction results at different timings . The prediction result selection unit 120 appropriately selects the prediction results output from the branch prediction units 100, 101, and 102 and reflects them in the instruction fetch address unit 130. The contradiction detection units 110 and 111 instruct the prediction result selection unit 120 to discard an unnecessary instruction fetch result according to the selection result .

Further, with reference to the flowchart of FIG. 2, the operation (a) of determining the instruction fetch address and determining the discard of the instruction fetch result (contradictory detection operation) will be described.
As shown in the figure, when the pipeline operation is started, the contradiction detection means including the contradiction detection units 110 and 111 monitors the outputs of the branch prediction units 100 to 102 (step S10).

  Contradiction detection means: (1) In the contradiction detection unit 111, the outputs of the branch prediction units 101 and 102 match (step S12; Yes), and in the contradiction detection unit 110, the outputs of the branch prediction units 100 and 101 match. If so (step S14; Yes), the prediction result selection unit 120 selects the output of the first branch prediction unit 100 and sets it in the instruction address unit 130 (step S16).

  The contradiction detection means: (2) When the outputs of the branch prediction units 101 and 102 match in the contradiction detection unit 111 (step S12; Yes), and the outputs of the branch prediction units 100 and 101 do not match in the contradiction detection unit 110 (Step S <b> 14; No), the prediction result selection unit 120 selects the output of the second branch prediction unit 101 and sets it in the instruction address unit 130. At the same time, the instruction fetch line valid bit sections 160 and 161 are set to “0” in order to discard the subsequent fetched instruction (step S20).

Further, the contradiction detection means (3) when the outputs of the branch prediction units 101 and 102 do not match in the conflict detection unit 111 (step S12; No), the output of the third branch prediction unit 102 to the prediction result selection unit 120 Is selected and set in the instruction address section 130. At the same time, the instruction fetch line valid bit unit 160 is set to “0” in order to discard the subsequent fetched instruction (step S18).
The branch prediction apparatus repeats such branch prediction processing (steps S10 to S20).

(Concrete example)
Next, an example of an instruction address selected by the instruction fetch operation of the branch predicting apparatus of the present invention will be described with reference to timing charts shown in FIGS. FIG. 3 shows an example when the prediction addresses of the branch prediction units 100 to 102 match. FIG. 4 shows an example of a case where a prediction address mismatch occurs between the branch prediction units 100 and 101 and a prediction address between the branch prediction units 101 and 102 (a case where a prediction address mismatch occurs between the branch prediction units). ing. The horizontal axis in both figures is the time axis, the stage of the process proceeds in accordance with the clock signal T0 through T10.

(Outline of instruction fetch operation)
First, the instruction fetch process is started using the instruction fetch address. At time T0, an instruction fetch instruction is output to the instruction cache using a predetermined instruction fetch address. At time T0, the instruction fetch address is output to the first, second, and third branch prediction units in parallel.

  The first branch predicting means calculates and outputs the next instruction fetch address between time T0 and time T1. The instruction fetch address part reflects this result as the instruction fetch address at time T1.

  The second branch prediction means outputs the branch prediction result started at time T0 between time T1 and time T2. It is assumed that this result matches the output of the first branch predicting means at time T1. In this case, the fetch of subsequent instructions is continued. In parallel with time T1, the instruction fetch address is output to the first, second and third branch prediction means.

  Between time T1 and time T2, the first branch prediction means outputs an instruction fetch address for time T2. In this case, the result of the first branch predicting means is reflected as the instruction fetch address for time T2 in accordance with the flowchart of FIG.

  The third branch prediction means outputs a branch prediction result started at time T0 between time T2 and time T3. It is assumed that this result matches the output of the second branch predicting means output from time T1 to time T2. In this case, the subsequent instruction fetch is continued.

Between time T2 and time T3, the second branch prediction means outputs the branch prediction result started at time T1. Since this result is different from the first branch prediction means obtained at time T2 (example in FIG. 4), the subsequent instruction fetch valid bit is reset.
The output result of the second branch predicting means is reflected in the instruction fetch address at time T3.

  From time T3 to time T4, the third branch prediction means outputs the branch prediction result started at time T1. Since this result does not match the second branch prediction result obtained at time T2, the subsequent instruction fetch is discarded.

  Time T7 is an inconsistent example between the output of the second branch prediction means and the third branch prediction means (example of FIG. 4). Address C5 is selected as the next fetch address and is used as the instruction fetch address.

(Example when predicted addresses match)
First, the case where the predicted addresses match will be described. As shown in FIG. 3, at time T0, the instruction fetch address unit 130 outputs an instruction fetch instruction to the instruction cache unit 140 using the instruction fetch address A0. At the same time, the instruction fetch address A0 is output to the first branch prediction unit 100, the second branch prediction unit 101, and the third branch prediction unit 102. Note that the initial values of the instruction fetch line valid bit sections 160 and 161 are “1”.

  Between time T0 and time T1, the branch prediction unit 100 calculates and outputs the next instruction fetch address A1. The branch prediction units 101 and 102 do not output a prediction address yet. The prediction result selection unit 120 selects the address A1 output by the branch prediction unit 100.

  At time T1, the instruction fetch address unit 130 reflects the address A1 as the instruction fetch address.

  Between time T1 and time T2, the instruction fetch address unit 130 outputs the address A1 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A2. The branch prediction unit 101 outputs the branch prediction result (address A1) started at time T0. The branch prediction unit 102 does not generate a prediction address yet. The contradiction detection unit 110 determines that the prediction address A1 of the branch prediction unit 101 matches the previous prediction address A1 of the branch prediction unit 100. The prediction result selection unit 120 selects the address A2 output by the branch prediction unit 100.

  At time T2, the instruction fetch address unit 130 reflects the address A2 as the instruction fetch address. Further, “1” is maintained in the instruction fetch line valid bit unit 160 by the match determination output of the contradiction detection unit 110, and the address A1 is not discarded (maintained).

  Between time T2 and time T3, the instruction fetch address unit 130 outputs the address A2 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A3. The branch prediction unit 101 outputs a branch prediction result (address A2). The branch prediction unit 102 outputs the prediction address A1. The contradiction detection unit 110 determines whether the prediction address A2 of the branch prediction unit 101 matches the previous prediction address A2 of the branch prediction unit 100. Further, the contradiction detection unit 111 determines whether the prediction address A1 of the branch prediction unit 102 matches the previous prediction address A1 of the branch prediction unit 101. The prediction result selection unit 120 selects the address A3 output by the branch prediction unit 100.

  At time T3, the instruction fetch address unit 130 reflects the address A3 as the instruction fetch address. Further, the instruction fetch line valid bit unit 160 is set to “1” by the match determination output of the contradiction detection unit 110, and the address A2 is not discarded (maintained). Further, the instruction fetch line valid bit units 160 and 161 are maintained at “1” by the match determination output of the contradiction detection unit 111, and the addresses A0 and A1 are not discarded (maintained). As a result, the execution results of the instruction addresses A0 and A1 are not discarded.

  Between time T3 and time T4, the instruction fetch address unit 130 outputs the address A3 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A4. The branch prediction unit 101 outputs the address A3. The branch prediction unit 102 outputs the prediction address A2. The contradiction detection unit 110 determines whether the prediction address A3 of the branch prediction unit 101 matches the previous prediction address A3 of the branch prediction unit 100. The contradiction detection unit 111 determines whether the prediction address A2 of the branch prediction unit 102 matches the previous prediction address A2 of the branch prediction unit 101. The prediction result selection unit 120 selects the address A4 output by the branch prediction unit 100.

  At time T4, the instruction fetch address unit 130 reflects the address A4 as the instruction fetch address. Further, the instruction fetch line effective bit unit 160 is maintained at “1” by the coincidence determination output of the contradiction detection unit 110, and the address A3 is not discarded (maintained). Further, the instruction fetch line valid bit units 160 and 161 are maintained at “1” by the match determination output of the contradiction detection unit 111, and the addresses A1 and A2 are not discarded (maintained). As a result, the execution results of the instruction addresses A1 and A2 are not discarded.

Similar processing is repeated, and the instruction addresses A0 to A9,... Are fetched as shown in FIG.
In this way, the processing is performed without waiting for the prediction result of the third branch prediction unit 102 whose output is delayed, so that the calculation time is shortened.

(Example when predicted addresses do not match)
Next, with reference to FIG. 4, the case where the prediction address mismatch occurs between the branch prediction units will be described. As described above, a branch prediction unit with a long prediction time has higher prediction accuracy than a branch prediction unit with a short prediction time.

  First, at time T0, the instruction fetch address unit 130 outputs an instruction fetch instruction to the instruction cache unit 140 using the instruction fetch address A0. At the same time, the instruction fetch address A0 is output to the first branch prediction unit 100, the second branch prediction unit 101, and the third branch prediction unit 102.

  Between time T0 and time T1, the branch prediction unit 100 calculates and outputs the next instruction fetch address A1. The branch prediction units 101 and 102 have not yet generated an output. The prediction result selection unit 120 selects the address A1 output by the branch prediction unit 100. Note that the instruction fetch line valid bit sections 160 and 161 are initially set to “1”.

  At time T1, the instruction fetch address unit 130 reflects the address A1 as the instruction fetch address.

  Between time T1 and time T2, the instruction fetch address unit 130 outputs the address A1 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the prediction address A2. The branch prediction unit 101 outputs the branch prediction result (address A1) started at time T0. The branch prediction unit 102 does not generate a prediction address yet. The contradiction detection unit 110 determines whether the prediction address A1 of the branch prediction unit 101 matches the previous prediction address A1 of the branch prediction unit 100. The prediction result selection unit 120 selects the address A2 output by the branch prediction unit 100.

  At time T2, the instruction fetch address unit 130 reflects the address A2 as the instruction fetch address. Further, “1” is maintained in the instruction fetch line valid bit unit 160 by the match determination output of the contradiction detection unit 110, and the address A1 is not discarded (maintained).

  Between time T2 and time T3, the instruction fetch address unit 130 outputs the address A2 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A3. Here, it is assumed that the branch prediction unit 101 outputs the address B2 as the branch prediction result. The branch prediction unit 102 outputs the prediction address A1. The contradiction detection unit 110 determines a mismatch because the prediction address B2 of the branch prediction unit 101 and the previous prediction address A2 of the branch prediction unit 100 do not match. Further, the contradiction detection unit 111 determines whether the prediction address A1 of the branch prediction unit 102 matches the previous prediction address A1 of the branch prediction unit 101. The prediction result selection unit 120 selects the address B2 output by the branch prediction unit 101.

  At time T3, the instruction fetch address unit 130 reflects the address B2 as the instruction fetch address. Further, the contradiction detection unit 110 sets “0” in the instruction fetch line valid bit unit 160 because the output (address A2) of the branch prediction unit 100 and the output (address B2) of the branch prediction unit 101 do not match. The processing at address A2 is discarded. Further, the contradiction detection unit 111 maintains “1” in the instruction fetch line valid bit unit 161 because the prediction address A1 of the branch prediction unit 102 matches the previous prediction address A1 of the branch prediction unit 101. The address A1 is not discarded (maintained). As a result, the execution result of the contents of the instruction address A1 is not discarded.

  Between time T3 and time T4, the instruction fetch address unit 130 outputs the address B2 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A4. The branch prediction unit 101 does not output an address yet. Here, it is assumed that the branch prediction unit 102 outputs the prediction address C2. The contradiction detection unit 111 determines a mismatch between the prediction address C2 of the branch prediction unit 102 and the previous prediction address B2 of the branch prediction unit 101. The prediction result selection unit 120 selects the address C2 output by the branch prediction unit 102.

  At time T4, the instruction fetch address unit 130 reflects the address C2 as the instruction fetch address. The contradiction detecting unit 111 resets both the instruction fetch line valid bit units 160 and 161 to “0” because the output of the branch prediction unit 102 (predicted address C2) and the output of the branch prediction unit 101 (B2) do not match. . As a result, the execution results of the contents of the instruction addresses A2 and B2 are discarded.

  Between time T4 and time T5, the instruction fetch address unit 130 outputs the address C2 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A5. The branch prediction unit 101 does not yet output a prediction address. The branch prediction unit 102 also does not output a prediction address.

  At time T5, the instruction fetch address unit 130 reflects the address A5 as the instruction fetch address. The instruction fetch line valid bit unit 160 is set to “1”, and the instruction fetch line valid bit unit 161 captures the previous “0” output of the instruction fetch line valid bit unit 160 and maintains “0”.

  Between time T5 and time T6, the instruction fetch address unit 130 outputs the address A5 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A6. The branch prediction unit 101 outputs the prediction address A5. The branch prediction unit 102 does not yet output a prediction address. The contradiction detection unit 110 determines a match between the output of the branch prediction unit 101 (address A5) and the previous output (address A5) of the branch prediction unit 100.

  At time T6, the instruction fetch address unit 130 reflects the address A6 as the instruction fetch address. The contradiction detection unit 110 maintains “1” in the instruction fetch line valid bit unit 160 because the output (address A5) of the branch prediction unit 100 matches the output (address A5) of the branch prediction unit 101. The instruction fetch line valid bit portion 161 takes in the previous “1” output of the instruction fetch line valid bit portion 160 and is set to “1”.

  Between times T6 and T7, the instruction fetch address unit 130 outputs the address A6 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A7. The branch prediction unit 101 outputs an address A6. Here, it is assumed that the branch prediction unit 102 outputs the prediction address C5. The contradiction detection unit 111 determines a mismatch between the prediction address C5 of the branch prediction unit 102 and the previous prediction address A5 of the branch prediction unit 101. The prediction result selection unit 120 selects the address C5 output by the branch prediction unit 102.

  At time T7, the instruction fetch address unit 130 reflects the address C5 as the instruction fetch address. Inconsistency output from the contradiction detection unit 111 resets both the instruction fetch line valid bit units 160 and 161 to “0”. As a result, the execution result of the contents of the instruction addresses A5 and A6 is discarded.

  Between time T7 and time T8, the instruction fetch address unit 130 outputs the address C5 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A8. The branch prediction unit 101 does not yet output a prediction address. The branch prediction unit 102 also does not output a prediction address.

  At time T8, the instruction fetch address unit 130 reflects the address A8 as the instruction fetch address. The instruction fetch line valid bit unit 160 is set to “1”, and the instruction fetch line valid bit unit 161 captures the previous “0” output of the instruction fetch line valid bit unit 160 and maintains “0”.

  Between time T8 and time T9, the instruction fetch address unit 130 outputs the address A8 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A9. The branch prediction unit 101 outputs the prediction address A8. The branch prediction unit 102 does not yet output a prediction address. The contradiction detection unit 110 determines a match between the output of the branch prediction unit 101 (address A8) and the previous output of the branch prediction unit 100 (address A8).

  At time T9, the instruction fetch address unit 130 reflects the address A9 as the instruction fetch address. The contradiction detection unit 110 maintains “1” in the instruction fetch line valid bit unit 160 because the previous output (address A8) of the branch prediction unit 100 matches the output (address A8) of the branch prediction unit 101. The instruction fetch line valid bit portion 161 takes in the previous “1” output of the instruction fetch line valid bit portion 160 and is set to “1”.

  Between times T9 and T10, the instruction fetch address unit 130 outputs the address A9 to the instruction cache unit 140 and the branch prediction units 100 to 102. The branch prediction unit 100 outputs the next prediction address A10. The branch prediction unit 101 outputs an address A9. The branch prediction unit 102 outputs the prediction address A8. The contradiction detection unit 111 determines whether the prediction address A8 of the branch prediction unit 102 matches the previous prediction address A8 of the branch prediction unit 101. The prediction result selection unit 120 selects the address A8 output by the branch prediction unit 102.

  At time T10, the instruction fetch address unit 130 reflects the address A10 as the instruction fetch address.

Thereafter, the same processing is repeated, and the instruction addresses A0, A1, C2, C5, A8, A9, A10,... Are fetched as shown in FIG.
As described above, the processing is performed without waiting for the prediction result of the third branch prediction unit 102 whose output is delayed, so that the calculation time (prediction latency) is shortened.

(Effect of Example)
A prediction example according to the configuration of the embodiment will be described with reference to FIG. For example, in the example shown in FIG. 1, when the first branch predicting means has an accuracy of 70%, the second branch predicting means has an accuracy of 90%, and the third branch predicting means has an accuracy of 95%, the average The latency is 1.54 from the result of FIG. Since the latency of the third branch predicting means is 3 cycles, the speed can be increased by about twice while maintaining the prediction accuracy.

As described above, according to the embodiment of the present invention, it is possible to suppress the occurrence of pipeline bubbles that become a problem when a highly accurate branch prediction unit is employed.
For example, if only the third branch prediction means is employed, the branch prediction result (branch to address A1) obtained at time T1 cannot be obtained until time T3. On the contrary, if only the first branch prediction means is employed, the instruction success rate of the branch prediction result obtained at time T2 is about 80%, so the instruction execution fails with a high probability.

  By adopting the present invention, high prediction accuracy can be calculated with substantially short latency, and the efficiency of the instruction fetch pipeline can be realized.

  It should be noted that the examples and application examples described through the above-described embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements. The present invention is described in the description of the above-described embodiments. It is not limited. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

(Possibility of industrial use)
The present invention can be applied to a high-performance processor. This is especially effective for processors with deep pipelines.

DESCRIPTION OF SYMBOLS 100 1st branch prediction part (means), 101 2nd branch prediction part (means), 102 3rd branch prediction part (means), 110,111 Contradiction detection part , 120 Prediction result selection part, 130 instruction fetch address 140, instruction cache unit , 160, 161 instruction fetch line valid bit unit, 170 instruction execution unit unit

Claims (3)

A branch prediction device for a processor having a multi-stage pipeline processing structure,
An instruction fetch address section for designating an address of an instruction to be executed next from a plurality of instructions;
A first branch prediction unit connected to the instruction fetch address unit and outputting a first predicted address of an instruction to be executed next from a history of addresses of designated instructions;
The first instruction is connected to the instruction fetch address section and outputs a second predicted address of an instruction to be executed next from a history of the address of the designated instruction with a predetermined time delay from the output of the first predicted address. A second branch predicting means having higher prediction accuracy than the branch predicting means of
A third instruction connected to the instruction fetch address section for outputting a predicted address of an instruction to be executed next from a history of the address of the designated instruction at a lower response speed and higher prediction accuracy than the second branch prediction means; Branch prediction means of
When all the outputs of the first to third branch predicting means are the same, the output of the first branch predicting means is designated as the instruction address to be fetched in the instruction fetch address section, and the second and third When the outputs of the third branch prediction means are different, the output of the third branch prediction means is designated as the instruction address to be fetched in the instruction fetch address section, and the outputs of the first and second branch prediction means are different. Predicting result selecting means for designating the output of the second branch predicting means in the instruction fetch address section as an instruction address to be fetched;
A branch prediction apparatus for a processor comprising:   A processor having a pipeline processing structure comprising the branch prediction device according to claim 1. A branch prediction method for a processor having a multi-stage pipeline processing structure,
A first branch prediction step for outputting a predicted address of an instruction to be executed next from a history of addresses of a specified instruction with a predetermined response speed and a predetermined prediction accuracy;
A second branch prediction step for outputting a predicted address of an instruction to be executed next from the history of the address of the designated instruction at a lower response speed and higher prediction accuracy than the first branch prediction step;
A third branch prediction step for outputting a predicted address of an instruction to be executed next from the history of the address of the designated instruction at a lower response speed and higher prediction accuracy than the second branch prediction step;
When the outputs of the first to third branch prediction steps are the same, specify the output of the first branch prediction step as an instruction address to be fetched;
When the outputs of the second and third branch prediction steps are different, the output of the third branch prediction step is designated as an instruction address to be fetched, and the first and second branch prediction steps are performed later in the pipeline. Discard the processing based on the instruction address of each output of
When the outputs of the first and second branch prediction steps are different, the output of the second branch prediction step is designated as an instruction address to be fetched, and the output of the first branch prediction step is output at a later stage of the pipeline. Abandon processing by fetch based on instruction address,
Processor branch prediction method.

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