JP5652166B2 - Power amplifier, W-CDMA power amplifier, multiband power amplifier, and portable information terminal - Google Patents

Description

  The present invention relates to a power amplifier module of a mobile phone device, and more particularly to a linear power amplifier of a power amplifier module of a multi-mode mobile phone device.

  The output power control of the conventional power amplifier module is realized by a method of supplying a bias current corresponding to the output power to each amplification stage.

  For example, the invention described in Japanese Patent Laid-Open No. 2006-270670 (Patent Document 1) discloses a method of supplying a bias current corresponding to output power to each amplification stage.

  In the technique described in Patent Document 1, a coupler is connected to the power amplifier output while the input power is constant. A desired output power is obtained by detecting the output of the coupler and applying a negative feedback to determine the bias current. Since the bias current is reduced when the output power is low, it is possible to supply the minimum necessary bias current for each output power.

  In the power amplifier described in Patent Document 1, when the output power is low, the bias current is reduced. For this reason, it is possible to supply the minimum necessary bias current to the output power of each output stage.

  On the other hand, in “Thermal Gain Variation Compensation Technique Using Thermistor on HPA Module for W-CDMA System” (Non-patent Document 1), the bias is set to be constant and the input signal is changed to reduce the distortion in a wide output power range. Techniques to do this are disclosed.

JP 2006-270670 A

Y. Kuriyama et. al. “Thermal Gain Variation Compensation Technology Using Thermistor on HPA Module for W-CDMA System”, IEEE Transaction on Electronics Vol. E91-C, no. 12, December 2008 pp 1933-1940

  However, the technology described in Patent Document 1 is based on GSM, which is the specification of the second generation mobile phone in Europe. Accordingly, it is assumed that the transmission signal has a constant amplitude, and problems such as adjacent channel leakage power (ACLR) degradation due to amplitude distortion are not assumed.

  Further, the technique of Non-Patent Document 1 has a problem that it is difficult to reduce current consumption when output power is low.

  The object of the present invention is to have both continuous bias current control as a gain variable means and variable gain means for discretely changing the gain, and by reducing the bias current according to the output power, even in output conditions other than the maximum output power. An object is to provide a means capable of reducing current consumption.

  Another object of the present invention is to provide means for suppressing temperature dependence of output power to be small because different temperature correction coefficients can be set according to operating conditions.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A power amplifier according to a representative embodiment of the present invention includes a first amplifier that amplifies an input signal, an amplification path that amplifies a signal derived from the output of the first amplifier, and a bypass path that does not perform amplification. And the second amplifier outputs a signal derived from the output of the first amplifier through a bypass path when the output of the first amplifier is less than a predetermined threshold.

  The power amplifier further includes a setting circuit that controls the bias current of the first amplifier, and a first bias current source that generates a bias current that is input to the first amplifier. The first bias current source may be controlled by the transmission path of the input signal of the amplifier and the internal temperature.

  The setting circuit of the power amplifier has a first temperature characteristic and a second temperature characteristic which are selectively used according to the transmission path of the input signal of the second amplifier and the internal temperature, and the first temperature characteristic and the second temperature characteristic. The output current of the first bias current source may be determined based on the above.

  The power amplifier further includes a second bias current source that generates a bias current that is input when the transmission path of the second amplifier is an amplification path, and the setting circuit also controls the second bias current source. It may be characterized.

  Another power amplifier according to an exemplary embodiment of the present invention includes a first amplifier that amplifies an input signal, and a second amplifier that amplifies a signal derived from the output of the first amplifier. One amplifier operates by selectively using output currents from the first bias current source and the second bias current source which are selectively used according to the internal temperature.

  The power amplifier further includes a setting circuit that controls the bias current of the first amplifier, and the setting circuit uses a first bias current source or a second bias current source, and a first circuit that is selectively used depending on the internal temperature. It is good also as having the temperature characteristic of this, and a 2nd temperature characteristic.

  This power amplifier may determine whether to use the first bias current source or the second bias current source according to the output power expected by the power amplifier.

  In the first bias current source of the power amplifier, the output power of the power amplifier is smaller than the output power of the power amplifier assumed by the second bias current source, and the first temperature characteristic used in the first bias current source is It may be characterized by being non-linear.

  A W-CDMA power amplifier, a multiband power amplifier, and a portable information terminal using these power amplifiers are also included in the scope of the present invention.

  Since the linear power amplifier according to the present invention performs temperature correction according to the operating conditions by the bias circuit, it is possible to reduce current consumption while obtaining stable output power.

1 is a block diagram of a power amplifier according to a first embodiment of the present invention. It is a block diagram of another power amplifier in connection with the 1st Embodiment of this invention. It is a graph showing the gain change of the back | latter stage amplifier in connection with the 1st Embodiment of this invention. It is a graph showing an example of the temperature correction characteristic used with the setting circuit in connection with the 1st Embodiment of this invention. It is a circuit diagram showing the specific structure of the bypass of a back | latter stage amplifier. FIG. 6 is an equivalent circuit diagram in which the circuit diagram of FIG. It is a block diagram of the power amplifier in connection with the 2nd Embodiment of this invention. It is a graph showing an example of the temperature correction characteristic used with the setting circuit in connection with the 2nd Embodiment of this invention. It is a graph which shows an example of a gain change in a 2nd embodiment of the present invention. It is a block diagram showing the structure of the power amplifier module corresponding to GSM / EDGE / W-CDMA in connection with the 3rd Embodiment of this invention. It is a block diagram showing another structure of the power amplifier module corresponding to GSM / EDGE / W-CDMA in connection with the 3rd Embodiment of this invention. It is a block diagram showing another structure of the power amplifier module corresponding to GSM / EDGE / W-CDMA in connection with the 3rd Embodiment of this invention. It is a conceptual diagram which shows the detail of the bypass circuit of FIG. It is a Smith chart of the bypass circuit of FIG. It is a block diagram of the power amplifier in connection with the 4th Embodiment of this invention. It is a graph showing an example of the temperature correction characteristic used with the setting circuit in connection with the 4th Embodiment of this invention.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, it is not irrelevant to one another, and one is related to some or all of the other, details, supplementary explanations, and the like. Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except for the specific number, the number may be more than or less than the specified number.

  Further, in the following embodiments, it is needless to say that the constituent elements are not necessarily essential unless particularly specified and apparently essential in principle. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by an integrated circuit technology such as CMOS (complementary MOS transistor). Note that in the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: abbreviated as a MOSFET transistor) does not exclude a non-oxide film as a gate insulating film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram of a power amplifier according to the first embodiment of the present invention. This embodiment will be described with reference to this figure.

  The power amplifier of the present invention includes an input matching circuit 101, first stage amplifiers 102-1, 102-2, rear stage amplifiers 103-1, 103-2, an output phase shift circuit 104, an internal temperature compensation current control circuit 105, and a setting circuit 106. It is comprised including. An external variable voltage source 107 is connected.

  The input matching circuit 101 is a matching circuit that performs impedance matching and performs a phase shift of ± 45 degrees with respect to an input signal. Due to the phase shift of ± 45 degrees, the two signals after the shift are orthogonal.

  The first stage amplifiers 102-1 and 102-2 are amplification circuits that amplify the two systems of signals shifted by the input matching circuit 101.

  The post-stage amplifiers 103-1 and 103-2 include an amplifier A that further amplifies the signals amplified by the first-stage amplifiers 102-1 and 102-2 and a bypass switch B that determines whether to enable this amplifier. It is an amplifier circuit.

  The post-stage amplifiers 103-1 and 103-2 are controlled as follows.

  That is, as the output power of the power amplifier becomes lower, the bias current of the variable voltage source 107 connected to the outside is reduced. When the output power of the power amplifier is further lowered, the feature of the post-stage amplifiers 103-1 and 103-2 is that the operation of the amplifier A is stopped simultaneously with the bypass switch B being turned on.

  The output phase shift circuit 104 is a shift circuit and a combining circuit that combine the signals amplified by the post-stage amplifiers 103-1 and 103-2 after phase shifting.

  The internal temperature compensation current control circuit 105 is a variable current source for compensating for a temperature change in the power amplifier. The internal temperature compensation current control circuit 105 generates bias currents for the first stage amplifiers 102-1 and 102-2.

  The setting circuit 106 is a variable voltage that changes the voltage used in the internal temperature compensation current control circuit 105 according to the operation setting of the power amplifier. Here, “operation setting” means that the power amplifier A is used in the post-stage amplifiers 103-1 and 103-2, the power amplifier A is stopped and the bypass switch B is connected, or the temperature correction characteristic KT 1 or KT 2.

  A variable voltage source 107, which is an external element, is a variable voltage source that generates a bias current for the post-stage amplifiers 103-1, 103-2.

  The operation will be described based on these configurations.

  First, when a signal is input to the power amplifier, the signal input by the input matching circuit 101 is divided into two, and each of the distributed signals is phase-shifted by +45 degrees and −45 degrees, and the input matching circuit 101. That is, the distributed signals are separated from each other by a phase difference of 90 degrees. The separated signals are output to the first stage amplifiers 102-1 and 102-2.

  The signals input to the first stage amplifiers 102-1 and 102-2 are biased by the bias current output from the internal temperature compensation current control circuit 105. Thereafter, the input signal is amplified by an FET (not shown) in the first stage amplifiers 102-1 and 102-2.

  Here, the setting circuit 106 corresponds to 1) when the post-stage amplifiers 103-1 and 103-2 are operating, and 2) when the post-stage amplifiers 103-1 and 103-2 are stopped, respectively. A plurality of temperature correction coefficients are provided, and the plurality of coefficients are appropriately switched to operate.

  The variable voltage source 107 is a variable voltage source for supplying a bias voltage to the post-stage amplifiers 103-1 and 103-2.

  Although this circuit is a case of two-stage amplification, it can be applied even to three-stage amplification. FIG. 2 is a block diagram of another power amplifier according to the first embodiment of the present invention.

  In the case of FIG. 2, middle stage amplifiers 108-1 and 108-2 are inserted, and a constant current source 109 is added as means for supplying a bias current thereto.

  In the case of this figure, the setting circuit 106 may define the coefficients in consideration of both the middle stage amplifiers 108-1 and 108-2 and the subsequent stage amplifiers 103-1 and 103-2. Further, the coefficient of the setting circuit 106 may be determined in consideration of only one of them.

  Next, a change in gain in the present embodiment will be described.

  FIG. 3 is a graph showing the gain change of the post-stage amplifiers 103-1 and 103-2 according to the first embodiment of the present invention. The horizontal axis of this graph represents output power, and the vertical axis represents the amplification factor of the entire amplifier.

  While the output power is low, a sufficient output can be obtained even if the gain is low. Therefore, the outputs of the first stage amplifiers 102-1 and 102-2 are guided to the output phase shift circuit 104 via the bypass B of the rear stage amplifiers 103-1 and 103-2. During this time, amplification by the post-stage amplifiers 103-1 and 103-2 is not performed, the loss of the bypass circuit and the gain of the first-stage amplifier cancel each other, and the overall gain is fixed at, for example, 0.0 dB.

  On the other hand, when the output power exceeds a certain value (0 dBm in FIG. 3), the rear-stage amplifiers 103-1 and 103-2 change the internal signal path to the amplifier A.

  Thereafter, the bias voltage (by the variable voltage source 107 in FIG. 1) is increased according to the outputs of the first stage amplifiers 102-1 and 102-2, and the subsequent stage amplifiers 103-1 and 103-2 increase the gain while maintaining linearity. To go. When the output power is 27 dBm, the overall gain of the subsequent stage is 26.5 dBm.

  The same applies when the output power falls below a certain value. When the output power is lowered, the input signal is lowered and the bias voltage of the second-stage amplifier (= the voltage value of the variable voltage source 107 in FIG. 1) is also lowered. This also reduces the gain of the amplifier.

  When the output power decreases to 0 dBm, the post-stage amplifiers 103-1 and 103-2 stop the operation of the amplifier A, and the post-stage amplifiers 103-1 and 103-2 change the signal internal path to the bypass B side.

  By operating in this way, the power consumption of the power amplifier can be greatly reduced.

  FIG. 4 is a graph showing an example of temperature correction characteristics KT1 and KT2 used in the setting circuit 106 according to the first embodiment of the present invention. The horizontal axis represents the temperature during operation of the power amplifier, and the vertical axis represents the output of the internal temperature compensation current control circuit 105.

  The temperature correction characteristic KT1 represents a characteristic during normal operation, that is, when the amplifier A of the post-stage amplifiers 103-1, 103-2 is operating. On the other hand, the temperature correction characteristic KT2 indicates a characteristic in a state where the amplifier A of the post-stage amplifiers 103-1 and 103-2 is stopped and a signal is sent to the output phase shift circuit 104 via the bypass B.

  As shown in this figure, the temperature correction characteristics KT1 and KT2 need to be set according to the temperature and the operation / stop of the amplifier A in the post-stage amplifiers 103-1 and 103-2.

  FIG. 5 is a circuit diagram showing a specific configuration of bypass B of post-stage amplifiers 103-1 and 103-2.

  In FIG. 2, the amplifier A and the bypass B are written. However, for example, the configuration shown in FIG.

  The amplifier A is an amplifier circuit such as a transistor having a resistor Ar as a peripheral circuit.

  The bypass B includes a resistor Rb, a switch Sb, and a capacitor Cb.

  The switch Sb is a switch that determines whether or not to pass through the bypass B.

  The capacitor Cb is a DC cutting capacitor for cutting a DC component.

  The resistor Rb is a resistor for adjusting impedance.

  The impedance of the bypass B is determined by the series connection of the capacitor Cb and the resistor Rb.

  Even when the signal passes through the bypass B, the outputs of the first stage amplifiers 102-1 and 102-2 can be guided to the output phase shift circuit 104 with low loss by the resistor Rb and the capacitor Cb. Yes. That is, the input / output unit of the bypass B can sufficiently perform impedance matching.

  Both the input impedance and the output impedance of the amplifier A have reactance components.

  FIG. 6 is an equivalent circuit diagram that details the circuit diagram of FIG. 5 to a state where it can be mounted. Unlike FIG. 5, in this figure, the switch Sb is formed of an FET. The gate potential of the switch is controlled complementarily to the gate voltage of the amplifier A.

  At the maximum output, the open switch waveform may be distorted. In order to suppress this, FETs constituting the switch are connected in series.

  Further, a switch Sbias is included for switching input / output on the amplifier A side. The switch Sbias includes two FETs, and determines whether the output voltage from the variable voltage source 107 is input to the resistor Ar. This switch Sbias is also controlled by the same control signal as the switch Sb.

  With the configuration as described above, it is possible to realize an amplifier that can be stably driven with low power consumption by changing the correction of the temperature characteristics at the time of large output and small output with different operation forms.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.

    FIG. 7 is a block diagram of a power amplifier according to the second embodiment of the present invention.

  An input signal to this power amplifier is distributed to a pair of first stage amplifiers 102-1 and 102-2 via an input matching circuit 101 that also serves as a phase shift of ± 45 degrees. Then, the output of the post-stage amplifiers 103-3 and 103-4 (different from the first embodiment and having no bypass) is shifted in phase again by the output phase shift circuit 104 to synthesize the outputs.

  The post-stage amplifiers 103-3 and 103-4 are controlled such that the bias voltage (depending on the variable voltage source 107) decreases as the output power expected by the power amplifier decreases. When the assumed output power is further reduced, the bias currents of the first stage amplifiers 102-1 and 102-2 are set low.

  When the bias currents of the first stage amplifiers 102-1 and 102-2 are set to be low, there is a high possibility that the bias current is excessively reduced due to gain correction. Therefore, two bias current sources are provided and controlled by switching with a switch 110.

  FIG. 8 is a graph showing an example of the temperature correction characteristics KT1 and KT2 used in the setting circuit 106 of the present invention. As in FIG. 4, the horizontal axis represents the temperature during operation of the power amplifier, and the vertical axis represents the output of the internal temperature compensation current control circuit 105.

  The present embodiment is characterized in that the temperature correction characteristic KT1 is kept linear while the temperature correction characteristic KT2 is made non-linear. By doing so, it is possible to prevent the bias current from decreasing uniformly.

  FIG. 9 is a graph showing an example of a gain change in the second embodiment of the present invention. In this graph, the maximum output power is 27 dBm.

  In the present embodiment, when the output power is lowered, the level of the input signal is lowered, and at the same time, the bias currents of the subsequent amplifiers 103-3 and 103-4 are lowered to lower the gain of the power amplifier.

  When the output power is reduced to 13.5 dBm, the bias current of the first stage amplifier is reduced, and the gain of the power amplifier as a whole is further reduced.

  By operating in this way, the power consumption of the power amplifier can be greatly reduced. Further, as in the first embodiment, it is possible to realize an amplifier capable of low power consumption operation by changing the correction of the temperature characteristic between the large output and the small output in different operation forms.

(Third embodiment)
Next, a third embodiment of the present invention will be described.

  FIG. 10 is a block diagram showing a configuration of a GSM / EDGE / W-CDMA compatible power amplifier module according to the third embodiment of the present invention.

  In this figure, a GSM / EDGE compatible amplifier that supports signal carrier frequencies of 1 GHz and 2 GHz, a W-CDMA amplifier that supports signal carrier frequencies of 1 GHz and 2 GHz, and a digital signal interface circuit IF for control (this book) In the figure, an SPI BUS is assumed).

  Terminals to which signals of the power amplifier module are input are prepared for 1 GHz band (LBIN terminal) and 2 GHz band (HBIN terminal) according to the carrier frequency. The input signal is input to an input demultiplexing circuit (1 GHz side: SW1, 2 GHz side SWh) corresponding to the carrier frequency band of the input signal. The signal input to the input branching circuit is output to the GSM / EDGE amplifier or the W-CDMA amplifier according to the corresponding communication method. In a W-CDMA amplifier, a balance matching circuit is passed, and in a GSM / EDGE amplifier that uses the same frequency in time division for transmission and reception, a matching circuit is passed.

  The bias setting condition of each amplifier is transmitted from the control digital signal interface circuit IF to the analog format by the digital / analog conversion circuit DAC and then transmitted to the bias circuit for each amplifier. At this time, the set value is also transmitted from the digital-analog converter circuit DAC to the setting circuit 106 and the variable voltage source 107 in FIG.

  After being amplified by each amplifier, it is output from an external terminal after passing through a matching circuit (GSM / EDGE) and an output matching circuit (W-CDMA). In the drawing, the output terminal of the W-CDMA high band side amplifier is HBOUT W-CDMA, and the output terminal of the W-CDMA low band side amplifier is LBOUT W-CDMA. The output terminal on the GSM / EDGE high band side is HBOUT GSM, and the output terminal on the GSM / EDGE low band side is LBOUT WGSM.

  From this output terminal, a circuit configuration corresponding to the application is made. For example, in W-CDMA, since the band is divided into several, it is branched by a switch so as to be input to a circuit corresponding to each band. On the other hand, GSM / EDGE is output to the outside as it is as the output of the power amplifier module without any particular modification.

  Next, a third alternative embodiment of the present invention will be described with reference to the drawings.

  FIG. 11 is a block diagram showing another configuration of the GSM / EDGE / W-CDMA compatible power amplifier module according to the third embodiment of the present invention. In this figure, the external terminals on the output side are the same as those in FIG. Further, the frequency to be used and the communication method are the same as those in the third embodiment.

  In this embodiment, the GSM / EDGE amplifier is characterized in that couplers CAPl and CAPh are provided at the output of each power amplifier. By detecting the output of the amplifier with these couplers and applying feedback, power corresponding to the output power control voltage Vramp signal can be stably output.

  FIG. 12 is a block diagram showing another configuration of the GSM / EDGE / W-CDMA compatible power amplifier module according to the third embodiment of the present invention. This figure is based on the configuration of FIG. 11, and the processing related to the GSM / EDGE amplifier is the same as that of FIG.

  This embodiment is characterized by processing on the W-CDMA amplifier side. Switches SWp1 and SWp2 are provided in the previous stage on the W-CDMA amplifier side. The switch is controlled so that a signal flows through the AllBypass during a low output operation. As a result, the power consumption can be reduced by completely stopping the power amplifier at the time of low output when using W-CDMA.

  FIG. 13 is a conceptual diagram showing details of the bypass circuit of FIG. 14 is a Smith chart of impedance viewed from the output terminal (see FIG. 13A) of the bypass circuit of FIG.

  As is clear from this figure and FIG. 12, in this bypass circuit, a switch is provided only at the input portion. When the operation of the power amplifier is completely stopped, the impedance along the outer circle is taken as shown in the Smith chart of FIG. This indicates that the amplifier output impedance can be regarded as an open impedance by providing a line having an appropriate length (see FIG. 13B) between the power amplifier output and the bypass path.

  As a result, low-loss bypass switching can be realized without attaching a switch to the lossy output side.

  In this way, the first embodiment and the second embodiment described above can be applied.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIGS.

  In the present embodiment, the switching operation between the amplifier operation and the bypass operation is performed in the post-stage amplifier of the first embodiment, while the amplifiers (1031-1, 1031- 2) is used by switching.

  For example, when the amplifier A and the amplifiers 1031-1 and 1031-2 use transistors as active elements, the gate widths of the transistors of the small amplifiers 1031-1 and 1031-2 are made smaller than those of the amplifier A transistors.

  The small amplifiers 1031-1 and 1031-2 output lower power than the amplifier A. That is, in FIG. 16, the small amplifiers 1031-1 and 1031-2 operate in a medium output mode with an output power of 15 dBm to 22 dBm.

  In the fourth embodiment, the gain can be kept as shown in FIG. 16 even when the output is low with respect to the bypass switching.

  Further, a level conversion circuit 1000 is provided so that the bias current (voltage) of the small amplifiers 1031-1 and 1031-2 can be adjusted even after switching to the small amplifiers 1031-1 and 1031-2. 1031-2 is moving.

  That is, the bias current (voltage) of the small amplifiers 1031-1 and 1031-2 can be controlled by the output of the level conversion circuit 1000. As described above, in the power amplifier according to the present embodiment, the amplifier gain can be controlled more finely than the power amplifier according to the first embodiment. Further, the use of a small (rear stage) amplifier as compared with the transistor of the amplifier A has an effect of improving efficiency.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Since the circuit of the present invention can be composed of standard MOS devices and bipolar transistors, it can be widely applied to power amplifier circuits. Specifically, the present invention can also be applied to variable gain amplifiers for various wireless applications such as mobile phone power amplifiers, mobile phones, and W-LANs.

101 ... Input matching circuit, 102-1, 102-2 ... First stage amplifier,
103-1, 103-2 ... latter stage amplifier, A ... amplifier, B ... bypass,
104... Phase shift circuit for output,
105 ... Internal temperature compensation current control circuit, 106 ... Setting circuit, 107 ... Variable voltage source,
108-1, 108-2 ... middle stage amplifier, 109 ... constant current source, 110 ... switch,
Ar ... resistance, Cb ... capacitance, Sb, Sbias ... switch, Rb ... resistance,
CAPl, CAPh ... coupler, SWh, SWl, SWp1, SWp2 ... switch,
All Bypass ... Bypass.

Claims (8)

A first amplifier for amplifying an input signal; and a second amplifier having an amplification path for amplifying a signal derived from the output of the first amplifier and a bypass path for not performing amplification.
When the output of the first amplifier is less than a predetermined threshold, the second amplifier outputs a signal derived from the output of the first amplifier through the bypass path;
And a setting circuit for controlling a bias current of the first amplifier, and a first bias current source for generating a bias current input to the first amplifier. The first bias current source is controlled according to the transmission path of the input signal and the internal temperature,
The setting circuit has a first temperature characteristic and a second temperature characteristic which are selectively used depending on a transmission path of an input signal of the second amplifier, and the setting circuit is based on the first temperature characteristic and the second temperature characteristic. Determining the output current of the first bias current source;
The first temperature characteristic is a power amplifier having a non-linear characteristic. An amplification bypass path that bypasses the first amplifier and the second amplifier;
2. The power amplifier according to claim 1, wherein when an output expected from the power amplifier is equal to or less than a predetermined value, an input signal is output via the bypass path.   The amplification path includes a first transistor having a gate to which a signal derived from the output of the first amplifier is supplied, and the bypass path includes a resistor connected in series between the gate and drain of the first transistor. The power amplifier according to claim 1, further comprising a switch and a capacitor. The amplification path includes a first transistor having a gate to which a signal derived from the output of the first amplifier is supplied;
The bypass path includes a plurality of second transistors connected in series between the gate and drain of the first transistor,
The second amplifier includes a resistor and a switch connected in series between the gate of the first transistor and a predetermined voltage, and the switch includes the resistor when the plurality of second transistors are turned on. A bias voltage is supplied to the gate of the first transistor via the resistor when the third transistor for supplying the predetermined voltage to the gate of the first transistor via the resistor and the plurality of second transistors are turned off. The power amplifier according to claim 1, further comprising a fourth transistor. A first amplifier for amplifying an input signal; and a second amplifier for amplifying a signal derived from the output of the first amplifier;
The first amplifier operates with current from a first bias current source or a second bias current source;
The circuit further includes a setting circuit for controlling the bias current of the first amplifier, the setting circuit including a first temperature characteristic used in the first bias current source and a second temperature used in the second bias current source. Temperature characteristics,
Whether to use the first bias current source or the second bias current source is determined by the expected output power of the power amplifier;
In the first bias current source, the output power of the power amplifier is smaller than the output power of the power amplifier assumed by the second bias current source,
A power amplifier in which the first temperature characteristic used in the first bias current source is nonlinear.   A power amplifier for W-CDMA using the power amplifier according to claim 1.   A multiband power amplifier using the power amplifier according to any one of claims 1 to 5.   A portable information terminal using the power amplifier according to any one of claims 1 to 5.

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