JP5644806B2 - Insulating substrate, semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an insulating substrate excellent in heat dissipation and a semiconductor device using the insulating substrate.

  Semiconductor modules used for power supply devices are applied in a wide range from consumer equipment such as home air conditioners and refrigerators to industrial equipment such as inverters and servo controllers. In particular, semiconductor modules equipped with power semiconductors such as IGBTs (Insulated Gate Bipolar Transistors) generate a large amount of heat from the power semiconductor elements. Therefore, metal base boards and ceramic boards with excellent heat dissipation are mounted on the power semiconductor element mounting boards. An insulating substrate using is used.

FIG. 4 is a cross-sectional view showing a conventional example of a metal base substrate.
In FIG. 4, 1 is a base metal plate such as aluminum or copper, 20 is an insulating layer made of an epoxy resin containing an inorganic filler (not shown), and 3 is a circuit pattern layer.

The metal base substrate has a three-layer structure in which an insulating layer 20 is formed on a base metal plate 1 and a circuit pattern 3 is formed on the insulating layer 20. Here, the inorganic filler is selected from silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride AlN, and the like.

  The circuit pattern 3 is usually made of copper foil, but aluminum foil may be used. The copper foil having a thickness of about 35 μm to 140 μm is usually used. This copper foil is processed into a predetermined circuit pattern by wet etching. In the case of a power semiconductor having a small current capacity of about 10 A and low heat generation, the power semiconductor is directly mounted on the circuit pattern 3 by soldering. When the current capacity of the power semiconductor increases, the heat is spread on the circuit pattern 3 to reduce the thermal resistance, so that the thickness of the copper foil is as thick as about 140 μm. If 140 μm is insufficient, a thicker copper foil such as 200 μm or 250 μm is used. Furthermore, if the thickness of the circuit pattern 103 is 1 mm or more, for example, 3 to 4 mm, the heat spreader effect is exhibited, the heat generated in the power semiconductor spreads in the lateral direction, and the thermal resistance is greatly reduced.

  The insulating layer 20 used for the metal base substrate needs to be excellent in insulation reliability and heat dissipation. Furthermore, the insulating layer 20 is also required to have excellent stress relaxation properties, moisture resistance, heat resistance, and the like, and resin compositions suitable for the insulating layer 20 are also known (see, for example, Patent Documents 1 to 3). ). In this way, the circuit pattern 3 is joined to the base metal plate 1 through the insulating layer 20 having excellent heat dissipation, so that the metal base substrate is used as a wiring substrate for mounting a high heat-generating component such as a power semiconductor. (See Patent Documents 1 to 4).

However, in the case of an epoxy resin containing an inorganic filler such as SiO ₂ , Al ₂ O ₃ , or AlN, there is a limit to the amount of inorganic filler that can be filled in the resin. Its thermal conductivity is currently about 7 to 10 W / m · K. Therefore, there is a limit to the current capacity of the power semiconductor module that can be applied, and at present, it can only be applied up to about 50 A class.

  On the other hand, in the case of a larger capacity semiconductor module exceeding 50A, an insulating substrate using a ceramic plate having a higher thermal conductivity of the insulating layer is used instead of the metal base wiring substrate.

  FIG. 5 is a cross-sectional view showing a conventional example of an insulating substrate (hereinafter referred to as a ceramic insulating substrate) in which a ceramic plate is to be used, where (a) shows a ceramic insulating substrate and (b) shows a ceramic to which a base metal is bonded. An insulating substrate is shown.

  The ceramic insulating substrate is configured by pasting circuit patterns 3 on both surfaces of a ceramic plate 31. The ceramic plate 31 is produced by kneading the raw material powder with a binder to form a sheet-like insulating plate called a green sheet and firing it at a high temperature. Thereafter, a copper foil or an aluminum foil for the circuit pattern 3 is joined at a high temperature to form a wiring board. Further, these ceramic wiring boards are usually bonded to a copper base metal 33 having a thickness of about 2 to 3 mm via a solder layer 32.

The ceramic plate 31 is made of SiO ₂ , Al ₂ O ₃ , AlN, Si ₃ N ₄ or the like as a raw material. The thermal conductivity of the ceramic plate 31 is about 20 W / m · K when the raw material is Al ₂ O ₃ , 160 to 180 W / m · K when the raw material is AlN, and when the raw material is Si ₃ N ₄ 80 W / m · K, which is 1 to 2 orders of magnitude higher than when an inorganic filler is added to an epoxy resin.

  4 and 5, in order to reduce the thermal resistance of the path from the power semiconductor mounted on the circuit pattern to the outside, an attempt is made to increase the thickness of the copper foil as the circuit pattern 3. Yes.

JP 2002-12653 A JP 2002-76549 A JP 2002-114836 A Japanese Patent Laid-Open No. 2003-229508

  However, in the case of the above-described conventional metal base substrate, when the copper foil is increased in order to reduce the thermal resistance, the etching process time for processing the circuit pattern layer becomes longer in proportion to the thickness. Therefore, there is a problem that the processing cost is significantly increased and the cost is greatly increased. Moreover, if the thickness of the circuit pattern layer is 3 to 4 mm, not only will it take a long time to melt copper, but the etching of the edge of the circuit pattern layer cannot be performed with high accuracy, so the etching process itself is realistic. Not.

  In the case of a ceramic insulating substrate, a ceramic plate is manufactured once, a circuit pattern layer is bonded to it, an etching process is performed, and the ceramic insulating substrate thus manufactured is bonded to a base metal with solder. Therefore, there is a problem that the price is high and it is difficult to reduce the price.

  Moreover, in the case of a ceramic insulating substrate, the copper foil for the circuit pattern cannot be made too thick. To increase the heat spreader effect, a thick copper foil or copper plate may be attached, but the copper plate is bonded to the ceramic insulating plate at a high temperature of about 1000 ° C or higher. Will bend due to bimetal effect during cooling. Further, as described above, since the etching cost increases significantly when the copper foil or the copper plate becomes thicker, the thickness of the circuit pattern of the ceramic insulating substrate is currently only used to about 0.6 mm or less. Not.

  Compared to the above-described conventional technology, in a wiring board in which a metal foil is bonded to an insulating plate and the metal foil is processed to form a circuit pattern, a metal material is laminated on the upper part of the circuit pattern by a cold spray method to increase the thickness. There is a method of forming by.

According to such an insulating substrate, a thicker stacked metal pattern can be formed on the circuit pattern of the metal foil.
However, there is a problem that expensive metal powder for cold spray must be used in many cases to accumulate by cold spray method, and there is a problem that the price is high, and film formation by cold spray method also takes time. there were.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an insulating substrate that can be manufactured with less man-hours, is inexpensive and has excellent heat dissipation, a manufacturing method thereof, and a semiconductor device using the same. It is in providing the manufacturing method of.

In the present invention, in order to solve the above problem, a metal block bonded to a circuit pattern formed on an insulating layer and plastically deformed metal particles are laminated so as to cover the upper and side surfaces of the metal block. And an overlaid circuit pattern .

  According to such an insulating substrate, the heat generated by the semiconductor element can be diffused by the stacked circuit pattern and the metal block, so that the thermal resistance can be reduced, and a wiring board having a small heat resistance and excellent heat dissipation can be configured. it can.

  According to the present invention, by forming a thick circuit pattern directly on a circuit pattern of a metal base substrate plate or a ceramic insulating substrate, an insulating substrate having low thermal resistance and excellent cooling performance can be obtained.

  Further, by forming the stacked circuit pattern so as to cover the metal block to be bonded on the circuit pattern, it is possible to save expensive metal powder used for cold spraying. A circuit pattern can be formed by cold spraying so as to cover not only the upper surface of the metal block but also the side surface so as to obtain the same effect as that formed in the bulk state of the metal used.

It is sectional drawing which shows the manufacturing process of the wiring board of this invention. It is a figure which shows the state which mounted the power semiconductor on the stacked circuit pattern laminated | stacked by cold spray. It is a figure which shows the state which formed the plating layer previously on the surface of a circuit pattern and a metal block. It is sectional drawing which shows the prior art example of a metal base board | substrate. It is sectional drawing which shows the prior art example of the insulated substrate which wants to use a ceramic board.

The best mode for carrying out the present invention will be described below with reference to the drawings.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view showing a manufacturing process of a wiring board according to the present invention. Hereinafter, it demonstrates along a figure.

In FIG. 1A, 1 is a base metal plate such as aluminum or copper, 2 is an insulating layer made of an epoxy resin containing an inorganic filler (not shown), and 3 is a circuit pattern layer.
The metal base substrate has a three-layer structure in which an insulating layer 2 is formed on a base metal plate 1 and a circuit pattern 3 is formed on the insulating layer 2. In this embodiment, copper is used for the base metal plate, and the inorganic filler is selected from silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride AlN, and the like.

  In the present embodiment, a copper foil is used for the circuit pattern 3. Aluminum foil may be used. This copper foil is processed into a predetermined circuit pattern by wet etching. Here, the thickness of the circuit pattern 3 is usually about 35 μm to 140 μm. This is a standard one used conventionally and can be manufactured at low cost.

The width / thickness of the circuit pattern 3 is selected according to the current capacity of the semiconductor module, which will be described later. However, the thinner one is advantageous from the viewpoint of etching.
Next, in FIG. 1B, a plate solder (sheet) 4 and a metal block 5 are placed on the circuit pattern 3 in which the power semiconductor is mounted in a later step. In this state, the metal block 5 may be soldered on the circuit pattern 3 by heating once. This soldering process will be described later. For the metal block, copper, aluminum, iron, titanium, molybdenum, or the like is used in consideration of conductivity and thermal expansion coefficient. In this embodiment, copper is used. Copper is inexpensive and easy to process, and has lower electrical resistance and higher thermal conductivity than iron and the like, and therefore is advantageous from the viewpoint of conductivity and thermal conductivity even when used in a current path of a power semiconductor.

Next, in FIG. 1C, reference numeral 6 denotes a mask opened only at predetermined positions. Since the metal powder is laminated on the metal block by the cold spray method, the metal block is opened.
Here, the cold spray method will be described. The cold spray method is one of thermal spraying techniques. In the cold spray method, a gas having a temperature lower than the melting point or softening temperature of the thermal spray material is converted to a supersonic flow, and the thermal spray material particles are injected into the flow to accelerate it. This is a technique for forming a film. The feature of cold spray is that the temperature of the working gas for heating and accelerating the sprayed material particles is significantly lower than plasma spraying, flame spraying, high-speed flame spraying, and the like. Plasma spraying and the like require a high working gas temperature of 2000 to 8000 ° C., but in the case of cold spray, a working gas of room temperature to about 600 ° C. may be used. The sprayed particles are heated so much that they are allowed to collide with the substrate at a high speed while in the solid state, and the energy causes plastic deformation of the substrate and the particles to form a film.

  The film forming apparatus by the cold spray method is configured as follows. A high-pressure gas supplied from a gas source such as a cylinder is branched to a powder supply device and a gas heater. Of these, the mainstream working gas flows through a coiled gas pipe heated directly or indirectly by an electric furnace or the like to increase the temperature, is supplied to a spray gun, is accelerated by a supersonic nozzle, and is ejected.

  On the other hand, a part of the working gas is diverted to the powder supply device and flows into the rear of the spray gun together with the spray powder as a carrier gas. In some cases, the working gas is not heated, but heating is advantageous in that it can increase the particle velocity and easily cause plastic deformation of the particles. Air, helium, or nitrogen is used as the gas.

  FIG.1 (c) has shown a mode that the metal particle is laminated | stacked by the cold spray method. In the present embodiment, molybdenum having a particle size of 1 to 50 μm is used. As the particulate material, copper, aluminum, iron, titanium, molybdenum, or the like can be used in consideration of conductivity, thermal expansion coefficient, and the like. These particles are deposited by spraying through a metal mask 6 from a position about 10 mm to 50 mm away at a speed of 500 m / s to 900 m / s. The stacked circuit pattern laminated by cold spray can obtain the thermal conductivity of the laminated metal. Molybdenum has a thermal expansion coefficient close to that of silicon forming a power semiconductor, compared to copper used for circuit patterns. Therefore, it is possible to suppress the stress applied to the joint portion between the power semiconductor and the stacked circuit pattern in the heat cycle accompanying the heat generation of the power semiconductor.

  FIG. 1 (d) shows a state in which the stacked circuit pattern 7 is formed. The film thickness of the stacked circuit pattern 7 can be set to a desired film thickness by controlling the spraying time of the cold spray. The thickness of the stacked circuit pattern 7 is set in consideration of the heat generated when the power semiconductor is energized. For example, it is about 0.5 mm to 5 mm. In addition, the thickness of the metal block is set to 50% to 70% of the thickness to be stacked by cold spray.

  The thickness of the sheet solder 4 shown in FIG. 1B is 125 μm to 250 μm. When the metal block 5 is soldered to the circuit pattern 3 in advance, the thickness of the solder layer is set to 100 μm to 150 μm.

  If the circuit pattern 3 and the metal block 5 are soldered before the stacked circuit patterns are stacked, the gas generated when the solder is melted easily escapes from the side surface, and voids are unlikely to remain between the metal block 5 and the circuit pattern 3. Become. Later, when soldering a semiconductor element or an external lead-out terminal, the solder of the circuit pattern 3 and the metal block 5 does not melt and flow out in the subsequent soldering process. It is necessary to select a high solder.

  Alternatively, plate solder may be used for soldering the circuit pattern 3 and the metal block 5 and may be performed simultaneously with the soldering of the semiconductor element and the external lead-out terminal after the formation of the stacked circuit pattern. In this case, the soldering process can be reduced, and the solder to be used can be selected to have the same melting point. In addition, if plate solder is used, there is almost no generation of gas when the solder is melted, and generation of voids is also suppressed. Further, although not shown, in order to easily remove the gas generated when the solder melts, when the upper circuit pattern is formed by the cold spray method, the joint between the circuit pattern 3 and the metal block 5 is not completely covered. The shape of the opening in the mask 6 may be adjusted.

Here, although the case of the metal base substrate has been described, the stacked circuit pattern 7 can be formed by the same manufacturing method even with the ceramic insulating substrate shown in FIG.
FIG. 2 shows a state in which the power semiconductor 8 is mounted on the stacked circuit pattern 7 laminated by cold spray. The power semiconductor 8 is usually joined with SnPb solder or SnAgCu solder. Subsequently, a wire 9 is connected to connect the power semiconductor 8 and an external circuit. In the case of an element having a large current capacity such as a power semiconductor, an aluminum wire is usually used.

  When a material difficult to be soldered is selected for the circuit pattern 3 and the metal block 5, as shown in FIG. 3, the surface (solder joint surface) of the circuit pattern 3 and the metal block 5 is previously plated with good solder wettability. The layer 10 is preferably formed. The plating layer 10 is preferably nickel plating.

3A is a cross-sectional view corresponding to FIG. 1D, FIG. 3B is a cross-sectional view of the main part, and the plating layer is different from FIG. 3A.
In the example of FIG. 3A, the plating layer 10 on the circuit pattern 3 is formed only in the solder joint region. Thus, by selectively forming the plating layer 10 on the circuit pattern 3, there is no plating layer between the circuit pattern 3 and the stacked circuit pattern 7, and the bonding between the two becomes strong.

  In the example of FIG. 3B, the plating layer 10 is formed on the entire surface of the circuit pattern 3. As described above, if the plating layer 10 is formed on the entire surface of the circuit pattern 3, a mask process for selective plating (partial plating) as shown in FIG. Moreover, the metal laminated | stacked by the cold spray as an upper layer circuit pattern is good to select the same metal as a plating layer, or a metal (for example, nickel) with a strong joint with a plating layer.

Finally, the setting of the total thickness of the circuit pattern 3, the solder 4, the metal block 5, and the stacked circuit pattern 7 will be described.
The heat flow generated from the power semiconductor 8 joined to the stacked circuit pattern has a property that it normally diffuses and spreads at an angle of 45 degrees toward the insulating substrate. Therefore, if the distance a from the chip end of the power semiconductor 8 to the end of the stacked circuit pattern 5 is equal to the total thickness b of the circuit pattern 3, solder 4, metal block 5, and stacked circuit pattern 7, the heat spreader effect is obtained. It can be maximized and the thermal resistance can be greatly reduced. For this reason, it is not necessary to forcefully increase the width of the circuit pattern 3 and the upper circuit pattern 5 with respect to the size of the power semiconductor 8, and it is not necessary to forcibly increase the thickness of the upper circuit pattern 5.

  From the above relationship, the ratio of the distance a from the end of the power semiconductor 8 to be mounted to the end of the stacked circuit pattern 5 and the total thickness b of the circuit pattern 3, the solder 4, the metal block 5, and the stacked circuit pattern 7 1 is optimal, but if it is in the range of 0.8 to 1.2, substantially sufficient thermal diffusivity can be obtained. If this is less than 0.8, sufficient thermal diffusibility may not be obtained, and if it exceeds 1.2, the effect will be saturated.

DESCRIPTION OF SYMBOLS 1 Base metal plate 2 Insulating layer 3 Circuit pattern 4 Solder 5 Metal block 6 Mask 7 Stacked circuit pattern 8 Power semiconductor 9 Wire

Claims (12)

A metal block bonded to a circuit pattern formed on the insulating layer;
An insulating substrate comprising: an upper circuit pattern formed by laminating plastically deformed metal particles so as to cover an upper surface and a side surface of the metal block.   The upper circuit pattern includes a distance from an end of a semiconductor chip mounted on the upper circuit pattern to an end of the upper circuit pattern, and the upper circuit pattern on the upper surface of the circuit pattern, the metal block, and the metal block. 2. The insulating substrate according to claim 1, wherein the ratio with respect to the total thickness is in the range of 0.8 to 1.2.   The upper circuit pattern has a distance from an end portion of a semiconductor chip mounted on the upper circuit pattern to an end portion of the upper circuit pattern, the distance between the circuit pattern, the metal block, and the upper surface of the metal block. 2. The insulating substrate according to claim 1, wherein the total thickness is equal to the total thickness.   The insulating substrate according to any one of claims 1 to 3, wherein the upper circuit pattern is one of copper, aluminum, iron, titanium, molybdenum, and nickel. Forming a plating layer on the entire surface of the metal block and the joint surface of the circuit pattern with the metal block, and solder-joining the circuit pattern and the metal block;
2. The insulating substrate according to claim 1, wherein the upper circuit pattern is formed of the metal particles having strong bonding with a plating layer formed on the entire surface of the metal block. A metal block bonded to a circuit pattern formed on the insulating layer, and an insulating substrate having an overlaid circuit pattern formed by laminating metal particles plastically deformed so as to cover an upper surface and a side surface of the metal block; ,
A semiconductor chip mounted on the stacked circuit pattern,
The ratio of the distance from the end of the semiconductor chip mounted on the stacked circuit pattern to the end of the stacked circuit pattern and the total thickness of the stacked circuit pattern on the top surface of the circuit pattern, the metal block, and the metal block Is in the range of 0.8 to 1.2. Bonding a metal block to the circuit pattern formed on the insulating layer,
A method of manufacturing an insulating substrate, comprising forming a stacked circuit pattern by plastically deforming and directly laminating metal particles so as to cover an upper surface and side surfaces of the metal block .   The upper circuit pattern includes a distance from an end of a semiconductor chip mounted on the upper circuit pattern to an end of the upper circuit pattern, and the upper circuit pattern on the upper surface of the circuit pattern, the metal block, and the metal block. 8. The method for manufacturing an insulating substrate according to claim 7, wherein the ratio of the total thickness is in the range of 0.8 to 1.2.   The upper circuit pattern has a distance from an end portion of a semiconductor chip mounted on the upper circuit pattern to an end portion of the upper circuit pattern, the distance between the circuit pattern, the metal block, and the upper surface of the metal block. 8. The method for manufacturing an insulating substrate according to claim 7, wherein the total thickness is equal to the total thickness.   The method for manufacturing an insulating substrate according to any one of claims 7 to 9, wherein the upper circuit pattern is any one of copper, aluminum, iron, titanium, molybdenum, and nickel. Forming a plating layer on the entire surface of the metal block and the joint surface of the circuit pattern with the metal block, and solder-joining the circuit pattern and the metal block;
The method for manufacturing an insulating substrate according to claim 7, wherein the upper circuit pattern is selected from metals having strong bonding with a plating layer formed on the entire surface of the metal block. A metal block is bonded to a circuit pattern formed on an insulating layer, and an insulating substrate is prepared by plastically deforming metal particles so as to cover the upper surface and side surfaces of the metal block and directly stacking to form a stacked circuit pattern , Including a step of mounting a semiconductor chip on the stacked circuit pattern;
The ratio between the distance from the end of the semiconductor chip mounted on the stacked circuit pattern to the end of the stacked circuit pattern and the total thickness of the stacked circuit pattern on the top surface of the circuit pattern, the metal block, and the metal block Is in the range of 0.8 to 1.2.

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