JP5643592B2 - Protective relay - Google Patents

Protective relay Download PDF

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JP5643592B2
JP5643592B2 JP2010227986A JP2010227986A JP5643592B2 JP 5643592 B2 JP5643592 B2 JP 5643592B2 JP 2010227986 A JP2010227986 A JP 2010227986A JP 2010227986 A JP2010227986 A JP 2010227986A JP 5643592 B2 JP5643592 B2 JP 5643592B2
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circuit
current transformer
current
analog signal
negative resistance
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JP2012085401A (en
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佑亮 柳橋
佑亮 柳橋
紘之 白川
紘之 白川
宏之 前原
宏之 前原
須賀 紀善
紀善 須賀
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Toshiba Corp
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Description

本発明の実施形態は、保護継電器に関する。   Embodiments of the present invention relate to a protective relay.

従来、電力系統の系統事故の有無を判断し、系統事故区間に設置された遮断器の動作判定をするために保護継電器を用いている。この保護継電器は、入力電流の大きさを変換する変流器と、変流器2次側の信号を所定レベルに変換するアナログ変換回路を介した後、A/D変換回路によりA/D変換している。更に、デジタル信号として演算処理回路に取り込み、演算処理回路にて所定の演算処理を行うことで、動作判定している。   Conventionally, a protective relay is used to determine the presence or absence of a grid fault in the power system and to determine the operation of a circuit breaker installed in the grid fault section. This protective relay goes through a current transformer that converts the magnitude of the input current and an analog conversion circuit that converts the signal on the secondary side of the current transformer to a predetermined level, and then A / D converts by the A / D conversion circuit. doing. Furthermore, the operation is determined by taking it into the arithmetic processing circuit as a digital signal and performing predetermined arithmetic processing in the arithmetic processing circuit.

この入力電流の大きさを変換する変流器は、直流分を含む系統事故電流が流れた場合の変流器飽和を防止するために、変流器の鉄心断面積増加、二次巻線の巻数増加、二次巻線の断面積増加等によって変流器飽和特性を向上させていた。しかし、これらの飽和対策は変流器の大型化を招くという課題があった。   The current transformer that converts the magnitude of the input current increases the core cross-sectional area of the current transformer and the secondary winding in order to prevent saturation of the current transformer when a system fault current including a DC component flows. Current transformer saturation characteristics were improved by increasing the number of turns and the cross-sectional area of the secondary winding. However, these saturation measures have the problem of causing an increase in the size of the current transformer.

また、従来の保護継電器は、変流器飽和による誤判定防止のため、A/D変換後のデジタル信号の正波・負波の各々の振幅が、保護継電器のアナログ変換および演算処理回路で決定されるフルスケール値を超えた場合に、動作判定を実行しているが、正波または負波の一方がフルスケール値を超えるような直流分を含む系統事故電流では、正しく動作判定できない虞があった。   In addition, in the conventional protective relay, in order to prevent erroneous determination due to current transformer saturation, the amplitude of each positive and negative wave of the digital signal after A / D conversion is determined by the analog conversion and arithmetic processing circuit of the protective relay However, it may not be possible to correctly determine the operation with a grid fault current that includes a DC component such that one of the positive or negative waves exceeds the full scale value. there were.

特開2009−201209号公報JP 2009-201209 A

上述したように、直流分を含む系統事故電流が流れた場合の変流器飽和を防止するために変流器が大型化するという課題がある。さらに、演算処理による変流器飽和時の誤判定防止策は、正波または負波の一方がフルスケール値を超えるような事故電流で、正しく動作判定できない可能性がある。   As described above, there is a problem that the current transformer increases in size in order to prevent current transformer saturation when a system fault current including a direct current component flows. Furthermore, the erroneous determination prevention measure at the time of current transformer saturation by the arithmetic processing may not be able to correctly determine the operation with an accident current in which one of the positive wave and the negative wave exceeds the full scale value.

本発明の実施形態は、直流分を含む系統事故電流が流れた場合にも、精度よく動作判定できる保護継電器を提供することを目的とする。   An object of the present invention is to provide a protective relay capable of accurately determining an operation even when a system fault current including a direct current component flows.

本発明の実施形態に係る保護継電器は、入力電流の大きさを変換し、アナログ信号として出力する入力変流器と、入力変流器から出力されたアナログ信号を、所定のアナログ信号を示す所定アナログ信号に変換するアナログ変換回路と、アナログ変換回路により変換された所定アナログ信号をデジタル信号に変換するA/D変換回路と、A/D変換回路により変換されたデジタル信号に基づいて演算処理を行う演算処理回路と、演算処理回路の演算結果に応じて接点出力を動作させるリレー出力回路とを備える保護継電器において、アナログ変換回路は、入力変流器から出力されたアナログ信号を、負性抵抗回路およびパワーブースタ回路を介して受信し、パワーブースタ回路は、負性抵抗回路から出力されるアナログ信号がプラスの場合に当該プラスのアナログ信号の強度を増大させてアナログ変換回路に出力する第1のトランジスタと、負性抵抗回路から出力されるアナログ信号がマイナスの場合に当該マイナスのアナログ信号の強度を増大させてアナログ変換回路に出力する第2のトランジスタとを備える。 A protective relay according to an embodiment of the present invention includes an input current transformer that converts the magnitude of an input current and outputs the converted signal as an analog signal, and an analog signal output from the input current transformer. An analog conversion circuit for converting into an analog signal, an A / D conversion circuit for converting a predetermined analog signal converted by the analog conversion circuit into a digital signal, and an arithmetic process based on the digital signal converted by the A / D conversion circuit In a protective relay comprising an arithmetic processing circuit to be performed and a relay output circuit that operates a contact output according to an arithmetic result of the arithmetic processing circuit , the analog conversion circuit converts the analog signal output from the input current transformer into a negative resistance Circuit and the power booster circuit, and the power booster circuit is used when the analog signal output from the negative resistance circuit is positive. A first transistor that increases the intensity of the positive analog signal and outputs it to the analog conversion circuit, and an analog signal that increases the intensity of the negative analog signal when the analog signal output from the negative resistance circuit is negative. And a second transistor that outputs to the conversion circuit .

第1の実施形態における保護継電器の構成を示すブロック図。The block diagram which shows the structure of the protection relay in 1st Embodiment. 第1の実施形態における入力変流器1の等価回路を示す図。The figure which shows the equivalent circuit of the input current transformer 1 in 1st Embodiment. 第1の実施形態における負性抵抗回路8の等価回路を示す図。The figure which shows the equivalent circuit of the negative resistance circuit 8 in 1st Embodiment. 第1の実施形態における負性抵抗回路8とパワーブースタ回路29の等価回路を示す図。The figure which shows the equivalent circuit of the negative resistance circuit 8 and the power booster circuit 29 in 1st Embodiment. 第2の実施形態におけるサーミスタ30を適用した負性抵抗回路8の等価回路を示す図。The figure which shows the equivalent circuit of the negative resistance circuit 8 to which the thermistor 30 in 2nd Embodiment is applied.

本発明の実施形態における保護継電器について図面を参照して説明する。   A protective relay according to an embodiment of the present invention will be described with reference to the drawings.

(第1の実施形態)
第1の実施形態における保護継電器の構成について図1を用いて説明する。図1は保護継電器の構成を示すブロック図である。保護継電器は入力変流器1、負性抵抗回路8、アナログ変換回路2、A/D変換回路3、演算処理回路4、リレー出力回路5、接点出力6から構成されている。
(First embodiment)
The configuration of the protective relay according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the protective relay. The protective relay includes an input current transformer 1, a negative resistance circuit 8, an analog conversion circuit 2, an A / D conversion circuit 3, an arithmetic processing circuit 4, a relay output circuit 5, and a contact output 6.

入力変流器1により入力電流の大きさを変換し、所定の電流比によって取り込まれた電流波形をアナログ信号として、負性抵抗回路8を介してアナログ変換回路2に送信する。   The magnitude of the input current is converted by the input current transformer 1, and the current waveform captured at a predetermined current ratio is transmitted as an analog signal to the analog conversion circuit 2 via the negative resistance circuit 8.

アナログ変換回路2は、アナログ前置フィルタやオペアンプ等から構成され、負性抵抗回路8から入力されたアナログ信号に含まれる高周波の除去や、信号強度を所定の値に変換を行う。さらに、高周波が除去され、信号強度が所定の値に変換された所定アナログ信号をA/D変換回路3に出力する。   The analog conversion circuit 2 includes an analog prefilter, an operational amplifier, and the like, and removes high frequency contained in the analog signal input from the negative resistance circuit 8 and converts the signal intensity to a predetermined value. Further, a predetermined analog signal from which the high frequency is removed and the signal intensity is converted to a predetermined value is output to the A / D conversion circuit 3.

A/D変換回路3は、アナログ変換回路2から入力された所定アナログ信号をデジタル信号に変換し、演算処理回路4にデジタル信号を出力する。   The A / D conversion circuit 3 converts the predetermined analog signal input from the analog conversion circuit 2 into a digital signal, and outputs the digital signal to the arithmetic processing circuit 4.

演算処理回路4は、A/D変換回路3から入力されたデジタル信号に基づいて、図示しない遮断器の動作判定を行うための演算処理を行い、演算結果をリレー出力回路5を介して接点出力6に出力する。   The arithmetic processing circuit 4 performs arithmetic processing for determining the operation of a circuit breaker (not shown) based on the digital signal input from the A / D conversion circuit 3, and outputs the arithmetic result via the relay output circuit 5 as a contact output. 6 is output.

接点出力6は、図示しない遮断器と接続されており、保護継電器の演算処理回路4からリレー出力回路5を介して入力される演算結果に基づいて、遮断器を動作させる。   The contact output 6 is connected to a circuit breaker (not shown), and operates the circuit breaker based on a calculation result input from the arithmetic processing circuit 4 of the protective relay through the relay output circuit 5.

次に、入力変流器1の構成について図2を用いて説明する。図2は、入力変流器1および負性抵抗回路8の構成を示す等価回路である。   Next, the configuration of the input current transformer 1 will be described with reference to FIG. FIG. 2 is an equivalent circuit showing the configuration of the input current transformer 1 and the negative resistance circuit 8.

入力端子9から入力端子10に入力電流Iを流し、変流器一次巻線11によって、図示しない変流器の鉄心に磁束φが発生し、磁束φによって変流器二次巻線12に誘起電圧Eが発生し、電流Iが変流器二次側に流れる。変流器飽和特性を示すための変流器の飽和電流算出式を導き出すにあたり、変流器入力インピーダンスZinと変流器飽和時の入力電圧Eを式(1)、式(2)、式(3)に示す。 An input current I 1 flows from the input terminal 9 to the input terminal 10, and a magnetic flux φ is generated in the iron core of a current transformer (not shown) by the current transformer primary winding 11, and the current transformer secondary winding 12 is generated by the magnetic flux φ. An induced voltage E 2 is generated, and a current I 2 flows to the current transformer secondary side. Upon deriving the saturation current equation for calculating the current transformer for indicating the current transformer saturation characteristics, current transformer input impedance Z in and the current transformer saturation when the input voltage E m the formula (1), equation (2), It shows in Formula (3).

変流器入力インピーダンスZinは、変流器一次巻線抵抗16、変流器二次巻線抵抗17、変流器二次負荷インピーダンス21、変流器一次巻回数18、変流器二次巻回数19から式(1)のように示される。

Figure 0005643592
The current transformer input impedance Z in is the current transformer primary winding resistance 16, the current transformer secondary winding resistance 17, the current transformer secondary load impedance 21, the current transformer primary winding frequency 18, the current transformer secondary. The number of windings 19 is expressed as in equation (1).
Figure 0005643592


変流器飽和時の入力電圧Eは、変流器鉄心に発生する磁束φの変化、変流器一次巻回数Nから式(2)のように示され、また変流器入力インピーダンスZinと変流器飽和電流Imaから式(3)のように示される。

Figure 0005643592

Figure 0005643592

Input voltage E m at current transformer saturation, the change of the magnetic flux φ generated in the current transformer core, shown from the current transformer primary windings N 1 as equation (2), also the current transformer input impedance Z From in and the current transformer saturation current I ma , it is expressed as in equation (3).
Figure 0005643592

Figure 0005643592


さらに、式(1)、式(2)、式(3)から変流器飽和電流Imaは式(4)のように示される。

Figure 0005643592

Furthermore, the current transformer saturation current I ma is expressed by the equation (4) from the equations (1), (2), and (3).
Figure 0005643592


(一般的な変流器は変流器一次巻線抵抗r≒0とし無視できる。)
ここで、
ma :変流器飽和電流(Arms
:変流器飽和時の入力電圧(Vrms
ω :角周波数(rad/s)
f :入力周波数(Hz)
:変流器一次巻線の巻回数18(T)
:変流器二次巻線の巻回数19(T)
S :鉄心断面積(cm
:最大磁束密度(Wb/m
φ :変流器鉄心発生磁束(Wb)
in :変流器入力インピーダンス(Ω)
:変流器一次巻線抵抗16の抵抗値(Ω)
:変流器二次巻線抵抗17の抵抗値(Ω)
:変流器二次負荷インピーダンス21の抵抗値(Ω)
としている。

(A typical current transformer is negligible with a current transformer primary winding resistance r 1 ≈0.)
here,
I ma : Current transformer saturation current (A rms )
E m : Input voltage at the time of current transformer saturation (V rms )
ω: angular frequency (rad / s)
f: Input frequency (Hz)
N 1 : Number of turns of the current transformer primary winding 18 (T)
N 2 : Number of turns of current transformer secondary winding 19 (T)
S: Iron core cross-sectional area (cm 2 )
B m : Maximum magnetic flux density (Wb / m 2 )
φ: Magnetic flux generated by current transformer core (Wb)
Z in : Current transformer input impedance (Ω)
r 1 : resistance value of the current transformer primary winding resistance 16 (Ω)
r 2 : Resistance value of the current transformer secondary winding resistor 17 (Ω)
Z L : Resistance value of the current transformer secondary load impedance 21 (Ω)
It is said.

(4)式で示されるよう、変流器飽和電流Imaを大きくするためには、変流器一次巻回数Nを少なくする、変流器二次巻回数Nを多くする、鉄心断面積Sを大きくする、最大磁束密度Bの高い鉄心を採用する、変流器二次巻線抵抗rを小さくする、変流器二次負荷インピーダンスZを小さくする方法がある。ここでは、保護継電器に負性抵抗回路8を供えることにより、変流器二次巻線抵抗17を小さくし、変流器飽和電流Imaを大きくしている。 As shown in the equation (4), in order to increase the current transformer saturation current I ma , the current transformer primary winding number N 1 is decreased, the current transformer secondary winding number N 2 is increased, the iron core breakage the area S is increased, it adopts a high iron core of maximum magnetic flux density B m, to reduce the current transformer secondary winding resistance r 2, there is a method of reducing the secondary load impedance Z L current transformer. Here, by providing the negative resistance circuit 8 in the protective relay, the current transformer secondary winding resistance 17 is reduced, and the current transformer saturation current Ima is increased.

次に、保護継電器における負性抵抗回路8の構成について図3を用いて説明する。図3は、負性抵抗回路8の構成を示す等価回路である。負性抵抗回路8は、抵抗22、23、24およびオペアンプ25から構成されている。   Next, the configuration of the negative resistance circuit 8 in the protective relay will be described with reference to FIG. FIG. 3 is an equivalent circuit showing the configuration of the negative resistance circuit 8. The negative resistance circuit 8 includes resistors 22, 23 and 24 and an operational amplifier 25.

負性抵抗回路8に入力される電圧Vは、変流器二次側に流れる電流と抵抗22、23、24と負性抵抗回路8から出力される電圧Vにより式(5)、(6)で与えられる。

Figure 0005643592


Figure 0005643592
Voltage V i which is input to the negative resistance circuit 8, the voltage V 0 which is output from the current flowing through the current transformer secondary side and the resistance 22, 23 and 24 a negative resistance circuit 8 (5), ( 6).
Figure 0005643592


Figure 0005643592


式(5)、(6)より負性抵抗回路8から出力される電圧Vは式(7)で与えられる。

Figure 0005643592

Equation (5), the voltage V o output from the negative resistance circuit 8 (6) given in equation (7).
Figure 0005643592


式(6)に式(7)を代入すると負性抵抗回路8に入力される電圧Vは式(8)で与えられる。

Figure 0005643592

Voltage V i which is input to the negative resistance circuit 8 Substituting equation (7) into equation (6) is given by Equation (8).
Figure 0005643592


式(8)から負性抵抗回路8の合成インピーダンスrは、式(9)のように示され負性の抵抗値を持つことになる。図3に示すように、負性抵抗回路8を設置しているため、負性の抵抗値である負性抵抗回路8の合成インピーダンス26により変流器二次巻線抵抗17をキャンセルできる。

Figure 0005643592

Combined impedance r 3 of the negative resistance circuit 8 from equation (8) will have a negative resistance value indicated by the equation (9). As shown in FIG. 3, since the negative resistance circuit 8 is installed, the current transformer secondary winding resistance 17 can be canceled by the combined impedance 26 of the negative resistance circuit 8 having a negative resistance value.
Figure 0005643592


ここで、
:負性抵抗回路8に入力される電圧(V0P
:負性抵抗回路8から出力される電圧(V0P
:変流器二次側に流れる電流(A0P
:抵抗22の抵抗値(Ω)
:抵抗23の抵抗値(Ω)
:抵抗24の抵抗値(Ω)
:負性抵抗回路8の合成インピーダンス26(Ω)
である。

here,
V i : Voltage input to the negative resistance circuit 8 (V 0P )
V o : voltage output from the negative resistance circuit 8 (V 0P )
I 2 : Current flowing in the secondary side of the current transformer (A 0P )
Z 1 : resistance value of the resistor 22 (Ω)
Z 2 : resistance value of the resistor 23 (Ω)
Z 3 : resistance value of the resistor 24 (Ω)
r 3 : Composite impedance 26 (Ω) of the negative resistance circuit 8
It is.

次に直流電流を含む系統事故電流が変流器に流れた場合の抵抗22、抵抗23、抵抗24、オペアンプ25の選定例を示す。   Next, a selection example of the resistor 22, the resistor 23, the resistor 24, and the operational amplifier 25 when a system fault current including a direct current flows to the current transformer will be described.

直流電流が100%重畳した場合の変流器二次側電流I2adは系統事故電流I1ad、変流器一次巻回数18、変流器二次巻回数19から式(10)のように示される。

Figure 0005643592
When the DC current is 100% superimposed, the current transformer secondary current I 2ad is expressed as shown in the equation (10) from the system fault current I 1ad , the current transformer primary winding number 18 and the current transformer secondary winding number 19. It is.
Figure 0005643592


系統事故電流I1ad=100Arms、系統周波数f=50Hz、変流器飽和電流Ima=180Arms、変流器一次巻回数N=1T、変流器二次巻回数N=3000T、変流器二次巻線抵抗r=210Ω、変流器二次負荷インピーダンスZ=10Ωを条件とすると、式(10)から変流器一次側に系統事故電流I1adが流れた場合の変流器二次側電流I2ad≒94.3mA0Pとなる。

Grid fault current I 1ad = 100 A rms , grid frequency f = 50 Hz, current transformer saturation current I ma = 180 A rms , current transformer primary winding number N 1 = 1 T, current transformer secondary winding number N 2 = 3000 T, variable Assuming that the current transformer secondary winding resistance r 2 = 210Ω and the current transformer secondary load impedance Z L = 10Ω, the change when the system fault current I 1ad flows to the primary side of the current transformer from Equation (10). The current flowing through the secondary side I 2ad ≈94.3 mA 0P .

ここで変流器の直流電流飽和を防止するため直流分を考慮し、直流分重畳無し時の飽和電流がオーバーサイズファクターK倍だけ多くなるよう設計する概念を導入し、変流器が飽和しない場合の変流器二次側電圧E2’を算出する。なおオーバーサイズファクターKは式(11)のように示される。

Figure 0005643592
Here, in order to prevent DC current saturation of the current transformer, the concept of designing so that the DC current is taken into consideration and the saturation current without DC superposition is increased by an oversize factor K times is introduced, and the current transformer is not saturated. In this case, the current transformer secondary side voltage E 2 ′ is calculated. The oversize factor K is expressed as shown in Equation (11).
Figure 0005643592


ここで、
K :オーバーサイズファクター
ω :角周波数(rad/s)
T :無飽和期待時間(ms)
である。

here,
K: Oversize factor ω: Angular frequency (rad / s)
T: Expected non-saturation time (ms)
It is.

無飽和時間Tを波高値検出形(ピーク値検出形)の演算処理が可能な無飽和時間T=15msを条件とする場合、式(11)からオーバーサイズファクターK≒5.71となる。直流電流が100%重畳しても飽和しない飽和限界電流Imdaは、変流器飽和電流Imaと式(11)で示されたオーバーサイズファクターKから式(12)で与えられる。

Figure 0005643592
When the saturation time T is set to the saturation time T = 15 ms that allows the peak value detection type (peak value detection type) calculation processing, the oversize factor K≈5.71 from Expression (11). The saturation limit current I mda that does not saturate even if the DC current is 100% superimposed is given by the equation (12) from the current transformer saturation current I ma and the oversize factor K expressed by the equation (11).
Figure 0005643592


式(12)から直流電流が100%重畳しても飽和しない飽和限界電流Imda≒31.5Armsとなる。

From equation (12), the saturation limit current I mda ≈31.5 A rms that does not saturate even when the direct current is superimposed 100%.

ここで、前述で求められた直流電流が100%重畳しても飽和しない飽和限界電流Imdaを系統事故電流I1adとして考えると、式(10)は式(13)のように変換できる。またこの時の変流器二次側電圧E2’は、変流器一次側に飽和限界電流Imdaが流れた場合の変流器二次側電流I2ad’、変流器二次巻線抵抗17、変流器二次負荷インピーダンス21から式(14)のように示される。

Figure 0005643592

Figure 0005643592
Here, when the saturation limit current I mda that does not saturate even if the DC current obtained as described above is superimposed 100% is considered as the system fault current I 1ad , the equation (10) can be converted into the equation (13). Further, the current transformer secondary side voltage E 2 ′ at this time is the current transformer secondary current I 2ad ′ when the saturation limit current I mda flows in the current transformer primary side, the current transformer secondary winding. From the resistor 17 and the current transformer secondary load impedance 21, the following equation (14) is obtained.
Figure 0005643592

Figure 0005643592


式(13)から変流器一次側に飽和限界電流Imdaが流れた場合の変流器二次側電流I2ad’≒29.7mA0Pとなり、変流器一次側に飽和限界電流Imdaが流れた場合の変流器二次側電流I2ad’と式(14)から変流器飽和時の変流器二次側電圧E2’≒6.5V0Pとなり、これが変流器二次側に発生可能な電圧値を示す。

From equation (13), when the saturation limit current I mda flows on the primary side of the current transformer, the current transformer secondary side current I 2ad ′ ≈29.7 mA 0P , and the saturation limit current I mda is on the primary side of the current transformer. From the current transformer secondary side current I 2ad ′ in the case of current flow and the equation (14), the current transformer secondary side voltage E 2 ′ at the time of saturation of the current transformer becomes 6.5V 0P , which is the current transformer secondary side. Shows the voltage values that can be generated.

ここで、変流器一次側に系統事故電流I1adが流れた場合の変流器二次側電流I2adと負性抵抗回路8の合成インピーダンス26を用いると式(14)は式(15)のように変換できる。

Figure 0005643592
Here, using the current transformer secondary current I 2ad and the combined impedance 26 of the negative resistance circuit 8 when the grid fault current I 1ad flows on the primary side of the current transformer, the equation (14) is expressed by the equation (15). Can be converted as follows.
Figure 0005643592


また式(14)と式(15)から負性抵抗回路8を設けた場合の変成器二次側電流I2adは式(16)のように示される。

Figure 0005643592

Further, the transformer secondary side current I 2ad when the negative resistance circuit 8 is provided from the equations (14) and (15) is represented by the following equation (16).
Figure 0005643592


さらに式(16)を式(13)へ代入すると負性抵抗回路8を設けた場合の飽和限界電流Imdaを示すことができ、式(17)のように示される。

Figure 0005643592

Further, when the equation (16) is substituted into the equation (13), the saturation limit current I mda when the negative resistance circuit 8 is provided can be shown as shown in the equation (17).
Figure 0005643592


ここで、r+Z>r+rになるようrの定数を選定するため、負性抵抗回路8を設けた場合は、(r+Z)/(r+r)だけ飽和限界電流Imdaを大きくできる。

Here, in order to select the constant of r 3 so that r 2 + Z L > r 2 + r 3 , when the negative resistance circuit 8 is provided, only (r 2 + Z L ) / (r 2 + r 3 ) is saturated. The limit current I mda can be increased.

算出された変流器二次側電圧E2’と変流器一次側に系統事故電流I1adが流れた場合の変流器二次側電流I2adと条件である変流器二次巻線抵抗rを式(15)に代入すると、負性抵抗回路8の合成インピーダンスr≒−141Ωとなり、更に式(9)へ代入すると、抵抗Z=10Ω、抵抗Z=20kΩ、抵抗Z=280kΩの結果が得られる。この結果、負性抵抗回路8を設けた場合、飽和限界電流Imda≒99Armsであり、負性抵抗回路8を設けない場合に対して飽和限界電流を約3.14倍向上できる。 Current transformer secondary winding is a current transformer secondary current I 2ad and conditions when the calculated current transformer secondary voltage grid fault current I 1ad the E 2 'and current transformers primary flows If the resistance r 2 is substituted into the equation (15), the combined impedance r 3 of the negative resistance circuit 8 ≈−141Ω, and further substituted into the equation (9), the resistance Z 1 = 10Ω, the resistance Z 2 = 20 kΩ, the resistance Z A result of 3 = 280 kΩ is obtained. As a result, when the negative resistance circuit 8 is provided, the saturation limit current I mda ≈99 A rms , and the saturation limit current can be improved by about 3.14 times compared to the case where the negative resistance circuit 8 is not provided.

負性抵抗回路8に使用するオペアンプ25は、抵抗22、抵抗23、抵抗24のパラメータから負性抵抗回路8から出力される電圧V≒14V0Pと変流器一次側に系統事故電流I1adが流れた場合の変流器二次側電流I2ad≒94.3mA0Pから、オペアンプ25の電源電圧は±15V以上、オペアンプ25の出力電流が94.3mA以上であるOPA551(TEXAS INSTRUMENTS)のようなオペアンプを採用する。 The operational amplifier 25 used for the negative resistance circuit 8 has a voltage V o ≈14V 0P output from the negative resistance circuit 8 based on the parameters of the resistors 22, 23, and 24, and a grid fault current I 1ad on the primary side of the current transformer. From the current transformer secondary current I 2ad ≈ 94.3 mA 0P when the current flows, the power supply voltage of the operational amplifier 25 is ± 15 V or more, and the output current of the operational amplifier 25 is 94.3 mA or more, as in OPA551 (TEXAS INSTRUMENTS) Adopt an op amp.

次に、出力電流に制限があるオペアンプを採用する場合について、図4を用いて説明する。図4は負性抵抗回路8の出力電流不足をパワーブースタ回路29で補う図である。図6において、オペアンプ25から出力される電流を、npn型トランジスタ27あるいはpnp型トランジスタ28のベース端子へ流し込み、電流増幅率hFEによって増幅されたnpn型トランジスタ27あるいはpnp型トランジスタ28のコレクタ電流とベース電流からエミッタ電流である電流I2’を流すことができる。 Next, the case where an operational amplifier with a limited output current is employed will be described with reference to FIG. FIG. 4 is a diagram for compensating for the shortage of output current of the negative resistance circuit 8 by the power booster circuit 29. 6, the current output from the operational amplifier 25, poured into the base terminal of the npn-type transistor 27 or the pnp transistor 28, the collector current of the current amplification factor h npn type amplified by the FE transistor 27 or the pnp transistor 28 A current I 2 ′ that is an emitter current can flow from the base current.

以上のようにして、負性抵抗回路8を設けた場合は負性抵抗回路8を設けない場合に対して、(r+Z)/(r+r)だけ飽和電流を大きくでき、変流器の外形、材料を変えずに変流器飽和特性を向上させる効果が得られる。また変流器飽和特性を向上させたことにより、飽和判定等の特殊な演算処理を行う必要がなくなり、演算負担の削減の効果が得られる。 As described above, when the negative resistance circuit 8 is provided, the saturation current can be increased by (r 2 + Z L ) / (r 2 + r 3 ) as compared with the case where the negative resistance circuit 8 is not provided. The effect of improving the current transformer saturation characteristics can be obtained without changing the shape and material of the current transformer. Further, by improving the current transformer saturation characteristics, it is not necessary to perform special calculation processing such as saturation determination, and the effect of reducing the calculation burden can be obtained.

(第2の実施形態)
第2の実施形態の保護継電器について図5を用いて説明する。本実施形態の構成が第1の実施形態と異なる点は、負性抵抗回路8にNTCサーミスタ30を追加した点である。
(Second Embodiment)
The protection relay according to the second embodiment will be described with reference to FIG. The configuration of this embodiment is different from that of the first embodiment in that an NTC thermistor 30 is added to the negative resistance circuit 8.

NTCサーミスタ30は、抵抗23と直列に接続されており、温度上昇に伴って抵抗が減少するように、マイナスの温度係数を持っている。   The NTC thermistor 30 is connected in series with the resistor 23 and has a negative temperature coefficient so that the resistance decreases as the temperature rises.

一般的な変流器の二次巻線は、抵抗の小さい銅を使用する。銅の温度係数α=0.43[%/℃]であり、温度変動によって期待する変流器二次巻線抵抗rが変化するため、期待する飽和限界電流Imdaにならない。そこで、マイナスの温度係数をもつNTCサーミスタ30を負性抵抗回路8の抵抗23と直列で接続する。このときの負性抵抗回路8の合成インピーダンスrは式(18)のように示される。

Figure 0005643592
The secondary winding of a typical current transformer uses copper with low resistance. Since the temperature coefficient α of copper is 0.43 [% / ° C.] and the expected current transformer secondary winding resistance r 2 changes due to temperature fluctuation, the expected saturation limit current I mda is not achieved . Therefore, an NTC thermistor 30 having a negative temperature coefficient is connected in series with the resistor 23 of the negative resistance circuit 8. Combined impedance r 3 of the negative resistance circuit 8 at this time is represented by equation (18).
Figure 0005643592


ここで、
:抵抗22の抵抗値(Ω)
:抵抗23の抵抗値(Ω)
:抵抗24の抵抗値(Ω)
:NTCサーミスタ30の抵抗値(Ω)
:負性抵抗回路8の合成インピーダンス26の抵抗値(Ω)
である。

here,
Z 1 : resistance value of the resistor 22 (Ω)
Z 2 : resistance value of the resistor 23 (Ω)
Z 3 : resistance value of the resistor 24 (Ω)
Z 4 : Resistance value of the NTC thermistor 30 (Ω)
r 3 : resistance value (Ω) of the combined impedance 26 of the negative resistance circuit 8
It is.

本実施形態によれば、第1の実施形態の効果に加えてNTCサーミスタ30はマイナスの温度係数を持つため、変流器二次巻線の温度係数による変流器二次巻線抵抗rの変化の方向と同じ方向に負性抵抗回路8の合成インピーダンスrの絶対値を変化させることが可能になり、温度変動があった場合でも期待する飽和限界電流Imdaとすることができる。 According to this embodiment, since the NTC thermistor 30 has a negative temperature coefficient in addition to the effects of the first embodiment, the current transformer secondary winding resistance r 2 due to the temperature coefficient of the current transformer secondary winding. it is possible to vary the absolute value of the combined impedance r 3 of the negative resistance circuit 8 in the same direction as the direction of the change can be a saturation limit current I mda expect even if there are temperature fluctuations.

本発明に係る実施形態によれば、直流分を含む系統事故電流が流れた場合にも、精度よく動作判定できる保護継電器を提供できる。   According to the embodiment of the present invention, it is possible to provide a protective relay that can accurately determine operation even when a system fault current including a direct current component flows.

以上、本発明のいくつかの実施形態について説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことが出来る。これら実施形態やその変形は、発明の範囲や要旨に含まれると共に、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   As mentioned above, although some embodiment of this invention was described, these embodiment was shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 :入力変流器
2 :アナログ変換回路
3 :A/D変換回路
4 :演算処理回路
5 :リレー出力回路
6 :出力接点
8 :負性抵抗回路
9 :入力端子
10 :入力端子
11 :変流器一次巻線
12 :変流器二次巻線
14 :出力端子
15 :出力端子
16 :変流器一次巻線抵抗
17 :変流器二次巻線抵抗
18 :変流器一次巻回数
19 :変流器二次巻回数
20 :変流器二次励磁インピーダンス
21 :変流器二次負荷インピーダンス
22 :抵抗
23 :抵抗
24 :抵抗
25 :オペアンプ
26 :負性抵抗8の合成インピーダンス
27 :npn型トランジスタ
28 :pnp型トランジスタ
29 :パワーブースタ回路
30 :NTCサーミスタ
1: Input current transformer 2: Analog conversion circuit 3: A / D conversion circuit 4: Arithmetic processing circuit 5: Relay output circuit 6: Output contact 8: Negative resistance circuit 9: Input terminal 10: Input terminal 11: Current transformation Current transformer primary winding 12: Current transformer secondary winding 14: Output terminal 15: Output terminal 16: Current transformer primary winding resistance 17: Current transformer secondary winding resistance 18: Current transformer primary winding number 19: Current transformer secondary winding number 20: Current transformer secondary excitation impedance 21: Current transformer secondary load impedance 22: Resistor 23: Resistor 24: Resistor 25: Operational amplifier 26: Composite impedance 27 of negative resistor 8: npn type Transistor 28: pnp type transistor 29: Power booster circuit 30: NTC thermistor

Claims (5)

入力電流の大きさを変換し、アナログ信号として出力する入力変流器と、
前記入力変流器から出力された前記アナログ信号を、所定のアナログ信号を示す所定アナログ信号に変換するアナログ変換回路と、
前記アナログ変換回路により変換された所定アナログ信号をデジタル信号に変換するA/D変換回路と、
前記A/D変換回路により変換されたデジタル信号に基づいて演算処理を行う演算処理回路と、
前記演算処理回路の演算結果に応じて接点出力を動作させるリレー出力回路と、
を備える保護継電器において、
前記アナログ変換回路は、前記入力変流器から出力された前記アナログ信号を、前記負性抵抗回路およびパワーブースタ回路を介して受信し、
前記パワーブースタ回路は、前記負性抵抗回路から出力される前記アナログ信号がプラスの場合に当該プラスの前記アナログ信号の強度を増大させて前記アナログ変換回路に出力する第1のトランジスタと、前記負性抵抗回路から出力される前記アナログ信号がマイナスの場合に当該マイナスの前記アナログ信号の強度を増大させて前記アナログ変換回路に出力する第2のトランジスタとを備える保護継電器。
An input current transformer that converts the magnitude of the input current and outputs it as an analog signal;
An analog conversion circuit that converts the analog signal output from the input current transformer into a predetermined analog signal indicating a predetermined analog signal;
An A / D conversion circuit for converting a predetermined analog signal converted by the analog conversion circuit into a digital signal;
An arithmetic processing circuit that performs arithmetic processing based on the digital signal converted by the A / D conversion circuit;
A relay output circuit that operates a contact output in accordance with a calculation result of the arithmetic processing circuit;
In a protective relay comprising:
The analog conversion circuit receives the analog signal output from the input current transformer through the negative resistance circuit and a power booster circuit,
The power booster circuit includes: a first transistor that increases the strength of the positive analog signal when the analog signal output from the negative resistance circuit is positive; And a second transistor that increases the strength of the negative analog signal and outputs the analog signal to the analog conversion circuit when the analog signal output from the resistive circuit is negative .
前記負性抵抗回路は、オペアンプおよび複数の抵抗器を備える請求項1記載の保護継電器。   The protective relay according to claim 1, wherein the negative resistance circuit includes an operational amplifier and a plurality of resistors. 前記負性抵抗回路は、マイナスの温度係数を持つサーミスタを備える請求項1または2記載の保護継電器。 The negative resistance circuit, protective relay of claim 1 or 2, wherein comprising a thermistor having a temperature coefficient of the negative. 前記サーミスタは、前記負性抵抗回路を構成する抵抗器と直列に接続する請求項記載の保護継電器。 The protective thermistor according to claim 3 , wherein the thermistor is connected in series with a resistor constituting the negative resistance circuit. 前記サーミスタは、温度変化に伴う前記入力変流器巻線の抵抗値の変化を補償する請求項または記載の保護継電器。 The protective thermistor according to claim 3 or 4 , wherein the thermistor compensates for a change in a resistance value of the input current transformer winding accompanying a temperature change.
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