JP5643154B2 - Power conditioner - Google Patents

Description

  The present invention relates to a power conditioner, and more particularly to an improvement of a power conditioner that links a distributed power source to a power system.

  In general, a distributed power source such as a solar power generation device, a wind power generation device, or a storage battery is connected to a power system supplied with power from a system power source of an electric power company via a power adjustment device. The power conditioning apparatus includes an inverter circuit that converts DC power input from a distributed power source into AC power synchronized with the power system, and a protection circuit that shuts off the inverter circuit from the power system (for example, a patent). Reference 1).

The inverter circuit synchronizes the output current Io with the system voltage Vo to link the distributed power supply with the power system. Specifically, a reference signal I _REF synchronized with the system voltage Vo is generated using a phase synchronization circuit, and an inverter circuit is driven based on the reference signal I _REF , thereby changing the phase and frequency of the output current Io. The phase and frequency of the system voltage Vo are matched.

  Further, the protection circuit protects the distributed power supply by shutting off the distributed power supply from the system power supply when an abnormality in the power system such as an instantaneous voltage drop or an instantaneous power failure is detected. That is, the disturbance of the system power supply is detected, the current output is stopped, and the distributed power supply is disconnected from the system power supply.

  FIG. 12 is a timing chart showing the operation of the conventional power adjustment apparatus during an instantaneous power failure, and shows a case where an instantaneous power failure of 0.3 seconds has occurred. In the figure, (a) and (b) are the instantaneous value and effective value of the system voltage Vo, (c) and (d) are the instantaneous value and effective value of the output current Io, and (e) is the gate block signal GB. The gate block signal GB is a control signal in the power adjustment device used for stopping the output current Io.

When the system voltage Vo decreases and the power system enters a power failure state, the gate block signal GB is generated and the current output is stopped. Thereafter, when the power system returns to the normal state, the current output is resumed. At this time, it is necessary to restart the current output after the synchronization of the reference signal _IREF with the system voltage Vo is completed so as not to adversely affect the power system. For this reason, if a large phase error φ occurs in the output current I _REF at the time of power recovery, it takes a long time to complete the synchronization, and in the conventional power adjustment device, an instantaneous power failure of 0.3 seconds occurred. Even in such a case, there may be a time lag of about 10 seconds before the current output is resumed after power recovery.

FIG. 13 is a timing chart showing the operation of the conventional power adjustment device at the momentary low voltage, and shows a case where a low voltage state of 0.3 seconds has occurred. When the system voltage Vo decreases and the power system enters a low voltage state, the gate block signal GB is generated in the same manner as in the instantaneous power failure in FIG. 12, and the current output is stopped. Thereafter, when power recovery to the normal state is detected, the current output is resumed after the synchronization of the reference signal _{IREF with} the system voltage Vo is completed. For this reason, even when an instantaneous low voltage of 0.3 seconds occurs, there may be a time lag of about 10 seconds before the current output is resumed after power recovery.

  In the future, the spread of solar power generation devices and the like will increase the proportion of distributed power supply devices in the total power output. Under such circumstances, if a large number of distributed power sources are disconnected from the power system at the same time due to the disturbance of the power system, the balance between supply and demand in the power system may be lost, and a wide range of power outages may occur. In order to solve such a problem, it is desirable that the power adjustment device continue the operation without disconnecting from the power system even when the system voltage Vo decreases. Further, even when the power system is disconnected, it is desirable to quickly return the output of the power adjustment device if the power system recovers.

However, if current output is to be continued when the power system is in a low voltage state, how to control the output current Io becomes a problem. Moreover, shortening the period until synchronization is complete reference signal I _REF from the power recovery of the power system, has a problem that it is not easy to quickly return the output current Io.

In general, the phase synchronization circuit for driving the power adjustment device detects a phase error between the reference signal I _REF and the system voltage Vo, and controls the frequency of the reference signal I _REF so as to minimize the phase error. (For example, Patent Document 2). The response speed of such a phase locked loop is determined by a proportional gain and an integral gain used for frequency PI control.

For this reason, it is conceivable to improve the response speed by adjusting these gains, but in this case, there is a problem that it is difficult to ensure the stability of the operation in the normal state. In addition, compared with the normal state in which the synchronization control is continued, the reference signal I _REF at the time of power recovery may have a large phase error φ, and even if the PI control gain is adjusted, the synchronization adjustment time There was a problem that it was not easy to shorten the length.

JP-A-11-122818 JP 2008-177991 A

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power adjustment device that can quickly suppress a phase error when a large phase error occurs in a reference signal. .

  It is another object of the present invention to provide a power adjustment device that can quickly complete the synchronization of the output of the inverter circuit with the system voltage when the power system recovers from the power failure state to the normal state.

  It is another object of the present invention to provide a power adjustment device capable of quickly returning the output of the inverter circuit when the power system is restored from a low voltage state or a power failure state to a normal state.

A power conditioner according to a first aspect of the present invention is a power conditioner for linking a distributed power source to a power system, based on a reference signal generation unit that generates a reference signal composed of a sine wave, and the reference signal. An inverter circuit that converts DC power supplied from the distributed power source into AC power and outputs the AC power, voltage detection means that detects a system voltage of the power system, and a phase of the reference signal with respect to the system voltage Phase error detection means for determining an error; phase offset control means for controlling the phase offset of the reference signal based on the phase error; and frequency control means for controlling the frequency of the reference signal based on the phase error. A power failure determination means for comparing the system voltage with a power failure determination threshold and determining a power failure state of the power system, and stopping the output of the inverter circuit at the time of a power failure. Output stop means, wherein the phase offset control means controls the phase offset of the reference signal during a first synchronization adjustment period after power recovery from a power failure, and the frequency control means controls the first synchronization adjustment period. Is configured to control the frequency of the reference signal in the second synchronization adjustment period after the end of the step .

  By controlling the phase offset of the reference signal based on the phase error of the reference signal with respect to the system voltage, the phase error can be quickly and effectively suppressed. In particular, the frequency error cannot be suppressed as compared with the case where the frequency of the reference signal is controlled, but the phase error can be suppressed more quickly.

  Therefore, if the output of the inverter circuit is controlled based on such a reference signal, even if a large phase error occurs due to some cause, the phase error can be quickly suppressed. In general, the frequency of the system voltage does not vary greatly, whereas the phase of the system voltage may vary greatly when the system is disturbed. For this reason, by adopting such a configuration, it is possible to quickly suppress the phase error of the output of the inverter circuit at the time of recovery from a system disturbance such as a power failure.

In addition, in the first synchronization adjustment period after power recovery, the phase error of the reference signal can be controlled, so that the phase error during power recovery can be quickly and effectively suppressed. On the other hand, in the second synchronization adjustment period after the end of the first synchronization adjustment period, both the frequency error and the phase error can be suppressed by setting the frequency of the reference signal to be controlled. For this reason, the reference signal can be synchronized with the system voltage with higher accuracy than in the first synchronization adjustment period in which the phase offset is controlled. Therefore, the synchronization of the reference signal after power recovery can be completed quickly.

A power adjustment apparatus according to a second aspect of the present invention includes, in addition to the above configuration, a comparison unit that compares the phase error with an adjustment determination threshold value, and the phase offset control unit is configured based on a comparison result of the comparison unit. It is configured to control the phase offset of the reference signal.

  With such a configuration, it is possible to select an appropriate synchronization control method according to the magnitude of the phase error immediately after power recovery from a power failure. That is, when the phase error of the reference signal at the time of power recovery is small, frequency control is performed instead of phase offset control. For this reason, it is possible to prevent the phase error from increasing due to the influence of the frequency error by controlling the phase offset even though the phase error is small.

In addition to the above-described configuration, the power adjustment device according to the third aspect of the present invention is configured to fix the frequency of the reference signal during a power failure and the first synchronization adjustment period so as to match the frequency of the reference signal before the power failure. The

  By fixing the frequency of the reference signal during a power failure and during the first synchronization adjustment period, it is affected by noise during the power failure and prevents the frequency error of the reference signal from increasing during the power failure and during the first synchronization adjustment period. can do. For this reason, the frequency of the reference signal and the system voltage in the first synchronization adjustment period can be substantially matched, and the phase error in the first synchronization adjustment period can be suppressed with high accuracy.

In the power adjustment device according to a fourth aspect of the present invention, in addition to the above configuration, the phase error detection means separates the system voltage into a first orthogonal component and a second orthogonal component that are orthogonal to each other using the reference signal. Quadrature component calculating means, first orthogonal component integrating means for obtaining an integrated value of the first orthogonal component for the integration period consisting of one or more periods of the reference signal, and integration of the second orthogonal component for the integration period Second orthogonal component integrating means for obtaining a value, and phase error calculating means for obtaining the phase error based on the integrated values of the first orthogonal component and the second orthogonal component.

  With such a configuration, if the system voltage and the frequency of the reference signal match, the phase error of the reference signal with respect to the system voltage can be accurately obtained. Usually, since the frequency of the system power supply does not fluctuate greatly, the phase error can be accurately obtained by adopting such a configuration.

In the power adjustment device according to the fifth aspect of the present invention, in addition to the above configuration, the first synchronization adjustment period is composed of one cycle of the reference signal. With such a configuration, by controlling the phase offset based on the phase error obtained in one cycle of the reference signal immediately after power recovery, and controlling the frequency based on the phase error obtained in each subsequent cycle, Regardless of the magnitude of the phase error, the reference signal can be synchronized quickly and accurately.

In addition to the above-described configuration, the power adjustment device according to the sixth aspect of the present invention compares the system voltage with a low voltage determination threshold value that is greater than the power failure determination threshold value, and determines a low voltage state for determining a normal state and a low voltage state of the power system. A voltage state determination means; an input voltage detection means for detecting an input voltage supplied from the distributed power source and input to the inverter circuit; and an output current for controlling an output current of the inverter circuit based on the input voltage. Control means, and if the power system is in a low voltage state, the output current control means obtains a target current based on the input voltage in a normal state before transition to the low voltage state, and the inverter circuit Is configured to perform constant current control.

  With such a configuration, when the power system is in a low voltage state, the target current can be obtained based on the input voltage in the immediately preceding normal state, and constant current control of the inverter circuit can be performed. For this reason, when the power system is in a low voltage state, the output of the inverter circuit can be quickly returned after power is restored from the low voltage state to the normal state, compared to when the output of the inverter circuit is stopped.

According to a seventh aspect of the present invention, in addition to the above-described configuration, the output control means uses the target current in the low voltage state during the stability check period after power recovery from the low voltage state, and the inverter The circuit is configured to perform constant current control.

  With such a configuration, the same control is performed on the inverter circuit before and after power recovery from the low voltage state. For this reason, the output of the inverter circuit can be quickly returned after the return from the low voltage state to the normal state.

In addition to the above configuration, the power adjustment device according to the eighth aspect of the present invention is configured such that the target current is smaller than the output current in the normal state before the transition to the low voltage state.

  With such a configuration, the target current during the low voltage state is made smaller than the output current in the normal state before the transition to the low voltage state, thereby reducing the power system compared to the output change of the distributed power source. If the period of voltage state is sufficiently short, constant current control can be continued even during the period of low voltage state.

  The power adjustment device according to the present invention controls the phase offset of the reference signal based on the phase error of the reference signal with respect to the system voltage. For this reason, even when a large phase error occurs in the reference signal, the phase error can be quickly suppressed.

  In addition, the power adjustment device according to the present invention controls the phase offset of the reference signal during the first synchronization adjustment period after power recovery from a power failure, and performs the reference during the second synchronization adjustment period after the end of the first synchronization adjustment period. Controls the frequency of the signal. For this reason, the synchronization with respect to the system voltage of the output of an inverter circuit can be completed rapidly after the power recovery from a power failure.

  The power adjustment device according to the present invention fixes the frequency of the reference signal during the power failure and during the first synchronization adjustment period, and matches the frequency of the reference signal before the power failure. For this reason, after the power recovery from the power failure, the synchronization of the reference signal can be completed quickly, and the output of the inverter circuit can be quickly returned.

  The power adjustment device according to the present invention controls the output current of the inverter circuit based on the input voltage to the inverter circuit in the normal state, while in the low voltage state, the normal state before the transition to the low voltage state. A target current is obtained based on the input voltage to the inverter circuit, and constant current control of the inverter circuit is performed. With such a configuration, the output of the inverter circuit can be quickly returned after power is restored from the low voltage state.

It is the block diagram which showed the example of 1 structure of the grid connection system S containing the power adjustment device 101 by embodiment of this invention. It is the timing chart which showed an example of operation | movement of the power adjustment apparatus 101 at the time of an instantaneous voltage fall. It is the timing chart which showed an example of operation | movement of the power adjustment apparatus 101 at the time of an instantaneous power failure. It is the figure which showed one structural example of the power adjustment apparatus 101 of FIG. It is the figure which showed one structural example of the voltage abnormality detection part 3 of FIG. FIG. 5 is a diagram illustrating a configuration example of a chopper circuit control unit 13 in FIG. 4. FIG. 5 is a diagram illustrating a configuration example of an inverter circuit control unit 24 in FIG. 4. FIG. 8 is a block diagram illustrating a configuration example of a synchronization control unit 43 in FIG. 7. 10 is a timing chart showing an example of the operation of the synchronization control unit 43 in FIG. 8. 5 is a flowchart showing an example of the operation of the power adjustment apparatus 101 of FIG. 5 is a flowchart showing an example of the operation of the power adjustment apparatus 101 of FIG. It is the timing chart which showed the operation | movement at the time of the momentary power failure of the conventional power conditioner. It is the timing chart which showed the operation | movement at the time of the instantaneous low voltage of the conventional power adjustment device.

<System configuration>
FIG. 1 is a block diagram showing a configuration example of a grid interconnection system S including a power adjustment device 101 according to an embodiment of the present invention. The grid interconnection system S includes a solar panel 100, a power adjustment device 101, a power grid 102, a distribution board 103, a grid power supply 104, and a load 105.

  The solar panel 100 is a solar power generation device that converts sunlight energy into electric power, generates direct-current power corresponding to the amount of solar radiation, and supplies it to the electric power system 102 via the power adjustment device 101. That is, the solar panel 100 is used as a distributed power source that is connected to the power system 102.

  The power adjustment device 101 is a device that converts DC power input from the solar panel 100 into single-phase AC power and supplies it to the power system 102, and is also called a power conditioner or PCS (Power Conditioner System). The power adjustment device 101 controls the input voltage Vi and the input current Ii from the solar panel 100, and performs MPPT (Maximum Power Point Tracking) control that maximizes the input power from the solar panel 100.

Further, the power adjustment apparatus 101 generates an output current Io having a frequency and phase synchronized with the system voltage Vo that is a voltage of the power system 102 and supplies the output current Io to the power system 102. Specifically, a reference signal I _REF synchronized with the system voltage Vo is generated in the power adjustment device 101, and an output current Io is generated based on the reference signal I _REF . For this reason, the output power Po can be supplied to the power system 102 without affecting the system voltage Vo. Further, it is possible to cause the output current Io to follow the frequency fluctuation of the system voltage Vo at a high speed. Note that the effective value of the output current Io is controlled to be a value corresponding to the input power Pi from the solar panel 100.

  The power system 102 is a system for supplying grid power transmitted from the grid power supply 104 of the power company to the load 105 of the consumer. Here, the distribution board 103 installed in the consumer, the power distribution A wiring network including a lead-in line that supplies system power to the panel 103 is called a power system 102. Distribution board 103 distributes system power supplied from system power supply 104 to load 105, and distributes power supplied from solar panel 100 to system power supply 104 or load 105 via power adjustment device 101. ing. The load 105 is a power consuming device that consumes power supplied from the solar panel 100 or the system power supply 104, and includes, for example, one or more electric devices installed in a house.

<Operation when instantaneous voltage drops>
FIG. 2 is a timing chart showing an example of the operation of the power adjustment apparatus 101 when the instantaneous voltage drops. The instantaneous voltage drop is a low voltage state for a short period in which the system voltage Vo is lower than the rated voltage but does not lead to a power failure. Here, an example is shown in which a low voltage state where the system voltage Vo is 20% of the rated voltage causes an instantaneous voltage drop that lasts for 1 second.

In the figure, (a) and (b) are instantaneous values and effective values of the system voltage Vo, (c) is a reference signal I _REF in the power adjustment device 101, and (d) and (e) are power adjustment devices. The instantaneous value and effective value of the output current Io of 101, (f), is the effective value of the output power Po of the power adjustment apparatus 101.

  When detecting that the system voltage Vo is lowered and the power system 102 is in a low voltage state, the power adjustment apparatus 101 switches from MPPT control to constant current control. In the normal state before the voltage drop, MPPT control is performed to maximize the input power Pi from the solar panel 100, and the output current Io of the power adjustment device 101 is controlled to be a value corresponding to the input power Pi. Has been. On the other hand, in the low voltage state, constant current control is performed with 90% of the output current Io immediately before the voltage drop as a target value. Since the input from the solar panel 100 does not fluctuate greatly for a short time, constant current control with a 10% margin is performed in this example.

Even in the low voltage state, the synchronization control of the output current Io with respect to the system voltage Vo is performed in the same manner as in the normal state. That is, the reference signal I _REF synchronized with the system voltage Vo is generated, and the frequency and phase of the output current Io are controlled based on the reference signal I _REF .

Thereafter, when the system voltage Vo rises and the power system 102 recovers to the normal state, the output power Po of the power adjustment device 101 recovers to 90% of the output power Po immediately before the voltage drop. The constant current control is continued until the stability confirmation period T _STB ends. The stability confirmation period T _STB is a period for confirming that the system voltage Vo after the power recovery is stably maintained at the rated voltage. The stability confirmation period T _STB is maintained without the system voltage Vo falling below the rated voltage. _{When the STB} has elapsed, the power adjustment apparatus 101 switches from constant current control to MPPT control. That is, if there is no change in the input power Pi from the solar panel 100, the effective values of the output current Io and the output power Po are recovered to the values just before the voltage drop.

  In this way, even when the power system 102 is in a low voltage state, the power adjustment apparatus 101 does not stop the current output, and sets the target value to 90% of the output current Io in the normal state immediately before the voltage drop. Current control is performed. Even when the power system 102 is in a low voltage state, the synchronous control of the output current Io with respect to the system voltage Vo is continued. For this reason, the output current Io of the power adjustment device 101 can be quickly returned after power recovery, as compared with a conventional power adjustment device that stops current output in a low voltage state. That is, after the power recovery, it is possible to quickly reach a state in which the output current Io is synchronized with the system voltage Vo and the effective value of the output current Io is 90% immediately before the voltage drop.

  In FIG. 2, the example in which the target current of the constant current control is set to 90% of the output current Io before the voltage drop has been described, but the present invention is not limited to such a case. That is, the target current for constant current control is a value determined based on the output current Io before the voltage drop and may be a value smaller than the output current Io. For example, the output current Io before the voltage drop May be 80%.

<Operation at momentary power failure>
FIG. 3 is a timing chart showing an example of the operation of the power adjustment apparatus 101 during an instantaneous power failure. Instantaneous power failure refers to a short-time power failure state in which the power system 102 is disconnected from the system power supply 104. Here, an example is shown in which an instantaneous power failure occurs in which the power failure state in which the system voltage Vo is 0% of the rated voltage continues for 1 second.

(A) and (b) in the figure are instantaneous values and effective values of the system voltage Vo, (c) is a reference signal I _REF , (d) is a gate block signal GB in the power adjustment device 101, (e ) And (f) are the instantaneous value and effective value of the output current Io, and (g) is the effective value of the output power Po. Further, the power failure period T _OUT in the figure is a period in which the power system 102 is in a power failure state, and the first synchronization adjustment period T _ADJ1 and the second synchronization adjustment period T _ADJ2 are the synchronization of the reference signal I _REF at the time of power recovery. This is a period for eliminating the deviation.

The gate block signal GB is a control signal in the power adjustment apparatus 101 and is used to stop the current output of the power adjustment apparatus 101. The gate block signal GB is output when it is detected that the power system 102 is in a power failure state. Further, when power recovery to the normal state is detected and the synchronization adjustment of the reference signal I _REF is completed, the output is ended. That is, the current output of the power adjustment apparatus 101 is stopped not only during the power failure period T _OUT but also during the subsequent synchronization adjustment periods T _ADJ1 and T _ADJ2 .

If the power system 102 is in a power failure state, the reference signal I _REF is in a self-running state with a fixed frequency, and the synchronization control of the reference signal I _REF with respect to the system voltage Vo is not performed. After that, when the system voltage Vo rises and the power system 102 returns to the normal state, synchronous adjustment for eliminating the phase error of the reference signal I _REF at the time of power recovery is started, and the reference signal I _REF If the phase error is less than or equal to a predetermined synchronization determination threshold value, the synchronization adjustment is terminated. This synchronization adjustment, firstly the first synchronization control is performed for the phase offset of the reference signal I _REF and the control object, then the second synchronization control to be controlled the frequency of the reference signal I _REF to is performed. Even after the synchronization is completed, since the frequency of the reference signal I _REF needs to follow the frequency fluctuation of the system voltage Vo, the synchronization control with the frequency as the control target is continuously performed.

The phase offset control is a process by adjusting the phase offset of the reference signal I _REF according to the phase error with respect to the system voltage Vo, that is, by changing the position to discontinuously shift the reference signal I _REF in the time axis direction. This is a process for canceling the error, and the synchronization adjustment can be performed quickly. That is, the frequency error cannot be suppressed, but the phase error can be quickly suppressed. Moreover, the phase error can be suppressed in a fixed time regardless of the magnitude of the phase error at the time of power recovery.

On the other hand, in the frequency control, both the frequency error and the phase error can be suppressed by controlling the frequency based on the phase error, and more accurate synchronous control can be performed as compared with the phase offset control. However, there is a drawback that the time until synchronization is completed varies significantly depending on the magnitude of the phase error. Therefore, as in the present embodiment, the synchronization of the reference signal I _REF is quickly completed after the power recovery by sequentially performing the synchronization control with the phase offset as the control target and the synchronization control with the frequency as the control target. be able to.

First synchronizing adjustment period T _ADJ1, in order to solve the out-of-sync reference signal I _REF at the time power is restored, a period for the phase offset control reference signal I _REF, is started when the power recovery detection, the reference signal It consists of a period corresponding to one or more periods of I _REF . Here, an example in which the first synchronization adjustment period T _ADJ1 corresponds to one cycle of the reference signal I _REF is shown.

The second synchronization adjustment period T _ADJ2 is a period for performing frequency control of the reference signal I _REF in order to eliminate the _loss of synchronization of the reference signal I _REF at the time of power recovery, and starts at the end of the first synchronization adjustment period T _ADJ1. When the synchronization of the reference signal I _REF is completed, the process ends. That is, it is a period for suppressing the frequency error and phase error that could not be eliminated in the first synchronization adjustment period T _ADJ1 to be equal to or less than the synchronization determination threshold value. Here, since the second synchronization adjustment period T _ADJ2 is completed in 3.5 cycles, the synchronization adjustment of the reference signal I _REF is completed in 4.5 cycles after power recovery. For example, if the system voltage Vo is 50 Hz, it means that the phase error at the time of power recovery is eliminated and the synchronization of the reference signal I _REF is completed in 0.09 seconds after power recovery.

The synchronization adjustment period includes a first synchronization adjustment period T _ADJ1 and a second synchronization adjustment period T _ADJ2 , and the first synchronization adjustment period T _ADJ1 includes a certain time. In addition, the second synchronization adjustment period T _ADJ2 is a period in which the phase error sufficiently suppressed in the first synchronization adjustment period T _ADJ1 is more accurately suppressed, so that the synchronization adjustment period from the power recovery until the synchronization adjustment is completed. Is substantially constant, and the synchronization adjustment period does not become longer as the phase error during power recovery increases.

The soft start period _TSFT is a period in which the output current Io is gradually increased after the gate block signal GB ends, and the effective value of the output current Io monotonously increases from 0% to 90% of the output current Io immediately before the power failure. Thus, constant current control of the output current Io is performed. Here, the soft start period _TSFT consists of a period corresponding to 5.5 cycles of the reference signal _IREF after the end of the gate block signal GB. For example, if the system voltage Vo is 50 Hz, the soft start period _TSFT Is 0.11 seconds. That is, the output current Io that is synchronized with the system voltage Vo and whose effective value is 90% before the power failure can be output 0.2 seconds after the detection of power recovery. When the soft start period _TSFT ends and the output current Io reaches 90% of the output current Io before the voltage drop, the stability check period _TSTB passes before the voltage drop, as in the case of power recovery from the instantaneous low voltage state. Return to the state.

<Configuration of Power Adjustment Device 101>
FIG. 4 is a diagram illustrating a configuration example of the power adjustment apparatus 101 in FIG. 1. This power adjustment device 101 includes a boost regulator 1 that boosts an input voltage Vi from the solar panel 100 to an intermediate voltage Vm, an inverter unit 2 that converts a DC intermediate voltage Vm to an AC system voltage Vo, and a voltage abnormality detection unit. 3.

<Boost regulator 1>
The boost regulator 1 is a step-up converter for boosting the input voltage Vi to the intermediate voltage Vm, and includes a voltage detector 10 that detects the input voltage Vi, a smoothing capacitor C1, and a current that detects the input current Ii. A detector 11, a chopper circuit 12, and a chopper circuit control unit 13 that controls the chopper circuit 12 are provided. The input voltage Vi from the solar panel 100 is input to the chopper circuit 12 via the current detector 11 after the high frequency component is removed by the capacitor C1, and is boosted to the intermediate voltage Vm.

  The chopper circuit 12 is a booster circuit that boosts the input voltage Vi by a switching operation and generates an intermediate voltage Vm. The choke coil L1 on the input side and the diode D1 on the output side are connected in series, and the connection point is a transistor. It is configured to be connected to the ground potential via a parallel circuit of Tr1 and diode D2. The transistor Tr1 is a switching element that electrically connects the connection point of the choke coil L1 and the diode D1 with the ground potential based on the gate drive signal GD1, and for example, an IGBT (Insulated Gate Bipolar Transistor) is used. The diode D1 is a reverse current blocking diode that prevents reverse current flow, and the diode D2 is a freewheeling diode that discharges an electromotive force generated in the choke coil L1.

  The chopper circuit control unit 13 generates a gate drive signal GD1 for driving the transistor Tr1 and controls the operation of the chopper circuit 12. The gate drive signal GD1 is a PWM (Pulse Width Modulation) signal generated based on the input voltage Vi, the input current Ii, and the gate block signal GB, and is input to the gate terminal of the transistor Tr1. Specifically, a gate drive signal GD1 that can efficiently draw power from the solar panel 100 is generated based on the input voltage Vi and the input current Ii. Further, by stopping the output of the gate drive signal GD1 based on the gate block signal GB indicating the power failure of the power system 102, the operation of the chopper circuit 12 at the time of the power failure is stopped.

<Inverter unit 2>
The inverter unit 2 is an inverse conversion device for converting the DC power supplied from the boost regulator 1 into AC power and obtaining an output current synchronized with the system voltage Vo, and a voltage detector 20 that detects the intermediate voltage Vm; , Smoothing capacitors C2, C3, inverter circuit 21, current detector 22 for detecting output current Io, voltage detector 23 for detecting system voltage Vo, and inverter circuit control unit for controlling inverter circuit 21 24. The intermediate voltage Vm input from the boost regulator 1 is input to the inverter circuit 21 after high frequency components are removed by the capacitor C2, and is converted into AC power. The output of the inverter circuit 21 is output to the power system 102 after the high frequency component is removed by the capacitor C3.

  The inverter circuit 21 is a conversion circuit that converts a DC intermediate voltage Vm into an AC voltage by a switching operation. The input / output terminal is connected via a choke coil L2, and the input terminal is a parallel circuit of a transistor Tr2 and a diode D3. It is configured to be connected to the ground potential via The transistor Tr2 is a switching element that performs switching based on the gate drive signal GD2. For example, an IGBT is used. The diode D3 is a free wheeling diode that discharges an electromotive force generated in the choke coil L2.

  The inverter circuit control unit 24 generates a gate drive signal GD2 for driving the transistor Tr2, and controls the operation of the inverter circuit 21. The gate drive signal GD2 is a PWM signal generated based on the input voltage Vi, the input current Ii, the gate block signal GB, the free-running control signal SR, and the constant current control signal CC, and is input to the gate terminal of the transistor Tr2. . Specifically, the output current Io is synchronized with the system voltage Vo by controlling the frequency or phase offset of the output current Io based on the system voltage Vo. Further, the effective value of the output current Io is controlled based on the intermediate voltage Vm or the constant current control signal CC. Furthermore, based on the gate block signal GB indicating the power failure of the power system 102, the output of the gate drive signal GD2 is stopped to stop the switching operation of the inverter circuit 21 at the time of the power failure, and the solar panel 100 is removed from the power system 102. Disconnect.

The boost regulator 1 and the inverter unit 2 operate in cooperation with each other without using a special control signal by using the intermediate voltage Vm. That is, the inverter unit 2 determines the effective value of the output current Io based on the intermediate voltage Vm, and operates so that the intermediate voltage Vm matches the target intermediate voltage Vm _REF . Further, the boost regulator 1 can control the input voltage Vi by controlling the input / output voltage ratio of the chopper circuit 12 by maintaining the intermediate voltage Vm at the target intermediate voltage Vm _REF .

<Voltage abnormality detection unit 3>
The voltage abnormality detector 3 outputs a gate block signal GB, a free-running control signal SR, and a constant current control signal CC based on the system voltage Vo. The gate block signal GB is a control signal for stopping the switching operation of the chopper circuit 12 and the inverter circuit 21. The self-running control signal SR is a control signal for causing the inverter unit 2 to stop synchronous control of the reference signal _IREF . The constant current control signal CC is a control signal for instructing the inverter unit 2 to perform constant current control.

  FIG. 5 is a diagram illustrating a configuration example of the voltage abnormality detection unit 3 in FIG. 4. The voltage abnormality detection unit 3 includes a first comparison unit 50, a second comparison unit 51, a gate block signal generation unit 52, a free-running control signal generation unit 53, and a constant current control signal generation unit 54.

  The first comparison unit 50 is a comparison unit that compares the system voltage Vo detected by the voltage detector 23 with a power failure determination threshold value Vt1 for determining a power failure state. The power failure determination threshold value Vt1 is determined in advance as a value smaller than the rated voltage of the power system 102. If the system voltage Vo is less than the power failure determination threshold value Vt1, it can be determined that the power failure state is present. In this example, 20% of the rated voltage of the electric power system 102 is set as the power failure determination threshold value Vt1.

  The second comparison unit 51 is a comparison unit that compares the system voltage Vo detected by the voltage detector 23 with a low voltage determination threshold value Vt2 for determining a low voltage state. The low voltage determination threshold value Vt2 is determined in advance as a value smaller than the lower limit value of the rated voltage of the power system 102 and larger than the power failure determination threshold value Vt1. For this reason, if the system voltage Vo is not less than the power failure determination threshold value Vt1 and less than the low voltage determination threshold value Vt2, it can be determined that it is in a low voltage state, and if it is not less than the low voltage determination threshold value Vt2, it is in a normal state. Can be determined. In this example, the lower limit value of the rated voltage of the power system 102 is set to the low voltage determination threshold value Vt2. That is, if the rated voltage is 101V ± 6V, the low voltage determination threshold Vt2 is 95V.

The gate block signal generation unit 52 generates the gate block signal GB based on the comparison result of the first comparison unit 50. Gate block signal GB is a boosting operation of the boost regulator 1, a control signal for stopping the current output of the inverter unit 2, a power outage period _{T OUT,} and output to the subsequent synchronization adjustment period _{T ADJ1, T ADJ2.} That is, based on the comparison result of the first comparison unit 50, when it is determined that the system voltage Vo has decreased and the power system 102 has transitioned from the normal state to the power failure state, the output of the gate block signal GB is started. On the other hand, if it is determined that the synchronization adjustment is completed after the power recovery based on the synchronization completion signal SC, the output of the gate block signal GB is stopped.

The self-running control signal generation unit 53 generates the self-running control signal SR based on the comparison result of the first comparison unit 50. The free-running control signal SR is a control signal for free-running the reference signal _IREF without fixing the frequency and phase offset and performing synchronous control, and is output during the power failure period _TOUT . That is, based on the comparison result of the first comparison unit 50, if it is determined that a power failure has occurred, the output of the self-running control signal SR is started, and if it is determined that the power has been restored, the output of the free-running control signal SR is Stop.

  The constant current control signal generation unit 54 generates a constant current control signal CC based on the comparison results of the first comparison unit 50 and the second comparison unit 51. The constant current control signal CC controls the output current Io based on the value of the output current Io before the voltage drop when the system voltage Vo is lowered and the power system 102 is in a low voltage state or a power failure state. Is a control signal for instructing.

That is, if it is determined that the power system 102 has transitioned from the normal state to the low voltage state based on the comparison result of the second comparison unit 51, the output of the constant current control signal CC is started. Thereafter, the power is restored from the constant current state to the normal state, and when the stability confirmation period T _STB elapses, the output of the constant current control signal CC is stopped. That is, the constant current control signal CC is output during the low voltage period T _LOW and the subsequent stability confirmation period T _STB .

If it is determined that the synchronization adjustment is completed after power recovery from the power failure state based on the comparison result of the first comparison unit 50 and the synchronization completion signal SC, the output of the constant current control signal CC is started. Thereafter, when the soft start period T _SFT and the stability confirmation period T _STB are finished, the output of the constant current control signal CC is stopped. That is, the constant current control signal CC is output in the soft start period T _SFT and the stability confirmation period T _STB after power is restored from the power failure state.

<Chopper circuit controller 13>
FIG. 6 is a diagram illustrating a configuration example of the chopper circuit control unit 13 of FIG. The chopper circuit control unit 13 is a control unit that generates the gate drive signal GD1 and controls the switching operation in the chopper circuit 12, and includes a multiplier 30, an MPPT (Maximum Power Point Tracking) control unit 31, a subtractor 32, and PWM control. It consists of a part 33 and a gate block part 34.

  The multiplier 30 is an arithmetic means that calculates the input power Pi from the solar panel 100 by multiplying the input voltage Vi and the input current Ii. The input power Pi obtained by the multiplier 30 is input to the MPPT control unit 31.

The MPPT control unit 31 performs a known maximum power point tracking process for maximizing the input power Pi by controlling the input voltage Vi. The target input voltage Vi _REF is a target value of the input voltage Vi designated by the MPPT control unit 31, and the MPPT control unit 31 changes the target input voltage Vi _REF to compare the input power Pi before and after the change, and this comparison By repeatedly changing the target input voltage Vi _REF based on the result, the maximum output point of the solar panel 100, that is, the target input voltage Vi _REF that maximizes the input power Pi is searched. Such a control method is known as a “mountain climbing method”. In addition, even if the solar radiation amount, environmental temperature, etc. change and the VP characteristic of a solar panel changes, it can track the change of VP characteristic with the same control method.

The subtractor 32 is calculation means for obtaining an input voltage error Vi _ERR as an error of the input voltage Vi with respect to the target input voltage Vi _REF . The input voltage error Vi _ERR obtained by the subtracter 32 is input to the PWM control unit 33.

The PWM control unit 33 is a pulse width modulation unit that performs pulse width modulation based on the input voltage error Vi _ERR to generate a gate drive signal GD1 including a PWM signal, and converts the input voltage Vi to the target input voltage Vi _REF . The pulse width is adjusted so that it is closer. For example, the gate drive signal GD1 is generated as a comparison result between a carrier signal composed of a triangular wave and a threshold value determined based on the input voltage error Vi _ERR . In order to perform quick and highly accurate control, the cycle of the carrier signal is sufficiently shorter than the cycle of the system voltage Vo and coincides with the sampling cycle of the input voltage Vi and the input current Ii. desirable.

  The gate block unit 34 is means for blocking the gate drive signal GD1 based on the gate block signal GB and stopping the boosting operation by the boost regulator 1. When the gate block signal GB is output from the voltage abnormality detection unit 3, the gate block unit 34 stops the output of the gate drive signal GD1. For this reason, the switching operation of the chopper circuit 12 is stopped, and the boosting operation by the boost regulator 1 can be stopped.

<Inverter circuit control unit 24>
FIG. 7 is a diagram showing a configuration example of the inverter circuit control unit 24 of FIG. The inverter circuit control unit 24 is a control unit that generates the gate drive signal GD2 and controls the switching operation in the inverter circuit 21, and includes an output current control unit 4, a synchronization control unit 43, a multiplier 44, a subtractor 45, and PWM control. Part 46 and a gate block part 47.

The output current control unit 4 is a means for obtaining the target effective value Ie _REF of the output current Io based on the intermediate voltage Vm and the constant current control signal CC. From the subtractor 40, the constant current control unit 41, and the control switching unit 42, Become.

The subtractor 40 is a calculation means for obtaining an intermediate voltage error Vm _ERR as an error of the intermediate voltage Vm with respect to the target intermediate voltage Vm _REF . The target intermediate voltage Vm _REF is a predetermined target value of the intermediate voltage Vm, and the intermediate voltage error Vm _ERR is obtained by subtracting the target intermediate voltage Vm _REF from the intermediate voltage Vm detected by the voltage detector 10. This intermediate voltage error Vm _ERR is input to the multiplier 44 as the target effective value Ie _REF of the output current Io.

The constant current control unit 41 is a control unit that obtains a specified target effective value Ie _CC for constant current control based on a constant current control signal CC when the system voltage Vo decreases. The designated target effective value Ie _CC is the target effective value Ie _REF of the output current Io during the constant current control, and is obtained based on the intermediate voltage Vm before the voltage drop. Here, the constant current control unit 41 stores the intermediate voltage error Vm _ERR output from the subtracter 40 to the voltage drop immediately before, when performing the constant current control after the voltage drop, the intermediate voltage error Vm _ERR immediately before the voltage drop Based on this, the designated target effective value Ie _CC is obtained.

Specifically, when the power system 102 is in a low voltage state, the value of 90% of the target effective value Ie _REF immediately before the voltage drop is set as the designated target effective value Ie _CC in the low voltage period T _LOW and the stability confirmation period T _STB . Is output.

In addition, when the power system 102 is in a power failure state, a value of 0% to 90% of the target effective value Ie _REF immediately before the power failure so as to increase in proportion to the passage of time within the soft start period _TSFT after the power recovery. Is output as the designated target effective value Ie _CC . Further, 90% of the target effective value Ie _REF immediately before the power failure is output as the designated target effective value Ie _CC in the subsequent stability confirmation period T _STB .

The control switching unit 42 switches output control for switching between MPPT control and constant current control by selecting one of the intermediate voltage error Vm _ERR and the specified target effective value Ie _CC based on the constant current control signal CC. Means.

When the constant current control signal CC is not input, the control switching unit 42 selects the intermediate voltage error Vm _ERR output from the subtractor 40 and outputs it to the multiplier 44 as the target effective value Ie _REF of the output current Io. To do. In this case, the gate drive signal GD2 is generated based on the intermediate voltage error Vm _ERR , and the inverter circuit 21 can be driven so that the intermediate voltage Vm approaches the target intermediate voltage Vm _REF .

On the other hand, when the constant current control signal CC is input, the control switching unit 42 selects the designated target effective value Ie _CC output from the constant current control unit 41, and as the target effective value Ie _REF of the output current Io, Output to the multiplier 44. In this case, the inverter circuit 21 is driven so that the effective value of the output current Io matches the designated target effective value Ie _CC .

The synchronization control unit 43 generates a reference signal I _REF whose frequency and phase are synchronized with the system voltage Vo detected by the voltage detector 23. By controlling the inverter circuit 21 using the reference signal I _REF and synchronizing the output current Io to the system voltage Vo, it is possible to prevent the operation of the inverter circuit 21 from affecting the system voltage Vo.

The multiplier 44 is a calculation unit that generates a target output current Io _REF based on the reference signal I _REF and the target effective value Ie _REF . That is, by multiplying the reference signal I _REF with the normalized effective value and the target effective value Ie _REF , the phase and the frequency coincide with the reference signal I _REF, and the effective value becomes the target effective value Ie _REF and A target output current Io _REF is obtained as a matching control signal.

The subtracter 45 is a calculation means for obtaining an output current error Io _ERR as an error of the output current Io with respect to the target output current Io _REF . The output current error Io _ERR is obtained by subtracting the output current Io detected by the current detector 22 from the target output current Io _REF obtained by the multiplier 44.

The PWM control unit 46 is a pulse width modulation unit that performs pulse width modulation based on the output current error Io _ERR to generate a gate drive signal GD2 composed of a PWM signal, and converts the output current Io to the target output current Io _REF . The pulse width is adjusted so that it is closer. For example, the gate drive signal GD2 is generated as a comparison result between a carrier signal composed of a triangular wave and a threshold value determined based on the output current error Io _ERR . In order to perform quick and highly accurate control, the cycle of the carrier signal is sufficiently shorter than the sampling cycle of the system voltage Vo and the output current Io, and is equal to the sampling cycle of the system voltage Vo and the output current Io. It is desirable to do it.

  The gate block unit 47 is an output stop unit that interrupts the gate drive signal GD2 and stops the current output of the inverter unit 2 based on the gate block signal GB. When the gate block signal GB is output from the voltage abnormality detection unit 3, the gate block unit 47 stops the output of the gate drive signal GD2. For this reason, the switching operation of the inverter circuit 21 is stopped, and the current output of the inverter unit 2 can be stopped.

<Synchronization control unit 43>
FIG. 8 is a block diagram showing a configuration example of the synchronization control unit 43 in FIG. The synchronization control unit 43 is a PLL (Phased Lock Loop) that generates a reference signal I _REF whose frequency and phase are synchronized with the system voltage Vo, and includes a phase error detection unit 6, a synchronization completion determination unit 64, and a frequency control unit. 65, a phase offset control unit 66, and a reference signal generation unit 67.

The phase error detection unit 6 is a means for detecting the phase error φ of the reference signal I _REF with respect to the system voltage Vo, and includes an orthogonal component calculation unit 60, a first orthogonal component integration unit 61, a second orthogonal component integration unit 62, and a phase error. The calculation unit 63 is included.

  The quadrature component calculation unit 60 is a means for separating the system voltage Vo detected by the voltage detector 23 into a first quadrature component VoD and a second quadrature component VoQ that are orthogonal to each other, and includes two multipliers 601, 602 and π / 2 phase shifter 603.

The π / 2 phase shifter 603 shifts the phase of the reference signal I _REF = cosωt by π / 2 to generate an orthogonal signal I _{REF ′} = sin ωt = cos (ωt−π / 2) orthogonal to the reference signal I _REF. . The multiplier 601 obtains a first quadrature component VoD in phase with the reference signal I _REF by _obtaining a product of the system voltage Vo and the reference signal I _REF . On the other hand, the multiplier 602 obtains a second quadrature component VoQ in phase with the quadrature signal I _{REF ′} by _obtaining the product of the system voltage Vo and I _{REF ′} . The system voltage Vo can be expressed as Vo = cos (ωt−φ) using the phase error φ. For this reason, the first orthogonal component VoD and the second orthogonal component VoQ can be expressed as Equations (1) and (2) by using a product-sum formula of trigonometric functions.

First orthogonal component integration unit 61, a first quadrature component VoD orthogonal component calculating section 60 is determined by integrating over one period of the reference signal _{I REF,} we obtain the integrated value ShigumaVoD. Similarly, the second orthogonal component integrating unit 62 integrates the second orthogonal component VoQ obtained by the orthogonal component calculating unit 60 over one period to obtain an integrated value ΣVoQ. The integrated values ΣVoD and ΣVoQ are both integrated values over one period of the reference signal I _REF , and are obtained every sampling period of the system voltage Vo after the first period has elapsed. The accumulated values ΣVoQ and ΣVoD obtained in this way are obtained by using the equations (1) and (2), and further utilizing the fact that the accumulated value over one period of the trigonometric function becomes zero. 4).

The phase error calculation unit 63 obtains the phase error φ of the reference signal I _REF with respect to the system voltage Vo by obtaining the arctangent arctan (VoQ / VoD) of the ratio of these integrated values. The arctangent arctan (VoQ / VoD) corresponds to the phase error φ as shown in the following equation (5).

  The synchronization completion determination unit 64 compares the phase error φ with the synchronization determination threshold value φth, and generates a synchronization completion signal SC based on the comparison result. The synchronization determination threshold φth is a predetermined value as an allowable value of the phase error at the time of completion of synchronization. If the phase error φ is equal to or less than the synchronization determination threshold φth, the synchronization completion signal SC is output.

The frequency control unit 65 controls the frequency of the reference signal I _REF based on the phase error φ. For example, by performing PI control using a predetermined proportional gain and integral gain, the frequency adjustment amount Δf of the reference signal I _REF corresponding to the phase error φ is obtained and output to the reference signal generator 67. By such PI control, the phase error φ can be accurately reduced. However, in order to stably suppress the phase error φ, the gain of PI control cannot be increased so much, and the response speed is improved. Has its limits.

The phase offset control unit 66 controls the phase offset of the reference signal I _REF based on the phase error φ. For example, the phase error φ is converted into the number of samplings of the reference signal I _REF and output to the reference signal generation unit 67 as the phase offset adjustment amount Δφ. Such phase offset control can quickly reduce the phase error φ regardless of the magnitude of the phase error φ. In particular, even when a large phase error occurs in the reference signal I _REF , such a phase error can be quickly suppressed. However, the frequency error of the reference signal I _REF cannot be suppressed. In addition, when the reference signal I _REF has a frequency error, the phase error φ cannot be obtained accurately, so that highly accurate synchronous control cannot be performed by the phase offset control.

Thus, the phase offset control unit 66 compares the absolute value of the phase error φ and the adjustment determination threshold Faith2, based on the comparison result, it is desirable to control the phase offset of the reference signal I _REF. The adjustment determination threshold φth2 is a value determined in advance as a lower limit value of the absolute value of the phase error φ to be subjected to phase offset control. If the phase error is in the range of −π to π, for example, π / 2 can be set as the adjustment determination threshold value φth2. If the absolute value of the phase error φ is equal to or greater than the adjustment determination threshold φth2, phase offset control is performed, whereas if it is less than the adjustment determination threshold φth2, phase offset control is not performed. By adopting such a configuration, it is possible to prevent the phase error φ from being enlarged by performing phase offset control when the phase error φ is small.

The reference signal generator 67 generates the reference signal I _REF based on the free-running control signal SR, the frequency adjustment amount Δf, and the phase offset adjustment amount Δφ. The reference signal I _REF is a periodic signal made up of, for example, a sine wave.

The synchronous control of the reference signal I _REF is performed based on the self-running control signal SR. That is, when the self-running control signal SR is input from the voltage abnormality detector 3, the self-running state in which synchronous control is not performed is entered, and the reference signal I _REF is generated while both the frequency and the phase offset are fixed. . On the other hand, when the self-running control signal SR is not input, synchronous control with the frequency or phase offset as the control target is performed. The frequency control is a synchronous control that changes the frequency of the reference signal I _REF based on the frequency adjustment amount Δf from the frequency control unit 65. On the other hand, the phase offset control is synchronous control that changes the phase offset of the reference signal _IREF based on the phase offset adjustment amount Δφ from the phase offset control unit 66. In other words, the reference signal I _REF performs position moving changes on the time axis, a synchronization control for changing the reference signal IREF discontinuously.

In this embodiment, the reference signal I _REF is in a free-running state only during a power failure period T _OUT in which the phase error φ cannot be obtained, and the phase offset control of the reference signal I _REF is performed. This is only the first synchronization adjustment period T _ADJ1 immediately after power is restored from the state. Therefore, except for these periods, the reference signal generator 67 performs frequency control of the reference signal I _REF based on the frequency adjustment amount Δf.

<Operation of Synchronization Control Unit 43>
FIG. 9 is a timing chart showing an example of the operation of the synchronization control unit 43 in FIG. 8, and shows the operation at the time of an instantaneous power failure similar to FIG. When the power system 102 is in a normal state, the reference signal generation unit 67 performs synchronous control with a frequency as a control target so as to reduce the phase error of the reference signal _IREF . Thereafter, when the system voltage Vo decreases and the power system 102 is in a power failure state, the voltage abnormality detection unit 3 outputs the self-running control signal SR. Reference signal generating unit 67, based on the free-running control signal SR, and stops the synchronization control of the reference signal I _REF, to the free-running state.

And if the electric power grid | system 102 returns from a power failure state, the voltage abnormality detection part 3 will complete | finish the output of the self-running control signal SR. If the absolute value of the phase error φ at this time is equal to or greater than the adjustment determination threshold φth2, the reference signal generation unit 67 performs phase offset control in the subsequent first synchronization adjustment period T _ADJ1 . In the figure, since phase error φ = π, phase offset control is performed in the first synchronization adjustment period T _ADJ1 . Here, in the first synchronization adjustment period T _ADJ1 corresponding to one cycle of the reference signal I _REF , the phase error φ immediately after power recovery is obtained, and the position is changed at the end of the first synchronization adjustment period T _ADJ1 . . Such phase offset control can effectively suppress the phase error φ.

When the first synchronization adjustment period T _ADJ1 ends, a second synchronization adjustment period T _ADJ2 for frequency control is started. In the second synchronization adjustment period T _ADJ2 , the frequency adjustment amount Δf is obtained based on the phase error φ, and the frequency of the reference signal I _REF is controlled. By such frequency control, the phase error φ can be more accurately suppressed. As a result, if the phase error φ is less than the synchronization determination threshold φth, the synchronization completion signal SC is generated, and the second synchronization adjustment period T _ADJ2 ends.

<Flowchart of power adjustment apparatus 101>
Steps S101 to S106 in FIG. 10 and steps S201 to S208 in FIG. 11 are flowcharts showing an example of the operation of the power adjustment apparatus 101 in FIG. This flowchart starts when the voltage detector 23 detects a decrease in the system voltage Vo. First, the system voltage Vo is compared with the voltage threshold value Vt1, and it is determined whether or not it is in a power failure state (step S101). As a result, when it is determined that a power failure has occurred, the process proceeds to step S201 for instantaneous power failure. On the other hand, when it is not a power failure state, the system voltage Vo is compared with the voltage threshold value Vt2, and it is discriminate | determined whether it is a low voltage state (step S102). As a result, if neither the power failure state nor the low voltage state is present, the processing of the flowchart is terminated.

  When it is determined in step S102 that the voltage is low, constant current control is started (step S103). That is, after the transition to the low voltage state, the current output is not stopped and the constant current control in which the target current is determined based on the output current Io before the voltage drop is started. For example, the target effective value of the output current Io is controlled to be 90% of the effective value of the output current Io immediately before the voltage drop.

Thereafter, if the system voltage Vo exceeds the voltage threshold value Vt2, it is determined that the power is restored from the low voltage state to the normal state (step S104). Then, if the system voltage Vo is maintained in the normal state during the stability confirmation period T _STB after the power recovery, the constant current control is terminated, the MPPT control is resumed, and the process of the flowchart is terminated (step S105). , S106). Incidentally, in the stability confirmation period T _STB, if transition to the power failure condition of the system voltage Vo becomes the threshold voltage Vt1 or less, the process proceeds to step S201, if transition to a low voltage condition to be voltage threshold Vt2 Hereinafter, stability confirmation period T Restart the _STB .

On the other hand, if it is determined in step S101 that a power failure has occurred, the current output is stopped (step S201). Further, the reference signal I _REF has a fixed frequency and phase offset, and is in a free-running state in which synchronization control is not performed (step S202).

Thereafter, if the system voltage Vo exceeds the voltage threshold value Vt2, it is determined that power has been restored to the normal state (step S203). In the first synchronization adjustment period T _ADJ1 after power recovery, the phase error φ at the time of power recovery is obtained and compared with the adjustment determination threshold value φth2 (step S204). As a result, if the phase error φ is less than the adjustment determination threshold φth2, the process proceeds to step S206. If the phase error φ is equal to or larger than the adjustment determination threshold φth2, the phase of the reference signal I _REF is canceled so as to cancel the phase error φ. Offset control is performed (step S205).

After the phase offset control is performed, the second synchronization adjustment period T _ADJ2 is started, and the synchronization control by the frequency control of the reference signal I _REF is resumed (step S206). Thereafter, if the phase error φ of the reference signal I _REF becomes equal to or smaller than the synchronization determination threshold φth, it is determined that the synchronization adjustment is completed, and the second synchronization adjustment period T _ADJ2 is ended (step S207).

After the end of the second synchronization adjustment period T _ADJ2 , a soft start period T _SFT is started, and current output by constant current control is resumed. Output current Io in the soft-start period T _SFT is determined on the basis of the current Io of the previous voltage drop. For example, the target effective value of the output current Io is determined to increase from 0% to 90% of the effective value of the output current Io immediately before the voltage drop. After the end of the soft-start period _{T SFT,} the process proceeds to step S105, through a stable confirmation period _{T STB,} MPPT control is resumed.

In the present embodiment, an example in which the phase offset of the reference signal _IREF is controlled after power is restored from the power failure state to the normal state is described. However, the present invention is not limited to such a case. That is, the synchronization is deviated with respect to the system voltage Vo, in the case where large phase error phi to the reference signal I _REF is generated, in the same manner, based on the phase error phi, by controlling the phase offset of the reference signal I _REF The phase error φ can be reduced quickly and effectively.

Further, in the present embodiment, an example in which the stability confirmation period T _STB is composed of a predetermined time has been described, but the present invention is not limited to such a case. That is, the length and end timing of the stability confirmation period T _STB can be determined as necessary.

  In this embodiment, an example in which the distributed power source is a solar panel has been described. However, the present invention is not limited to such a case. For example, the present invention can be applied to a power adjustment device for connecting a distributed power source such as a storage battery, a fossil fuel power generation device, and a wind power generation device to a power system. Accordingly, the present invention is not limited to the power adjustment device that includes the boost regulator 1 and performs MPPT control.

DESCRIPTION OF SYMBOLS 1 Boost regulator 10 Voltage detector 11 Current detector 12 Chopper circuit 13 Chopper circuit control part 2 Inverter units 20 and 24 Voltage detector 21 Inverter circuit 22 Current detector 24 Inverter circuit control part 3 Voltage abnormality detection part 30 Multiplier 31 MPPT Control unit 32 Subtractor 33 PWM control unit 34 Gate block unit 4 Output current control unit 40, 45 Subtractor 41 Constant current control unit 42 Control switching unit 43 Synchronization control unit 44 Multiplier 46 PWM control unit 47 Gate block unit 50 First Comparison unit 51 Second comparison unit 52 Gate block signal generation unit 53 Self-running control signal generation unit 54 Constant current control signal generation unit 6 Phase error detection unit 60 Orthogonal component calculation unit 61 First orthogonal component integration unit 62 Second orthogonal component integration Unit 63 phase error calculation unit 64 synchronization completion determination unit 65 frequency control unit 66 phase offset Control unit 67 reference signal generation unit 100 solar panel 101 power adjustment device 102 power system 103 distribution board 104 system power supply 105 load CC constant current control signal GB gate block signal GD1, GD2 gate drive signal Ie _CC specified target effective value Ie _REF target effective value Ii input current Io output current Io _ERR output current error Io _REF target output current I _REF reference signal S grid interconnection system SC synchronization completion signal SR free-running control signal T _ADJ1 first synchronization adjustment period T _ADJ2 second synchronization Adjustment period T _LOW Low voltage period T _OUT Power outage period T _SFT soft start period T _STB stability confirmation period Vi Input voltage Vi _ERR input voltage error Vi _REF target input voltage Vm Intermediate voltage Vm _ERR intermediate voltage error Vm _REF target intermediate voltage Vo System voltage VoD 1st orthogonal component VoQ 1st Quadrature component Vt1 power failure detection threshold Vt2 low voltage determination threshold φ phase error φth synchronization determination threshold φth2 adjustment determination threshold

Claims (8)

In the power conditioner for connecting the distributed power source to the power system,
Reference signal generating means for generating a reference signal composed of a sine wave;
An inverter circuit that converts DC power supplied from the distributed power source into AC power based on the reference signal, and outputs the AC power to the power system;
Voltage detection means for detecting the system voltage of the power system;
Phase error detection means for obtaining a phase error of the reference signal with respect to the system voltage;
Phase offset control means for controlling the phase offset of the reference signal based on the phase error ;
Frequency control means for controlling the frequency of the reference signal based on the phase error;
A power failure determination means for comparing the system voltage with a power failure determination threshold and determining a power failure state of the power system,
Output stopping means for stopping the output of the inverter circuit at the time of a power failure,
The phase offset control means controls the phase offset of the reference signal in the first synchronization adjustment period after power recovery from a power failure,
The frequency control means controls the frequency of the reference signal in a second synchronization adjustment period after the end of the first synchronization adjustment period . Comparing means for comparing the phase error with an adjustment determination threshold value,
The power adjustment apparatus according to claim 1 , wherein the phase offset control unit controls a phase offset of the reference signal based on a comparison result of the comparison unit. 3. The power adjustment device according to claim 2 , wherein the frequency of the reference signal is fixed during a power failure and during the first synchronization adjustment period, and is matched with the frequency of the reference signal before the power failure. The phase error detecting means is
Orthogonal component calculation means for separating the system voltage into a first orthogonal component and a second orthogonal component orthogonal to each other using the reference signal;
A first orthogonal component integrating means for obtaining an integrated value of the first orthogonal component for an integration period comprising one or more cycles of the reference signal;
A second orthogonal component integrating means for obtaining an integrated value of the second orthogonal component for the integration period;
The power adjustment device according to claim 3 , further comprising a phase error calculation unit that obtains the phase error based on each integrated value of the first orthogonal component and the second orthogonal component. The power adjustment apparatus according to claim 4 , wherein the first synchronization adjustment period is one cycle of the reference signal. Low voltage state determination means for comparing the system voltage with a low voltage determination threshold value greater than the power failure determination threshold value, and determining a normal state and a low voltage state of the power system;
Input voltage detection means for detecting an input voltage supplied from the distributed power source and input to the inverter circuit;
Output current control means for controlling the output current of the inverter circuit based on the input voltage,
If the power system is in a low voltage state, the output current control means obtains a target current based on the input voltage in a normal state before shifting to the low voltage state, and performs constant current control of the inverter circuit The power adjustment device according to claim 1 , wherein the power adjustment device is a power adjustment device. Said output control means is the stability confirmation period after power recovery from the low voltage state, using the target current in the low voltage state, according to claim 6, characterized in that the constant current control of the inverter circuit Power conditioner. The power adjustment device according to claim 7 , wherein the target current has a value smaller than the output current in a normal state before the transition to the low voltage state.

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