JP5641202B2 - Interposer, module, and electronic device equipped with the same - Google Patents

Description

  The present invention relates to an interposer and module for relaying electrical and mechanical connections of a plurality of electronic devices having different wiring rules, and an electronic apparatus including the same.

  There is a gap of one digit or more between the pad pitch of a semiconductor chip that is rapidly miniaturized and the pad pitch of a substrate (mounting substrate) on which the chip is mounted. This makes it difficult to reflect the performance of a high-performance and high-performance chip obtained by progress in semiconductor technology in a device or system. For example, the pad pitch of a semiconductor chip is practically used to 50 μm or less, while the pad pitch of a mounting board (for example, a printed circuit board (PCB)) is about 500 μm. In the future, the reduction of the pad pitch of the semiconductor chip is predicted to progress according to the scaling law, but the progress of the reduction of the pad pitch of the PCB is considered to be relatively slow.

  Conventionally, gold (Au) or aluminum (Al) wiring has been used as means for electrically and mechanically coupling a semiconductor chip and a mounting substrate to compensate for this pad pitch gap. Specifically, a semiconductor chip is die-bonded (mechanically connected) on an organic substrate having a 500 μm class wiring rule, and then both wiring pads are wire-connected (electrically connected).

By the way, the influence of the length of the signal line increases as the carrier frequency increases. A signal having a clock frequency of 400 MHz class is used for a carrier of a digital circuit, whereas a high frequency band (GHz to millimeter wave band) is used for a carrier of a transmission / reception circuit. The high frequency has a short wavelength, for example, a half wavelength of 60 GHz is 2.5 mm in a vacuum and 1.2 mm on a PCB. When the physical length of a single signal line becomes more than half of the electrical length of the carrier frequency, the problem of signal resonance in the signal line becomes obvious. For this reason, from the viewpoint of ensuring signal quality, it is desirable that the length of the signal line should be laid out with reference to less than half the electrical length of the carrier signal to be transmitted. Therefore, in recent years, silicon interposers that can be packaged in a smaller size compared to wire-based packaging, and that can be expected to reduce power loss and improve signal quality due to short wiring have attracted attention, and technology development is actively underway. (For example, Patent Document 1).

  The silicon interposer according to Patent Document 1 is composed of wiring (including TSV (Through Silicon Via)) for wiring pitch conversion and a cavity (concave) for an antenna component described later. This silicon interposer is obtained by integrating an antenna pattern formed on another silicon substrate (upper silicon portion) on an interposer substrate. Thereby, the connection distance with the semiconductor chip which is a high frequency analog circuit is shortened, and it becomes possible to improve signal quality.

JP 2008-42904 A

  However, in the interposer exemplified above, there is a problem that reliability and yield are lowered due to complicated manufacturing processes such as bonding of a silicon substrate provided with an antenna pattern and patterning of an antenna portion and a semiconductor chip portion.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an interposer, a module, and an electronic apparatus including the same that can simplify the manufacturing process.

The interposer of the present invention includes a substrate having a front surface and a back surface, wiring formed on the front surface side of the substrate, electrically connected to the semiconductor chip, electrical elements connected to the wiring, and positions corresponding to the electrical elements. In addition to being formed from the back side of the substrate, the bottom is provided with a recess in which at least part of the substrate remains in a fence shape or a lattice shape .

  Here, the “recessed portion” includes not only the shape in which the substrate remains on the bottom portion but also the shape in which the substrate on the bottom portion is completely removed and penetrated. Further, “corresponding” refers to a state in which at least a part of the electric element provided on the substrate is provided on the recess.

  The module of the present invention includes the interposer of the present invention and a semiconductor chip mounted on the interposer.

  An electronic apparatus of the present invention includes the interposer of the present invention, a semiconductor chip mounted on the interposer, and a mounting substrate on which the interposer is mounted.

In the interposer, module, and electronic apparatus including the same according to the present invention, wiring and electrical elements are provided in advance on the substrate, so that bonding of the substrate and wiring and patterning of an electrical element portion such as an antenna and a semiconductor chip portion are performed. And the manufacturing process is simplified.

According to the interposer and module of the present invention and the electronic apparatus including the same , the manufacturing process is simplified because the wiring and the electric element are provided on the substrate. As a result, reliability and yield can be improved.

It is sectional drawing of the module which concerns on one embodiment of this invention. It is a top view of the module shown in FIG. It is sectional drawing showing the other example of a module. FIG. 2 is a characteristic diagram of radio wave radiation of the module shown in FIG. 1. It is a figure showing the manufacturing method of the module shown in FIG. 1 in order of a process. It is a diagram illustrating a process following FIG. It is sectional drawing of the module which concerns on a comparative example. It is a figure showing the manufacturing method of the module shown in FIG. 7 in order of a process. It is a diagram illustrating a process following FIG. FIG. 10 is a diagram illustrating a process following FIG. 9 . It is sectional drawing of the module which concerns on a modification. It is a top view of the module shown in FIG. It is sectional drawing showing the other example of a module. It is a functional block diagram of the electronic device which concerns on the application example of a module.

Embodiments of the present invention will be described below with reference to the drawings in the following order.
(1) Overall configuration (2) Manufacturing method

(1) Overall Configuration FIG. 1 shows a cross-sectional structure of a module 1A provided with an interposer 10A and a semiconductor chip 20 according to an embodiment of the present invention, and FIG. 2 shows its planar configuration. 1 is a cross-sectional structure taken along the line II of FIG. In this interposer 10A, a dielectric layer 14 is formed on a substrate 11 having a recess 19A, and a wiring layer 16 and an electric element 17 (here, an antenna) are provided on the dielectric layer 14. A semiconductor chip 20 connected to the wiring layer 16 is provided on the dielectric layer 14, and the interposer 10 </ b> A penetrates the semiconductor chip 20 and a mounting substrate 30 (here, a printed circuit board) provided in the substrate 11. The electrodes 12 are connected.

The substrate 11 is preferably a silicon (Si) substrate or silicon carbide (SiC) substrate having a thickness of 50 to 400 μm, for example, in accordance with the material of the semiconductor chip 20 described later. This is because the coefficient of thermal expansion becomes substantially equal by combining the material with the semiconductor chip 20 and the reliability of bonding between the semiconductor chip 20 and the interposer 10A is improved. The substrate 11 is not limited to this, and other semiconductor materials and dielectric materials may be used. Examples of other semiconductor materials include SiGe and GaAs, and examples of dielectric materials include ceramic, glass (for example, Pyrex (registered trademark), SD2, quartz), resin (glass epoxy, BT resin ), and organic polymers. Can be mentioned.

  The substrate 11 is provided with a recess 19 </ b> A having a depression on the back side of the substrate 11 at a position corresponding to at least a part of the antenna 17 provided on the dielectric layer 14. However, it is desirable that the recess 19A is formed so as to include the antenna 17 as a whole, as shown in FIG. Here, the substrate 11 remains at the bottom of the recess 19A. However, the present invention is not limited to this, and the substrate 11 may be completely removed as shown in FIG. Further, the substrate 11 may not be completely removed and a part thereof may remain. Specifically, for example, it may be formed in a fence shape or a lattice shape. Furthermore, the planar pattern of the recess 19A (opening 19B) is, for example, a circular shape or a rectangular shape, but is not limited to this, and is determined by the relationship with the shape and size of the electrical element disposed above the recess 19A (opening 19B). Is done.

  The substrate 11 includes a through electrode 12 having a diameter of 50 μm, for example. The through electrode 12 is formed of, for example, copper (Cu), and pads 13A and 13B are provided above and below.

An insulating layer 11 </ b> A is provided between the substrate 11 and the dielectric layer 14. This insulating layer 11A is formed, for example, by forming a silicon nitride film (SiN) having a thickness of 0.01 to 0.3 μm on a silicon oxide film (SiO ₂ ) having a thickness of 0.01 to 4 μm. This insulating layer 11A serves as an etching stopper layer when a recess 19A (opening 19B) is provided in the substrate 11 as will be described later, but has a recess 19A (opening 19B) like the interposer 10A of the present embodiment. The structure for achieving the performance of the so-called membrane element is not essential.

The dielectric layer 14 is formed of a low dielectric constant material with little loss with respect to a high frequency signal, for example, benzocyclobutene (BCB). The thickness of the dielectric layer 14 is determined in terms of both electrical characteristics and mechanical strength, and is, for example, 1 μm to 20 μm. However, the optimum film thickness of the dielectric layer 14 varies depending on the wiring layout rule. For example, in the requirements of electrical characteristics, the film thickness range is determined from the viewpoint of impedance matching of wiring. Specifically, for example, a wiring of 60 GHz, a high frequency wiring with a line / space of 50 μm / 50 μm, and a thickness of 20 μm is required for 50Ω matching in a microstrip line. Considering a line / space corresponding to a CMOS (Complementary Metal Oxide Semiconductor) pad that is increasingly narrow pitch and multi-pin, for example, if the line / space is 30 μm / 30 μm, the thickness is 12 μm, and if the line / space is 15 μm / 15 μm, the thickness is 6 μm. When the thickness is 5 μm / 5 μm, the thickness is 3 μm, and 50Ω is matched. Therefore, the dielectric layer 14 is desirably manufactured by a BCB film forming technique from a thin film of several μm or less to a thick film of several tens of μm or a technique for forming a multilayer film. Further, the dielectric layer 14 has a low loss with respect to a high-frequency signal among the generally used dielectric materials, and has a cross-linked structure even if the concave portion 19A (opening 19B) is provided on the substrate 11 as described above. Other materials can be used as long as they have a strength that can be held. Specifically, diamond-like carbon (DLC) can be used in addition to an inorganic material such as SiO ₂ .

  A wiring layer 16 and an antenna 17 are provided in the dielectric layer 14. The wiring layer 16 is composed of a combination of at least one or more multilayer wiring layers (here, the wirings 16A and 16B) and an interlayer connection wiring layer (via contact 15A). These wiring layers 16 are formed of a conductive material, for example, a metal material such as Al (aluminum) or AlCu (aluminum copper). Here, the antenna 17 is a pseudo Yagi Uta antenna using Al wiring. Of course, the present invention is not limited to this, and other passive elements such as a patch antenna or a slot antenna may be used. Also, a metal material other than Al may be used as the material. It is desirable that the antenna 17 and the semiconductor chip 20 described later are laid out close to each other in order to ensure signal quality. By shortening the distance between the antenna 17 and the semiconductor chip 20, the integrated loss of the transmission / reception circuit can be reduced. For example, when the semiconductor chip 20 and the antenna 17 are connected via a wire, for example, a gold (Au) wire having a diameter of about 1.5 mm and a diameter of 20 μm has a parasitic inductance of 0.8 nH and causes a signal loss of about 1 dB at 60 GHz. . On the other hand, when each is laid out as in the present embodiment, the distance between the antenna 17 and the semiconductor chip 20 is 200 μm, and the signal loss is as small as 0.1 dB. Further, by forming the antenna 17 on the recess 19A (opening 19B) as described above, signal loss due to the substrate is also reduced, and a higher antenna gain can be obtained. As shown in FIGS. 1, 3, and 5, the interlayer connection wiring layer is formed by forming a through hole 14a in the dielectric layer 14A and embedding a metal material in the through hole 14a. The shape is not particularly limited as long as wirings of different layers are connected to each other.

  4A shows the characteristic of the reflection characteristic (S11) of the pseudo Yagi Uta antenna having a center frequency of 60 GHz, and FIG. 4B shows the calculation result of the far-field radio wave radiation characteristic (three-dimensional display). . In the main lobe in the radiation characteristic, the calculation result of the antenna gain of the membrane antenna is −5 dBi, whereas the calculation result of the reference antenna that is not the membrane antenna is −10 dBi. From this, a high antenna gain can be obtained by providing the recess 19A (opening 19B) at a position facing the antenna 17 as in the present embodiment.

  The semiconductor chip 20 is an RFIC. Here, for example, it is a device that up-converts a signal of several hundreds MHz band input from a baseband chip into a high frequency band to obtain a signal of a millimeter wave band, for example. The semiconductor chip 20 is connected to the wirings 16A and 16B via the pads 21A and 21B and the solder layers 22A and 22B. The wiring 16A is connected to the through electrode 12 via the via 15A and the pad 13A. On the other hand, the wiring 16B is connected to the antenna 17.

  In addition to the module 1A (1B), the printed board 30 is a mounting board on which a large number of electronic components such as resistors and capacitors are mounted, and an electronic circuit is configured by connecting these electronic components by wiring.

  Module 1A (1B) can be manufactured by the method shown, for example in FIG. 5 (A)-(C) and FIG. 6 (A)-(C).

(2) Manufacturing Method First, as shown in FIG. 5A, after forming the through hole 11B in the substrate 11, the insulating layer 11A is formed. Specifically, for example, an etching mask is patterned on the surface of the substrate 11 having a thickness of 400 μm. Next, the substrate 11 is etched in the thickness direction under a vacuum condition using a DRIE (Deep Reactive Ion Etching) apparatus to form a through hole 11B. Subsequently, the substrate 11 is heated at 1000 ° C., for example, and a SiO ₂ film having a thickness of 3 μm is formed by thermal oxidation in a water vapor atmosphere. Next, an SiN film having a thickness of 0.1 to 0.3 μm is formed on the SiO ₂ film on the surface of the substrate 11 by, for example, a CVD (Chemical Vapor Deposition) method to form an insulating film 11A. .

  Subsequently, the through electrode 12 is formed as shown in FIG. Specifically, for example, as a seed layer (not shown), a base titanium (Ti) having a thickness of, for example, 50 nm and a copper (Cu) thin film having a thickness of, for example, 300 nm are formed on the surface of the through-hole 11B by, for example, PVD (Physical Vapor Deposition). To do. Next, after filling the through hole 11B with Cu by electrolytic copper plating, the substrate 11 is polished by CMP (Chemical Mechanical Polishing) to form the through electrode 12. Subsequently, an AlCu thin film having a diameter of, for example, 100 μm and a thickness of 100 nm is formed on the pads 13A, 13B, and 13C by dry etching such as photolithography and DRIE.

  Next, as shown in FIG. 5C, the dielectric layer 14A, the via contact 15A, the wirings 16A and 16B, and the antenna 17 are formed. Specifically, first, a dielectric layer 14A is formed on the upper surface of the substrate 11 by spin coating using BCB, which is a low dielectric constant material, and a through hole 14a reaching the pad 13A is formed in the dielectric layer 14A. After that, the via contact 15A is formed by filling the through hole 14a with AlCu. Next, wirings 16A and 16B and an antenna 17 are formed on the dielectric layer 14A by photolithography and dry etching. Next, the dielectric layer 14C, the via contacts 15B and 15C, and the pads 16C and 16D are formed on the lower surface of the substrate 11 using the same method.

  Subsequently, as shown in FIG. 6A, after the dielectric layer 14C is formed on the upper surface of the substrate 11, openings 18A and 18B for connecting the semiconductor chip 20 and the wirings 16A and 16B are formed. Specifically, the dielectric layer 14C is formed on the upper surface of the substrate 11 by spin coating using, for example, BCB, and then the dielectric layer 14C in the region where the semiconductor chip 20 is mounted is removed by photolithography and dry etching. Next, for example, after forming a hard mask on the lower surface of the substrate 11, the substrate 11 is etched by, for example, DRIE to form a recess 19A (opening 19B), thereby completing the interposer 10A having a desired membrane structure. As etching conditions, vertical processing using SF6 / C4H8, which is known as a Bosch process, or a dry process using XeF2 is used. Alternatively, a wet process using tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) may be used. At this time, since the insulating layer 11A provided between the substrate 11 and the dielectric layer 14 functions as an etching stopper layer, etching stops in the insulating layer 11A. In addition, when the insulating layer 11A is thin, overetching may occur.

  Next, as shown in FIG. 6B, the semiconductor chip 20 is mounted on the upper surface of the interposer 10A. Specifically, the pads 21A and 21B provided on the lower surface of the semiconductor chip 20 are thermocompression bonded to the upper surface of the interposer 10A, for example, at 150 ° C. and 100 kPa, thereby completing the bonding between the semiconductor chip 20 and the interposer 10A.

  Finally, as shown in FIG. 6C, the pads 16C and 16D of the interposer 10A and the pads 31A and 31B formed on the printed circuit board 30 are connected via the bumps 32A and 32B, and the semiconductor chip 20 is connected to the printed circuit board 30. The interposer 10A equipped with is mounted. Thereby, the module 1A is completed.

  The interposer 10 </ b> A (10 </ b> B) of the present embodiment includes a dielectric layer 14 formed on a substrate 11, and a wiring layer 16 and an antenna 17 are provided in the dielectric layer 14. Further, a through electrode 12 is provided on the substrate 11, and the interposer 10 </ b> A connects the printed circuit board 30 and the semiconductor chip 20 mounted on the interposer 10 </ b> A through the through electrode 12. As described above, by using the interposer 10A, it is possible to electrically and mechanically relay the semiconductor chip 20 and the printed board 30 having different wiring pitches.

  Further, a recess 19 </ b> A (opening 19 </ b> B) formed from the back side of the substrate 11 is provided at a position corresponding to the antenna 17 of the substrate 11. Thereby, the generation of parasitic capacitance and eddy current between the substrate 11 and the antenna 17 can be suppressed.

  As described above, the semiconductor chip 20 and the printed circuit board 30 are connected at a narrow wiring pitch at the connection part on the semiconductor chip 20 side and at a wide wiring pitch at the connection part on the printed circuit board 30 side. The pads constituting the connecting portion and the wiring connecting them are the wiring layer 16 provided in the dielectric layer 14 on the substrate 11 of the interposer 10A, the through electrode 12 and the wiring layer 16 on the back side of the substrate 11 (pads 13B and 16C). , Via contacts 15B), and these lines and spaces are manufactured using semiconductor chip processing means. Therefore, compared with a general mounting board, it is processed by a rule equivalent to a minute processing technique of one digit or more or a wiring processing rule of a semiconductor chip. Note that the wiring layer 16 (pads 13C and 16D and via contact 15C) on the right side of the back surface of the substrate 11 of the interposer 10A (10B) in FIG. 1 (FIG. 3) takes a mechanical balance when mounted on the printed circuit board 30, for example. This is a dummy connection layer or a GND (ground) connection layer of the substrate 11.

  FIG. 7 illustrates a cross-sectional configuration of a conventional module 100 according to a comparative example. The interposer 100A in this module has a second Si substrate 211 on which a semiconductor chip (integrated circuit chip) 220 having a wiring 216 and an antenna 217 on the lower surface is mounted on a first Si substrate (interposer) 111 having a recess 119 by a bonding metal. It is joined. The recess 119 is for housing the semiconductor chip 220.

In order to actually obtain such a module 100, the manufacturing steps shown in FIGS. 8 (A) to (C), FIGS. 9 (A) to (C), and FIGS. 10 (A) and 10 (B) can be considered. . Each step will be briefly described. First, as shown in FIG. 8A, the first Si substrate 111 is processed to form a through hole 111B, and then an insulating film (not shown) is formed. Next, as shown in FIG. 8B, after the through electrode 112A is formed, pads 113A, 113B, 113C, and 113D are formed. Subsequently, as shown in FIG. 8C, a recess 119 is formed, and a first Si substrate 111 serving as an interposer is manufactured. Next, as shown in FIG. 9 (A), a dielectric layer 214 having wirings 216A and 216B and an antenna 217 is formed on the second Si substrate 211 , and then the second Si substrate as shown in FIG. 9 (B). 211 is thinned by CMP. Subsequently, as shown in FIG. 9C, a concave portion 219 is provided in the second Si substrate 211 to form a membrane structure, and then the semiconductor chip 220 is connected to produce the second Si substrate 211 on which the semiconductor chip 220 is mounted. Next, after bonding the first Si substrate 111 and the second Si substrate 211 by thermocompression bonding as shown in FIG. 10A, finally, as shown in FIG. And the module 100 is completed.

  The module 100 thus obtained and its manufacturing process have the following problems. First, since two Si substrates are used, the size is necessarily increased. Therefore, a thinning process (FIG. 9B) that compensates for this is required. In addition to forming the recess 119 in the first Si substrate 111, it is necessary to provide the recess 219 at a position facing the second Si substrate 211 in order to radiate radio waves from the antenna 217. At this time, since the second Si substrate 211 is thinned as described above, the second Si substrate 211 may be easily broken. Further, when the second Si substrate 211 is mounted on the first Si substrate 111, the through electrodes 112A and 112B of the first Si substrate 111 and the wiring layer 216 provided on the lower surface of the second Si substrate 211 are bonded. The joining process is restricted in miniaturization due to low alignment accuracy, and when the transmission frequency is high, signal loss due to wiring mismatch or the like becomes obvious. Further, wiring processing for joining the first Si substrate 111 and the second Si substrate 211 is also required. As described above, the manufacturing process becomes complicated.

  On the other hand, in the interposer 10A (10B) of the present embodiment, the wiring layer 16 is provided in the dielectric layer 14 formed directly on the substrate 11, so that the above process is not required, and thus the manufacturing process is simplified. Can be achieved.

  As described above, in the interposer 10A (10B) of this embodiment and the module 1A (1B) including the same, the dielectric layer 14 is formed on the substrate 11, and the wiring layer 16 and the antenna are formed in the dielectric layer 14. 17 was provided. As described above, the structure in which the substrate 11 and the wiring layer 16 are integrated can simplify the manufacturing process and improve the yield.

  In addition, since the bonding process that causes a decrease in alignment accuracy is reduced, the characteristics of the module 1A (1B) are improved. Furthermore, since the manufacturing process is shortened, the cost can be suppressed.

  Further, since the semiconductor chip 20 and the printed board 30 are connected by the through electrode 12, the wiring area can be reduced. That is, the module 1A (1B) can be downsized. Furthermore, by using the through electrode 12, another module can be stacked on the module 1A (1B).

Further, in the interposer 10A (10B) and the module 1A (1B) including the interposer 10A according to the present embodiment, the recess 19A (or the substrate 11 is penetrated on the back side of the substrate 11 at a position corresponding to at least a part of the antenna 17. An opening 19B) was provided. As a result, generation of parasitic capacitance and eddy current between the substrate portion and the element can be suppressed, so that signal loss can be suppressed.

(Modification)
Next, an interposer 10C (10D) according to a modification of the interposer 10A (10B) and the module 1A (1B) including the interposer 10A and the module 2A (2B) including the same will be described. FIG. 11 illustrates a cross-sectional configuration of a module 2A including an interposer 10C having a recess 19A on the substrate 11, and FIG. 12 illustrates a planar configuration thereof. FIG. 13 illustrates a cross-sectional configuration of a module 2B provided with an interposer 10D having an opening 19B in the substrate 11. 11 and 13 are cross-sectional structures taken along line II-II in FIG. The same components as those in the above embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  This interposer 10 </ b> C (10 </ b> D) is obtained by connecting the wiring layer 16 and the printed circuit board 30 via wires 33. On the substrate 11, in addition to the dielectric layer 14 on which the wiring layer 16 and the electric element 17 described in the above embodiment are formed, a wire pad for wire connection to the printed circuit board 30 and wiring noise are removed. In addition to the decoupling capacitor (MIM capacitor) (not shown), a chip connecting portion 23 is provided.

  In the interposer 10C (10D) and the module 2A (2B) having the same in the present modification, the wiring layer 16 and the printed board 30 are connected by the wire 33, so in addition to the effects of the above embodiment, printing is performed. There is an effect that the modules 2A (2B) can be freely arranged on the substrate 30. Further, for example, when the number of pins is small and the difference in the area occupied by the elements is small compared to a BGA (Ball Grid Array) or the like, the wiring by the wire 33 is cheaper than the through electrode 12 is manufactured. There is also an effect that the cost can be reduced.

(Application example)
Next, a configuration of a communication apparatus using the interposer 10A of the present invention will be described with reference to FIG. FIG. 14 illustrates a block configuration of a communication device as an electronic device.

  The communication device shown in FIG. 14 is, for example, a mobile phone, a personal digital assistant (PDA), a wireless LAN device, or the like. For example, as shown in FIG. 14, the communication apparatus includes a transmission system circuit 300A (module), a reception system circuit 300B (module), a transmission / reception switch 301 that switches transmission / reception paths, a high-frequency filter 302, and a transmission / reception circuit. The antenna 303 is provided.

  The transmission system circuit 300A includes two digital / analog converters (DACs) 311I and 311Q and two band-pass filters 312I and 312Q corresponding to I-channel transmission data and Q-channel transmission data, and modulation. 320, a transmission PLL (Phase-Locked Loop) circuit 313, and a power amplifier 314. The modulator 320 includes two buffer amplifiers 321I and 321Q and two mixers 322I and 322Q corresponding to the two bandpass filters 312I and 312Q, a phase shifter 323, an adder 324, and a buffer amplifier 325. It is comprised including.

  The reception system circuit 300B includes a high frequency unit 330, a band pass filter 341, a channel selection PLL circuit 342, an intermediate frequency circuit 350, a band pass filter 343, a demodulator 360, an intermediate frequency PLL circuit 344, and an I channel reception. Two band-pass filters 345I and 345Q and two analog / digital converters (ADC) 346I and 346Q corresponding to the data and Q-channel received data are provided. The high frequency unit 330 includes a low noise amplifier 331, buffer amplifiers 332 and 334, and a mixer 333. The intermediate frequency circuit 350 includes buffer amplifiers 351 and 353, and automatic gain adjustment (AGC; Auto Gain). Controller) circuit 352. The demodulator 360 includes a buffer amplifier 361, two mixers 362I and 362Q corresponding to the two band-pass filters 345I and 345Q, two buffer amplifiers 363I and 363Q, and a phase shifter 364. Yes.

  In this communication apparatus, when I-channel transmission data and Q-channel transmission data are input to the transmission system circuit 300A, each transmission data is processed in the following procedure. That is, first, analog signals are converted by the DACs 311I and 311Q, signal components other than the band of the transmission signal are subsequently removed by the bandpass filters 312I and 312Q, and then supplied to the modulator 320. Subsequently, the modulator 320 supplies the signals to the mixers 322I and 322Q via the buffer amplifiers 321I and 321Q, and subsequently mixes and modulates the frequency signal corresponding to the transmission frequency supplied from the transmission PLL circuit 313, The mixed signal is added in the adder 324 to obtain one transmission signal. At this time, with respect to the frequency signal supplied to the mixer 322I, the phase shifter 323 shifts the signal phase by 90 ° so that the I channel signal and the Q channel signal are orthogonally modulated. Finally, the signal is supplied to the power amplifier 314 via the buffer amplifier 325 to be amplified so as to have a predetermined transmission power. The signal amplified in the power amplifier 314 is supplied to the antenna 303 via the transmission / reception switch 301 and the high frequency filter 302, so that it is wirelessly transmitted via the antenna 303. The high-frequency filter 302 functions as a band-pass filter that removes signal components other than the frequency band of signals transmitted or received in the communication apparatus.

  On the other hand, when a signal is received from the antenna 303 via the high frequency filter 302 and the transmission / reception switch 301 to the reception system circuit 300B, the signal is processed in the following procedure. That is, first, in the high frequency unit 330, the received signal is amplified by the low noise amplifier 331, and subsequently, signal components other than the received frequency band are removed by the band pass filter 341, and then supplied to the mixer 333 via the buffer amplifier 332. Subsequently, the frequency signals supplied from the channel selection PPL circuit 342 are mixed, and a signal of a predetermined transmission channel is used as an intermediate frequency signal, which is supplied to the intermediate frequency circuit 350 via the buffer amplifier 334. Subsequently, in the intermediate frequency circuit 350, signal components other than the band of the intermediate frequency signal are removed by supplying the band pass filter 343 via the buffer amplifier 351, and then the AGC circuit 352 generates a substantially constant gain signal. And supplied to the demodulator 360 via the buffer amplifier 353. Subsequently, in the demodulator 360, the frequency signals supplied from the intermediate frequency PPL circuit 344 are mixed after being supplied to the mixers 362I and 362Q via the buffer amplifier 361, and the I-channel signal component and the Q-channel signal component are mixed. And demodulate. At this time, with respect to the frequency signal supplied to the mixer 362I, the phase shifter 364 shifts the signal phase by 90 ° to demodulate the I-channel signal component and the Q-channel signal component that are orthogonally modulated with each other. Finally, by removing the signal components other than the I channel signal and the Q channel signal by supplying the I channel signal and the Q channel signal to the band pass filters 345I and 345Q, respectively, the signals are supplied to the ADCs 346I and 346Q. Digital data. Thereby, I-channel received data and Q-channel received data are obtained.

  In this communication apparatus, the interposers 10A to 10D described in the above embodiments and modifications are applied to the connection between the antenna 303, the high frequency filter 302, the band pass filters 341 and 343, the modulator 320 and the demodulator 360, and the mounting board. Therefore, it has excellent high frequency characteristics due to the action described in the above embodiment.

  In the communication apparatus shown in FIG. 14, the case where the interposers 10 </ b> A to 10 </ b> D described in the above embodiment and the modified examples are applied to the connection between each element and the mounting board is described, but the present invention is not limited to this. is not. For example, the interposers 10 </ b> A to 10 </ b> D may be applied to the connection of both wirings in the integrated device of the CMOS element and the MEMS sensor that are separated in miniaturization. Even in this case, the same effect as described above can be obtained. The present invention can also be applied to integration of analog circuit elements and digital circuit elements.

  Although the present invention has been described with reference to the embodiment and the modifications, the present invention is not limited to the above-described embodiment and the like, and various modifications can be made. For example, in the above embodiment, the through electrode 12 is used for connection between the semiconductor chip 20 and the printed circuit board 30, but the same effect can be obtained even if the connection is made by through-hole wiring.

  In the above-described embodiment and the like, the antenna 17 is used as an electric element (passive element). However, the present invention is not limited to this. For example, an inductor or a coupler may be used. Furthermore, a filter and a variable filter combining an electric element other than a passive element, for example, a high-frequency switch, a varicap when used as a coupling capacitor of a high-frequency transmission line, or an electric element may be used.

  1A, 1B, 2A, 2B, 100 ... module, 10A, 10B, 10C, 10D, 100A ... interposer, 11 ... substrate, 11A ... insulating layer, 12 ... penetrating electrode, 13A, 13B, 13C, 16C, 16D, 21A, 21B, 31A, 31B ... Pad, 14 (14A, 14B, 14C) ... Dielectric layer, 15A, 15B, 15C ... Via contact, 16A, 16B ... Wiring, 16 (15A, 16A, 16B) ... Wiring layer, 17 ... Antenna, 18A, 18B, 19A ... recess, 19B ... opening, 20 ... semiconductor chip, 22, 32A, 32B ... solder, 30 ... printed circuit board.

Claims (12)

A substrate having a front surface and a back surface;
Wiring formed on the surface side of the substrate and electrically connected to the semiconductor chip;
An electrical element connected to the wiring;
An interposer which is formed from the back side of the substrate at a position corresponding to the electric element, and has a recess at the bottom of which at least a part of the substrate remains in a fence shape or a lattice shape .   The interposer according to claim 1, wherein the electrical element is a passive element. The interposer according to claim 2 , wherein the passive element is an antenna, an inductor, or a coupler. 4. The interposer according to claim 1 , further comprising a dielectric layer on the substrate, wherein the wiring is provided in at least one layer inside or on the dielectric layer. 5. The interposer according to claim 4 , wherein the dielectric layer includes an organic material. The interposer according to claim 4 , further comprising an insulating layer between the substrate and the dielectric layer.   The interposer according to claim 1, further comprising a through electrode connected to the wiring in the substrate.   The interposer according to claim 1, wherein the substrate is a semiconductor substrate or a dielectric substrate. The interposer according to claim 8 , wherein the substrate is a silicon substrate. An interposer and a semiconductor chip mounted on the interposer,
The interposer is
A substrate having a front surface and a back surface, and the semiconductor chip mounted on the front surface side;
Wiring formed on the surface side of the substrate and electrically connected to the semiconductor chip;
An electrical element connected to the wiring;
A module which is formed from the back side of the substrate at a position corresponding to the electric element, and has a recess at the bottom of which at least a part of the substrate remains in a fence shape or a lattice shape . The module according to claim 10 , wherein the semiconductor chip is electrically connected to a mounting substrate through the wiring and a through electrode provided in the substrate. An interposer, a semiconductor chip mounted on the interposer, and a mounting board electrically connected to the interposer,
The interposer is
A substrate having a front surface and a back surface, and the semiconductor chip mounted on the front surface side;
Wiring formed on the surface side of the substrate and electrically connected to the semiconductor chip;
An electrical element connected to the wiring;
An electronic device that is formed from a back surface side of the substrate at a position corresponding to the electrical element, and has a concave portion in which at least a part of the substrate remains in a fence shape or a lattice shape at a bottom portion.

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