JP5626240B2 - Driver circuit - Google Patents
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Description
本発明は、差動信号が伝送される二線式の伝送線路を駆動するドライバ回路に関する。 The present invention relates to a driver circuit that drives a two-wire transmission line through which a differential signal is transmitted.
従来、二線式の伝送線路により差動信号を用いて通信を行うＣＡＮ（Controller Area Network ）等の通信システムが知られている。
この種の通信システムでは、伝送線路の配線が長くなったり、伝送線路に接続するノードの数が増えたりすると、伝送線路の端部やノードの接続端にてインピーダンス不整合による反射が生じ、その結果、リンギングによる波形歪が生じる。また、波形歪が生じるとその信号を受信する側で信号レベルの誤判定が生じる可能性がある。
Conventionally, a communication system such as a CAN (Controller Area Network) that performs communication using a differential signal by a two-wire transmission line is known.
In this type of communication system, when the wiring of the transmission line becomes long or the number of nodes connected to the transmission line increases, reflection due to impedance mismatch occurs at the end of the transmission line or the connection end of the node, As a result, waveform distortion due to ringing occurs. Further, when waveform distortion occurs, there is a possibility that an erroneous determination of the signal level occurs on the side receiving the signal.
このような波形歪を低減する手法の一つとして、伝送線路を終端するインピーダンスを可変設定するインピーダンス可変部を設け、出力データの変化に伴って、出力インピーダンスがロウインピーダンスの状態からハイインピーダンスの状態に変化するタイミングで所定期間だけ、インピーダンス可変部のインピーダンスが伝送線路の特性インピーダンスに近い値となるように制御するものがある（例えば、特許文献１参照。）。 As one of the methods for reducing such waveform distortion, an impedance variable section that variably sets the impedance that terminates the transmission line is provided, and the output impedance changes from the low impedance state to the high impedance state as the output data changes. In some cases, the impedance of the variable impedance unit is controlled to a value close to the characteristic impedance of the transmission line for a predetermined period at the timing of changing to (for example, see Patent Document 1).
しかし、特許文献１に記載の手法では、出力データの変化を検出してインピーダンス可変部のインピーダンスを所定期間だけ変化させるための制御回路が必要であり、ドライバ回路の回路構成が複雑化すると共に回路規模が増大するという問題があった。 However, the method described in Patent Document 1 requires a control circuit for detecting a change in output data and changing the impedance of the impedance variable section only for a predetermined period, which complicates the circuit configuration of the driver circuit and There was a problem that the scale increased.
また、所定タイミングで所定時間だけ動作するため、出力データの変化に伴う出力インピーダンスの変化以外の原因に基づいて発生する波形歪については、これを低減することができないという問題もあった。 Further, since the operation is performed for a predetermined time at a predetermined timing, there is a problem that the waveform distortion generated based on a cause other than the change in the output impedance accompanying the change in the output data cannot be reduced.
更に、出力データの変化を検知してからインピーダンス可変部が作動するまでに遅延が生じるため、その遅延時間の間も歪を低減することができないという問題があった。
本発明は、上記問題点を解決するために、簡易な構成で波形歪を低減するドライバ回路を提供することを目的とする。
Furthermore, since a delay occurs between the time when the change of output data is detected and the impedance variable section is activated, there is a problem that distortion cannot be reduced during the delay time.
In order to solve the above-described problems, an object of the present invention is to provide a driver circuit that reduces waveform distortion with a simple configuration.
本発明のドライバ回路では、動作制御部が、２値信号が一方の信号レベル（以下「第１レベル」という）の時に、第３抵抗器及び第４抵抗器の給電端を開放状態とし、２値信号が他方の信号レベル（以下「第２レベル」という）の時に、第３抵抗器の給電端に高電位側基準電圧を印加すると共に、第４抵抗器の給電端に低電位側基準電圧を印加する。 In the driver circuit of the present invention, when the operation control unit has one signal level (hereinafter referred to as “first level”), the power supply terminals of the third resistor and the fourth resistor are opened. When the value signal is at the other signal level (hereinafter referred to as “second level”), the high potential side reference voltage is applied to the power supply end of the third resistor, and the low potential side reference voltage is applied to the power supply end of the fourth resistor. Apply.
これにより、２値信号が第１レベルの時には、高電位側端子（ひいては第１の信号線）及び低電位側端子（ひいては第２の信号線）には、いずれにも中立電圧が印加され、差動信号の信号レベルは低レベルとなる。一方、２値信号が第２レベルの時には、第１の信号線には、高電位側基準電圧と中立電圧との電圧差を第１分圧回路で分圧した電圧（高位分圧電圧）が印加され、第２の信号線には、中立電圧と低電位側基準電圧との電圧差を第２分圧回路で分圧した電圧（低位分圧電圧）が印加されるため、差動信号の信号レベルは高レベルとなる。 Thus, when the binary signal is at the first level, a neutral voltage is applied to both the high potential side terminal (and hence the first signal line) and the low potential side terminal (and thus the second signal line), The signal level of the differential signal is low. On the other hand, when the binary signal is at the second level, a voltage obtained by dividing the voltage difference between the high potential side reference voltage and the neutral voltage by the first voltage dividing circuit (high voltage divided voltage) is applied to the first signal line. A voltage obtained by dividing the voltage difference between the neutral voltage and the low potential side reference voltage by the second voltage dividing circuit (low voltage division voltage) is applied to the second signal line. The signal level is high.
つまり、第１の信号線の電圧が、中立電圧或いは高位分圧電圧に保たれ、また、第２の信号線の電圧が、中立電圧或いは低位分圧電圧に保たれている状態、即ち、伝送線路上の信号に波形歪が生じていない場合は、第１ダイオード及び第２ダイオードが導通することはない。 That is, the voltage of the first signal line is kept at a neutral voltage or a high divided voltage, and the voltage of the second signal line is kept at a neutral voltage or a low divided voltage, that is, transmission. When the waveform distortion is not generated in the signal on the line, the first diode and the second diode do not conduct.
一方、伝送線路上の信号に波形歪が生じることによって、第１の信号線の電圧が、中立電圧からダイオードの順電圧を減じた大きさの高位側しきい値電圧を越えて小さくなると、第１ダイオードが導通し、それ以上電圧が低下することがない。同様に、第２の信号線の電圧が、中立電圧にダイオードの順電圧を加えた大きさの低位しきい値電圧を越えて大きくなると、第２ダイオードが導通し、それ以上電圧が上昇することがない。 On the other hand, if the waveform distortion occurs in the signal on the transmission line, and the voltage of the first signal line becomes smaller than the high-order threshold voltage that is obtained by subtracting the diode forward voltage from the neutral voltage, One diode conducts and the voltage does not drop any more. Similarly, when the voltage of the second signal line becomes larger than the low threshold voltage, which is the magnitude obtained by adding the forward voltage of the diode to the neutral voltage, the second diode becomes conductive, and the voltage further increases. There is no.
このように本発明のドライバ回路によれば、歪んだ波形を第１ダイオード及び第２ダイオードによってクランプするため、波形歪の振幅を小さく抑えることができ、また波形歪を速やかに収束させることができる。 As described above, according to the driver circuit of the present invention, since the distorted waveform is clamped by the first diode and the second diode, the amplitude of the waveform distortion can be kept small, and the waveform distortion can be quickly converged. .
なお、本発明のドライバ回路において、第１ダイオード及び第２ダイオードには、それぞれコンデンサが直列接続されていてもよい。
この場合、直流成分はカットされ交流成分（波形歪成分）のみが通過することになるだけでなく、第１の信号線に地絡等の故障が発生した時に、第１ダイオード及び第２ダイオードが接続された経路を介して、第２の信号線から第１の信号線に大きな故障電流が流れ込むことが防止されるため、安全性を向上させることができる。
In the driver circuit of the present invention, a capacitor may be connected in series with each of the first diode and the second diode.
In this case, not only the DC component is cut and only the AC component (waveform distortion component) passes, but also when a failure such as a ground fault occurs in the first signal line, the first diode and the second diode are Since a large fault current is prevented from flowing from the second signal line to the first signal line through the connected path, safety can be improved.
以下に本発明の実施形態を図面と共に説明する。
＜全体構成＞
図２は、通信プロトコルとしてＣＡＮ（Ｃｏｎｔｒｏｌｌｅｒ Ａｒｅａ Ｎｅｔｗｏｒｋ）が用いられた車載用の通信システム１の構成を表すブロック図である。
Embodiments of the present invention will be described below with reference to the drawings.
<Overall configuration>
FIG. 2 is a block diagram showing a configuration of an in-vehicle communication system 1 in which a CAN (Controller Area Network) is used as a communication protocol.
図２に示すように、通信システム１は、車両に搭載された複数の電子制御ユニット１０ａ，１０ｂ，１０ｃ，…を、共通の伝送線路３を介して相互に通信可能となるように接続することで構成され、これら電子制御ユニット１０ａ，１０ｂ，１０ｃ，…のそれぞれがノードとして機能するようにされている。以下では、電子制御ユニットをＥＣＵとよび、また、ＥＣＵ１０ａ，１０ｂ，１０ｃ…を、特に区別しないでいずれか一つを指す場合はＥＣＵ１０と表記する。 As shown in FIG. 2, the communication system 1 connects a plurality of electronic control units 10 a, 10 b, 10 c,... Mounted on a vehicle so that they can communicate with each other via a common transmission line 3. Each of these electronic control units 10a, 10b, 10c,... Functions as a node. In the following, the electronic control unit is referred to as an ECU, and the ECUs 10a, 10b, 10c,.
このうち、伝送線路３は一対の信号線３ａ，３ｂ（以下、一方をＣＡＮＨ３ａ，他方をＣＡＮＬ３ｂと表記する）で構成された二線式のバス型伝送線路からなり、その両端は、終端抵抗５，５によってそれぞれ終端されている。そして、伝送線路３では、ＣＡＮＨ３ａ，ＣＡＮＬ３ｂ間の電位差によって信号レベルを表現した差動信号が伝送される。以下では、ＣＡＮＨ３ａ，ＣＡＮＬ３ｂ間の電位差が予め設定された符号判定閾値以上である場合をドミナント、その電位差が符号判定閾値未満である場合をレセッシブと称する。 Among these, the transmission line 3 is composed of a two-wire bus type transmission line composed of a pair of signal lines 3a and 3b (hereinafter, one is represented as CANH 3a and the other as CANL 3b). , 5 respectively. The transmission line 3 transmits a differential signal representing a signal level by a potential difference between the CANH 3a and the CANL 3b. Hereinafter, the case where the potential difference between CANH 3a and CANL 3b is greater than or equal to a preset code determination threshold is referred to as dominant, and the case where the potential difference is less than the code determination threshold is referred to as recessive.
＜ＥＣＵ＞
ＥＣＵ１０は、通信システム１を介してＣＡＮプロトコルに従った通信制御（送信フレームの生成、受信フレームの解析）を行うＣＡＮコントローラ１２と、ＣＡＮコントローラ１２から与えられる２値符号のデータ列（送信フレーム）ＴＸを差動信号に変換して伝送線路ＬＮに出力すると共に、伝送線路ＬＮ上の差動信号を受信して２値符号に復号したデータ列（受信フレーム）ＲＸをＣＡＮコントローラ１２に入力するトランシーバ１３と、車両各部を制御するための制御処理や、ＣＡＮコントローラ１２を用いて他のＥＣＵ１０との通信を行うための処理等を実行するマイクロコンピュータ１１とを備えている。
<ECU>
The ECU 10 includes a CAN controller 12 that performs communication control (transmission frame generation and reception frame analysis) according to the CAN protocol via the communication system 1, and a binary code data string (transmission frame) provided from the CAN controller 12. A transceiver that converts TX into a differential signal and outputs it to the transmission line LN, and receives a differential signal on the transmission line LN and inputs a data string (reception frame) RX decoded into a binary code to the CAN controller 12 13 and a microcomputer 11 that executes a control process for controlling each part of the vehicle, a process for communicating with other ECUs 10 using the CAN controller 12, and the like.
以下では、トランシーバ１３において、ＣＡＮＨ３ａが接続される端子をＣＡＮＨ端子１３１、ＣＡＮＬ３ｂが接続される端子をＣＡＮＬ端子１３２、ＣＡＮコントローラ１２から供給されるデータ列を入力する端子をＴＸ端子１３３、ＣＡＮコントローラ１２へ供給するデータ列を出力する端子をＲＸ端子１３４と称する。 Hereinafter, in the transceiver 13, the CANH terminal 131 is connected to the CANH 3a, the CANL terminal 132 is connected to the CANL 3b, the TX terminal 133 is a terminal for inputting a data string supplied from the CAN controller 12, and the CAN controller 12 is connected to the CAN controller 12. A terminal that outputs a data string to be supplied to is called an RX terminal 134.
＜トランシーバ＞
トランシーバ１３は、図１に示すように、ＴＸ端子１３３を介して入力される２値符号のデータ列ＴＸを差動信号に変換してＣＡＮＨ端子１３１，ＣＡＮＬ端子１３２に出力するドライバ回路２０と、ＣＡＮＨ端子１３１，ＣＡＮＬ端子１３２を介して入力される差動信号を２値符号のデータ列ＲＸに復号してＲＸ端子に出力するレシーバ回路３０とを備えている。
<Transceiver>
As shown in FIG. 1, the transceiver 13 converts a binary-coded data string TX input via the TX terminal 133 into a differential signal and outputs the differential signal to the CANH terminal 131 and the CANL terminal 132; And a receiver circuit 30 that decodes a differential signal input via the CANH terminal 131 and the CANL terminal 132 into a binary code data string RX and outputs the data to the RX terminal.
このうち、レシーバ回路３０は周知のものであるため、ここでは説明を省略し、以下では、本発明の主要部となるドライバ回路２０を中心に説明する。
ドライバ回路２０は、差動信号がドミナントである場合にＣＡＮＨ３ａ，ＣＡＮＬ３ｂが示す電圧である中立電圧Ｖｃ（ここでは、後述する電圧ＶDDの１／２）を発生させる中立電圧発生回路２１を備えている。そして、中立電圧発生回路２１の出力端は、並列接続された抵抗器２２Ｈ及びダイオード２３Ｈを介してＣＡＮＨ端子１３１に接続されていると共に、並列接続された抵抗器２２Ｌ及びダイオード２３Ｌを介してＣＡＮＬ端子１３２に接続されている。但し、ダイオード２３Ｈは、中立電圧発生回路２１の出力端からＣＡＮＨ端子１３１に向かう方向が順方向となり、ダイオード２３Ｌは、ＣＡＮＬ端子１３２から中立電圧発生回路２１の出力端に向かう方向が順方向となるように接続されている。
Among these, since the receiver circuit 30 is a well-known one, the description thereof is omitted here, and the following description will focus on the driver circuit 20 that is the main part of the present invention.
The driver circuit 20 includes a neutral voltage generation circuit 21 that generates a neutral voltage Vc (1/2 of a voltage VDD described later) that is a voltage indicated by CANH3a, CANL3b when the differential signal is dominant. . The output terminal of the neutral voltage generation circuit 21 is connected to the CANH terminal 131 via a resistor 22H and a diode 23H connected in parallel, and a CANL terminal via a resistor 22L and a diode 23L connected in parallel. 132. However, the direction of the diode 23H from the output end of the neutral voltage generation circuit 21 toward the CANH terminal 131 is the forward direction, and the direction of the diode 23L from the CANL terminal 132 toward the output end of the neutral voltage generation circuit 21 is the forward direction. So connected.
また、抵抗器２２ＨのＣＡＮＨ端子側接続端と、高電位側電源（電圧ＶDD）との間には、抵抗器２４Ｈ，ダイオード２５Ｈ，トランジスタ２６Ｈが直列に接続され、抵抗器２２ＬのＣＡＮＬ端子側接続端と、低電位側電源（電圧ＶＧ、ここでは０Ｖ）との間には、抵抗器２４Ｌ，ダイオード２５Ｌ，トランジスタ２６Ｌが直列に接続されている。 A resistor 24H, a diode 25H, and a transistor 26H are connected in series between the CANH terminal side connection end of the resistor 22H and the high potential side power supply (voltage VDD), and the CANL terminal side connection of the resistor 22L is connected. A resistor 24L, a diode 25L, and a transistor 26L are connected in series between the terminal and the low-potential-side power supply (voltage VG, here 0 V).
但し、ダイオード２５Ｈは、高電位側電源から抵抗器２２Ｈに向かう方向が順方向となるように接続され、ダイオード２５Ｌは、抵抗器２２Ｌから低電位側電源に向かう方向が順方向となるように接続されている。また、トランジスタ２６Ｈは、ＰＭＯＳ電界効果トランジスタからなり、トランジスタ２６ＬはＮＭＯＳ電界効果トランジスタからなる。 However, the diode 25H is connected so that the direction from the high-potential side power supply to the resistor 22H is a forward direction, and the diode 25L is connected so that the direction from the resistor 22L to the low-potential side power supply is a forward direction. Has been. The transistor 26H is a PMOS field effect transistor, and the transistor 26L is an NMOS field effect transistor.
更に、ドライバ回路２０は、ＴＸ端子１３３を介して入力されるデータのレベルに応じて、トランジスタ２６Ｈ，２６Ｌのゲートに印加する駆動信号ＧＨ，ＧＬを発生させるレベル変換回路２７を備えている。このレベル変換回路２７は、具体的には、入力されるデータがレセッシブに対応させるレベル（例えば‘１’）である場合に、トランジスタ２６Ｈ，２６Ｌをいずれもオフ状態にし、入力されるデータがドミナントに対応させるレベル（例えば‘０’）である場合に、トランジスタ２６Ｈ，２６Ｌをいずれもオン状態にするような駆動信号ＧＨ，ＧＬを発生させる。 Furthermore, the driver circuit 20 includes a level conversion circuit 27 that generates drive signals GH and GL to be applied to the gates of the transistors 26H and 26L in accordance with the level of data input via the TX terminal 133. Specifically, the level conversion circuit 27 turns off the transistors 26H and 26L when the input data is at a level (eg, “1”) corresponding to recessive, and the input data is dominant. Drive signals GH and GL are generated so as to turn on both the transistors 26H and 26L.
以下では、トランジスタ２６Ｈ，２６Ｌのオン電圧をＶon、ダイオード２３Ｈ，２３Ｌ，２５Ｈ，２５Ｌの順電圧をＶｆ、抵抗器２２Ｈ，２２Ｌの抵抗値をＲ１、抵抗器２４Ｈ，２４Ｌの抵抗値をＲ２とする。 Hereinafter, the on voltage of the transistors 26H and 26L is Von, the forward voltage of the diodes 23H, 23L, 25H and 25L is Vf, the resistance values of the resistors 22H and 22L are R1, and the resistance values of the resistors 24H and 24L are R2. .
＜動作＞
このように構成されたドライバ回路２０では、トランジスタ２６Ｈ，２６Ｌがオフ状態である場合、ＣＡＮＨ端子１３１（ひいてはＣＡＮＨ３ａ）の電圧ＶＨ及びＣＡＮＬ端子１３２（ひいてはＣＡＮＬ３ｂ）の電圧ＶＬは、いずれも中立電圧Ｖｃとなる。その結果、伝送線路３上の差動信号はレセッシブとなる。一方、トランジスタ２６Ｈ，２６Ｌがオン状態の場合、抵抗器２２Ｈ，２４Ｈ、及び抵抗器２２Ｌ，２４Ｌがそれぞれ分圧回路として動作することにより、ＣＡＮＨ端子１３１の電圧ＶＨは（１）式で表され、ＣＡＮＨ端子１３１の電圧ＶＬは（２）式で表される。その結果、伝送線路３上の差動信号はドミナントとなる。
<Operation>
In the driver circuit 20 configured as described above, when the transistors 26H and 26L are in the OFF state, the voltage VH of the CANH terminal 131 (and hence CANH3a) and the voltage VL of the CANL terminal 132 (and thus CANL3b) are both neutral voltages Vc. It becomes. As a result, the differential signal on the transmission line 3 becomes recessive. On the other hand, when the transistors 26H and 26L are in the on state, the resistors 22H and 24H and the resistors 22L and 24L operate as voltage dividing circuits, respectively, so that the voltage VH of the CANH terminal 131 is expressed by Equation (1). The voltage VL of the CANH terminal 131 is expressed by equation (2). As a result, the differential signal on the transmission line 3 becomes dominant.
ＶＨ＝Ｖｃ＋（ＶDD−Ｖon−Ｖf−Ｖｃ）×Ｒ１／（Ｒ１＋Ｒ２） （１）
ＶＬ＝Ｖｃ−（Ｖｃ−Ｖon−Ｖf−ＶＧ）×Ｒ１／（Ｒ１＋Ｒ２） （２）
なお、Ｖｃ＝ＶDD／２，ＶＧ＝０とするか、Ｖｃ＝０，ＶＧ＝−ＶDDとすれば、（１）（２）式の右辺第２項の絶対値はいずれも同じ大きさとなる。
VH = Vc + (VDD-Von-Vf-Vc) * R1 / (R1 + R2) (1)
VL = Vc− (Vc−Von−Vf−VG) × R1 / (R1 + R2) (2)
If Vc = VDD / 2, VG = 0, or Vc = 0, VG = −VDD, the absolute values of the second terms on the right side of equations (1) and (2) all have the same magnitude.
次に、伝送線路３上の信号に波形歪が生じた場合を考える。図３に示すように、この波形歪によって、ＣＡＮＨ３ａの電圧が、高位側しきい値電圧Ｖth_H（＝Ｖｃ−Ｖｆ）を越えて小さくなると、ダイオード２３Ｈが導通するため、ＣＡＮＨ３ａ上の信号波形（図中の実線を参照）は、Ｖth_Hを下限とする形状にクランプされる。同様に、ＣＡＮＬ３ｂの電圧が、低位側しきい値電圧Ｖth_L（＝Ｖｃ＋Ｖｆ）を越えて大きくなると、ダイオード２３Ｌが導通するため、ＣＡＮＬ３ｂ上の信号波形（図中の一点鎖線を参照）は、Ｖth_Lを上限とする形状にクランプされる。つまり、図３において、斜線で示した部分が、ダイオード２３Ｈ，２３Ｌによってカットされる歪みである。特に、差動信号がドミナントからレセッシブに変化した直後に現れる最大の歪を抑制することにより、その後に続く波形歪を速やかに収束させることができる。 Next, consider a case where waveform distortion occurs in the signal on the transmission line 3. As shown in FIG. 3, when the voltage of the CANH 3a becomes smaller than the high threshold voltage Vth_H (= Vc−Vf) due to this waveform distortion, the diode 23H becomes conductive, and therefore the signal waveform on the CANH 3a (see FIG. 3). Is clamped in a shape with Vth_H as the lower limit. Similarly, when the voltage of the CANL 3b becomes larger than the lower threshold voltage Vth_L (= Vc + Vf), the diode 23L becomes conductive, so that the signal waveform on the CANL 3b (see the one-dot chain line in the figure) Clamped to the upper limit shape. That is, in FIG. 3, the hatched portions are distortions cut by the diodes 23H and 23L. In particular, by suppressing the maximum distortion that appears immediately after the differential signal changes from dominant to recessive, the subsequent waveform distortion can be quickly converged.
＜効果＞
以上、説明したように、通信システム１によれば、ドライバ回路２０に設けたダイオード２３Ｈ，２３Ｌによって、伝送線路３に生じた波形歪の振幅を抑制することができる。
<Effect>
As described above, according to the communication system 1, the amplitude of the waveform distortion generated in the transmission line 3 can be suppressed by the diodes 23 </ b> H and 23 </ b> L provided in the driver circuit 20.
しかも、ダイオード２３Ｈ、２３Ｌは、波形歪のない信号に対しては機能しないため、通常の差動信号の伝送に悪影響を及ぼすことなく波形歪の抑制を実現することができる。
波形歪を抑制する効果は、図４に示すシミュレーション結果からも明らかである。なお、図４において、細線がダイオード２３Ｈ，２３Ｌがない場合、太線がダイオード２３Ｈ，２３Ｌがある場合を示す。
In addition, since the diodes 23H and 23L do not function for signals without waveform distortion, it is possible to achieve suppression of waveform distortion without adversely affecting normal differential signal transmission.
The effect of suppressing waveform distortion is also apparent from the simulation results shown in FIG. In FIG. 4, the thin line indicates that the diodes 23H and 23L are not present, and the thick line indicates the case where the diodes 23H and 23L are present.
＜他の実施形態＞
以上、本発明の一実施形態について説明したが、本発明は上記実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において、様々な態様にて実施することが可能である。
<Other embodiments>
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects.
例えば、上記実施形態では、抵抗器２２Ｈ，２２Ｌと並列に、ダイオード２３Ｈ，２３Ｌをそれぞれ設けたが、図５（ａ）に示すように、ダイオード２３Ｈ，２３Ｌに、それぞれコンデンサ２８Ｈ，２８Ｌを直列接続したものを設けてもよい。 For example, in the above embodiment, the diodes 23H and 23L are provided in parallel with the resistors 22H and 22L, respectively, but as shown in FIG. 5A, capacitors 28H and 28L are connected in series to the diodes 23H and 23L, respectively. You may provide what you did.
この場合、直流成分はカットされ交流成分（波形歪成分）のみが通過することになるため、ＣＡＮＨ３ａに地絡等の故障が発生した時に、ダイオード２３Ｈ，２３Ｌが接続された経路を介して、ＣＡＮＬ３ｂからＣＡＮＨ３ａに大きな故障電流が流れ込むことを防止することができ、通信システム１の安全性を向上させることができる。 In this case, since the direct current component is cut and only the alternating current component (waveform distortion component) passes, when a fault such as a ground fault occurs in the CANH 3a, the CANL 3b is connected via a path to which the diodes 23H and 23L are connected. Therefore, it is possible to prevent a large fault current from flowing into the CANH 3a, and the safety of the communication system 1 can be improved.
また、図５（ｂ）に示すように、コンデンサ２８Ｈ，２８Ｌの代わりにスイッチ２９Ｈ，２９Ｌを設け、適宜スイッチ２９Ｈ，２９Ｌをオンすることで波形歪を抑制したい期間だけダイオード２３Ｈ，２３Ｌを機能させるように構成してもよい。 Further, as shown in FIG. 5B, switches 29H and 29L are provided instead of the capacitors 28H and 28L, and the diodes 23H and 23L are caused to function only during a period in which waveform distortion is desired to be suppressed by appropriately turning on the switches 29H and 29L. You may comprise as follows.
１…通信システム ３…伝送線路 ３ａ…ＣＡＮＨ ３ｂ…ＣＡＮＬ ５…終端抵抗 １０（１０ａ〜１０ｃ）…電子制御ユニット １１…マイクロコンピュータ １２…ＣＡＮコントローラ １３…トランシーバ ２０…ドライバ回路 ２１…中立電圧発生回路 ２２Ｈ，２２Ｌ，２４Ｈ，２４Ｌ…抵抗器 ２３Ｈ，２３Ｌ，２５Ｈ，２５Ｌ…ダイオード ２６Ｈ，２６Ｌ…トランジスタ ２７…レベル変換回路 ２８Ｈ，２８Ｌ…コンデンサ ２９Ｈ，２９Ｌ…スイッチ ３０…レシーバ回路 １３１…ＣＡＮＨ端子 １３２…ＣＡＮＬ端子 １３３…ＴＸ端子 １３４…ＲＸ端子 ＬＮ…伝送線路 DESCRIPTION OF SYMBOLS 1 ... Communication system 3 ... Transmission line 3a ... CANH 3b ... CANL 5 ... Termination resistor 10 (10a-10c) ... Electronic control unit 11 ... Microcomputer 12 ... CAN controller 13 ... Transceiver 20 ... Driver circuit 21 ... Neutral voltage generation circuit 22H , 22L, 24H, 24L ... resistors 23H, 23L, 25H, 25L ... diodes 26H, 26L ... transistors 27 ... level conversion circuit 28H, 28L ... capacitors 29H, 29L ... switch 30 ... receiver circuit 131 ... CANH terminal 132 ... CANL terminal 133 ... TX terminal 134 ... RX terminal LN ... Transmission line
Claims (2)
予め設定され中立電圧を発生させる中立電圧発生回路（２１）と、
前記中立電圧発生回路の出力端と前記第１の信号線を接続する高電位側端子（１３１）との間に接続される第１抵抗器（２２Ｈ）と、
前記中立電圧発生回路の出力端と前記第２の信号線を接続する低電位側端子（１３２）との間に接続される第２抵抗器（２２Ｌ）と、
前記高電位側端子を分圧電圧の出力端とする第１分圧回路（２２Ｈ，２４Ｈ）を前記第１抵抗器と共に構成する第３抵抗器（２４Ｈ）と、
前記低電位側端子を分圧電圧の出力端とする第２分圧回路（２２Ｌ，２４Ｌ）を前記第２抵抗器と共に構成する第４抵抗器（２４Ｌ）と、
前記２値信号が一方の信号レベルの時に、前記第３抵抗器及び前記第４抵抗器の前記分圧電圧の出力端とは反対側端である給電端を開放状態とし、前記２値信号が他方の信号レベルの時に、前記第３抵抗器の給電端に前記中立電圧より高い高電位側基準電圧を印加し且つ前記第４抵抗器の給電端に前記中立電圧より低い低電位側基準電圧を印加する動作制御部（２５Ｈ，２５Ｌ，２６Ｈ，２６Ｌ，２７）と、
前記第１抵抗器と並列かつ前記中立電圧発生回路の出力端から前記高電位側端子に向かう方向が順方向となるように接続された第１ダイオード（２３Ｈ）と、
前記第２抵抗器と並列かつ前記低電位側端子から前記中立電圧発生回路の出力端に向かう方向が順方向となるように接続された第２ダイオード（２３Ｌ）と、
を備えることを特徴とするドライバ回路。 A driver circuit (20) connected to a transmission line (3) comprising a first signal line (3a) and a second signal line (3b), which converts a binary signal into a differential signal and outputs it to the transmission line. Because
A neutral voltage generation circuit (21) configured to generate a neutral voltage set in advance;
A first resistor (22H) connected between an output terminal of the neutral voltage generation circuit and a high potential side terminal (131) connecting the first signal line;
A second resistor (22L) connected between an output terminal of the neutral voltage generation circuit and a low potential side terminal (132) connecting the second signal line;
A third resistor (24H) that constitutes a first voltage divider circuit (22H, 24H) with the first resistor having the high potential side terminal as an output terminal of a divided voltage;
A fourth resistor (24L) that configures a second voltage dividing circuit (22L, 24L) with the second resistor using the low potential side terminal as an output terminal of a divided voltage;
When the binary signal is at one signal level, the feeding end, which is the end opposite to the divided voltage output end of the third resistor and the fourth resistor, is opened, and the binary signal is At the other signal level, a high potential side reference voltage higher than the neutral voltage is applied to the power supply end of the third resistor, and a low potential side reference voltage lower than the neutral voltage is applied to the power supply end of the fourth resistor. An application control unit (25H, 25L, 26H, 26L, 27) to be applied;
A first diode (23H) connected in parallel with the first resistor and connected in a forward direction from the output terminal of the neutral voltage generation circuit to the high potential side terminal;
A second diode (23L) connected in parallel with the second resistor so that the direction from the low potential side terminal toward the output terminal of the neutral voltage generating circuit is a forward direction;
A driver circuit comprising:
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