JPH11122089A - Output drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the jump-backs of undershoot so as not to exceed a logical amplitude in the state of keeping drive ability high and to improve degrees of freedom on designing. SOLUTION: This circuit is provided with a P-channel type transistor 1 and an N-channel type transistor 2, respective gates of which are connected to an input terminal 5 and respective drains are connected to an output terminal 6. Diodes 3 and 4 are connected between the drains of the P-channel type transistor 1 and the N-channel type transistor 2 as high resistance elements for suppressing the flow of a current to the P-channel type transistor 1 and the N-channel type transistor 2, in the case that a voltage which exceeds logical amplitude is supplied to the output terminal 6 and the connection part (connection point 7) of the diodes 3 and 4 is connected to the output terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output drive circuit, and more particularly, to an output drive circuit for avoiding a delay or malfunction caused by reflection of a signal flowing on a line between ICs.

In recent years, the operating speed of electronic devices such as personal computers has been increasing year by year. In this case, the speed of the IC itself mounted on the electronic device is increased. For that purpose, it is important to realize high-speed signal transmission between ICs. However, on the transmission line between the ICs, signal disturbance due to signal reflection has occurred with the increase in speed. For these reasons, there is a demand for a technique for transmitting a signal at a high speed by reducing waveform disturbance due to the signal disturbance.

[0003]

2. Description of the Related Art Conventionally, in an output drive circuit of an IC,
It has been common practice to increase the driving capability for speeding up and to speed up signal transmission between ICs while securing a fast rise time.

When the rise time of a signal is shortened, an IC
The wiring between them acts as a distributed constant line, and a signal may be reflected at the transmitting end / receiving end to cause extra delay or malfunction. For example, if the driving capability is 24 mA and the rise time of the signal is 1 ns, it is necessary to regard a wiring exceeding 7 cm as a distributed constant line.

Therefore, as a means for preventing the influence of reflection while keeping the rise time of the signal at a high speed, the transmitting end or the receiving end, or both the transmitting end and the receiving end are matched with the characteristic impedance of the wiring and terminated. The method (matching termination) is fundamental. However, since this matching termination causes an increase in the number of components and an increase in power consumption, it has not been used for any other purpose.

As a means other than the matching termination method, there is a method of terminating (clamping) the receiving end of a signal with a diode (diode clamp). Referring to FIGS. 7 and 8, a CMOS (Complementary) is an example of an output drive circuit to which the diode clamp is applied.
Metal Oxide Semiconductor
r) The circuit will be described. FIG. 7 is a graph showing output static characteristics of a CMOS circuit, FIG. 8 is a circuit diagram showing an output equivalent circuit of a CMOS circuit, and FIG. 9 is a CMO of FIG.
It is sectional drawing of an S circuit.

In a CMOS circuit as an output driving circuit, as shown in FIG. 7, static current output characteristics can be represented by plotting current (I) on the vertical axis and voltage (V) on the horizontal axis. . Reference numeral 61 denotes a high-side curve which is a high-side output static characteristic, and reference numeral 62 denotes a low-side curve which is a low-side output static characteristic. These high side curves 6
1, the low-side curve 62 shows the characteristic that the voltage increases as the current flows. In particular, even when the output voltage exceeds the logical amplitude, the current easily flows.

FIG. 8 shows an equivalent circuit of a CMOS circuit having the above output static characteristics. The CMOS circuit shown in FIG. 8 has a P-channel diode 31 in which a source terminal and a substrate electrode terminal are connected to a power supply terminal VDD and a gate terminal is connected to an input terminal 35, and a drain terminal of the P-channel diode 31 is connected to the P-channel diode 31. An N-channel diode 32 having its own drain terminal connected, its gate terminal connected to the input terminal 35, and a ground potential applied to the substrate electrode.

Further, in this CMOS circuit, an output terminal a is connected to a connection line between the drain terminal of the P-channel diode 31 and the drain terminal of the N-channel diode 32. A series circuit composed of diodes 33 and 34 as clamp elements is connected to the line of the output terminal a. In the diode 33, the cathode is connected to the same or different power supply terminal as the power supply for driving the internal logic circuit, and the anode is connected to the line of the output terminal a. In the diode 34, the anode is grounded,
The cathode is connected to the line of the output terminal a.

In the CMOS circuit shown in FIG. 8, the pulse waveform at the input terminal 35 is amplified and inverted by a series circuit including a P-channel diode 31 and an N-channel diode 32, and the pulse waveform at the output terminal a is changed. can get. At this time, even if a reflected wave is generated from the output terminal 36 side, a generated voltage exceeding a certain level is clipped by the series circuit of the diodes 33 and 34 arranged at the farthest end, so that delay or malfunction due to signal reflection is avoided. can do.

[0011]

The reflection waveform of the CMOS circuit shown in FIG.
The waveform analysis on the line can be performed using the ergeron projection. Hereinafter, the waveform analysis will be described with reference to FIG. FIG. 9 is a graph showing input / output characteristics when a line is driven by a CMOS circuit. here,
With the Berschelon projection, in order to grasp the response characteristics of the signal on the transmission line given the characteristic impedance,
It focuses on changes in current and voltage at a specific location on the line.

FIG. 9A shows the high side of FIG.
The output static characteristics 61 and 62 on the low side show the output characteristics on the near end (sending end) side and the input characteristics on the far end (receiving end) side, which are the driving sides. This graph takes the current on the vertical axis,
Take the voltage on the horizontal axis. FIG. 3B shows an output waveform on the near end side and an input waveform on the far end side. In this graph, voltage is plotted on the vertical axis, and time is plotted on the horizontal axis.

FIG. 9 shows a procedure for obtaining an output waveform from high to low, but the same applies to the output waveform from low to high. In FIG. 9A, point A indicates a high-side stable point (for example, 3.3 V as Vdd). On the first high-to-low transition, the high side A
A straight line of -1 / Z0 is drawn from the point toward the low side, and the intersection of the straight line and the low side curve 62 is defined as point B. here,
Z0 indicates the characteristic impedance of the line. This point B is the first pulse at the near end. Further, this time, a straight line of 1 / Z0 is drawn from point B, and the intersection of the straight line and the horizontal axis is set as point C. This point C is the first pulse at the far end.

Subsequently, a straight line of -1 / Z0 is drawn again from the point C, and the intersection of the straight line and the low-side curve 62 is defined as a point D. This point D is the second pulse at the near end. Further, a straight line of 1 / Z0 is drawn from this point D, and the intersection of the straight line and the horizontal axis is set as point E. This point E is the second pulse at the far end.

Similarly, a straight line of -1 / Z0 is drawn again from the point E, and the intersection of the straight line and the low-side curve 62 is defined as a point F. This point F is the third pulse at the near end. Further, a straight line of 1 / Z0 is drawn from the point F, and an intersection of the straight line and the horizontal axis is set as a point G. This point G is the third pulse at the far end.

FIG. 9B shows the change in FIG. 9A divided into a near-end output waveform and a far-end input waveform.
become that way. That is, the output waveform 91 on the near end changes so as to sequentially take points A, B, D, and F in accordance with the change in FIG. On the other hand, the far-end input waveform 9
2 changes so that points A, C, E, and G are sequentially taken.
Thus, the output waveform 91 and the input waveform 92 form a ringing waveform.

With respect to the input waveform 92 on the far end side, it does not matter much that the voltage drops negatively, but the problem is that the rebound of the undershoot increases and shifts to positive. The output characteristic shown in FIG. 9A has a low resistance characteristic in which a current easily flows even when the voltage is a negative potential. For this reason, when looking at the input waveform 92 on the far end side in FIG. 9B, a large rebound of undershoot from the negative side to the positive side appears when moving from the point C to the point E. This bounce is at a voltage level exceeding the low-to-high threshold value of the next stage input.

As described above, in a conventional output driving circuit such as the above-described CMOS circuit, the higher the driving capability, the lower the rebound of undershoot is the threshold value (about half of the power supply voltage (for example, 1.5 V)). ), The undershoot is prevented from bouncing, so that the driving capability should be reduced or the rise time should be delayed. However, if the driving capability is reduced, the rise of the signal itself is delayed due to the rounding of the waveform due to the concentrated capacitance, and if the rise time of the signal is delayed, the delay or malfunction due to reflection does not occur. There was a problem that a delay was caused by itself.

Further, in the output drive circuit to which the diode clamp is applied, it is necessary to incorporate an antireflection structure on the load side. Therefore, when the load is such as a memory module, the farthest end is arranged inside the memory module, so that it is often impossible to add a diode inside the memory module. Therefore, in the case of a diode clamp, it may be difficult to incorporate an anti-reflection structure depending on the load, and thus there is a problem that the degree of freedom in design is low.

The present invention solves the above-mentioned problems of the prior art, and therefore, it is possible to prevent the undershoot from rebounding while maintaining a high driving capability, and to improve the design freedom. It is intended to provide a circuit.

[0021]

Means for Solving the Problems The above-mentioned problems are solved,
To achieve the above object, an output driving circuit according to the present invention includes a P-channel transistor and an N-channel transistor each having a gate connected to an input terminal and a drain connected to an output terminal. An output drive circuit, comprising a high-resistance element formed of a series circuit in which at least two diodes are connected in series in the same direction, between the drains of the P-channel transistor and the N-channel transistor. A resistor element is connected to the output terminal.

According to the first aspect of the present invention, the high resistance element having the output terminal connected between the drains of the P-channel transistor and the N-channel transistor is provided.
Even if the output voltage becomes negative due to the reflected signal from the receiving end of the transmission line, the current flow is suppressed, and it is not necessary to provide an anti-reflection structure on the load side like a diode clamp. While the logic amplitude is kept high, the undershoot can be prevented from rebounding, and the degree of freedom in design can be improved.

According to a second aspect of the present invention, in the output driving circuit according to the first aspect of the present invention, the series circuit connects a connection portion of the at least two diodes to the output terminal.

In the first aspect of the present invention, at least the connection portion of the diode may be connected to the output terminal as in the second aspect of the present invention. In this case, opposite-phase reflection in the P-channel transistor and the N-channel transistor is prevented by the corresponding diodes.

According to a third aspect of the present invention, in the output drive circuit according to the second aspect, the series circuit connects an anode forming one end to a drain of the P-channel transistor and forms the other end. A cathode connected to the drain of the N-channel transistor.

According to a second aspect of the present invention, the anode forming one end of the series circuit is connected to the drain of a P-channel transistor, and the cathode forming the other end is connected to an N-channel transistor. Should be connected to the drain.

According to a fourth aspect of the present invention, in the output driving circuit according to the first aspect, a series circuit in which at least two resistors are connected in series is connected in parallel to the series circuit of the at least two diodes. It is characterized by having made it.

According to a first aspect of the present invention, as in the fourth aspect, a series circuit in which at least two resistors are connected in series may be connected in parallel to a series circuit of at least two diodes.

According to a fifth aspect of the present invention, in the output driving circuit according to the fourth aspect of the present invention, a connection portion of the at least two diodes and a connection portion of the at least two resistors are connected to the output terminal. It is characterized by.

According to a fourth aspect of the present invention, as in the fifth aspect of the present invention, a connection portion of at least two diodes and a connection portion of at least two resistors may be connected to an output terminal. In this case, the reverse-phase reflection to the P-channel transistor and the N-channel transistor is prevented by the corresponding diode and resistor pair.

According to a sixth aspect of the present invention, in the output drive circuit according to the fourth or fifth aspect, the series circuit of the diode includes an anode forming one end connected to a drain of the P-channel transistor, and the other end connected to the other end. Is connected to the drain of the N-channel transistor.

[0032] The invention of claim 4 or 5 provides the invention according to claim 6.
As in the invention, the anode forming one end of the series circuit of the diodes may be connected to the drain of the P-channel transistor, and the cathode forming the other end may be connected to the drain of the N-channel transistor.

According to a seventh aspect of the present invention, in the output driving circuit, a first P-channel transistor having a gate connected to the input terminal and a drain connected to the output terminal, and a first N-channel transistor. An output drive circuit comprising a channel-type transistor, wherein a high-resistance element composed of a series circuit of a second P-channel transistor and a second N-channel transistor is connected to the first P-channel transistor and the second P-channel transistor. It is characterized in that it is connected between the drains of one N-channel transistor.

According to the seventh aspect of the present invention, the second P-channel transistor and the second N-channel transistor each having an output terminal connected between the drains of the first P-channel transistor and the first N-channel transistor. A high-resistance element consisting of a series circuit with a type transistor is provided, so that even if the output voltage becomes negative due to a reflected signal from the receiving end of the transmission line, the current flow is suppressed, and the load side, like a diode clamp, Eliminates the need for anti-reflection
Thereby, it is possible to prevent the undershoot from rebounding so as not to exceed the logic amplitude while keeping the driving capability high, and to improve the degree of freedom in design.

According to an eighth aspect of the present invention, in the output drive circuit according to the seventh aspect of the present invention, the series circuit includes a connection portion between the second P-channel transistor and the second N-channel transistor. Is connected to the output terminal.

According to a seventh aspect of the present invention, a connection portion between the second P-channel transistor and the second N-channel transistor may be connected to the output terminal. In this case, a P-channel transistor,
N-channel type transistor for high resistance, N-type transistor for high resistance
It is prevented by the channel type transistor.

According to a ninth aspect of the present invention, in the output drive circuit according to the seventh or eighth aspect, the second P-channel transistor has a source connected to a drain of the first P-channel transistor. And the gate and the drain are commonly connected to the output terminal, and the second N-channel transistor has a source connected to the first terminal.
And the gate and the drain are commonly connected to the output terminal.

According to the invention of claim 7 or 8,
As in the invention, the source of the second P-channel transistor is connected to the drain of the first P-channel transistor, and the gate and the drain are commonly connected to the output terminal. The source may be connected to the drain of the first N-channel transistor, and the gate and drain may be commonly connected to the output terminal.

According to a tenth aspect of the present invention, in the output driving circuit according to the seventh, eighth or ninth aspect, the high-resistance element further includes a series circuit of at least two resistors in parallel with the series circuit. Characterized by being connected to.

According to a seventh, eighth, or ninth aspect of the present invention, as in the tenth aspect of the present invention, the high-resistance element is connected to a series circuit and a series circuit of at least two resistors is connected in parallel. Is also good.

According to an eleventh aspect of the present invention, in the output driving circuit according to the tenth aspect, a connection portion of the at least two resistors is connected to the output terminal.

According to a tenth aspect, as in the eleventh aspect, a connection portion of at least two resistors may be connected to the output terminal.

According to a twelfth aspect of the present invention, in the output driving circuit according to any one of the first to sixth aspects, the resistance value of the high-resistance element and the output of the P-channel transistor and the N-channel transistor are different. The resistance value of the high resistance element is set such that the sum of the resistance and the resistance becomes equal to the characteristic impedance of the line to be driven.

According to the twelfth aspect, the sum of the resistance value of the high resistance element and the output resistance of the P-channel transistor and the N-channel transistor is set to be equal to the characteristic impedance of the line to be driven. Since the resistance value of the resistive element is set, the driving output can be set to a high driving capability, that is, low impedance during driving, and can be set to a low driving capability, that is, high impedance when driving is completed.

An output drive circuit according to a thirteenth aspect of the present invention is the output drive circuit according to any one of the seventh to eleventh aspects,
The resistance value of the high-resistance element is set such that the sum of the resistance value of the high-resistance element and the output resistance of the P-channel transistor or the N-channel transistor becomes equal to the characteristic impedance of the line to be driven. Features.

According to the thirteenth aspect of the present invention, the resistance of the high-resistance element and the output resistance of the P-channel transistor or the N-channel transistor are set so as to be equal to the characteristic impedance of the line to be driven. Since the resistance value of the resistive element is set, the driving output can be set to a high driving capability, that is, low impedance during driving, and can be set to a low driving capability, that is, high impedance when driving is completed.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an output drive circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing an output drive circuit according to Embodiment 1 of the present invention. The CMOS circuit shown in FIG. 1 has a P-channel transistor 1 in which a source terminal and a substrate electrode terminal are connected to a power supply terminal VDD, and a gate terminal is connected to an input terminal 5, and a drain terminal of the P-channel transistor 1 An N-channel transistor 2 having its own drain terminal connected, its gate terminal connected to the input terminal 5, and a ground potential applied to the substrate electrode.

Further, in this CMOS circuit, at least two diodes 3 and 4 as high resistance elements are connected in series in the same direction between the drain terminal of the P-channel transistor 1 and the drain terminal of the N-channel transistor 2. Let me. That is, the two diodes 3, 4
The cathode of the diode 3 is connected to the anode of the diode 4 to form a series circuit. In the series circuit including the two diodes 3 and 4, a connection portion (connection point 7) of the diodes 3 and 4 is connected to the output terminal 6.

In this series circuit, the anode of the diode 3 forming one end is connected to the drain of the P-channel transistor 1, and the cathode of the diode 4 forming the other end is connected to the drain of the N-channel transistor 2. Let me.

According to the above configuration, when, for example, a negative voltage is applied to the output terminal 6 at the time of driving, the current flows to the P-channel transistor 1 which is in the ON state by the high resistance element. The diodes 3 and 4 will work to suppress.

Next, the CMOS described above with reference to FIG.
The antireflection function of the circuit will be described. FIG. 2 shows C in FIG.
FIG. 4 is a graph showing input / output characteristics when a line is driven by a MOS circuit. Also in this case, the Bell Cheron projection described in the conventional example is used.

Normally, when the driving capability of the output drive circuit is high, the reflected waveform from the far end (receiving end) is reflected again in reverse phase at the near end (transmitting end) and rebounds at the far end. Because of the waveform, a malfunction or delay occurs. Therefore, in the first embodiment, attention is paid to preventing the reverse-phase reflection at the near end. In the first place, the reverse-phase reflection occurs when the impedance at the near end is much smaller than the characteristic impedance of the transmission line.

For example, with a driving capability of 24 mA, the output impedance is about 10Ω. Therefore, assuming that the output impedance during driving is r and the characteristic impedance of the line is Z0, in the case of a general line of Z0 = 70Ω,
The reflection coefficient at the near end is (r−ZO) / (r + Z0)
= (10−70) / (10 + 70) = − 0.75. Therefore, 75% of the incident waveform is reflected with the opposite polarity. On the other hand, with a driving capability of 4 mA, the output impedance is about 50Ω. Therefore, in the case of a general Z0 = 70Ω line, the reflection coefficient at the near end is (r−ZO) / (r + Z0) = (50−70) /
(50 + 70) = − 0.17.

Therefore, at the time of driving, the resistance value of the diodes 3 and 4 may be determined so that the driving output becomes high driving capability, that is, low impedance, and when driving is completed, the driving output becomes low driving capability, that is, high impedance.

Therefore, of the output characteristics of the CMOS circuit shown in FIG.
At the high level, the current flows from the CMOS circuit at the high level.
For this reason, the portions other than the portion contributing to the drive in the CMOS circuit, that is, the diodes 3 and 4 should have reduced drive capability, or ideally the output characteristics should be equal to the line impedance.

According to the above principle, the CMO shown in FIG.
The S circuit has the input / output characteristics shown in FIG. FIG. 2 (a),
FIGS. 10 (a) and 10 (b) show a conventional example, respectively.
Similar to the characteristic of (b), the characteristic by the high side curve 21 and the low side curve 22 according to the first embodiment is shown.

Conventionally, as shown in FIGS. 10A and 10B, after a point A and a point B, an undershoot to a point C causes a rebound to a point E exceeding a threshold voltage as a rebound. There was a transition. Therefore, the low side curve 22
When the impedance exceeds the logic amplitude in a low impedance state, the impedance becomes high and becomes infinite, and thereafter, a leak current flows and approaches the original logic amplitude value. on the other hand,
The high-side curve 21 is also symmetric with the low-side curve 22, but has a high impedance when it exceeds the logic amplitude in a low impedance state. The impedance of the high-side curve 21 has a polarity opposite to that of the low-side curve 22 and becomes infinite, and approaches the original logical amplitude value.

In this manner, after the undershoot from point B occurs, the undershoot does not rebound beyond the threshold voltage that causes point E. In FIG. 2B, the output waveform 23 on the near end side is
The points A, B, and D are taken in order, and the level is settled to the low level. On the other hand, the far-end input waveform 24
Is set to a low level by sequentially taking points A and C. That is, the diodes 3 and 4 function dominantly within the logic amplitude, and the diodes 3 and 4 outside the logic amplitude.
4 is cut off and the output impedance becomes infinite. The output waveform has a constant value outside the logical amplitude.

As described above, according to the first embodiment, the diodes 3 and 4 having the output terminal 6 connected between the drains of the P-channel transistor 1 and the N-channel transistor 2 are provided. Even if the output voltage becomes negative due to the reflection signal from the receiving end side, the flow of current is suppressed, and it is not necessary to provide an antireflection structure on the load side unlike a diode clamp. by this,
The undershoot can be prevented from rebounding so as not to exceed the logic amplitude while the driving capability is kept high, and the degree of freedom in design can be improved.

(Embodiment 2) In Embodiment 1 described above, the impedance is set to be high when the logic amplitude is exceeded. However, as in Embodiment 2 described below, the logic amplitude is set to high. Even if the impedance does not reach the high impedance as in the first embodiment after exceeding the above, it is better to perform the same function with a slightly lower impedance. In Embodiment 2 described below, FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 3 is a circuit diagram showing an output drive circuit according to Embodiment 2 of the present invention. In the CMOS circuit shown in FIG. 2, a built-in configuration of a P-channel transistor 1 and an N-channel transistor 2 is similar to that of FIG. This CMOS circuit includes a P-channel transistor 1
Between the drain terminal of the N-channel transistor 2 and the drain terminal of the N-channel transistor 2 and the series circuit composed of the two diodes 3 and 4 and the series circuit composed of at least two resistors 8 and 9 are connected in parallel. is there.

In the above-mentioned CMOS circuit, the connection portion of the diodes 3 and 4 (connection point 7) and the connection portion of the resistors 8 and 9 (connection point 10) are connected to the output terminal 6. Also,
As for the series circuit composed of the diodes 3 and 4, the anode of the diode 3 forming one end is connected to the drain of the P-channel transistor 1, and the diode 4 Is connected to the drain of the N-channel transistor 2.

According to the above configuration, when, for example, a negative voltage is applied to the output terminal 6 at the time of driving, the current flows to the P-channel transistor 1 and the N-channel transistor 2 by the high resistance element. The diodes 3 and 4 and the resistors 8 and 9 work to suppress.

Next, the CMOS described above with reference to FIG.
The antireflection function of the circuit will be described. FIG. 4 shows C in FIG.
FIG. 4 is a graph showing input / output characteristics when a line is driven by a MOS circuit. Also in this case, the Bell Cheron projection described in the conventional example is used. FIGS. 4A and 4B show the characteristics of the high-side curve 41 and the low-side curve 42 according to the second embodiment, respectively, similarly to the characteristics of FIGS. 2A and 2B.

In FIGS. 4A and 4B, when the vehicle reaches the point C due to the undershoot from the point B, the first embodiment is performed.
Is obtained by the diodes 3, 4 and the resistors 8, 9 a little lower than the high impedance at, so that the following points E and F are controlled so as not to exceed the threshold voltage. In addition, when it is outside the logic amplitude,
Since the diodes 3 and 4 are cut off, the resistors 8 and 9 are dominant, and the output impedance has a constant slope.

As described above, in the case of the CMOS circuit shown in FIG. 3, when the output impedance outside the logical amplitude is matched with the line impedance, only one undershoot occurs in the far-end input waveform 44, On the other hand, in the output waveform 43 at the near end, only an undershoot having half the amplitude at the far end occurs, but no large undershoot rebounds.

As described above, according to the second embodiment, a set of diodes 3 and 4 and resistors 8 and 9 having output terminals connected between the drains of P-channel transistor 1 and N-channel transistor 2 is used. With this arrangement, even if the output voltage exceeds the logical amplitude due to the reflected signal from the receiving end side of the transmission line, the flow of current is suppressed, and it is not necessary to provide an antireflection structure on the load side unlike a diode clamp. As a result, it is possible to prevent undershoot from rebounding so as not to exceed the threshold voltage while keeping the driving capability high, and to improve the degree of freedom in design.

(Embodiment 3) In Embodiments 1 and 2 described above, the high resistance element is constituted by the diodes 3 and 4 and the resistors 8 and 9. However, in Embodiment 3 described below, As described above, a P-channel transistor and an N-channel transistor may be added as high resistance elements. In the third embodiment described below, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 5 is a circuit diagram showing an output drive circuit according to Embodiment 3 of the present invention. In the CMOS circuit shown in FIG. 5, a high-resistance P-channel transistor 11 and a high-resistance N-channel transistor 12 are connected instead of the diodes 3 and 4 of the CMOS circuit of FIG.

Specifically, the source of the high-resistance P-channel transistor 11 is connected to the drain of the P-channel transistor 1 and the gate and the drain are connected to the output terminal 6 in common. on the other hand,
In the high-resistance N-channel transistor 12, the source is connected to the drain of the N-channel transistor 2, and the gate and the drain are commonly connected to the output terminal 6.

According to the above configuration, the input / output characteristics similar to those in FIG. 2 are exhibited, and the reflected signal from the far end side is supplied to each gate of the high-resistance P-channel transistor 11 and the high-resistance N-channel transistor 12. , The reflection of the driving of the P-channel transistor 1 and the N-channel transistor 2 can be suppressed.

As described above, the P-channel transistor 1
And high-resistance P-channel transistor 11 having an output terminal connected between the drains of N-channel transistor 2 and N-channel transistor 2
Even if the N-channel transistor 12 for high resistance is provided, even if the output voltage becomes negative due to the reflected signal from the receiving end side of the transmission line, the current flow is suppressed, and the current is reflected to the load side like a diode clamp. There is no need to provide a prevention configuration. As a result, it is possible to prevent undershoot from rebounding so as not to exceed the threshold voltage while keeping the driving capability high, and to improve the degree of freedom in design.

Further, the present invention relates to the third embodiment described above.
May be applied to a modification described below. FIG. 6 is a circuit diagram showing an output drive circuit according to a modification of the third embodiment. As in the modification shown in FIG. 6, resistors 8 and 9 may be connected in parallel to transistors 11 and 12, respectively. FIG. 4 shows the input / output characteristics in this case.
Are obtained.

As described above, the present invention is applied to the first to third embodiments.
However, various modifications are possible within the scope of the present invention, and these are not excluded from the scope of the present invention.

[0076]

As described above, according to the present invention, a high-resistance element having an output terminal connected between the drains of a P-channel transistor and an N-channel transistor is provided. Even if the output voltage exceeds the logic amplitude due to the reflected signal of, the current flow is suppressed,
In addition, it is not necessary to provide an anti-reflection structure on the load side unlike a diode clamp, which can prevent undershoot from rebounding so as not to exceed a logic amplitude while maintaining a high driving capability, and to prevent a design problem. An output driving circuit capable of improving the degree of freedom can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output drive circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing input / output characteristics when a line is driven by the CMOS circuit of FIG. 1;

FIG. 3 is a circuit diagram showing an output drive circuit according to a second embodiment of the present invention.

FIG. 4 is a graph showing input / output characteristics when a line is driven by the CMOS circuit of FIG. 3;

FIG. 5 is a circuit diagram showing an output drive circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing an output drive circuit according to a modification of the third embodiment of the present invention.

FIG. 7 is a graph showing static output characteristics of a CMOS circuit.

FIG. 8 is a circuit diagram showing a CMOS circuit according to a conventional example.

FIG. 9 is a graph showing input / output characteristics when a line is driven by the CMOS circuit of FIG. 8;

[Explanation of symbols]

Reference Signs List 1 P-channel transistor (first P-channel transistor) 2 N-channel transistor (first N-channel transistor) 3, 4 Diode 5 Input terminal 6 Output terminal 7, 10 Connection point 8, 9 Resistance 11 High resistance P-channel transistor for transistor (second P-channel transistor) 12 N-channel transistor for high resistance (second N-channel transistor)

[Procedure amendment]

[Submission date] June 4, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

As a means other than the matching termination method, there is a method of terminating (clamping) the receiving end of a signal with a diode (diode clamp). Referring to FIGS. 7 and 8, a CMOS (Complementary) is an example of an output drive circuit to which the diode clamp is applied.
Metal Oxide Semiconductor
r) The circuit will be described. FIG. 7 is a graph showing static output characteristics of the CMOS circuit, and FIG. 8 is a circuit diagram showing an output equivalent circuit of the CMOS circuit.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

The reflection waveform of the CMOS circuit shown in FIG.
The waveform analysis on the line can be performed using the ergeron projection. Referring to FIG. 9 will be described below for the waveform analysis. FIG. 9 is a graph showing input / output characteristics when a line is driven by a CMOS circuit. Here, the Bell Cheron projection focuses on changes in current and voltage at a specific location on a transmission line in order to reliably grasp the response characteristics of a signal on a transmission line given a characteristic impedance.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction contents]

For example, with a driving capability of 24 mA, the output impedance is about 10Ω. Therefore, assuming that the output impedance during driving is r and the characteristic impedance of the line is Z0, in the case of a general line of Z0 = 70Ω,
The reflection coefficient at the near end is (r−Z 0 ) / (r + Z 0)
= (10−70) / (10 + 70) = − 0.75. Therefore, 75% of the incident waveform is reflected with the opposite polarity. On the other hand, with a driving capability of 4 mA, the output impedance is about 50Ω. Therefore, in the case of a general Z0 = 70Ω line, the reflection coefficient at the near end is (r−Z 0 ) / (r + Z 0) = (50−70) /
(50 + 70) = − 0.17.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0057

[Correction method] Change

[Correction contents]

According to the above principle, the CMO shown in FIG.
The S circuit has the input / output characteristics shown in FIG. FIG. 2 (a),
To (b) is a view respectively according to the conventional example 9 (a), (b)
Similarly to the characteristics of the above, the characteristics by the high side curve 21 and the low side curve 22 according to the first embodiment are shown.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0058

[Correction method] Change

[Correction contents]

[0058] Conventionally, as shown in FIG. 9 (a) and (b), A point, after the point B, the undershoot of the point C, to point E exceeds the threshold voltage as a bounce There was a transition. Therefore, if the low-side curve 22 becomes high impedance and becomes infinite when the low-side curve 22 exceeds the logical amplitude in a low-impedance state, a leak current flows thereafter and the original logical amplitude value gradually approaches. On the other hand, the high-side curve 21 is also symmetric with respect to the low-side curve 22, but has a high impedance when it exceeds the logical amplitude in a low impedance state. The impedance of the high-side curve 21 has a polarity opposite to that of the low-side curve 22 and becomes infinite, and approaches the original logical amplitude value.

Claims (13)

[Claims] A gate connected to an input terminal;
What is claimed is: 1. An output drive circuit comprising a P-channel transistor and an N-channel transistor having respective drains connected to an output terminal, the high-resistance element comprising a series circuit in which at least two diodes are connected in series in the same direction. Is connected between the drains of the P-channel transistor and the N-channel transistor, and the high resistance element is connected to the output terminal. 2. The output drive circuit according to claim 1, wherein the series circuit connects a connection portion of the at least two diodes to the output terminal. 3. The series circuit according to claim 1, wherein an anode forming one end is connected to a drain of the P-channel transistor, and a cathode forming the other end is connected to a drain of the N-channel transistor. Item 2
4. The output drive circuit according to claim 1. 4. The output drive circuit according to claim 1, wherein a series circuit in which at least two resistors are connected in series is connected in parallel to the series circuit of the at least two diodes. 5. The output drive circuit according to claim 4, wherein a connection portion of said at least two diodes and a connection portion of said at least two resistors are connected to said output terminal. 6. The series circuit of the diode, wherein an anode forming one end is connected to a drain of the P-channel transistor, and a cathode forming the other end is connected to a drain of the N-channel transistor. The output drive circuit according to claim 4 or 5, wherein: 7. An output drive circuit comprising: a first P-channel transistor and a first N-channel transistor each having a gate connected to an input terminal and a drain connected to an output terminal. A high-resistance element composed of a series circuit of a second P-channel transistor and a second N-channel transistor is connected between the drains of the first P-channel transistor and the first N-channel transistor; An output drive circuit, characterized by: 8. The output according to claim 7, wherein the series circuit connects a connection portion between the second P-channel transistor and the second N-channel transistor to the output terminal. Drive circuit. 9. The second P-channel transistor has a source connected to the drain of the first P-channel transistor, a gate and a drain commonly connected to the output terminal, and the second N-channel transistor connected to the output terminal. 9. The output drive circuit according to claim 7, wherein the channel type transistor has a source connected to the drain of the first N-channel type transistor and a gate and a drain connected to the output terminal in common. . 10. The high resistance element is connected to the series circuit,
10. The output drive circuit according to claim 7, wherein a series circuit of at least two resistors is connected in parallel. 11. The output terminal according to claim 1, wherein a connection portion of the at least two resistors is connected to the output terminal.
The output drive circuit according to 0. 12. The resistance value of the high-resistance element such that the sum of the resistance value of the high-resistance element and the output resistance of the P-channel transistor and the N-channel transistor becomes equal to the characteristic impedance of the line to be driven. The output drive circuit according to claim 1, wherein 13. The driving circuit according to claim 1, wherein a sum of a resistance value of said high-resistance element and an output resistance of said first P-channel transistor or said first N-channel transistor is equal to a characteristic impedance of a line to be driven. 12. The output drive circuit according to claim 7, wherein a resistance value of the high resistance element is set.