JP5625769B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus. More specifically, the present invention relates to an image processing apparatus suitable for reducing power consumption.

  In image processing apparatuses such as printers, scanners, facsimile apparatuses, and digital multi-function peripherals, there is a great demand for power consumption reduction, and in particular, reduction in power consumption during standby without operation or job execution has been demanded. In order to reduce power consumption, image processing devices have been provided with a power-saving mode that stops the power supply of units that consume a large amount of current, such as engines, and reduced power consumption by shifting to this power-saving mode during standby. To be done.

  In the conventional power saving mode, power was supplied to the CPU of the control board that controls each part and its peripheral circuits. However, in recent years, the demand for reducing the power consumption in the power saving mode has become stronger. An image processing apparatus that reduces the power by shifting the power of the substrate CPU itself to the low power mode is already known.

  However, the image processing apparatus has a problem that it takes time to initialize the CPU of the control board to return from the low power mode. For this reason, in order to avoid frequent transition between the normal mode and the power saving mode, if the transition timer is not set relatively long, the waiting time due to the rise frequently occurs, which causes a problem in practicality.

  As a result, it is necessary to prohibit the CPU from shifting to the low power mode or to equip the image processing apparatus with a backup power source such as a battery, and the transition to the low power mode is not performed as expected. As a result, there has been a problem that the power saving effect as much as possible cannot be produced and the cost is increased.

  To deal with such a problem, for example, Patent Document 1 discloses an electronic device including two memories for storing data necessary for control in the normal mode for the purpose of returning from the power saving mode to the normal mode in a short time. An invention relating to an apparatus is disclosed. The electronic device described in Patent Document 1 includes a memory that stores data necessary for control in the normal mode and a memory that can be accessed at a higher speed than the memory and consumes less power. At least a part of necessary data is stored in the latter memory, and the latter data is used to return from the power saving mode. Patent Document 2 discloses a technique related to a memory control device that can use highly reliable information stored in a volatile memory when returning from the power saving mode.

  In the above-mentioned patent document, when returning from the power saving mode, a high-speed accessible memory is used to speed up the return to the normal mode. However, the power consumption in the power saving mode is sufficiently reduced. It was not possible to plan and there was room for further study.

  Accordingly, the present invention provides an image processing apparatus that can enhance the power saving effect and can quickly return from the power saving mode to the normal mode even when the transition between the normal mode and the power saving mode frequently occurs. With the goal.

In order to achieve this object, the image processing apparatus according to claim 1 supplies power to the main body operation unit when the operation is not performed for a certain period in the normal mode in which power is supplied to the main body operation unit and the control controller unit. In the image processing apparatus that shifts to the power saving mode in which power is supplied to the control controller unit, at least the predetermined information required for returning to the normal mode is copied to the nonvolatile memory Based on the information in the volatile memory when a recovery event for returning from the power saving mode to the normal mode occurs within a predetermined time. A first return means for returning to the normal mode; and if a return event does not occur within a predetermined time, Transition means for stopping power supply and shifting to the low power mode; and second return means for returning to the normal mode based on information in the nonvolatile memory when a return event occurs in the low power mode. In addition , a predetermined time can be varied by arbitrarily selecting a return event .

The invention according to claim 2, in the image processing apparatus according to claim 1, the use frequency storing means for storing the usage frequency of each function unit of the main body operation unit in time units, the switches of each functional unit Switching pattern storage means for storing a predetermined number of switching patterns, and selects a switching pattern based on the frequency of use.

According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect , the first capacitor capable of being rapidly charged with a small capacity, and the charging time with a larger capacity than the first capacitor. A second capacitor required, and copying of predetermined information from the volatile memory to the nonvolatile memory and shifting to the backup state of the volatile memory are performed based on power supply from the first capacitor. .

In addition, the image processing apparatus according to claim 4 stops the power supply to the main body operation unit when the operation is not performed for a certain period in the normal mode in which the power supply to the main body operation unit and the control controller unit is performed. In an image processing apparatus that shifts to a power saving mode in which power is supplied to the control controller unit, a copy unit that copies at least predetermined information required for returning to the normal mode among the information in the volatile memory to the nonvolatile memory, and volatile The backup means for backing up the memory for a predetermined time by the capacitor power supply, and when the return event for returning from the power saving mode to the normal mode occurs within the predetermined time, the normal mode is returned based on the information of the volatile memory. If a return event does not occur within a predetermined time with the first return means, power supply to the volatile memory is stopped to Transition means for shifting to the mode, second return means for returning to the normal mode based on information in the nonvolatile memory when a return event occurs in the low power mode, and use of each functional unit of the main body operation unit A usage frequency storage means for storing the frequency in units of time; and a switching pattern storage means for storing a predetermined number of switching patterns of the switches of each functional unit, selecting a switching pattern based on the usage frequency, and Means for comparing the time required for copying the predetermined information from the volatile memory to the non-volatile memory and the time until the next return event occurs until the time required for copying the predetermined information occurs until the return event occurs If the time is shorter than the predetermined time, the predetermined information is copied to the low power mode.

  According to the present invention, even when the transition between the normal mode and the power saving mode occurs frequently, the power saving effect can be enhanced and the power saving mode can be quickly returned to the normal mode.

It is a block block diagram of the image processing apparatus which concerns on this embodiment. It is a flowchart (1) which shows transfer to power saving mode and return processing to normal mode. It is a time chart which shows the operation | movement of the status of each MPU, and the power supply of a control controller. It is another example of the block block diagram of an image processing apparatus. (A) A list showing the observation results of usage records, and (B) a list showing an example of automatic setting of the switch according to the time zone. It is a flowchart (2) which shows transfer to power saving mode and return processing to normal mode. It is a flowchart (3) which shows transfer to power saving mode and return processing to normal mode.

  Hereinafter, a configuration according to the present invention will be described in detail based on the embodiment shown in FIGS.

  The image processing apparatus according to the present invention supplies power to the main body operation unit when the operation is not performed for a certain period in the normal mode in which power is supplied to the main body operation unit (engine control unit 1) and the control controller unit (2). In the image processing apparatus that switches to the power saving mode in which power is supplied to the control controller unit, at least predetermined information required for returning to the normal mode is stored in the nonvolatile memory (DRAM_M6b). Replicating means (S106 in FIG. 2) for copying to FROM_S5c), backup means (S107, etc.) for backing up the volatile memory by a capacitor power source for a predetermined time, and returning from the power saving mode to the normal mode within the predetermined time. When a recovery event occurs (S108: No, etc.), the normal mode is set based on the information in the volatile memory. If the return event does not occur within a predetermined time (S108: Yes, etc.), and the power supply to the volatile memory is stopped (S109, etc.) Transition means for shifting to the low power mode (S112, etc.), and a second return for returning to the normal mode based on information in the nonvolatile memory when a return event occurs in the low power mode (S118: Yes, etc.) Means (S124 to S125, etc.). The return event can be arbitrarily selected and set, and the predetermined time can be changed.

  As described above, in the image processing apparatus according to the present invention, the control board CPU also shifts to the low power mode during the shift to the power saving mode and the return process to the normal mode, and the information of the volatile memory is stored for a predetermined time. It is held by the power from the capacitor power supply, and if there is a factor to return to the normal mode, the CPU of the control board will return at high speed with the information of the volatile memory, and this predetermined time is adjusted by selecting the necessary function It is something that can be done. In addition, when it is necessary to return to the normal mode within the predetermined time, the volatile memory information is activated at high speed, and power is reduced during that time.

<First Embodiment>
(Configuration of image processing apparatus)
First, the configuration of the image processing apparatus according to the present embodiment will be described. FIG. 1 is a block diagram of an image processing apparatus according to this embodiment. The image processing apparatus includes an engine control unit 1, a control controller unit 2, a first power saving control unit 3a, a second power saving control unit 3b, a power cord 16a, a power switch (SW) 16b, and a power source unit 16c. The

  The DC voltage Ve generated by the power supply unit 16c is a voltage for the engine control unit 1, and the voltage Vm is a voltage for the control controller unit 2. It should be noted that even though the DC voltages Ve and Vm are actually generated, several voltages are actually generated, but here, they will be described in units. The voltage Vs is extremely high in energy efficiency, but the current is a voltage that can output only a small capacity. For example, Vm and Vc can supply a current of 5 A, whereas Vs can supply only a very low power of about 0.01 A.

  In the image processing apparatus, information exchange between the engine control unit 1, the control controller unit 2, and the first power saving control unit 3a is performed by serial communication. The COM_ME signal is used between the engine MPU 4a and the main MPU 4b, and the COM_MS signal is used between the main MPU 4b and the energy saving activation MPU 4c. Although details of the image path are omitted, it is only necessary that the engine MPU 4a and the main MPU 4b be connected by a Video bus (for example, a high-speed serial bus such as PCI Express). Also, a video bus may be provided in the engine MPU 4a and the main MPU 4b and connected via an arbiter.

  The engine control unit 1 includes various IO units of the image processing apparatus, which are controlled by the engine MPU 4a. FROM_E5a and DRAM_E6a are connected to the bus of engine MPU4a. Further, a scanner 8a and a scanner control unit 8b, a laser 9a and a laser control unit 9b, a plotter I / O 10a, and a plotter control unit 10b are provided. In addition, the plotter I / O 10a has a circuit that generates a high voltage to be used by using the AC power supply Vp from the power supply unit 16c. Further, an ADF (Auto Document Feeder) 11a, a motor / clutch 11b, and various sensors 11c for conveying an original or print paper are controlled and detected by an I / O control unit 11d.

  The control controller unit 2 is controlled by the main MPU 4b. To the bus (main MPU bus), FROM_M5b and an image processing control unit 7 for performing image processing are connected. In addition, a USBPHY 15 to which the operation unit 12, a line I / F 13a and a FAX modem 13b for analog FAX, a LAN I / F 14 for network, USB / D (device), and USB / H (host) are connected to the bus. Is connected.

  The main MPU bus of the control controller unit 2 is also connected to the first power saving control 3a, and is connected to a DRAM_M6b which is a main memory of the main MPU 4b via a multiplexer (MUX) 6c. Note that a multiplexer may be built in the main MPU 4b. In this case, the main MPU 4b may have a plurality of power supply systems.

  The first power saving control unit 3a is controlled by the energy saving activation MPU 4c. The energy saving activation MPU 4c includes a CPU, a DMA controller, a DRAM I / F, a FROM I / F, a parallel I / O, and the like.

  Moreover, FROM_S5c which is a non-volatile memory of a save destination is connected to the energy saving activation MPU 4c via a local bus. The voltage Vc is supplied including the multiplexer 6c. The supply voltage Vdr to the DRAM_M6b is generated from the voltage Vc by the memory voltage generation circuit 6d and can be turned ON / OFF by the DR_EN signal.

  The second power saving control unit 3b is a circuit that controls the voltage used for the transition from the voltage Vm of the control controller unit 2 to a power saving mode described later and the return processing to the normal mode. The voltage Vm is connected to the capacitor 17c and the SWs 18a and 18b via the rectifier diodes 17a and 17b. Further, when the voltage Vm connected to the voltage Vc through the rectifier diode 17d is valid, the voltage Vs is supplied and the voltage Vs is adjusted so that no current flows. Even when the voltage Vm is OFF and current is supplied from the capacitor 17c (the voltage Vc is valid), the voltage Vs is adjusted so as not to flow. For example, a slight potential difference may be provided for each voltage, and the voltage Vs may be the lowest in the sum of the forward voltage of the rectifier diode.

  Normally, the SWs 18a and 18b are closed, the capacitor 17c (capacitance C) is charged with the voltage Vm, and the voltage Vc of the first power saving control 3a is supplied from Vm. Further, in order to detect an event for returning from the power saving mode, the detection unit of the sensor 11c of the ADF is driven with a voltage Vu1 different from the voltage Ve. The key press detection of the operation unit 12 is driven by a voltage Vu2 different from the voltage Vm. Similarly, the call signal detection from the analog line is driven by the voltage Vu3, the packet detection from the network is driven by the voltage Vu4, and the USB port connection and packet detection are driven by the voltage Vu5. In addition, each event detection is input to the PIO of the energy saving activation MPU 4c as signals IVT_1 to 5 and recognized.

  The voltage values of the voltages Vm and Vc are detected by the first and second voltage detections 19a and 19b, and detection signals DET_Vm and Vc are output to the energy saving activation MPU 4c. It should be noted that more detailed control can be performed by using several voltage detection devices, but a 1-bit signal is shown for explanation.

  The signals SW_1 to 9 are port-controlled by the PIO of the energy saving activation MPU 4c. Output voltages Ve, Vm, and Vs of the power supply unit 16c are ON / OFF controlled by signals SW_1, 2, and 3, respectively. The SW 18b for turning on / off the voltage Vc of the capacitor 17c is controlled by a signal SW_4, and the SW group 18a for turning on / off the voltages Vu1-5 is controlled by signals_SW5-9.

(Operation of image processing device)
Next, the operation of the image processing apparatus will be described.

[Power up process]
First, the power-on process will be described. When the power cord 16a is connected to an outlet and the power SW 16b is turned on, a DC voltage is generated by the power supply unit 16c, and each unit is turned on. When the power becomes valid, the reset of the engine MPU 4a and the main MPU 4b is released, and an initialization process is performed.

  The engine control unit 1 and the control controller unit 2 are initialized from the MPU sequentially after the respective MPUs 4a and 4b are initialized, thereby starting up the entire image processing apparatus. Further, by the operation from the operation unit 12, the copy function, the scanner function, and the FAX transmission function operate using the ADF 11, the scanner 8a, the laser 9a, and the plotter I / O 10a. In addition, a print function can be used from a client PC via a network or USB. Further, FAX reception from the analog telephone network is printed out using a laser 9a, a plotter I / O 10a, or the like.

[Transition to power saving mode and return to normal mode]
In the power saving mode, the laser plotter or the like uses a large amount of electric power for residual heat, and thus the power source of the engine control unit 1 is turned off. For example, when there is no operation, no printing, no FAX reception, etc., after a certain time (for example, the power saving mode transition time set by the user from the operation unit 12) has passed, the mode is shifted to the power saving mode. Is. As a conventional device, there is a device that keeps the controller controller 2 powered on even in the power saving mode, or a device that is equipped with a dedicated microcomputer that consumes relatively little power and turns off other power sources in the controller 2. Widely known.

  FIG. 2 is a flowchart illustrating an example of a transition process to the power saving mode and a return process to the normal mode executed by the image processing apparatus according to the present embodiment. Hereinafter, the operation of the image processing apparatus according to the present embodiment will be described.

  First, the main MPU 4b has a timer for the transition time to the power saving mode. When this time has elapsed, the engine MPU 4a is notified of the transition to the power saving mode, and when the ACK is returned, the transition to the power saving mode is performed. Processing begins. This is sleep processing such as handshaking with the engine MPU 4a and post-processing such as processing for freezing each part of the controller 2 (start of FIG. 2).

  The energy saving activation MPU 4c receives a notification of transition from the main MPU 4b to the power saving mode through the COM_MS signal (S101). Further, the energy saving activation MPU 4c turns the SW1 of the power supply unit 16c from ON to OFF and turns off the voltage Ve (S102).

  Which of the power saving return events is to be enabled can be set in advance by the device manager or the like from the operation unit 12. The ON / OFF switch 18a of the voltage Vu1-5 corresponding to the I / O set to be enabled is turned OFF using the signal SW5-9 (S103). In the present embodiment, the number of parts is five, but it goes without saying that other parts or parts may be further divided. In the present embodiment, an example of receiving a return event from the operation unit 12, the FAX 13, and the network 14 will be described. That is, SW5 and SW9 are turned from ON to OFF.

  Next, the voltage Vm of the controller 2 is turned off by turning off SW2 (S104). Since there is a certain amount of current capacity, the DET_Vm signal of the first voltage detection 19b is monitored for the voltage falling below the effective voltage (S105). When disabled (S105: Yes), DMA is used from the DRAM_M6b. The data is acquired and copied from the FROM I / F to a predetermined area of FROM_S5c via the internal buffer (S106).

  Here, the multiplexer 6c corresponds to both the voltages Vm and Vc, and when the voltage Vm is cut off, the energy saving start MPU 4c and the DRAM_M 6b are directly connected. The reference voltage in the case of DDR is also switched, and the energy saving MPU 4c can normally access the DRAM_M6b. Copying from the DRAM may be the entire area, or may be an area uniquely or dynamically determined by the main MPU 4b. In addition, it includes at least information that allows the main MPU 4b to start up normally in the state before shifting to power saving. Moreover, the capacity of the FROM_S5c can be reduced by releasing the RAM developed for the cache or the like before shifting to the power saving mode from the DRAM_M6b. Thereafter, the self-backup of the DRAM_M6b is held with the power charged in the capacitor 17c (S107).

  Further, the energy saving activation MPU 4c monitors whether the voltage of the capacitor 17c is valid using the second voltage detection 19a (S108). If DET_Vc is not disabled (S108: No), it is monitored whether there is a power saving return event (S113). In this embodiment, since Vu1 and 5 are OFF, IVT_1 and 5 are invalid even if a flag is set.

  If there is an event (S113: Yes), the refresh of the DRAM_M6c is canceled (S114), the voltage Vm is turned on (S115), a fast return flag is set and notified to the main MPU 4b (S116).

  Here, the main MPU 4b detects reception from the COM_MS signal at the time of start-up, and when there is this notification, it recognizes that it is a fast return, which is a characteristic operation of the present invention. When the fast return flag is set, the main MPU 4b does not perform initialization processing, and uses the data in the DRAM_M6c to return quickly (end (at the return event)). Depending on the event, the voltage Ve of the engine control unit 1 may be turned on (S117), and if the return is only to store data from a fax or network in the memory, the voltage of the engine control unit 1 is kept off. This is preferable because it is not necessary to generate invalid power consumption.

  When the processing of the return event is finished and the power saving transition time has elapsed, the operation starts again from the top of the processing flow. If the engine control unit 2 is not activated, the SW1 process may be skipped. However, even if the OFF process is performed, no operational problem occurs.

  On the other hand, if the voltage of the capacitor 17c is monitored and DET_Vc is disabled (S108: Yes), the event has not occurred within the period. In this case, the voltage is switched to the Vs voltage to further reduce the power. First, the DR_EN signal is turned off to turn off the voltage Vdr of the DRAM_M6b (S109). Next, when SW3 is turned on (S110) and SW4 is turned off (S111), the voltage Vc is switched to the voltage Vs, and the energy saving activation MPU 4c performs control for suppressing its own power consumption (S112). For example, the clock is lowered, or the supply voltage to cells not used (DMAC, DRAM I / F, FROM I / F in FIG. 1) is stopped. The DRAM_M6b is turned off and can reduce a current of several tens of mA from the time of self-refresh (to branch A).

  If there is a return event after shifting to the low power mode (S118: Yes), the controller 2 is started. That is, all SW5-9 are turned on (S119). This is useful when the user wants to return at some event and have another event. Also, SW4 is turned on (S120), SW2 is turned on and then SW3 is turned off (S121 to S122), so that the voltage Vs is switched to the voltage Vm, the DR_EN signal is turned on, and the DRAM voltage Vdr is also turned on. (S123).

  Next, data is copied from FROM_S5c to DRAM_M6b (S124), and the high speed return flag is turned off and notified to the main MPU 4b (S125). As described above, the main MPU 4b detects reception from the COM_MS signal at the time of start-up, and when there is a notification, the main MPU 4b recognizes that the high-speed recovery is a characteristic operation of the present invention.

  When this fast return flag is not set, the main MPU 4b does not perform initialization handling of the engine control unit 1, performs its own initialization processing (initialization of the part where the return event has occurred is limited to a part), Return using the data of DRAM_M6c copied from FROM_S5c (End (when WAIT ends)). At this time, the consistency of memory data such as a SUM check value is checked in consideration of a copy error or the like. Also, because of some initialization processing and memory data consistency check, it takes more time to recover than the above-mentioned rapid recovery. However, in the case of a system that develops a program from FROM to DRAM, the time can be saved and the program can be restored at high speed.

  Depending on the return event, the I / O of the engine control unit 1 may be used. In this case, the main MPU 4b determines and notifies the energy saving activation MPU 4c, or depending on the part (in the above example, Although the voltage Vu1 is OFF, for example, if the voltage Vu1 is ON, if it is an ADF sensor, the engine control unit 1 is uniquely activated), the energy saving activation MPU 4c determines that the SW1 is turned on and the voltage is Ve is turned ON (S126).

  FIG. 3 is a time chart showing the status of each MPU and the operation of the power supply of the controller. The operations of the main MPU 4a and the energy saving start MPU 4b in the transition processing to the power saving mode and the return to the normal mode shown in FIG. It shows the status and changes in the voltages Vm and Vc.

  As described above, when there is no return event and the capacitor 17c is discharged, the low power mode is entered. FIG. 3A shows a state where there is no return event and waiting for a return event (at the end of WAIT in FIG. 2, S101 to S112, S118 to S126). Time Tb indicates a period during which the DRAM main can be in a self-refresh state by the capacitor voltage.

  On the other hand, FIG. 3B shows a case where there is a return event before the capacitor 17c is discharged (S101 to S108, S113 to S117 at the time of the return event in FIG. 2).

In the example illustrated in FIG. 2, the example in which the return event of the operation unit (IVT_2), the analog telephone line (IVT_3), and the network (IVT_4) is monitored has been described. In this case, the DRAM main self-backup time Tb in FIG. 3 is expressed by the following equation (1).
Tb = Vm × C / (Iu2 + Iu3 + Iu4) (1)

  The relationship between the number of parts of the return event and the self-backup time is described in, for example, the instruction manual of the image processing apparatus, etc., and the apparatus administrator tries to make it longer by omitting unnecessary ones. In addition, it is preferable that the time can be adjusted by setting any one of the operation unit, the analog telephone line, and the network so that the return event is not possible.

  Hereinafter, other embodiments of the image processing apparatus according to the present invention will be described. In addition, the description about the same point as the said embodiment is abbreviate | omitted.

<Second Embodiment>
The image processing apparatus preferably includes a plurality of capacitors. The adjustment of the voltage supply time of the capacitor will be described with reference to the block diagram of the image processing apparatus shown in FIG. In FIG. 4, only the block relating to the adjustment of the voltage supply time of the capacitor is shown, and the illustration of the same part as in FIG. 1 is omitted.

  In the first embodiment (FIG. 1), the case where there is one capacitor 17c and the return event is five parts has been described. However, in this embodiment (FIG. 4), the capacitors are 21a and 21b (capacitors C1, C1, respectively). C2), and can be switched by SW18c by signal SW10.

  The capacitors 21a and 21b are supplied to the voltage Vc by rectifying diodes 20a to 20e for rectification. In the case of one capacitor, only the voltage Vc is monitored. In order to switch the capacitor, the capacitors 21a and 21b are provided with the third voltage detection 19c and the fourth voltage detection 19d, respectively, and the voltage is higher than the threshold. The detection signals DET_Vc1 and 2 for detecting whether or not they are valid can be detected by the energy saving activation MPU 4c.

  For example, when the voltage of the capacitor 21a falls below the effective value, the SW 18c is switched to a contact different from the contact shown in the figure and switched to voltage supply from the capacitor 21b. In the first embodiment, the validity / invalidity of the voltage Vc is detected. In this embodiment, DET_Vc2 of the capacitor 21b is detected.

The DRAM main self-backup time Tb in this embodiment is expressed by the following equation (2).
Tb = Vm × (C1 + C2) / (Iu2 + Iu3 + Iu4) (2)

  Note that when the apparatus administrator shortens the time Tb, the switch of the SW 18c may be stopped. Thereby, if it is within a certain period after shifting to the power saving mode, self-backup of the memory by the capacitor can be performed and high-speed recovery can be performed, and the time can be adjusted.

  Here, in the image processing apparatus configured as described above, a plurality of settings (switching pattern) for switching the power source according to the selection are stored (switching pattern storage unit), and the frequency of use of each function of the image processing apparatus is determined. It is also preferable to store with time (usage frequency storage means) and select a setting based on the stored usage frequency. As a result, the memory information is retained for a certain period in a lower power state according to the usage status when the mode is changed to the power saving mode, and when the return event from the mode occurs, the memory controller information is retained. Can return fast.

  The switching setting of each SW using the image processing apparatus having the configuration shown in FIG. 4 will be described. The main MPU 4b notifies the energy saving activation MPU 4c of which part is normally used. The energy saving activation MPU 4c has a real-time clock for time, and stores the notified time in a FROM_S5c area different from the memory saving of the main MPU 4b. Further, the recording is performed in the same manner when a return event occurs in the power saving mode. Next, it is assumed that the aggregated recording data is statistically diagnosed at a predetermined time and merged when the usage frequency changes, as shown in FIG.

  The observation result of the usage record shown in FIG. 5A assumes a certain office. Here, at night when there are no personnel, when the number of FAX reception is small and the interval is longer than the time required by one capacitor, it can be considered that the capacitor is switched. Based on this observation result, for example, five setting values (settings 1 to 5) are determined, and as shown in FIG. 5B, which setting value is used for each time zone is determined, The setting of SW5-10 is switched for each band. In the example shown in FIG. 5, the setting is divided into five and the time zone is divided into six. However, it is preferable that the time zone and the number of settings are about five in practical use. You should keep it in one of the rules. Setting 0 is a default setting that is adopted before resetting the set value of the above-described operation and at the time of resetting.

<Third Embodiment>
In addition, equipped with multiple capacitors with different charging times, equipped with means to use the supply current of the capacitor that can be charged earlier to the processing to shift to the power saving mode, longer period of operation with low power, and frequent It is also preferable to ensure the supply current even when the mode is shifted to the power saving mode.

  FIG. 6 is a flowchart showing another example of the transition to the power saving mode and the return processing to the normal mode executed by the image processing apparatus according to the present embodiment. Note that the processing of S101 to S126 in the flowchart of FIG. 2 corresponds to S201 to S226 of FIG. 6, respectively, and FIG. 6 is obtained by adding the processing of S227 to S229. In the present embodiment, the image processing apparatus shown in FIG. 4 will be described as an example.

  Capacitor (first capacitor) 21a has a relatively small capacity (C1), so that it can be charged quickly but can only supply power for a short time, while capacitor (second capacitor) 21b has a relatively large capacity (C2). ) And power can be supplied for a long time, but charging takes time.

  As in the above embodiment, the CPU waits for the voltage Vm to become disabled, saves the data in the DRAM_M6b to the FROM_S5c, and shifts the DRAM_M to self-refresh (S205 to S207). Here, the SW 18c is a relay or semiconductor switch that can be continuously connected and does not cause an open state. Next, the SW 18c is switched from the capacitor 21a default to the capacitor 21b side by the signal SW10 (S227). Thereby, the saving operation from the DRAM to the FROM and the transition to the self refresh can be performed by the capacitor 21a, and the self backup can be held by the power supplied from the capacitor 21b.

  Further, it can be determined by the voltage detection signal DET_Vc2 that the voltage on the capacitor 21b side is disabled (S208). When it becomes invalid, the DR_EN signal is turned OFF, and the current supply to the DRAM is stopped (S209). Before the energy saving activation MPU 4c shifts to the low power mode, the SW 18c returns to the default (S228).

  If any return event occurs while holding the self-backup, the self-refresh is canceled, the SW2 is turned on and the voltage Vm is turned on (S214, S215), and the SW18c is returned to the default. (S229).

  As described above, according to the present embodiment, the operation of saving from the DRAM to the FROM and shifting to the self-refresh can be performed by feeding the capacitor that can be rapidly charged. As a result, it is possible to lengthen the time for holding the self-backup, and when frequent transition to the power saving mode occurs, for example, even if a recovery event occurs immediately after the power of the capacitor is exhausted, the recovery event The battery can be fully charged, and data can be securely saved during the next operation.

<Fourth Embodiment>
In addition, as will be described below, when shifting to the power saving mode, means for storing the time elapsed until the next return event occurs, and the time required to save the memory information (normal speed and relatively low in the low power mode) It is also preferable to use a power mode in which the power used for saving the memory is reduced when there is a time margin for saving the memory.

  FIG. 7 is a flowchart illustrating another example of the transition to the power saving mode and the return processing to the normal mode executed by the image processing apparatus according to the present embodiment. Note that the processing of S101 to S126 in the flowchart of FIG. 2 corresponds to S301 to S326 of FIG. 7, respectively, and FIG. 7 is obtained by adding the processing of S327 to S336. In the present embodiment, the image processing apparatus shown in FIG. 4 will be described as an example.

  In the example shown in FIG. 7, the main MPU 4b notifies the energy saving activation MPU 4c of the memory area to be saved together with the notification of transition to the power saving mode. Upon receiving this, the energy saving activation MPU 4c turns off SW1, turns off the switch of unnecessary parts from SW5-9, and turns off SW2 (S301 to S304).

  Further, after waiting for whether or not the voltage Vm has become invalid (S305: Yes), the time T1 that elapses from the speed used for saving from the DRAM to the FROM, which is determined in advance, is notified of the memory area to be saved. Is calculated (S327). In FIG. 7, the calculation is performed after waiting, but the calculation may be performed while waiting. Further, although the capacitor power is consumed by the normal current of the DRAM, it can be performed in a relatively short time than the discharge, so that the current at that time is also taken into consideration.

  Further, the time T2 until the return event occurs in the time zone of FIG. 5 is acquired from the value stored in the FROM_S5c area (S328). When T1 and T2 are compared, and T1> T2 (S329: Yes), the next event occurs during evacuation, so the flow is the same as in FIG.

  When T1> T2 is not satisfied (S329: No) (it is assumed that variation is taken into consideration for stability in the system), the power is reduced by turning on SW3 and turning off SW4 without shifting the DRAM to self-backup. The voltage Vs is shifted (S330 to S332), and the energy saving activation MPU 4c is evacuated from DRAM to FROM in the low power mode with a low processing speed (S333 to S334). Next, SW4 is turned on and SW3 is turned off (S335 to S336), and thereafter, the flow is the same as in FIG.

  As described above, when FROM save is executed at high speed, power is relatively consumed. Therefore, when time is available, it is preferable to reduce the speed and further reduce power. If the DRAM is accessed without shifting to the self-backup, a larger amount of current may be consumed than the self-backup, but the voltage Vdr is cut off and the DRAM is operated by the power supply portion of the DRAM and the capacitor capacity for smoothing and noise removal. Thus, adjustment can be made so that the power of the capacitor is not consumed. The adjustment is adjusted in consideration of the speed of each part.

  The above-described embodiment is a preferred embodiment of the present invention, but is not limited thereto, and various modifications can be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Engine control part 2 Control controller part 3a 1st power saving control part 3b 2nd power saving control part 4a Engine MPU
4b Main MPU
4c Energy saving start MPU
5a FROM_E
5b FROM_M
5c FROM_S
6a DRAM_E
6b DRAM_M
6c Multiplexer 6d Memory voltage generation circuit 7 Image processing controller 8a Scanner 8b Scanner controller 9a Laser 9b Laser controller 10a Plotter I / O
10b Plotter controller 11a ADF
11b Motor / clutch 11c Sensor 11d I / O control unit 12 Operation unit 13a Line I / F
13b FAX modem 14 LAN I / F
15 USBPHY
16a Power cord 16b Power switch 16c Power supply units 17a, 17b, 17d Rectifier diode 17c Capacitors 18a, 18b, 18c Switch 19a Second voltage detection 19b First voltage detection 19c Third voltage detection 19d Fourth voltage detection 20a, 20b, 20c, 20d, 20e Rectifier diode 21a, 21b Capacitor

Japanese Patent No. 3798353 JP 2006-350859 A

Claims (4)

In the normal mode in which power is supplied to the main body operation unit and the control controller unit, when the operation is not performed for a certain period, the power supply to the main body operation unit is stopped and the power supply to the control controller unit is performed. In the image processing apparatus to be transferred
Duplicating means for duplicating at least predetermined information required for returning to the normal mode among the information in the volatile memory to the nonvolatile memory;
Backup means for backing up the volatile memory by a capacitor power source for a predetermined time;
First return means for returning to the normal mode based on information of the volatile memory when a return event for returning from the power saving mode to the normal mode occurs within the predetermined time;
Transition means for stopping the power supply to the volatile memory and shifting to the low power mode when the return event does not occur within the predetermined time;
A second return means for returning to the normal mode based on information in the nonvolatile memory when the return event occurs in the low power mode;
The image processing apparatus is characterized in that the predetermined time is varied so that the return event can be arbitrarily selected . Usage frequency storage means for storing the usage frequency of each functional unit of the main body operation unit in units of time;
Switching pattern storage means for storing a predetermined number of switching patterns of the switches of each functional unit,
Based on the frequency of use, the image processing apparatus according to claim 1, characterized by selecting the switching pattern. A first capacitor that can be rapidly charged with a small capacity, and a second capacitor that has a larger capacity and requires a charging time than the first capacitor;
The copy of the predetermined information from the volatile memory to the nonvolatile memory and the shift to the backup state of the volatile memory, according to claim 1, characterized in that conducted on the basis of the power supply from the first capacitor or 2. The image processing apparatus according to 2. In the normal mode in which power is supplied to the main body operation unit and the control controller unit, when the operation is not performed for a certain period, the power supply to the main body operation unit is stopped and the power supply to the control controller unit is performed. In the image processing apparatus that shifts to
Duplicating means for duplicating at least predetermined information required for returning to the normal mode among the information in the volatile memory to the nonvolatile memory;
Backup means for backing up the volatile memory by a capacitor power source for a predetermined time;
First return means for returning to the normal mode based on information of the volatile memory when a return event for returning from the power saving mode to the normal mode occurs within the predetermined time;
Transition means for stopping the power supply to the volatile memory and shifting to the low power mode when the return event does not occur within the predetermined time;
A second return means for returning to the normal mode based on information in the nonvolatile memory when the return event occurs in the low power mode;
Usage frequency storage means for storing the usage frequency of each functional unit of the main body operation unit in units of time;
Switching pattern storage means for storing a predetermined number of switching patterns of the switches of each functional unit,
Based on the frequency of use, select the switching pattern, and
Means for comparing a time required for copying the predetermined information from the volatile memory to the non-volatile memory and a time until a return event occurs next;
The time required for replication of the predetermined information, the shorter than the time until recovery event occurs, the predetermined data replica migration to images processor you and performs the to the low power mode.

Images