JP5614341B2 - Data processing apparatus, system, and method of operating data processing apparatus - Google Patents

Description

  The present invention relates to a data processing device and a system in which the data processing device is mounted.

  Generally, a data processing apparatus has a processor and a memory accessed by the processor. In this type of data processing device, in order to reduce power consumption, when the processor issues a read command for the same address in the memory, access to the memory corresponding to the second and subsequent read commands is prohibited (for example, , See Patent Document 1). In a data processing apparatus including a general-purpose processor that executes a program and a dedicated processor that executes data processing, the general-purpose processor is stalled in response to a wait request from the dedicated processor in order to reduce power consumption (for example, patents). References 2 and 3.)

JP 2007-299044 A Japanese Patent Laid-Open No. 2004-199630 Special table 2001-501330 gazette

  Some general-purpose processors fetch instructions and data stored in memory even while stalled due to a request from a dedicated processor. Instructions and data fetched during the stall are discarded without being used. Memory power consumption occupies a large weight in a data processing apparatus. For this reason, the power efficiency of the data processing apparatus decreases due to unnecessary fetch operations.

  In one aspect of the present invention, a data processing device includes a first processor that outputs a request for access to a memory and a processing request generated using data read from the memory to instruct data processing; A second processor that executes data processing in response to the request and outputs a status signal indicating prohibition of accepting the processing request to the first processor when a state in which the processing request cannot be accepted occurs; a first processor; a memory; And a memory control unit that executes prohibition control for prohibiting the supply of the access request to the memory when the output of the processing request and the output of the status signal are detected.

  By suppressing unnecessary access from the first processor to the memory, the power consumption of the memory can be reduced, and the power consumption of the data processing apparatus can be reduced.

1 illustrates an example of a data processing apparatus according to an embodiment. The example of the data processor in another embodiment is shown. 3 shows an example of the operation of the data processing apparatus shown in FIG. The example of the data processor in another embodiment is shown. 5 shows an example of the address space of the instruction memory shown in FIG. 5 shows an example of the operation of the data processing apparatus shown in FIG. The example of the data processor in another embodiment is shown. 8 shows an example of the mask control circuit shown in FIG. The example of the data processor in another embodiment is shown. 10 shows an example of the address space of the instruction memory shown in FIG. The example of the data processor in another embodiment is shown. The example of the system by which the data processing apparatus mentioned above is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a data processing device DPD in one embodiment. The data processing device DPD includes a processor 1, a processor 2, a memory 3, and a memory control unit 4. The memory 3 may be arranged outside the data processing device DPD. The data processing device DPD may be formed as one semiconductor chip or may be formed using a plurality of semiconductor chips.

  The processor 1 outputs an access request EN to the memory 3 in order to read data DT for processing data processing from the memory 3, and outputs a processing request REQ instructing data processing to the processor 2. For example, the processor 1 uses the data DT read from the memory 3 to generate a processing request REQ. When the data DT is an instruction to be decoded by the processor 1, information on the processing request REQ is included in the instruction. When the memory 3 has a plurality of storage areas identified by a plurality of addresses, the processor 1 outputs the address AD together with the access request EN to the memory 3. Although not particularly limited, the processing request REQ and the access request EN are valid when the logic is 1, and are invalid when the logic is 0.

  The processor 2 receives the processing request REQ and executes data processing. The processor 2 outputs a state signal ST indicating prohibition of accepting the processing request REQ to the first processor 1 when a state where the processing request REQ cannot be accepted occurs. The state in which the processing request REQ is not accepted is a state in which the time of data processing executed in response to the processing request REQ is longer than the supply interval of the processing request REQ. For example, when the processor 2 has a buffer for holding a plurality of processing requests REQ, the state signal ST is output when the buffer is full (full state). The buffer full state is likely to occur when the supply interval of the processing request REQ continues to exceed the data processing time of the processor 2. Although not particularly limited, the status signal ST indicates that the buffer is full when it is logic 1, and indicates that the buffer is empty when it is logic 0.

  The memory 3 operates when the access request EN is asserted to logic 1. For example, in the read operation, the memory 3 reads the data DT from the memory cell selected by the address AD, and outputs the read data DT to the processor 1. The access request EN may include a chip select signal and an output enable signal. When the memory 3 is a ROM (Read Only Memory), the data DT is read from the memory 3 to the processor 1 and is not written from the processor 1 to the memory 3.

  The memory control unit 4 is arranged between the processor 1 and the memory 3 and supplies the access request EN to the memory 3 when it detects that the output of the processing request REQ and the output of the status signal ST overlap. Prohibit prohibition control. For example, the prohibition control is executed by an access prohibition circuit 4 a formed in the memory control unit 4. The data DT and the address AD are transmitted via the memory control unit 4, but may be directly transmitted between the processor 1 and the memory 3.

  The access prohibition circuit 4a transmits the access request EN from the processor 1 to the memory 3 when the status signal ST is logic 0, that is, when the processor 2 can execute normal data processing. On the other hand, when the status signal ST is logic 1 and the processing request REQ is logic 1, the access prohibition circuit 4a prohibits the transmission of the access request EN from the processor 1 to the memory 3.

  When the logic 1 state signal ST is output, the processor 2 is in a state where it cannot accept the processing request REQ. The processing request REQ is generated based on the data DT read from the memory 3. When the processor 1 accesses the memory 3 and reads the data DT while the status signal ST is being output, the read data DT is not used, so the memory 3 consumes useless power. However, in this embodiment, when the logic 1 processing request REQ and the status signal ST are output, access to the memory 3 is prohibited by prohibition control, so that the memory 3 is prevented from consuming unnecessary power. it can.

  As described above, in this embodiment, when a state where the processor 2 cannot accept the processing request REQ occurs, the power consumption of the memory 3 can be reduced by suppressing unnecessary access from the processor 1 to the memory 3. The power consumption of the processing device DPD can be reduced.

  FIG. 2 shows an example of a data processing device DPD in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The data processing device DPD of this embodiment includes a processor 10, a coprocessor 12, an instruction memory 14, and a memory control unit 16. Note that the instruction memory 14 may be formed outside the data processing device DPD.

For example, the processor 10 is a general-purpose processor that executes a program by fetching data DT (instruction) read from the instruction memory 14, and includes a program counter PC that generates an address AD to be output to the instruction memory 14. Yes. The processor 10, when the instruction read from the instruction memory 14 of the instruction to the processor 10, when to perform data processing by itself, the instruction is read from the instruction memory 14 of the instruction to the coprocessor 12, the queue data QDT based on instructions Is generated. That is, the processor 10 uses the data DT read from the instruction memory 14 to generate queue data QDT to be output to the coprocessor 12, and outputs it to the coprocessor 12 together with the queue push request QPREQ.

  The queue data QDT is an instruction for causing the coprocessor 12 to execute data processing. For example, the queue data QDT includes information such as a storage address and data size of data processed by the coprocessor 12. Data processed by the coprocessor 12 is stored in a data memory such as a DRAM (Dynamic Random Access Memory) disposed inside or outside the data processing device DPD. Data memory is accessible by the processor 10 and the coprocessor 12. The queue push request QPREQ is a trigger signal for notifying the coprocessor 12 of the capture timing of the queue data QDT. The queue push request QPREQ is valid when the logic is 1, and is invalid when the logic is 0. The queue push request QPREQ is an example of a processing request generated using data DT read from the instruction memory 14 in order to instruct the coprocessor 12 to perform data processing.

When receiving the full signal QFUL from the coprocessor 12, the processor 10 transitions from the normal operation state to the stall state, and stops the output of the queue data QDT and the queue push request QPREQ. For example, the full signal QFUL is valid when the logic is 1, and is invalid when the logic is 0. When the processor 10 receives the busy signal BUSY from the memory control unit 16, the processor 10 recognizes that access to the instruction memory 14 is prohibited, and on the data line DT wired between the instruction memory 14 and the processor 1. Is determined to be invalid. For example, the processor 10 is a general-purpose processor and has a function of outputting an access request EN for the instruction memory 14 during a stall.

  The coprocessor 12 is a dedicated processor such as a baseband processor, a DSP (Digital Signal Processor), or a vector processor, and executes data processing based on the queue data QDT. The coprocessor 12 includes an instruction buffer 12a (for example, a FIFO (First-In, First-Out) memory) that sequentially holds the queue data QDT from the processor 10. For example, the coprocessor 12 fetches the queue data QDT into the instruction buffer 12a in the next clock cycle that receives the queue push request QPREQ. The coprocessor 12 may fetch the queue data QDT into the instruction buffer 12a in the clock cycle that receives the queue push request QPREQ.

  The coprocessor 12 reads and decodes the queue data QDT in the order stored in the instruction buffer 12a, and executes data processing of data stored in the data memory or the like. The coprocessor 12 outputs the full signal QFUL when the queue data QDT is stored in all areas of the instruction buffer 12a. The full signal QFUL is an example of a state signal indicating that the queue push request QPREQ is not accepted when a state where the queue push request QPREQ cannot be accepted occurs. In FIG. 2, the instruction buffer 12a has four storage areas, but the maximum number of queue data QDT stored in the instruction buffer 12a is not limited to four.

  The instruction memory 14 stores instructions to be executed by the processor 10 and operates in response to the access request EN, similarly to the memory 3 shown in FIG. The instruction memory 14 may be a flash memory, a ROM such as a mask ROM, an SRAM (Static Random Access Memory), a DRAM, or the like.

  The memory control unit 16 is disposed between the processor 10 and the instruction memory 14, and includes AND circuits AND1, AND2 and an inverter IV1. The AND circuit AND1 receives the queue push request QPREQ and the full signal QFUL at the inputs, and connects the output to the input of the inverter IV1. The AND circuit AND2 receives the output signal of the inverter IV1 and the access request EN at the input, and outputs the operation result as an access request EN to the instruction memory 14.

  When the full signal QFUL is negated to logic 0, that is, when the coprocessor 12 can execute normal data processing, the AND circuit AND2 receives the logic 1 from the inverter IV1 and sends the access request EN to the instruction memory 14. Acts as a buffer to communicate. On the other hand, when the queue push request QPREQ is asserted to the logic 1 and the full signal QFUL is asserted to the logic 1, the AND circuit AND2 receives the logic 0 from the inverter IV1 and transmits the access request EN to the instruction memory 14. Ban. That is, when the memory control unit 16 detects that the output of the queue push request QPREQ and the output of the full signal QFUL overlap, the memory control unit 16 executes prohibition control for prohibiting the supply of the access request EN to the instruction memory 14. The AND circuits AND1 and AND2 and the inverter IV1 are examples of access prohibition circuits that execute prohibition control.

  Further, the memory control unit 16 outputs the output of the AND circuit AND1 to the processor 10 as the busy signal BUSY. The busy signal BUSY is valid when the logic is 1, and is invalid when the logic is 0. A logic 1 busy signal BUSY indicates that prohibition control is being executed. In FIG. 2, the data DT and the address AD are transmitted via the memory control unit 16, but may be directly transmitted between the processor 10 and the instruction memory 14.

  FIG. 3 shows an example of the operation of the data processing device DPD shown in FIG. In FIG. 3, a rectangular frame indicates that the corresponding circuit block (each of the instruction memory 14, the memory control unit 16, the processor 10, and the coprocessor 12) is executing processing. In the operation of the memory control unit 16, a hatched rectangular frame indicates a prohibition control period in which access to the instruction memory 14 is prohibited. A shaded rectangular frame indicates a period during which the processor 10 is stalled.

  First, the processor 10 outputs an access request EN (read request) and an address AD to the instruction memory 14 in order to cause the instruction memory 14 to execute a read operation (FIG. 3A). The instruction memory 14 executes a read operation in response to the access request EN, and outputs the read data DT to the processor 10 (FIG. 3B). The AND circuit AND2 of the memory control unit 16 shown in FIG. 2 operates as a buffer in response to the logic 1 from the inverter IV1, and transfers the access request EN from the processor 10 to the instruction memory 14. For example, the coprocessor 12 enters an idle state when the queue data QDT is not held in the instruction buffer 12a (FIG. 3C).

  The processor 10 analyzes the data DT (instruction) received from the instruction memory 14 and, when the instruction for the coprocessor 12 is included in the data DT, queue data including an instruction that causes the coprocessor 12 to execute data processing. Generate QDT. Then, the processor 10 outputs the queue data QDT and the queue push request QPREQ to the coprocessor 12 (FIG. 3 (d)). In response to the queue push request QPREQ, the coprocessor 12 stores the queue data QDT in the instruction buffer 12a.

  Thereafter, as described above, access to the instruction memory 14 by the processor 10 is executed, and the queue data QDT generated based on the data DT read from the instruction memory 14 is output to the coprocessor 12 together with the queue push request QPREQ. (FIG. 3 (e, f)). The coprocessor 12 executes data processing corresponding to the queue data QDT in the order stored in the instruction buffer 12a. The queue data QDT for which data processing has been completed is deleted, for example, by moving the pointer indicating the latest queue data QDT.

  When the instruction buffer 12a is filled with new queue data QDT supplied from the processor 10, the coprocessor 12 asserts the full signal QFUL to logic 1 (FIG. 3 (g)). While receiving the logic 1 full signal QFUL from the coprocessor 12, the processor 10 transitions from the normal operation state to the stall state (FIG. 3 (h)). The memory control unit 16 receives the logic 1 queue push request QPREQ and the logic 1 full signal QFUL, and prohibits the access request EN output from the processor 10 from being supplied to the instruction memory 14. That is, the memory control unit 16 executes prohibition control (FIG. 3 (i, j)). The memory control unit 16 outputs a busy signal BUSY to the processor 10 during the prohibition control period (FIG. 3 (k)). Note that the memory control unit 16 detects the logic of the queue push request QPREQ for one clock cycle in order to detect the output of the queue push request QPREQ and the output of the full signal QFUL corresponding to the queue push request QPREQ. , You may hold.

  Based on the busy signal BUSY, the processor 10 recognizes that the access request EN output during the prohibition control period is invalid. As a result, the processor 10 can prevent the logic on the data line DT that is not the data DT from the instruction memory 14 from being received as the data DT from the instruction memory 14, and can prevent the processor 10 from malfunctioning. Note that the processor 10 may stop issuing the access request EN while the busy signal BUSY is being output. Thereby, useless operation | movement of the processor 10 is suppressed and power consumption can be reduced.

  The coprocessor 12 negates the full signal QFUL to logic 0 when data processing proceeds and a space is generated in the instruction buffer 12a (FIG. 3 (l)). Upon receiving the logic 0 full signal QFUL, the processor 10 returns from the stall state to the normal operation state (FIG. 3 (m)). The memory control unit 16 receives the logic 0 full signal QFUL and cancels the inhibition control (FIG. 3 (n)). Then, access to the instruction memory 14 by the processor 10 is started again, and the queue data QDT generated based on the data DT read from the instruction memory 14 is output to the coprocessor 12 together with the queue push request QPREQ (FIG. 3 ( o, p)).

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. In particular, even when using a general-purpose processor 10 that outputs an access request EN during a stall, unnecessary access from the processor 10 to the instruction memory 14 can be suppressed, and the power consumption of the instruction memory 14 and the data processing device DPD is reduced. it can. Further, the memory control unit 16 outputs a busy signal BUSY to the processor 10 during a prohibition control period in which access to the instruction memory 14 is prohibited. As a result, the processor 10 can recognize that the data DT on the data line DT is erroneous data that has not been read from the instruction memory 14, and can prevent malfunction. Furthermore, by stopping the issuance of the access request EN while the busy signal BUSY is being output, useless operations of the processor 10 can be suppressed and power consumption can be reduced.

  FIG. 4 shows an example of a data processing device DPD in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The data processing device DPD of this embodiment has a processor 10A and a memory control unit 16A instead of the processor 10 and the memory control unit 16 shown in FIG. The configuration excluding the processor 10A and the memory control unit 16A is the same as that shown in FIG.

  The processor 10A receives the interrupt request IREQ and adds a function for executing interrupt processing to the processor 10 shown in FIG. For example, the interrupt request IREQ is supplied to the processor 10 via the interrupt terminal when causing the processor 10 to execute processing not related to the data processing of the coprocessor 12. The memory control unit 16A adds a mask control circuit MSKCNT1 and an AND circuit AND3 to the memory control unit 16 shown in FIG.

  For example, the mask control circuit MSKCNT1 has an OR circuit OR1 that receives the most significant bit MSB of the address AD output from the processor 10A and the second bit MSB-1 from the most significant bit MSB. Here, the bits MSB and MSB-1 are the most significant 2 bits of the address AD assigned to the instruction memory 14. Mask control circuit MSKCNT1 negates mask signal / MSK to logic 1 when either bit MSB or MSB-1 is logic 1, and mask signal / MSK when both bits MSB and MSB-1 are logic 0. Is asserted to logic zero.

  That is, the mask signal / MSK is negated when the upper third quarter of the memory area of the instruction memory 14 is accessed, and the mask signal when the lower quarter of the memory area of the instruction memory 14 is accessed. / MSK is asserted. Note that the memory area where the mask signal / MSK is asserted may be reduced by increasing the number of upper bits of the address AD received by the OR circuit OR1.

  The AND circuit AND3 masks the inhibition control described above by setting the output of the inverter IV1 to logic 1 regardless of the state of the AND circuit AND1 when receiving the mask signal / MSK of logic 0. The AND circuit AND3 permits the inhibition control by permitting the logic 1 from the AND circuit AND1 to be transmitted to the inverter IV1 when receiving the logic 1 mask signal / MSK. The AND circuit AND3 is an example of a mask circuit that masks prohibition control when the mask signal / MSK is asserted in order to supply the access request EN to the instruction memory 14.

  FIG. 5 shows an example of the address space of the instruction memory 14 shown in FIG. For example, the instruction memory 14 has a 512 kB (kilobyte) storage area allocated in the address space AS used in the data processing device DPD, and is accessed using 19-bit address signals AD18-AD0. The The address AD shown in FIG. 5 is a hexadecimal number, and “x” indicates an arbitrary value.

  In this embodiment, the 128 kB storage area in which the bits AD18 and AD17 corresponding to the bits MSB and MSB-1 are both logic 0 is assigned to an interrupt instruction area in which an instruction used in interrupt processing is stored. The interrupt instruction area includes a vector area in which an interrupt vector is stored and a handler area in which an interrupt handler that is an interrupt processing program is stored. The interrupt vector indicates the start address where the interrupt handler is stored. A storage area of 384 kB in which either bit AD18 or AD17 is logic 1 is allocated to a normal instruction area in which instructions used in normal operation are stored.

  In this embodiment, as shown in FIG. 6, the memory control unit 16 </ b> A receives the interrupt instruction area even during the prohibition control period in which the queue push request QPREQ and the full signal QFUL are output in duplicate. The prohibition control is masked.

  FIG. 6 shows an example of the operation of the data processing device DPD shown in FIG. Detailed descriptions of the same operations as those in FIG. 3 are omitted. As in FIG. 3, the hatched rectangular frame indicates the prohibition control period, and the shaded rectangular frame indicates the stall period of the processor 10. A black rectangular frame indicates a period during which interrupt processing is executed. The operation excluding the period during which the interrupt process is executed is the same as that in FIG.

  When receiving the interrupt request IREQ during the prohibition control period, the processor 10 outputs an access request EN together with the address signal AD in order to access the vector area shown in FIG. 5 (FIG. 6A). Since address signal AD indicates a vector area, memory control unit 16A asserts mask signal / MSK and sets the output of inverter IV1 to logic 1. As a result, even during the prohibition control period in which the AND circuit AND1 outputs logic 1, the access request EN from the processor 10 is supplied to the instruction memory 14 (FIG. 6B). Thereafter, the processor 10 accesses the handler area of the instruction memory 14 and executes interrupt processing (FIG. 6C).

  In the example shown in FIG. 6, after completion of the interrupt process indicated by the black rectangular frame, the coprocessor 12 sets the full signal QFUL to logic 0 in response to the instruction buffer 12a being free (FIG. 6 (d)). . Thereafter, similarly to FIG. 3, the processor 10 starts to access the instruction memory 14 again, and the queue data QDT generated based on the read data DT is output to the coprocessor 12 together with the queue push request QPREQ (FIG. 3). 6 (e, f)).

  The coprocessor 12 may negate the full signal QFUL to logic 0 when the instruction buffer 12a becomes empty during execution of interrupt processing. At this time, the processor 10 receives the full signal QFUL during the interrupt process, returns from the stalled state to the normal operation state, and starts accessing the instruction memory 14 by the normal operation after the end of the interrupt process.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by masking prohibition control when a predetermined area of the instruction memory 14 is accessed by the memory control unit 16A, the processor 10 can access the instruction memory 14 during the prohibition control period. Thereby, for example, when executing processing not related to the data processing of the coprocessor 12, it is possible to access the instruction memory 14 even during the prohibition control period, and to prevent the performance of the data processing device DPD from deteriorating. . Here, the processing not related to the data processing of the coprocessor 12 is, for example, interrupt processing.

  FIG. 7 shows an example of a data processing device DPD in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The data processing device DPD of this embodiment has a processor 10B and a memory control unit 16B instead of the processor 10 and the memory control unit 16 shown in FIG. The configuration excluding the processor 10B and the memory control unit 16B is the same as that shown in FIG.

  The processor 10B receives an interrupt request IREQ and adds a function for executing interrupt processing and a register REG to the processor 10 shown in FIG. The function of executing the interrupt process is the same as that of the processor 10A shown in FIG. The register REG is assigned to, for example, an I / O space. The register REG masks the prohibition control described above and holds the control bits MC (MC2, MC1, MC0) for designating a storage area of the instruction memory 14 that can be accessed even during the prohibition control. In other words, the control bit MC of the register REG holds information indicating a predetermined storage area in the instruction memory 14 in a rewritable manner.

  The memory control unit 16B adds a mask control circuit MSKCNT2, an OR circuit OR2, and an AND circuit AND3 to the memory control unit 16 shown in FIG. The mask control circuit MSKCNT2 receives the value of the upper 8 bits AD18 to AD11 and the value of the control bits MC2 to MC0 in the address AD output from the processor 10B, and receives 8 bits of mask address bits MAD (MAD18 to MAD11). Is output. The OR circuit OR2 negates the mask signal / MSK to logic 1 when any of the mask address bits MAD18 to MAD11 is logic 1, and outputs the mask signal / MSK when all the mask address bits MAD18 to MAD11 are logic 0. Assert to logic zero. The operations of the AND circuits AND1, AND2, AND3 and the inverter IV1 are the same as those in FIG.

  The instruction memory 14 has a storage area of 512 kB (kilobyte) allocated in the address space AS used by the data processing device DPD, and uses 19-bit address signals AD18-AD0, as in FIG. And accessed.

  FIG. 8 shows an example of the mask control circuit MSKCNT2 shown in FIG. The mask control circuit MSKCNT2 has a mask decoder MSKDEC and a mask enable circuit MSKEN. Mask decoder MSKDEC sets the logic of 8-bit mask bits MB (MB18-MB11) according to the values of control bits MC2-MC0.

  The mask decoder MSKDEC sets the mask bits MB18 to MB11 to logic 1 from the upper side by the number obtained by adding 1 to the value (0 to 7) indicated by the control bits MC2 to MC0. For example, when the control bits MC2-MC0 are “001” (decimal number 1), the 2-bit mask bits MB18 and MB17 are set to logic 1, and the other mask bits MB16 to MB11 are set to logic 1. When the control bits MC2-MC0 are "100" (decimal number 4), the 5-bit mask bits MB18-MB14 are set to logic 1, and the other mask bits MB13-MB11 are set to logic 0.

  The mask enable circuit MSKEN has nine AND circuits corresponding to the addresses AD18 to AD11. Each AND circuit receives an address AD and a mask bit MB having the same number, and outputs a mask address bit MAD. Each AND circuit outputs a mask address bit MAD having the same logic as the address signal AD when the mask bit MB is logic 1, and sets the mask address bit MAD to logic 0 when the mask bit MB is logic 0.

  For example, when the control bits MC2 to MC0 are “001”, the mask bits MB16 to MB11 are set to logic 0, so that the mask address bits MAD16 to MAD11 are fixed to logic 0. Since the mask bits MB18 and MB17 are set to logic 1, the mask address bits MAD18 and MAD17 are set to the same logic as the addresses AD18 and AD17. Therefore, when either address AD18 or AD17 is logic 1, either mask address bit MAD18 or MAD17 is set to logic 1, and mask signal / MSK is negated to logic 1. When both addresses AD18 and AD17 are logic 0, all mask address bits MAD18-MAD11 are set to logic 0, and the mask signal / MSK is asserted to logic 0. As a result, as in FIG. 5, the 128 kB storage area in the instruction memory 14 can be set as an accessible area during prohibition control.

  The value of the control bit MC2-0 indicates the size of an area that can be accessed in the instruction memory 14 during prohibition control. For example, when the control bit MC2-0 is a decimal number “0”, 256 kB is set as an accessible area during prohibition control, and when the control bit MC2-0 is a decimal number “2”, 64 kB is prohibited control. It is set as an accessible area inside. When the control bit MC2-0 is “3” in decimal, 32 kB is set as an accessible area during prohibition control, and when the control bit MC2-0 is “4” in decimal, 16 kB is in prohibition control. Set as an accessible area.

  Similarly, when the control bit MC2-0 is decimal number “5”, 8 kB is set as an accessible area during the prohibition control, and when the control bit MC2-0 is decimal number “6”, 4 kB is prohibited. When the control bit MC2-0 is a decimal number “7”, 2 kB is set as an accessible area during prohibition control. Thus, the size of the interrupt instruction area shown in FIG. 5 can be changed according to the value set in the control bits MC2 to MC0 of the register REG.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, the storage area of the instruction memory 14 that can be accessed during prohibition control can be arbitrarily set according to the value of the register REG. Thereby, for example, the size of the interrupt instruction area can be optimally set for each of the data processing devices DPD having various specifications.

  FIG. 9 shows an example of a data processing device DPD in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The data processing device DPD of this embodiment has a processor 10C and a memory control unit 16C instead of the processor 10 and the memory control unit 16 shown in FIG. The configuration excluding the processor 10C and the memory control unit 16C is the same as that shown in FIG.

  The processor 10C is formed by adding a function for receiving an interrupt request IREQ and executing interrupt processing and a register REG to the processor 10 shown in FIG. The function of executing the interrupt process is the same as that of the processor 10A shown in FIG. The register REG is assigned to, for example, an I / O space and has a rewritable control bit CON. The control bit CON masks prohibition control and is set to logic 0 when the instruction memory 14 is forcibly accessible even during prohibition control, and is set to logic 1 when the prohibition control is not masked.

  The memory control unit 16C has a mask control circuit MSKCNT3 instead of the mask control circuit MSKCNT1 shown in FIG. The memory control unit 16C is formed by adding an inverter IV2, an OR circuit OR3, and an AND circuit AND4 to the memory control unit 16A shown in FIG.

  For example, the mask control circuit MSKCNT3 has an OR circuit OR4 that receives 7 bits (MSB, MSB-1, MSB-2,..., MSB-6) from the most significant address AD output from the processor 10A. Yes. Mask control circuit MSKCNT3 negates mask signal / MSK to logic 1 when any of the bit values received by OR circuit OR4 is logic 1, and mask signal when all the bit values received by OR circuit OR4 are logic 0 / MSK is negated to logic zero. As a result, as shown in FIG. 10, a 4 kB area (for example, an interrupt instruction area) accessible during prohibition control can be allocated to the instruction memory 14.

  The inverter IV2 inverts the logic of the control bit CON and outputs it to the OR circuit OR3. The OR circuit OR3 outputs a logic 1 to the AND circuit AND2 when either of the outputs of the inverters IV1 and IV2 is a logic 1, and outputs a logic 0 when both of the outputs of the inverters IV1 and IV2 are a logic 0. Output to AND2. In other words, the OR circuit OR3 performs logic to permit the access request EN from the processor 10C to be supplied to the instruction memory 14 when any one of the mask signal / MSK, the control bit CON, and the full signal QFUL is logic 0. 1 is output. The OR circuit 3 outputs a logic 1 to inhibit the access request EN from the processor 10C from being supplied to the instruction memory 14 when the mask signal / MSK, the control bit CON, and the full signal QFUL are all logic 1. To do. In other words, the OR circuit OR3 masks the inhibition control when either the mask signal / MSK or the control bit CON is logic 0 even if the full signal QFUL is asserted to logic 1, and A logic 1 is output to supply the access request EN to the instruction memory 14.

  The AND circuit AND4 masks that the busy signal BUSY is set to logic 1 in response to the change of the full signal QFUL to logic 1 when the control bit CON is set to logic 0. Thereby, when the instruction memory 14 is forcibly made accessible by the control bit CON, it is possible to prevent the busy signal BUSY from being output to the processor 10C.

  FIG. 10 shows an example of the address space of the instruction memory 14 shown in FIG. Detailed description of the same elements as those in FIG. 5 is omitted. As in FIG. 5, the instruction memory 14 has a 512 kB storage area and is accessed using 19-bit address signals AD18-AD0. The seven bit values MSB, MSB-1, MSB-2,..., MSB-6 shown in FIG. 9 are addresses AD18-AD12. In this example, the interrupt instruction area is used only for a vector area in which an instruction for setting the control bit CON from logic 1 to logic 0 and an interrupt vector are stored, and is allocated to 4 kB. The normal instruction area is allocated to the remaining 508 kB. A part of the normal instruction area is used as a handler area in which an interrupt handler is stored.

  In this embodiment, when the interrupt request IREQ is generated during the prohibition control period in which the queue push request QPREQ and the full signal QFUL are output in duplicate, the mask signal / MSK is asserted as in FIG. The area becomes accessible. The processor 10C reads from the instruction memory 14 an interrupt vector indicating an instruction for setting the control bit CON from logic 1 to logic 0 and a handler area. When the control bit CON is set to logic 0, the normal instruction area can be accessed during the prohibition control period, and the processor 10C can execute the interrupt handler stored in the normal instruction area. The interrupt handler sets the control bit CON from logic 0 to logic 1 when ending the interrupt processing. As a result, the access to the normal instruction area is prohibited during the prohibition control period after the interruption process is completed. As a result, unnecessary access to the instruction memory 14 can be suppressed and power consumption can be reduced.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, the interrupt handler can be stored in an arbitrary area of the instruction memory 14 by adding a function of forcibly masking the prohibition control by the control bit CON and accessing the instruction memory 14 in the data processing device DPD. As a result, the degree of freedom in assigning programs stored in the instruction memory 14 is improved.

  FIG. 11 shows an example of a data processing device DPD in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The data processing device DPD of this embodiment has a processor 10D and a memory control unit 16D instead of the processor 10 and the memory control unit 16 shown in FIG. The configuration excluding the processor 10D and the memory control unit 16D is the same as that in FIG.

  The processor 10D adds a register REG, which is a combination of the functions of the register REG shown in FIGS. 7 and 9, to the processor 10 shown in FIG. The function of executing the interrupt process is the same as that of the processor 10A shown in FIG. That is, the register REG has, for example, control bits MC2, MC1, MC0, and CON that are allocated to the I / O space and are held so as to be rewritable.

  The memory control unit 16D has a mask control circuit MSKCNT2 shown in FIG. 7 instead of the mask control circuit MSKCNT3 shown in FIG. Other configurations of the memory control unit 16D are the same as those of the memory control unit 16C illustrated in FIG. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 12 shows an example of a system SYS on which the above-described data processing device DPD is mounted. The system SYS is, for example, a built-in communication device such as a mobile phone, and includes an antenna ANT, a high-frequency circuit RF, an analog-digital converter A / D, a data processing device DPD, a processor PROC, and an input / output unit I / O. ing.

  The high-frequency circuit RF extracts a necessary frequency component from the high-frequency signal received via the antenna ANT and outputs it as a baseband signal to the analog / digital converter A / D. The analog-digital converter A / D converts an analog baseband signal into a digital signal. The high-frequency circuit RF and the analog-digital converter A / D are an example of a first data processing unit that outputs data for data processing executed by the coprocessor to the data processing device DPD.

  The data processing device DPD operates as a circuit for baseband processing, for example, and is formed in the DSP chip as a part of a DSP (Digital Signal Processor). In addition to the above-described configuration, the data processing device DPD has a DRAM in which data to be processed and intermediate data are stored. The DRAM may be arranged outside the data processing device DPD. The data processing device DPD demodulates the baseband signal supplied from the analog / digital converter A / D, and acquires data contained in the signal received by the antenna ANT.

  The processor PROC is a processor for an application that executes processing corresponding to the data acquired by the data processing device DPD. For example, the processor PROC executes a decoding process for reproducing audio data and a decoding process for reproducing image data. Note that a plurality of processors PROG that respectively perform audio data decoding processing and image data decoding processing may be formed. The processor PROC is an example of a second data processing unit that processes data generated by data processing executed by the coprocessor. Note that a plurality of processors PROG that respectively perform audio data decoding processing and image data decoding processing may be formed.

  The input / output unit I / O is a user interface unit such as a display that displays image data decoded by the processor PROC, a speaker that outputs audio data decoded by the processor PROG, an input key, and a camera. By mounting the data processing device DPD of the above-described embodiment in the system SYS, the power consumption of the system SYS can be reduced. In particular, a built-in communication device such as a mobile phone is driven by a battery. For this reason, by reducing power consumption, the operation time and standby time of the communication device can be extended, and the performance of the communication device can be improved.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A first processor that outputs a memory access request and a processing request generated using data read from the memory to direct data processing;
A second processor that executes data processing in response to the processing request and outputs a status signal indicating prohibition of acceptance of the processing request to the first processor when a state in which the processing request cannot be accepted occurs;
A memory that is arranged between the first processor and the memory and that executes prohibition control for prohibiting the access request from being supplied to the memory when the output of the processing request and the output of the status signal are detected. A data processing apparatus comprising: a control unit.
(Appendix 2)
The memory control unit
A mask control circuit that asserts a mask signal when an address included in the access request indicates a predetermined area of the memory;
The data processing apparatus according to claim 1, further comprising: a mask circuit that masks the prohibition control and supplies the access request to the memory when a mask signal is asserted.
(Appendix 3)
The first processor includes a first register that holds information indicating the predetermined area in a rewritable manner,
The mask control unit asserts the mask signal when the address output from the first processor is included in an area indicated by information held in the first register. Data processing equipment.
(Appendix 4)
The first processor has a function of executing an interrupt process in response to an interrupt request;
4. The data processing device according to appendix 2 or appendix 3, wherein an interrupt vector and an interrupt handler used for the interrupt processing are stored in the predetermined area of the memory.
(Appendix 5)
The first processor includes a second register that is set to a first logic when masking the inhibition control;
The mask circuit is configured to mask the prohibition control and permit the supply of the access request to the memory when the second register is set to the first logic. The data processing device according to attachment 3.
(Appendix 6)
The first processor has a function of executing an interrupt process in response to an interrupt request;
An instruction and an interrupt vector for setting the second register to the first logic at the start of interrupt processing are stored in the predetermined area of the memory,
An interrupt handler that is executed after the second register is set to the first logic is stored in an area excluding the predetermined area of the memory,
The data processing apparatus according to appendix 5, wherein the interrupt handler sets the second register to the second logic at the end of interrupt processing.
(Appendix 7)
The appendix 1 to appendix 6, wherein the memory control unit outputs a busy signal indicating prohibition of access to the memory to the first processor when executing the prohibition control. Data processing equipment.
(Appendix 8)
The second processor includes a buffer that sequentially holds the processing requests, executes the processing requests held in the buffer, deletes the executed processing requests from the buffer, and the buffer becomes full The data processing device according to any one of appendix 1 to appendix 7, wherein the status signal is output.
(Appendix 9)
The data processing device according to any one of appendix 1 to appendix 8, and
A first data processing unit for outputting data for data processing executed by the second processor to the data processing device;
And a second data processing unit for processing data generated by data processing executed by the second processor.
(Appendix 10)
A first processor that outputs a memory access request and a processing request generated using data read from the memory to direct data processing;
A second processor that executes data processing in response to the processing request and outputs a status signal indicating prohibition of acceptance of the processing request to the first processor when a state in which the processing request cannot be accepted occurs. A method of operating the data processing apparatus,
An operation method for a data processing apparatus, comprising: performing prohibition control for prohibiting supply of the access request to the memory when detecting the output of the processing request and the output of the status signal.
(Appendix 11)
11. The operation of the data processing device according to claim 10, wherein when the address included in the access request indicates a predetermined area of the memory, the prohibition control is masked and the access request is supplied to the memory. Method.
(Appendix 12)
Masking the prohibition control when the address output from the first processor is included in the area indicated by the information held in the first register of the first processor, and supplying the access request to the memory The operation method of the data processing device according to appendix 11, characterized by:
(Appendix 13)
When the first processor receives an interrupt request, the first processor executes interrupt processing using an interrupt vector and an interrupt handler stored in the predetermined area of the memory. A method for operating the data processing apparatus according to claim 1.
(Appendix 14)
APPENDIX 11 or APPENDIX 12 wherein the prohibition control is masked and supply of the access request to the memory is permitted when the second register of the first processor is set to the first logic. A method for operating the data processing apparatus according to claim 1.
(Appendix 15)
When the first processor receives an interrupt request,
Executing an instruction to set the second register stored in the predetermined area of the memory to the first logic;
Using an interrupt vector stored in the predetermined area of the memory, and executing an interrupt handler stored in an area excluding the predetermined area of the memory;
15. The operation method of the data processing apparatus according to appendix 14, wherein the second register is set to the second logic at the end of the interrupt process.
(Appendix 16)
The operation of the data processing device according to any one of appendix 10 to appendix 15, wherein when the prohibition control is executed, a busy signal indicating prohibition of access to the memory is output to the first processor. Method.
(Appendix 17)
The second processor sequentially holds the processing requests, executes the processing requests held in the buffer, deletes the executed processing requests from the buffer, and when the buffer becomes full, the state The method of operating a data processing apparatus according to any one of appendix 1 to appendix 6, wherein a signal is output.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 1 ... Processor; 2 ... Processor; 3 ... Memory; 4 ... Memory control part: 10, 10A, 10B, 10C, 10D ... Processor; 12 ... Coprocessor; 14 ... Instruction memory; 16, 16A, 16B, 16C, 16D ... Memory control unit; AD ... address; BUSY ... busy signal; CON ... control bit; DPD ... data processing device; DT ... data; EN ... access request; MC2, MC1, MC0 ... control bit; MSKCNT2, MSKCNT3 Mask control circuit; QDT queue data; QFUL full signal; QPREQ queue push request; REQ processing request; ST state signal

Claims (6)

A first processor that outputs a memory access request and a processing request generated using data read from the memory to direct data processing;
A second processor that executes data processing in response to the processing request and outputs a status signal indicating prohibition of acceptance of the processing request to the first processor when a state in which the processing request cannot be accepted occurs;
A memory that is arranged between the first processor and the memory and that executes prohibition control for prohibiting the access request from being supplied to the memory when the output of the processing request and the output of the status signal are detected. A data processing apparatus comprising: a control unit. The memory control unit
A mask control circuit that asserts a mask signal when an address included in the access request indicates a predetermined area of the memory;
The data processing apparatus according to claim 1, further comprising: a mask circuit that masks the prohibition control and supplies the access request to the memory when a mask signal is asserted. The first processor includes a first register that holds information indicating the predetermined area in a rewritable manner,
3. The mask control circuit asserts the mask signal when the address output from the first processor is included in an area indicated by information held in the first register. The data processing apparatus described. The said memory control part outputs the busy signal which shows prohibition of the access of the said memory to the said 1st processor, when performing the said prohibition control. The said any one of Claim 1 thru | or 3 characterized by the above-mentioned. The data processing apparatus described in 1. A data processing device according to any one of claims 1 to 4,
A first data processing unit for outputting data for data processing executed by the second processor to the data processing device;
And a second data processing unit for processing data generated by data processing executed by the second processor. A first processor that outputs a memory access request and a processing request generated using data read from the memory to direct data processing;
A second processor that executes data processing in response to the processing request and outputs a status signal indicating prohibition of acceptance of the processing request to the first processor when a state in which the processing request cannot be accepted occurs. A method of operating the data processing apparatus,
Prohibition of prohibiting supply of the access request to the memory when a memory control unit arranged between the first processor and the memory detects the output of the processing request and the output of the status signal A method of operating a data processing apparatus, characterized by executing control.

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