JP5612024B2 - High side current detection circuit - Google Patents

High side current detection circuit Download PDF

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JP5612024B2
JP5612024B2 JP2012126783A JP2012126783A JP5612024B2 JP 5612024 B2 JP5612024 B2 JP 5612024B2 JP 2012126783 A JP2012126783 A JP 2012126783A JP 2012126783 A JP2012126783 A JP 2012126783A JP 5612024 B2 JP5612024 B2 JP 5612024B2
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入江 寿一
寿一 入江
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大光電気株式会社
入江 寿一
寿一 入江
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本発明は、LED(発光ダイオード)の定電流制御等で直流電源のハイサイドに接続された負荷に流れる負荷電流を検出する際、ハイサイドのシャント抵抗(電流検出抵抗)に生じる電流検出電圧を直流電源のローサイドに導くためにカレントミラー回路を使用する場合、直流電源の電圧変動の影響を補償できるハイサイド電流検出回路に関するものである。   In the present invention, when detecting a load current flowing in a load connected to the high side of a DC power source by constant current control of an LED (light emitting diode) or the like, a current detection voltage generated in a high side shunt resistor (current detection resistor) is detected. The present invention relates to a high-side current detection circuit that can compensate for the influence of voltage fluctuations of a DC power supply when a current mirror circuit is used to guide the DC power supply to the low side.

LEDの明るさを一定に保って点灯するとき、LEDのような定電圧特性を持つ負荷を安定に駆動するには、電源電圧が変化しても負荷電流を一定に保つ定電流駆動が適当である。また、LEDのような効率の高い負荷を駆動するには、やはり電力変換効率の高いスイッチング式のDC−DC(直流−直流)コンバータが用いられる。DC−DCコンバータのスイッチング素子として代表的なFET(電界効果トランジスタ)は、普通、直流電源のローサイドに置かれ、これを制御・駆動する制御用ICもローサイドに置かれる。負荷であるLEDはFETと直列にして電源に接続されるので、直流電源のハイサイドに置かれることになる。   In order to stably drive a load with constant voltage characteristics such as an LED when the LED is lit with constant brightness, constant current drive that keeps the load current constant even when the power supply voltage changes is appropriate. is there. In order to drive a load having high efficiency such as an LED, a switching DC-DC (direct current-direct current) converter having high power conversion efficiency is used. A typical FET (field effect transistor) as a switching element of a DC-DC converter is usually placed on the low side of a DC power supply, and a control IC for controlling and driving the FET is also placed on the low side. Since the LED as a load is connected to the power supply in series with the FET, it is placed on the high side of the DC power supply.

前記負荷の電流を定電流制御するためには該負荷の電流を検出することが必要であり、前記負荷電流を検出するための電流検出抵抗は前記負荷のあるハイサイドに置かれる。前記電流検出抵抗の電圧降下すなわち負荷電流に比例した検出電圧はハイサイドが基準となるから、スイッチング素子のオンオフを制御する制御用ICに供給するため,レベルシフト回路を用いてローサイドを基準とする電圧にレベルシフトする必要がある。この場合、レベルシフト回路は電源電圧変動の影響を受けないようにしなければならない。   In order to carry out constant current control of the current of the load, it is necessary to detect the current of the load, and a current detection resistor for detecting the load current is placed on the high side with the load. Since the voltage drop of the current detection resistor, that is, the detection voltage proportional to the load current is based on the high side, in order to supply it to the control IC that controls the on / off of the switching element, the low side is referenced using a level shift circuit. It is necessary to level shift to voltage. In this case, the level shift circuit must be free from the influence of power supply voltage fluctuations.

電流検出抵抗の電圧降下は電力損失となるので小さいことが望ましく、通常は1ボルト以下となるような低抵抗が用いられる。前記直流電源の電源電圧はハイサイドとローサイドとの電位差で、代表的な値は100ボルト程度である。したがって、電流検出抵抗の電圧を1パーセントの精度で前記制御用ICに供給するために、前記レベルシフト回路が受ける電源電圧の影響は0.1パーセント以下にする必要があり、レベルシフト回路には電源電圧の影響が小さく精度の高い回路が望ましい。   Since the voltage drop of the current detection resistor causes power loss, it is desirable that the voltage drop be small, and a low resistance that is usually 1 volt or less is used. The power supply voltage of the DC power supply is a potential difference between the high side and the low side, and a typical value is about 100 volts. Therefore, in order to supply the voltage of the current detection resistor to the control IC with 1% accuracy, the influence of the power supply voltage received by the level shift circuit needs to be 0.1% or less. A highly accurate circuit that is less affected by the power supply voltage is desirable.

そのような電源電圧の影響が小さく精度の高いレベルシフト回路として、一般に、2つのトランジスタのエミッタにそれぞれ抵抗を接続し、一方の抵抗を電流検出抵抗とするカレントミラー回路が用いられる。しかし、カレントミラー回路は参照電流が電源電圧で変化し、加えてアーリ効果の影響で電源電圧変動の影響を受ける。こうした電源電圧変動の影響を補償するには簡単で効果のある補償が望ましい。   As such a level shift circuit that is less affected by the power supply voltage and has high accuracy, a current mirror circuit is generally used in which resistors are connected to the emitters of two transistors, and one of the resistors is a current detection resistor. However, in the current mirror circuit, the reference current changes with the power supply voltage, and in addition, the current mirror circuit is affected by the power supply voltage fluctuation due to the Early effect. Simple and effective compensation is desirable to compensate for the effect of such power supply voltage fluctuations.

〔従来回路〕
図5は直流電源とDC−DCコンバータとLED等の負荷とこの負荷に流れる負荷電流を検出する従来のハイサイド電流検出回路とを示す。従来のハイサイド電流検出回路によって負荷電流を検出して、負荷電流を定電流制御する。図5において、1はPWM制御回路、2はDC−DCコンバータ、3はカレントミラー回路を使用するハイサイド電流検出回路である。
[Conventional circuit]
FIG. 5 shows a DC power supply, a DC-DC converter, a load such as an LED, and a conventional high-side current detection circuit for detecting a load current flowing through the load. A load current is detected by a conventional high-side current detection circuit, and the load current is controlled at a constant current. In FIG. 5, 1 is a PWM control circuit, 2 is a DC-DC converter, and 3 is a high-side current detection circuit using a current mirror circuit.

従来のハイサイド電流検出回路3では、ハイサイドにあるシャント抵抗である電流検出抵抗R1によりDC−DCコンバータ2の負荷電流I0を検出する。DC−DCコンバータ2はスイッチング素子Qsw、環流ダイオードD1、リアクトルL1、及び平滑コンデンサC1より成り、負荷Lに制御された電力を供給する。直流電源V1の電源電圧はV1であり、ハイサイドをP、ローサイドをGで表す。   In the conventional high side current detection circuit 3, the load current I0 of the DC-DC converter 2 is detected by a current detection resistor R1 which is a shunt resistor on the high side. The DC-DC converter 2 includes a switching element Qsw, a freewheeling diode D1, a reactor L1, and a smoothing capacitor C1, and supplies controlled electric power to a load L. The power supply voltage of the DC power supply V1 is V1, and the high side is represented by P and the low side is represented by G.

負荷電流の定電流制御では、制御用ICから成るPWM制御回路1は、ハイサイド電流検出回路3で検出された検出出力V2が一定になるようにスイッチング素子Qswのオンオフを制御する。電流検出抵抗R1は負荷電流Ioを検出するシャント抵抗であると同時にカレントミラー回路の一部に含めることができる。   In the constant current control of the load current, the PWM control circuit 1 including the control IC controls the on / off of the switching element Qsw so that the detection output V2 detected by the high side current detection circuit 3 is constant. The current detection resistor R1 is a shunt resistor that detects the load current Io and can be included in a part of the current mirror circuit.

電流検出回路3は、カレントミラー回路の参照トランジスタQ1と出力トランジスタQ2とを含み、電流検出抵抗R1に負荷電流Ioを流さなければ出力電流I2は参照電流I1に比例する。ハイサイド電流検出回路3では、参照トランジスタQ1のエミッタに接続した電流検出抵抗R1を電流検出のシャント抵抗とし、出力トランジスタQ2のエミッタには比例抵抗R2を接続し、参照トランジスタQ1にはコレクタ抵抗R1cによって参照電流I1を流し、出力トランジスタQ2のコレクタ電流I2はコレクタ抵抗R2cにより検出出力V2を与える。   The current detection circuit 3 includes a reference transistor Q1 and an output transistor Q2 of a current mirror circuit. If the load current Io does not flow through the current detection resistor R1, the output current I2 is proportional to the reference current I1. In the high-side current detection circuit 3, a current detection resistor R1 connected to the emitter of the reference transistor Q1 is used as a shunt resistor for current detection, a proportional resistor R2 is connected to the emitter of the output transistor Q2, and a collector resistor R1c is connected to the reference transistor Q1. Causes the reference current I1 to flow, and the collector current I2 of the output transistor Q2 gives the detection output V2 by the collector resistor R2c.

回路条件は、参照電流I1及び出力電流I2を負荷電流Ioよりも十分小さい電流値とするために、電流検出抵抗R1の抵抗値R1を比例抵抗R2の抵抗値R2より十分小さくR1<<R2とし、電流検出抵抗R1での電圧降下Io・R1を電源電圧V1より十分小さくIo・R1<<V1とし、トランジスタQ1,Q2はいずれも電流増幅率が大きくベース電流はエミッタ電流に比べて無視できるものとする。   The circuit condition is that the resistance value R1 of the current detection resistor R1 is sufficiently smaller than the resistance value R2 of the proportional resistor R2 so that the reference current I1 and the output current I2 are sufficiently smaller than the load current Io, and R1 << R2. The voltage drop Io · R1 at the current detection resistor R1 is sufficiently smaller than the power supply voltage V1 to be Io · R1 << V1, and the transistors Q1 and Q2 both have a large current amplification factor and the base current is negligible compared to the emitter current. And

カレントミラー回路の基本動作は、ハイサイドから見た2つのトランジスタQ1、Q2のエミッタ電圧が等しくなるように出力電流I2が流れるので各抵抗R1、R2での電圧降下は等しく、次式(1)が成立する。   The basic operation of the current mirror circuit is that the output current I2 flows so that the emitter voltages of the two transistors Q1 and Q2 as seen from the high side are equal. Therefore, the voltage drops at the resistors R1 and R2 are equal. Is established.

Io・R1=I2・R2 …(1)
式(1)より出力トランジスタQ2のコレクタ電流I2は、次式(2)で与えられる。
Io · R1 = I2 · R2 (1)
From the equation (1), the collector current I2 of the output transistor Q2 is given by the following equation (2).

I2=(R1/R2)Io…(2)
これにより出力トランジスタQ2のコレクタ電流I2は、負荷電流Ioに比例し、出力トランジスタQ2のコレクタ抵抗R2cにはローサイドGを基準とした検出出力V2が得られ、その検出出力V2は、次式(3)で与えられる。
I2 = (R1 / R2) Io (2)
As a result, the collector current I2 of the output transistor Q2 is proportional to the load current Io, and the detection output V2 with respect to the low side G is obtained for the collector resistance R2c of the output transistor Q2. The detection output V2 is expressed by the following equation (3 ).

V2=I2・R2c=(R2c/R2)Io・R1…(3)
式(3)から、参照電流I1は、検出出力V2には含まれず、トランジスタQ1,Q2に適当な動作点を与えるための電流となる。
V2 = I2 · R2c = (R2c / R2) Io · R1 (3)
From the equation (3), the reference current I1 is not included in the detection output V2, but becomes a current for giving an appropriate operating point to the transistors Q1 and Q2.

回路はI1≠I2であるため2つのトランジスタQ1.Q2のベース・エミッタ間電圧に違いがあり、厳密には式(2)が成立せず、誤差を生じる。中でも電源電圧V1の変動の影響が検出電流I2に現れると、負荷を定電流制御する際、電源電圧V1によって検出電流I2が変化するので好ましくない。以下、図5の動作をやや詳しく述べる。   Since the circuit is I1 ≠ I2, the two transistors Q1. There is a difference in the base-emitter voltage of Q2, and strictly speaking, equation (2) does not hold and an error occurs. In particular, when the influence of the fluctuation of the power supply voltage V1 appears in the detection current I2, it is not preferable because the detection current I2 changes depending on the power supply voltage V1 when the load is controlled at a constant current. Hereinafter, the operation of FIG. 5 will be described in some detail.

〔従来回路の解析〕
トランジスタQ1、Q2は互いのベースが共通に接続されているのでハイサイドPから見た前記両ベースにおける電位が等しく、電流検出抵抗R1に流れる参照電流I1を無視すると
VBE1+IoR1=VBE2+I2R2…(4)
ただし、VBE1:Q1のベース電圧、VBE2:Q2のベース電圧、
コレクタ抵抗R1cの両端間電圧はほぼ電源電圧V1に等しいので流れる参照電流I1は、コレクタ抵抗R1cの抵抗値をR1cとして次式(5)で与えられる。
[Analysis of conventional circuit]
Since the bases of the transistors Q1 and Q2 are connected in common, the potentials at both bases viewed from the high side P are equal, and the reference current I1 flowing through the current detection resistor R1 is ignored.
VBE1 + IoR1 = VBE2 + I2R2 (4)
However, VBE1: Q1 base voltage, VBE2: Q2 base voltage,
Since the voltage across the collector resistor R1c is substantially equal to the power supply voltage V1, the flowing reference current I1 is given by the following equation (5), where the resistance value of the collector resistor R1c is R1c.

I1=V1/R1c…(5)
式(4)を整理し、出力電流I2をI2R2で表すと次式(6)のようになる。
I1 = V1 / R1c (5)
When the expression (4) is arranged and the output current I2 is expressed by I2R2, the following expression (6) is obtained.

I2R2=IoR1+VBE1−VBE2 …(6)
式(6)における右辺第1項IoR1は、信号成分である。VBE1−VBE2は誤差を表す。
I2R2 = IoR1 + VBE1-VBE2 (6)
The first term IoR1 on the right side in Equation (6) is a signal component. VBE1-VBE2 represents an error.

各トランジスタQ1,Q2のベース電圧VBE1、VBE2はそれぞれコレクタ電流I1、I2の対数に比例し、次式(7)(8)が成立する。   The base voltages VBE1 and VBE2 of the transistors Q1 and Q2 are proportional to the logarithm of the collector currents I1 and I2, respectively, and the following equations (7) and (8) are established.

VBE1≒(kT/q)ln(I1/IS1)…(7)
VBE2≒(kT/q)ln(I2/IS2)…(8)
ただし、(kT/q):定数、Is1:Q1の飽和電流、Is2:Q2の飽和電流、k:ボルツマン定数、T:絶対温度、q:電子の電荷である。
VBE1≈ (kT / q) ln (I1 / IS1) (7)
VBE2≈ (kT / q) ln (I2 / IS2) (8)
However, (kT / q): constant, Is1: Q1 saturation current, Is2: Q2 saturation current, k: Boltzmann constant, T: absolute temperature, q: electron charge.

式(6)に式(7)、(8)を代入すると、次式(9)が成立する。   Substituting the equations (7) and (8) into the equation (6), the following equation (9) is established.

I2R2=IoR1+(kT/q)ln(I1/IS1)
−(kT/q)ln(I2/IS2)
=IoR1+(kT/q){ln(I1)−ln(I2)
−ln(IS1)+ln(IS2)}…(9)
アーリ効果はトランジスタのコレクタ電圧によってコレクタ電流が変化する現象を云い、次のように飽和電流の変化で説明される。出力トランジスタQ2の飽和電流IS2はコレクタ電圧VBCの関数となり、VAF:アーリ電圧、IS2(0):VBC=0のときのIS2で表すと、飽和電流IS2は次式(10)のように変化する。
I2R2 = IoR1 + (kT / q) ln (I1 / IS1)
-(KT / q) ln (I2 / IS2)
= IoR1 + (kT / q) {ln (I1) -ln (I2)
−ln (IS1) + ln (IS2)} (9)
The Early effect is a phenomenon in which the collector current changes depending on the collector voltage of the transistor, and is explained by the change in saturation current as follows. The saturation current IS2 of the output transistor Q2 is a function of the collector voltage VBC. When expressed as IS2 when VAF: Early voltage and IS2 (0): VBC = 0, the saturation current IS2 changes as shown in the following equation (10). .

IS2=IS2(0)(1+VBC/VAF)…(10)
両トランジスタQ1、Q2は同じ特性でIS1=IS2(0)=ISとし、I2R2<<V1かつV2<<V1であってV1≒VBCとして、式(9)のI1に式(5)、IS2には式(10)を代入すると、次式(11)が成立する。
IS2 = IS2 (0) (1 + VBC / VAF) (10)
Both transistors Q1 and Q2 have the same characteristics, IS1 = IS2 (0) = IS, I2R2 << V1 and V2 << V1, and V1≈VBC, so that I1 in Equation (9) is changed to Equations (5) and IS2. Substituting equation (10), the following equation (11) is established.

I2R2=IoR1−(kT/q)ln(R1C)
−(kT/q)ln(I2)+(kT/q)ln(V1)
+(kT/q)ln(1+V1/VAF) …(11)
式(11)の右辺第1項は信号成分、第2項は一定値となり、第3項はI2の関数であるから非線形成分、第4項はR1cを通じてのV1の変動成分、第5項はアーリ効果によるV1の変動成分である。R1cの値はV1の変動成分には関係しない。非線形は定電流制御には悪影響がない。
I2R2 = IoR1- (kT / q) ln (R1C)
-(KT / q) ln (I2) + (kT / q) ln (V1)
+ (KT / q) ln (1 + V1 / VAF) (11)
The first term on the right side of equation (11) is a signal component, the second term is a constant value, the third term is a function of I2, so it is a nonlinear component, the fourth term is the fluctuation component of V1 through R1c, and the fifth term is It is a fluctuation component of V1 due to the Early effect. The value of R1c is not related to the fluctuation component of V1. Non-linearity has no adverse effect on constant current control.

〔従来回路の特性〕
従来回路の電流検出特性の例として、図5においてR1=0.5Ω、R2=1kΩ、R2c=1kΩ、R1c=100kΩとし、V1=90V±20VにおけるV2−Io特性を図6に示す。図6は横軸に負荷電流Io、縦軸に検出出力V2をとる電流検出特性を示す。図6において、V1中は電源電圧V1の大きさが中、V1大は電源電圧V1の大きさが大、V1小は電源電圧V1の大きさが小の場合のそれぞれの電流検出特性を示す。図6で示すように、電源電圧V1の大きさが大、中、小に変動したときV1の影響が検出出力V2に現れているのが見られる。
[Conventional circuit characteristics]
As an example of the current detection characteristic of the conventional circuit, FIG. 6 shows the V2-Io characteristic at V1 = 90 V ± 20 V, with R1 = 0.5Ω, R2 = 1 kΩ, R2c = 1 kΩ, and R1c = 100 kΩ in FIG. FIG. 6 shows current detection characteristics in which the horizontal axis represents the load current Io and the vertical axis represents the detection output V2. In FIG. 6, the current detection characteristics when the power supply voltage V1 is medium during V1, large V1 when the power supply voltage V1 is large, and small V1 are when the power supply voltage V1 is small. As shown in FIG. 6, it can be seen that the influence of V1 appears in the detection output V2 when the magnitude of the power supply voltage V1 varies from large to medium to small.

従来回路の中にはカレントミラー回路の参照電流を定電流回路から得るようにして、コレクタ抵抗R1cを通じて発生する電源電圧V1の影響を減少したものもある。(特許文献1、図7)
しかしながら、特許文献1の回路に示された定電流源は回路構成が複雑であったり、損失が大きかったりするなどするし、また,出力トランジスタQ2のアーリ効果による電源電圧V1の影響はこの定電流源で取り除くことは出来ない。
Some conventional circuits reduce the influence of the power supply voltage V1 generated through the collector resistor R1c by obtaining the reference current of the current mirror circuit from the constant current circuit. (Patent Document 1, FIG. 7)
However, the constant current source shown in the circuit of Patent Document 1 has a complicated circuit configuration or a large loss, and the influence of the power supply voltage V1 due to the Early effect of the output transistor Q2 is the constant current source. It cannot be removed at the source.

特開平11−160368号公報JP-A-11-160368

本発明は、上述に鑑みてなされたものであり、簡単な回路構成にて、電源電圧の変動の影響がカレントミラー回路の検出出力電圧に現れることを補償することを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to compensate for the influence of fluctuations in the power supply voltage appearing in the detected output voltage of the current mirror circuit with a simple circuit configuration.

上記目的を達成するための本発明第1に係るハイサイド電流検出回路は、直流電源のハイサイドに負荷を接続したDC−DCコンバータにおいて、電流検出抵抗を直流電源のハイサイドと負荷の間に挿入し、第1及び第2のトランジスタのベースと第1のトランジスタのコレクタを共通に接続したカレントミラー回路の、前記第1のトランジスタのエミッタを電流検出抵抗の一端に接続しかつコレクタは第1のコレクタ抵抗を通じて前記直流電源のローサイドに接続し、前記第2のトランジスタのエミッタは比例抵抗を通じて前記電流検出抵抗の他端とともに前記直流電源のハイサイドに接続し、前記第2のトランジスタのコレクタは、第2のコレクタ抵抗を通じて前記直流電源のローサイドに接続し、前記電流検出抵抗に流れる被検出電流に比例した検出出力電圧を前記第2のコレクタ抵抗に得るハイサイド電流検出回路であって、前記第2のトランジスタのエミッタと前記直流電源のローサイドとの間に補償抵抗を接続するとともに、前記補償抵抗の抵抗値を所定の値として前記比例抵抗に電源電圧に比例した補償電流を与えることにより、前記直流電源の電源電圧変動の影響を補償することを特徴とする。 In order to achieve the above object, a high-side current detection circuit according to the first aspect of the present invention is a DC-DC converter in which a load is connected to the high side of a DC power supply , and a current detection resistor is provided between the high side of the DC power supply and the load. The emitter of the first transistor is connected to one end of the current detection resistor of the current mirror circuit inserted and commonly connected to the bases of the first and second transistors and the collector of the first transistor, and the collector is the first The collector of the second transistor is connected to the low side of the DC power source through the collector resistor, the emitter of the second transistor is connected to the high side of the DC power source together with the other end of the current detection resistor through the proportional resistor, and the collector of the second transistor is , through a second collector resistor connected to the low side of the DC power supply, the current to be detected flowing before Symbol current detection resistor A high-side current detection circuit for obtaining a proportional detection output voltage at the second collector resistor, wherein a compensation resistor is connected between an emitter of the second transistor and a low side of the DC power supply, and the compensation resistor A compensation current proportional to the power supply voltage is applied to the proportional resistance with a predetermined resistance value, thereby compensating for the influence of fluctuations in the power supply voltage of the DC power supply.

本発明第2に係るハイサイド電流検出回路は、直流電源のハイサイドに負荷を接続したDC−DCコンバータにおいて、電流検出抵抗を直流電源のハイサイドと負荷の間に挿入し、第1及び第2のトランジスタのベースと第1のトランジスタのコレクタを共通に接続したカレントミラー回路の、前記第1のトランジスタのエミッタを電流検出抵抗の一端に接続しかつコレクタは第1のコレクタ抵抗を通じて負荷のローサイド端子に接続し、前記第2のトランジスタのエミッタは比例抵抗を通じて前記電流検出抵抗の他端とともに前記直流電源のハイサイドに接続し、前記第2のトランジスタのコレクタは第2のコレクタ抵抗を通じて前記直流電源のローサイドに接続し、前記電流検出抵抗に流れる被検出電流に比例した検出出力電圧を前記第2のコレクタ抵抗に得ることを特徴とするハイサイド電流検出回路であって、前記第2のトランジスタのエミッタと前記直流電源のローサイドとの間に補償抵抗を接続することにより、前記検出出力電圧に与える前記直流電源の電源電圧変動の影響を補償することを特徴とする。 The high-side current detection circuit according to the second aspect of the present invention is a DC-DC converter in which a load is connected to the high side of a DC power supply, and a current detection resistor is inserted between the high side of the DC power supply and the load . In the current mirror circuit in which the base of the two transistors and the collector of the first transistor are connected in common, the emitter of the first transistor is connected to one end of the current detection resistor, and the collector is connected to the low side of the load through the first collector resistor. And the emitter of the second transistor is connected to the high side of the DC power supply together with the other end of the current detection resistor through a proportional resistor, and the collector of the second transistor is connected to the DC through a second collector resistor. connected to a power supply low-side, the detection output voltage proportional to the detected current flowing before Symbol current detection resistor a A high-side current detection circuit, wherein the obtaining of the collector resistor, by connecting a compensation resistor to the low side of the emitter and the DC power source of said second transistor, given to the detection output voltage Compensating for the influence of power supply voltage fluctuations of the DC power supply.

参考回路として、第1のトランジスタのコレクタ電流である参照電流の変動を無くするために従来使用されていた定電流回路を使用せず、定電流制御されている負荷端子から抵抗を通して第1のトランジスタのコレクタ電流を供給することで、電源電圧変動の影響を軽減するものがある。本発明第2は、この参考回路に電圧補償を適用し、前記第2のトランジスタのエミッタと前記直流電源のローサイドとの間に補償抵抗を接続することにより、前記検出出力電圧に与える前記直流電源の電源電圧変動の影響を補償する。As a reference circuit, the first transistor is passed through a resistor from a load terminal under constant current control without using a constant current circuit which has been conventionally used in order to eliminate the fluctuation of the reference current which is the collector current of the first transistor. There are some which reduce the influence of power supply voltage fluctuations by supplying a collector current. The second aspect of the present invention applies the voltage compensation to the reference circuit, and connects the compensation resistor between the emitter of the second transistor and the low side of the direct current power supply to provide the direct current power supply to the detected output voltage. To compensate for the effects of power supply voltage fluctuations.

本発明によれば、直流電源のハイサイドの電流をローサイドの電圧として検出でき、直流電源の電圧が変動したときに検出出力に与える影響を除くことが出来る。   According to the present invention, the high-side current of the DC power supply can be detected as a low-side voltage, and the influence on the detection output when the voltage of the DC power supply fluctuates can be eliminated.

本発明の第1の実施形態に係るハイサイド電流検出回路の回路図。1 is a circuit diagram of a high-side current detection circuit according to a first embodiment of the present invention. 図1の電流検出特性を示す図。The figure which shows the electric current detection characteristic of FIG. 参考回路に係るハイサイド電流検出回路の回路図。The circuit diagram of the high side current detection circuit which concerns on a reference circuit . の実施形態に係るハイサイド電流検出回路の回路図。The circuit diagram of the high side current detection circuit concerning a 2nd embodiment. 従来のハイサイド電流検出回路の回路図。The circuit diagram of the conventional high side current detection circuit. 図5の電流検出特性を示す図。The figure which shows the electric current detection characteristic of FIG. 参照電流を定電流回路で供給する従来の回路図。The conventional circuit diagram which supplies a reference current with a constant current circuit.

以下、添付した図面を参照して本発明の実施形態に係るハイサイド電流検出回路を詳細に説明する。   Hereinafter, a high-side current detection circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

〔第1の実施形態〕
図1を参照して、本発明の第1の実施形態に係るハイサイド電流検出回路を説明する。図1において、V1は直流電源、1はPWM(パルス幅変調)制御回路、2はDC−DCコンバータ、3はカレントミラー回路を含むハイサイド電流検出回路である。
[First Embodiment]
With reference to FIG. 1, a high-side current detection circuit according to a first embodiment of the present invention will be described. In FIG. 1, V1 is a DC power source, 1 is a PWM (pulse width modulation) control circuit, 2 is a DC-DC converter, and 3 is a high-side current detection circuit including a current mirror circuit.

PWM制御回路1は、内部に安定化電源を内蔵した制御用ICからなる。   The PWM control circuit 1 is composed of a control IC having a built-in stabilized power supply.

DC−DCコンバータ2は、MOSFETからなるスイッチング素子Qsw、環流ダイオードD1、リアクトルL1、及び平滑コンデンサC1より成り、負荷Lに対し制御された電力を供給する。スイッチング素子Qswのドレインは、環流ダイオードD1のアノードとリアクトルL1の一端側との接続ノードに接続され、環流ダイオードD1のカソードはハイサイドPに接続される。スイッチング素子QswのソースはローサイドGに接続される。リアクトルL1の他端側は平滑コンデンサC1の一端側と負荷Lの一端側との接続ノードに接続され、平滑コンデンサC1の他端側はハイサイドPに接続される。   The DC-DC converter 2 includes a switching element Qsw made of a MOSFET, a freewheeling diode D1, a reactor L1, and a smoothing capacitor C1, and supplies controlled electric power to a load L. The drain of the switching element Qsw is connected to a connection node between the anode of the freewheeling diode D1 and one end of the reactor L1, and the cathode of the freewheeling diode D1 is connected to the high side P. The source of the switching element Qsw is connected to the low side G. The other end side of the reactor L1 is connected to a connection node between one end side of the smoothing capacitor C1 and one end side of the load L, and the other end side of the smoothing capacitor C1 is connected to the high side P.

なお、DC−DCコンバータ2は、図示例に限定されるものではなく、スイッチング素子を備え、ハイサイド電流検出回路3で検出された検出出力V2が一定になるようにスイッチング素子のオンオフをPWM制御回路1により制御して、直流−直流変換できるものであればよい。以下の実施形態においても同様である。   The DC-DC converter 2 is not limited to the illustrated example, and includes a switching element, and PWM control of on / off of the switching element is performed so that the detection output V2 detected by the high-side current detection circuit 3 is constant. Any device can be used as long as it can be controlled by the circuit 1 to perform DC-DC conversion. The same applies to the following embodiments.

カレントミラー回路は、ベースコレクタが接続されたPNP型の参照トランジスタ(第1のトランジスタ)Q1と、参照トランジスタQ1のベースにベースが接続されたPNP型の出力トランジスタ(第2のトランジスタ)Q2とを含む。   The current mirror circuit includes a PNP-type reference transistor (first transistor) Q1 having a base collector connected thereto, and a PNP-type output transistor (second transistor) Q2 having a base connected to the base of the reference transistor Q1. Including.

参照トランジスタQ1のエミッタは、電流検出抵抗R1を介してハイサイドPに接続される。参照トランジスタQ1のエミッタはまた、負荷Lの他端側に接続される。参照トランジスタQ1のコレクタは、コレクタ抵抗R1Cを介してローサイドGに接続される。   The emitter of the reference transistor Q1 is connected to the high side P via the current detection resistor R1. The emitter of the reference transistor Q1 is also connected to the other end of the load L. The collector of the reference transistor Q1 is connected to the low side G via the collector resistor R1C.

出力トランジスタQ2のエミッタは比例抵抗R2を介してハイサイドPに接続され、また、コレクタはコレクタ抵抗R2Cを介してローサイドGに接続される。出力トランジスタQ2のコレクタはまた、PWM制御回路1の入力部INに接続される。PWM制御回路1の出力部OUTはDC−DCコンバータ2のスイッチング素子Qswのゲートに接続される。   The emitter of the output transistor Q2 is connected to the high side P via a proportional resistor R2, and the collector is connected to the low side G via a collector resistor R2C. The collector of the output transistor Q2 is also connected to the input section IN of the PWM control circuit 1. The output part OUT of the PWM control circuit 1 is connected to the gate of the switching element Qsw of the DC-DC converter 2.

カレントミラー回路において、参照トランジスタQ1のエミッタは電流検出抵抗R1の一端に接続されかつコレクタはコレクタ抵抗Rc1を通じて直流電源V1のローサイドに接続され、出力トランジスタQ2のエミッタは比例抵抗R2を通じて電流検出抵抗R1の他端とともに直流電源V1のハイサイドに接続され、出力トランジスタQ2のコレクタは、コレクタ抵抗Rc2を通じて直流電源V1のローサイドに接続され、電流検出抵抗R1は負荷Lに直列に挿入されている。   In the current mirror circuit, the emitter of the reference transistor Q1 is connected to one end of the current detection resistor R1, the collector is connected to the low side of the DC power supply V1 through the collector resistor Rc1, and the emitter of the output transistor Q2 is connected to the current detection resistor R1 through the proportional resistor R2. Is connected to the high side of the DC power source V1 together with the other end of the output transistor Q2, the collector of the output transistor Q2 is connected to the low side of the DC power source V1 through the collector resistor Rc2, and the current detection resistor R1 is inserted in series with the load L.

そして、定電流制御では、PWM制御回路1は、前記したように、内部に安定化電源を内蔵した制御用ICであり、電源電圧V1が変動しても安定動作が可能であり、電流検出出力V2(出力トランジスタQ2のコレクタ電位)が一定になるようにDC−DCコンバータ2のスイッチング素子Qswのオンオフを制御する。電流検出抵抗R1は、負荷Lを流れる負荷電流Ioを検出するシャント抵抗であり、カレントミラー回路の一部でもある。   In the constant current control, as described above, the PWM control circuit 1 is a control IC with a built-in stabilized power supply, and can operate stably even when the power supply voltage V1 fluctuates. The on / off of the switching element Qsw of the DC-DC converter 2 is controlled so that V2 (the collector potential of the output transistor Q2) becomes constant. The current detection resistor R1 is a shunt resistor that detects the load current Io flowing through the load L, and is also a part of the current mirror circuit.

電流検出抵抗R1に負荷電流Ioが流れなければ出力トランジスタQ2のコレクタから流出する出力電流I2は、参照トランジスタQ1のコレクタから流出する参照電流I1に比例し、カレントミラー回路を構成する。参照電流I1は参照トランジスタQ1のコレクタからコレクタ抵抗R1Cに流れ、出力電流I2は出力トランジスタQ2のコレクタからコレクタ抵抗R2cを流れ、検出出力V2を与える。検出出力V2はPWM制御回路1の入力部INに入力される。   If the load current Io does not flow through the current detection resistor R1, the output current I2 flowing out from the collector of the output transistor Q2 is proportional to the reference current I1 flowing out from the collector of the reference transistor Q1, and forms a current mirror circuit. The reference current I1 flows from the collector of the reference transistor Q1 to the collector resistor R1C, and the output current I2 flows from the collector of the output transistor Q2 to the collector resistor R2c to give the detection output V2. The detection output V2 is input to the input unit IN of the PWM control circuit 1.

本実施形態では、カレントミラー回路を使用したハイサイド電流検出回路3に補償抵抗Rcmpを追加接続し、補償抵抗Rcmpを通じて電源電圧V1に比例した補償電流I3を比例抵抗R2に流すことで、電源電圧V1の変動を補償するようにしたことを特徴とする。   In the present embodiment, a compensation resistor Rcmp is additionally connected to the high-side current detection circuit 3 using a current mirror circuit, and a compensation current I3 proportional to the power supply voltage V1 is passed through the compensation resistor Rcmp to the proportional resistor R2, thereby supplying the power supply voltage. It is characterized in that the fluctuation of V1 is compensated.

式で表すと前記した式(11)の左辺の出力電流I2は(I2+I3)となるので、次式(12)が成立する。   When expressed by the equation, since the output current I2 on the left side of the above equation (11) is (I2 + I3), the following equation (12) is established.

(I2+I3)R2=IoR1−(kT/q)ln(R1C)
−(kT/q)ln(I2)+(kT/q)ln(V1)
+(kT/q)ln(1+V1/VAF) …(12)
式(12)にI3=V1/Rcmpを代入すると、次式(13)が成立する。
(I2 + I3) R2 = IoR1- (kT / q) ln (R1C)
-(KT / q) ln (I2) + (kT / q) ln (V1)
+ (KT / q) ln (1 + V1 / VAF) (12)
Substituting I3 = V1 / Rcmp into equation (12), the following equation (13) is established.

I2R2=IoR1−(kT/q)lnR1C−(kT/q)lnI2
+(kT/q)ln(V1)+(kT/q)ln(1+V1/VAF)
−V1R2/Rcmp…(13)
式(13)の右辺第4、5項は電源電圧V1に対して(+)であるが、同右辺第6項Rcmpの項は電源電圧V1に対して(−)であるから、補償抵抗Rcmpを所定の値とすれば電源電圧V1の変動を補償することができる。
I2R2 = IoR1- (kT / q) lnR1C- (kT / q) lnI2
+ (KT / q) ln (V1) + (kT / q) ln (1 + V1 / VAF)
-V1R2 / Rcmp (13)
The fourth and fifth terms on the right side of the expression (13) are (+) with respect to the power supply voltage V1, but the term of the sixth term Rcmp on the right side is (−) with respect to the power supply voltage V1, so the compensation resistance Rcmp If the value is set to a predetermined value, the fluctuation of the power supply voltage V1 can be compensated.

式(13)をV1で微分し、dI2/dV1=0とすると次式(14)が成立する。   When the equation (13) is differentiated by V1 and dI2 / dV1 = 0, the following equation (14) is established.

R2/Rcmp=(kT/q){1/V1+1/(VAF+V1)}
…(14)
この式(14)により補償抵抗Rcmpの最適値が決められる。先の定数でV1=90V、VAF=100Vとすれば、補償抵抗Rcmpの最適値は2.2MΩとなる。
R2 / Rcmp = (kT / q) {1 / V1 + 1 / (VAF + V1)}
... (14)
The optimum value of the compensation resistance Rcmp is determined by this equation (14). If V1 = 90V and VAF = 100V with the above constants, the optimum value of the compensation resistor Rcmp is 2.2 MΩ.

図2は横軸に負荷電流Io、縦軸に検出出力V2をとって、補償抵抗Rcmpの抵抗値が2.2MΩである場合の電流検出特性を示す。図2において、V1中は電源電圧V1の大きさが中の場合の電流検出特性を示し、V1大は電源電圧V1の大きさが大の場合の電流検出特性を示し、V1小は電源電圧V1の大きさが小の場合の電流検出特性を示す。図2では電源電圧V1の大きさが大、中、小に変動しても、電流検出特性は変化していないので、本実施形態では補償抵抗Rcmpを設けることにより電源電圧V1変動の影響がほぼ完全に補償されることが明らかである。   FIG. 2 shows current detection characteristics when the resistance value of the compensation resistor Rcmp is 2.2 MΩ, with the load current Io on the horizontal axis and the detection output V2 on the vertical axis. In FIG. 2, V1 indicates current detection characteristics when the power supply voltage V1 is medium, V1 large indicates current detection characteristics when the power supply voltage V1 is large, and V1 small indicates power supply voltage V1. The current detection characteristic when the magnitude of is small is shown. In FIG. 2, even if the power supply voltage V1 varies from large to medium to small, the current detection characteristic does not change. Therefore, in this embodiment, the compensation resistor Rcmp is provided so that the influence of the power supply voltage V1 is almost unchanged. It is clear that it is fully compensated.

なお、V1=90V±20Vの場合、負荷電流Ioが1(A)のとき式(13)の右辺第1項の検出電圧500mVに対して、電源電圧V1による変動量は同右辺第4項のR1cを通じて12mV、同右辺第5項アーリ電圧が6mV、同右辺第6項Rcmpによる補償電圧は−18mVとなっている。これにより補償抵抗Rcmpを通じて電源電圧V1の変動に比例した補償電流I3を比例抵抗R2に流すことで、電源電圧V1による変動は補償される。   When V1 = 90V ± 20V, when the load current Io is 1 (A), the amount of fluctuation due to the power supply voltage V1 is the same as the fourth term on the right side of the detected voltage 500 mV in the first term on the right side of Equation (13). Through R1c, 12 mV, the fifth term Early voltage on the right side is 6 mV, and the compensation voltage based on the sixth term Rcmp on the right side is −18 mV. Thus, the fluctuation due to the power supply voltage V1 is compensated by causing the compensation current I3 proportional to the fluctuation of the power supply voltage V1 to flow through the compensation resistance Rcmp to the proportional resistance R2.

参考回路
図3は、参考回路を示すものである。従来回路である図5の参照電流I1を流すコレクタ抵抗R1cの接続点を、電源のローサイドGから負荷電圧Voのローサイド(DC−DCコンバータ2の平滑コンデンサC1とリアクトルL1との接続ノード)に変更したものである。負荷Lが定電圧駆動される場合に限らず、定電流駆動される場合も負荷電圧Voはほぼ一定となっており、電源電圧V1の影響は小さくなっている。電源電圧V1が変動した場合も、参照電流I1は一定の電流となる。
[ Reference circuit ]
FIG. 3 shows a reference circuit . The connection point of the collector resistor R1c through which the reference current I1 of FIG. 5 that is the conventional circuit flows is changed from the low side G of the power source to the low side of the load voltage Vo (a connection node between the smoothing capacitor C1 of the DC-DC converter 2 and the reactor L1). It is a thing. The load voltage Vo is substantially constant not only when the load L is driven at a constant voltage but also when driven at a constant current, and the influence of the power supply voltage V1 is small. Even when the power supply voltage V1 varies, the reference current I1 becomes a constant current.

式(13)では右辺第4項のV1が負荷電圧Voとなり、電源電圧V1による変動は同右辺第5項のみとなる。V1=90V±20Vに対する検出量I2R2の変動はアーリ電圧の6mVとなり、従来回路の1/3程度となっている。   In Expression (13), V1 in the fourth term on the right side is the load voltage Vo, and the fluctuation due to the power supply voltage V1 is only in the fifth term on the right side. The fluctuation of the detected amount I2R2 with respect to V1 = 90V ± 20V is 6 mV of the Early voltage, which is about 1/3 of the conventional circuit.

この参考回路ではコレクタ抵抗R1cの接続点を負荷電圧Voのローサイドに変更するのみであるから、回路の複雑さ増加、コスト増加は生じない。 In this reference circuit , since the connection point of the collector resistor R1c is only changed to the low side of the load voltage Vo, the circuit complexity and cost do not increase.

〔第の実施形態〕
図4は、本発明の第の実施形態を示すものである。図3の参考回路に電源電圧V1の変動を補償する補償抵抗Rcmpを追加接続したものである。
Second Embodiment
Figure 4 shows a second embodiment of the present invention. A compensation resistor Rcmp that compensates for fluctuations in the power supply voltage V1 is additionally connected to the reference circuit of FIG.

先の実施例で式(13)の右辺第4項の変動はなくなっており、同右辺第5項の変動を同右辺第6項が補償することになる。補償抵抗Rcmpの値は式(14)より
R2/Rcmp=(kT/q)/(VAF+V1)…(15)
となる。
In the previous embodiment, the variation of the fourth term on the right side of Equation (13) is eliminated, and the variation of the fifth term on the right side is compensated for by the sixth term on the right side. The value of the compensation resistance Rcmp is calculated from the equation (14): R2 / Rcmp = (kT / q) / (VAF + V1) (15)
It becomes.

先の条件ではRcmp=7.3MΩで電源電圧V1の変動を補償できる。   Under the above conditions, the fluctuation of the power supply voltage V1 can be compensated with Rcmp = 7.3 MΩ.

なお、実施形態では参照トランジスタQ1、出力トランジスタQ2を共にPNP型のトランジスタとしたが、NPN型のトランジスタでも同様である。また、実施形態ではカレントミラー回路3はバイポーラトランジスタで構成したが、FETで構成してもよい。   In the embodiment, the reference transistor Q1 and the output transistor Q2 are both PNP type transistors, but the same applies to NPN type transistors. In the embodiment, the current mirror circuit 3 is composed of a bipolar transistor, but may be composed of an FET.

1 PWM制御回路
2 DC−DCコンバータ
3 ハイサイド電流検出回路
Q1 カレントミラー回路の参照トランジスタ(第1のトランジスタ)
Q2 カレントミラー回路の出力トランジスタ(第2のトランジスタ)
R1 電流検出抵抗(シャント抵抗)
R2 比例抵抗
R1c Q1のコレクタ抵抗(参照電流用)
R2c Q2のコレクタ抵抗(検出出力用)
Rcmp 補償抵抗
Io 負荷電流(被検出電流)
I1 カレントミラー回路の参照電流
I2 カレントミラー回路の出力電流
I3 補償電流
V1 直流電源V1の電源電圧
V2 検出出力電圧
Vo 負荷電圧
P 直流電源V1のハイサイド
G 直流電源V1のローサイド
DESCRIPTION OF SYMBOLS 1 PWM control circuit 2 DC-DC converter 3 High side current detection circuit Q1 Reference transistor (1st transistor) of a current mirror circuit
Q2 Output transistor of the current mirror circuit (second transistor)
R1 Current detection resistor (shunt resistor)
R2 proportional resistance R1c Q1 collector resistance (for reference current)
R2c Q2 collector resistance (for detection output)
Rcmp Compensation resistor Io Load current (Detected current)
I1 Reference current of current mirror circuit I2 Output current I3 of current mirror circuit Compensation current V1 Power supply voltage V2 of DC power supply V1 Detection output voltage Vo Load voltage P High side G of DC power supply V1 Low side of DC power supply V1

Claims (2)

直流電源のハイサイドに負荷を接続したDC−DCコンバータにおいて、電流検出抵抗を直流電源のハイサイドと負荷の間に挿入し、第1及び第2のトランジスタのベースと第1のトランジスタのコレクタを共通に接続したカレントミラー回路の、前記第1のトランジスタのエミッタを電流検出抵抗の一端に接続しかつコレクタは第1のコレクタ抵抗を通じて前記直流電源のローサイドに接続し、前記第2のトランジスタのエミッタは比例抵抗を通じて前記電流検出抵抗の他端とともに前記直流電源のハイサイドに接続し、前記第2のトランジスタのコレクタは、第2のコレクタ抵抗を通じて前記直流電源のローサイドに接続し、前記電流検出抵抗に流れる被検出電流に比例した検出出力電圧を前記第2のコレクタ抵抗に得るハイサイド電流検出回路であって、
前記第2のトランジスタのエミッタと前記直流電源のローサイドとの間に補償抵抗を接続するとともに、前記補償抵抗の抵抗値を所定の値として前記比例抵抗に電源電圧に比例した補償電流を与えることにより、前記直流電源の電源電圧変動の影響を補償することを特徴とするハイサイド電流検出回路。
In a DC-DC converter in which a load is connected to the high side of the DC power supply, a current detection resistor is inserted between the high side of the DC power supply and the load, and the bases of the first and second transistors and the collector of the first transistor are connected. The emitter of the first transistor of the current mirror circuit connected in common is connected to one end of a current detection resistor, and the collector is connected to the low side of the DC power supply through the first collector resistor, and the emitter of the second transistor is connected with the other end of the current detection resistance via the proportional resistance to the high side of the DC power source, the collector of the second transistor, through a second collector resistor connected to the low side of the DC power supply, pre-SL current detection A high-side current that obtains a detection output voltage proportional to the current to be detected flowing through the resistor at the second collector resistor. A detection circuit,
By connecting a compensation resistor between the emitter of the second transistor and the low side of the DC power supply, and giving a compensation current proportional to the power supply voltage to the proportional resistor with a resistance value of the compensation resistor as a predetermined value A high-side current detection circuit that compensates for the influence of power supply voltage fluctuations of the DC power supply.
直流電源のハイサイドに負荷を接続したDC−DCコンバータにおいて、電流検出抵抗を直流電源のハイサイドと負荷の間に挿入し、第1及び第2のトランジスタのベースと第1のトランジスタのコレクタを共通に接続したカレントミラー回路の、前記第1のトランジスタのエミッタを電流検出抵抗の一端に接続しかつコレクタは第1のコレクタ抵抗を通じて負荷のローサイド端子に接続し、前記第2のトランジスタのエミッタは比例抵抗を通じて前記電流検出抵抗の他端とともに前記直流電源のハイサイドに接続し、前記第2のトランジスタのコレクタは第2のコレクタ抵抗を通じて前記直流電源のローサイドに接続し、前記電流検出抵抗に流れる被検出電流に比例した検出出力電圧を前記第2のコレクタ抵抗に得ることを特徴とするハイサイド電流検出回路であって、
前記第2のトランジスタのエミッタと前記直流電源のローサイドとの間に補償抵抗を接続することにより、前記検出出力電圧に与える前記直流電源の電源電圧変動の影響を補償することを特徴とするハイサイド電流検出回路。
In a DC-DC converter in which a load is connected to the high side of the DC power supply, a current detection resistor is inserted between the high side of the DC power supply and the load, and the bases of the first and second transistors and the collector of the first transistor are connected. In the commonly connected current mirror circuit, the emitter of the first transistor is connected to one end of a current detection resistor, the collector is connected to the low side terminal of the load through the first collector resistor, and the emitter of the second transistor is the connected with the other end of the current detection resistor in the high side of the DC power source through a proportional resistor, the collector of the second transistor is connected to the low side of the DC power source through a second collector resistor, before Symbol current detection resistor A detection output voltage proportional to a flowing current to be detected is obtained at the second collector resistor. A Ido current detection circuit,
A high side compensates for the influence of the power supply voltage fluctuation of the DC power supply on the detected output voltage by connecting a compensation resistor between the emitter of the second transistor and the low side of the DC power supply. Current detection circuit.
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US9899926B2 (en) 2015-12-02 2018-02-20 Kabushiki Kaisha Toshiba Power supply device and semiconductor device
US11201543B2 (en) 2018-11-01 2021-12-14 Texas Instruments Incorporated Methods and apparatus to improve the safe operating area of switched mode power supplies

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CN108334146A (en) * 2018-04-08 2018-07-27 杭州欣美成套电器制造有限公司 A kind of constant-current drive circuit of burn out detection
CN112630498A (en) * 2020-12-08 2021-04-09 中国空间技术研究院 High-side sampling circuit
CN115932379B (en) * 2022-12-27 2023-08-08 希荻微电子集团股份有限公司 High-side current detection circuit, overcurrent protection circuit, calibration method and electronic equipment

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JP3417891B2 (en) * 1999-10-27 2003-06-16 株式会社オートネットワーク技術研究所 Current detector
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899926B2 (en) 2015-12-02 2018-02-20 Kabushiki Kaisha Toshiba Power supply device and semiconductor device
US11201543B2 (en) 2018-11-01 2021-12-14 Texas Instruments Incorporated Methods and apparatus to improve the safe operating area of switched mode power supplies

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