JP5609657B2 - Low power design support apparatus and method for semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a technology for supporting design of a low-power memory in a semiconductor integrated circuit.

  In recent years, increasing the density of semiconductor integrated circuits and reducing their power consumption have become important issues. In a semiconductor integrated circuit, the proportion of RAM (Random Access Memory) power is large, and by designing a low-power integrated circuit that eliminates unnecessary operations of the RAM, a great power reduction effect can be obtained.

  For example, in a cache memory that supports multi-way set associative, a large-scale address memory that stores tag addresses for the number of ways and a small bit that stores valid / invalid indicating the validity / invalidity of the contents of the data memory corresponding to the tag address. It is arranged separately from the large effective bit memory, and for the way where the effective bit is invalid, the read or output operation of the large address memory is stopped or the subsequent circuit of the RAM is monitored. It has been proposed to detect a useless read operation of a RAM by checking whether or not data read from the RAM is used in a subsequent circuit.

Japanese Patent Laid-Open No. 10-111182

"PowerPro MG automates memory power optimization", [online], Calypto, [October 5, 2010 search], Internet <URL: http://www.calypto.com/powerpromg.php>

  However, the above-described conventional technology cannot sufficiently detect a useless operation of the RAM in actual data access.

  For example, in the detection method for checking whether or not the data read from the RAM is used in the subsequent circuit, it is difficult to comprehensively check all the circuits in the subsequent stage of the RAM, and the monitored circuit is used in a wasteful access. When data is discarded in a circuit that cannot be monitored after the operation, all unnecessary accesses cannot be detected because the logical value of the minimum number of RAM read operations is not referred to. There was a problem.

In the disclosed technique, access to target data in the memory is obtained according to the access to the memory, which is obtained by the first simulation using the evaluation program for evaluating the semiconductor integrated circuit stored in the storage area. Using the number information, calculation means for calculating a logical read number and a logical write number, and using the evaluation program, according to the design data of the semiconductor integrated circuit stored in the storage area According to a second simulation, acquisition means for acquiring the actual number of reads and the actual number of writes to the memory, and when the actual number of reads is larger than the logical number of reads, or when the actual number of writes is wherein if logical larger write count, a semiconductor collector characterized in that it comprises a waste power determination means for determining a wasteful power is in the said memory Configured as a low power design support apparatus of the circuit.

  Further, as means for solving the above problems, a program for causing a computer to function as the low power design support apparatus, a recording medium recording the program, and a low power design support method for a semiconductor integrated circuit can be used. .

  In the disclosed technique, a logical value of the number of accesses to the RAM constituting the memory is determined, and whether or not there is useless access in the entire memory is determined by comparing the logical value with the actual number of accesses to the RAM. Can be judged. Therefore, it is possible to determine whether or not there is wasted power in the entire memory.

It is a figure which shows the hardware constitutions of a low power design support apparatus. It is a figure showing the example of the 1st functional composition of a low power design support device. It is a flowchart for demonstrating the 1st process example which judges the waste of RAM access. It is a figure which shows the 2nd function structural example of a low-power design assistance apparatus. It is a flowchart for demonstrating the 2nd process example which judges the waste of RAM access. It is a figure which shows the structural example of a memory system. It is a figure for demonstrating the calculation method (procedure 3) in an application example. It is a figure which shows the operation | movement correspondence table of a cache.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The low power design support apparatus according to the present embodiment has a hardware configuration as shown in FIG. 1, for example. FIG. 1 is a diagram illustrating a hardware configuration of a low power design support apparatus.

  In FIG. 1, a low power design support apparatus 100 is an apparatus controlled by a computer, and includes a CPU (Central Processing Unit) 11, a memory unit 12, a display unit 13, an output unit 14, and an input unit 15. The communication unit 16, the storage device 17, and the driver 18 are connected to the system bus B.

  The CPU 11 controls the low power design support apparatus 100 according to a program stored in the memory unit 12. The memory unit 12 uses a RAM (Random Access Memory), a ROM (Read-Only Memory), or the like, and is obtained by a program executed by the CPU 11, data necessary for processing by the CPU 11, and processing by the CPU 11. Stored data. A part of the memory unit 12 is allocated as a work area used for processing by the CPU 11.

  The display unit 13 displays various information required under the control of the CPU 11. The output unit 14 has a printer or the like, and is used for outputting various types of information in accordance with instructions from the user. The input unit 15 includes a mouse, a keyboard, and the like, and is used by a user to input various information necessary for the low-power design support apparatus 100 to perform processing.

  The communication unit 16 is a device that is connected to, for example, the Internet, a LAN (Local Area Network), and the like and controls communication with an external device. For example, a hard disk unit is used as the storage device 17 and stores data such as programs for executing various processes.

  A program for realizing the processing performed by the low power design support apparatus 100 is provided to the low power design support apparatus 100 by a storage medium 19 such as a CD-ROM (Compact Disc Read-Only Memory). That is, when the storage medium 19 storing the program is set in the driver 18, the driver 18 reads the program from the storage medium 19, and the read program is installed in the storage device 17 via the system bus B. . When the program is activated, the CPU 11 starts its processing according to the program installed in the storage device 17. The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.

  In addition, a program that realizes processing performed by the power consumption analysis device 100 may be provided from an external device via the communication unit 16.

  FIG. 2 is a diagram illustrating a first functional configuration example of the low power design support apparatus. In FIG. 2, the low-power design support apparatus 100 includes processing units such as a logic simulator 121, a performance evaluation simulator 123, an access count calculation unit 125, and a waste power presence / absence determination unit 126. The CPU 11 functions as each of these processing units by executing a corresponding program.

  The low-power design support apparatus 100 also includes a logic evaluation result 173 and a performance evaluation result 174 including design data 171, an evaluation program 172, and the actual number of accesses 175 in the storage area 170 of the memory unit 12 and / or the storage device 17. , Data for performing processing in the first functional configuration example such as the logical access number 176 and the determination result 176 are stored.

  The logic simulator 121 is a processing unit that performs a logic simulation according to the design data 171 using the evaluation program 172. The number of accesses to the RAM macro by the logic simulation is extracted and stored in the storage area 170 as the actual access number 175.

  The performance evaluation simulator 123 uses the evaluation program 172 to perform a performance evaluation simulation of a macro (including a CPU macro, a RAM macro, an I / O macro, etc.) that represents the operation of the functional blocks constituting the semiconductor integrated circuit. It is. From the performance evaluation simulation, the load / store count, cache miss rate, and MOVE IN / MOVE OUT count related to the RAM macro are extracted and stored in the storage area 170 as the performance evaluation result 174.

  The access number calculation unit 125 is a processing unit that calculates the logical RAM macro access number using the design data 171 and the performance evaluation result 174 and stores the logical RAM macro access number in the storage area 170 as the logical access number 176. .

  The waste power presence / absence determination unit 126 determines whether or not there is waste power with respect to access to the RAM by acquiring the actual access number 175 and the logical access number 176 from the storage area 170 and comparing them. Is a processing unit. A determination result 176 indicating the determination result is stored in the storage area 170.

  By displaying the determination result 176 stored in the storage area 170 on the display unit 13, the designer of the semiconductor integrated circuit can review the design for reducing power consumption.

  The design data 171 includes data indicating the number of ways, line structure, input / output relationship between cells, and the like.

  The evaluation program 172 is an evaluation program that operates on the logic simulator 121 and the performance evaluation simulator 123, and includes at least an operation pattern related to the RAM macro. The evaluation program 172 includes an operation pattern for evaluating the operation of each macro.

  The logic evaluation result 173 is data indicating a result obtained when the logic simulator 121 performs a logic simulation based on the design data 171 using the evaluation program 172. The logical evaluation result 173 includes the actual number of RAM macro accesses.

  The performance evaluation result 174 is data indicating a result obtained by the performance evaluation simulator 123 performing a performance evaluation simulation using the evaluation program 172. The performance evaluation result 174 includes the load / store count to the RAM macro, the cache miss rate, and the MOVE IN / MOVE OUT count to the lower memory.

  The actual access number 175 indicates the actual access number of the RAM macro obtained by the logic simulator 121 using the evaluation program 172 to perform a logic simulation based on the design data 171.

  The logical access number 176 indicates the logical RAM macro access number obtained by the performance evaluation simulator 123 using the evaluation program 172 to perform a performance evaluation simulation.

  The determination result 176 indicates a determination result by the waste power presence / absence determination unit 126 and indicates whether it is determined that there is waste power or there is no waste power.

  Next, processing for determining waste of RAM access performed by the processing units 121 to 126 described above will be described. FIG. 3 is a flowchart for explaining a first processing example for determining waste of RAM access. FIG. 3 shows a processing example in the first functional configuration example shown in FIG.

  In FIG. 3, the performance evaluation simulator 123 inputs the evaluation program 172 stored in the storage area 170, executes a performance evaluation simulation for evaluating the performance of the semiconductor integrated circuit, and shows a performance evaluation result 174 indicating the result. Is stored in the storage area 170 (step S11). Since the load / store count, cache miss rate, and MOVE IN / MOVE OUT count related to the RAM macro are extracted in a certain period during which the evaluation program 172 is executed by the performance evaluation simulator 123, the performance evaluation result 174 Contains data.

  After executing the performance evaluation simulation, the access count calculation unit 125 acquires the load / store count, cache miss rate, and MOVE IN / MOVE OUT count related to the RAM macro from the performance evaluation result 174 (step S12).

  Then, the access count calculation unit 125 reads the design data 171 from the storage area 170 to acquire the RAM configuration information, and based on the acquired RAM configuration information, the Load / store related to the RAM macro acquired in step S12. The number of accesses to the logical RAM macro (read / write) is calculated using the number of times, the cache miss rate, and the number of MOVE IN / MOVE OUT (step S13). A logical access number 176 indicating the calculated number of accesses (read / write) to the logical RAM macro is stored in the storage area 170.

  On the other hand, the logic simulator 121 inputs the design data 171 and the evaluation program 172 stored in the storage area 170, executes a logic simulation according to the design data 171, and outputs a logic evaluation result 173 indicating the result thereof to the storage area 170. (Step S21). By executing this logic simulation, the actual number of accesses 175 indicating the number of accesses of the RAM macro is extracted, so that data is included in the logic evaluation result 173.

  After executing the performance evaluation simulation and the logic simulation, the waste power presence / absence determination unit 126 reads the actual access number 175 from the storage area 170 and sets it as the actual RAM macro access number M (step S22). In addition, the waste power presence / absence determination unit 126 reads the logical access number 176 from the storage area 170 and sets it as the logical RAM macro access number N (step S23).

  Then, the waste power presence / absence determination unit 126 determines whether or not the number of accesses M is greater than the number of accesses N, and outputs and stores the determination result 176 in the storage area 170 (step S24). When the access number M is greater than the access number N, the waste power presence / absence determination unit 126 outputs a determination result 176 indicating that there is waste power in the operation of the RAM macro to the storage area 170. On the other hand, when the access number M is less than or equal to the access number N, the waste power presence / absence determination unit 126 outputs a determination result 176 indicating that there is no waste power in the operation of the RAM macro to the storage area 170.

  In FIG. 3, the order of execution of the logic simulation in step S21 and the execution of the performance evaluation simulation in step S11 is not limited. That is, a logic simulation may be executed before the performance evaluation simulation in step S11.

  FIG. 4 is a diagram illustrating a second functional configuration example of the low-power design support apparatus. In the second functional configuration example shown in FIG. 4, the same components as those in the first functional configuration example shown in FIG. The difference from the first functional configuration example of FIG. 2 is that an event counter (PA 17a) for counting event statistical information is built in the design data 171 and only the logic evaluation result 173 obtained from the logic simulation by the logic simulator 121 is used. Thus, the presence / absence of RAM macro waste power is determined without the need for the performance evaluation simulator 123.

  In the second functional configuration example illustrated in FIG. 4, the low power design support apparatus 100 includes processing units such as a logic simulator 121, an access count calculation unit 135, and a waste power presence / absence determination unit 126. The CPU 11 functions as each of these processing units by executing a corresponding program.

  In addition, the low power design support apparatus 100 stores the logic evaluation result 173 including the design data 171 having the PA 17a, the evaluation program 172, and the actual access number 175 in the storage area 170 of the memory unit 12 and / or the storage device 17. The data for performing processing in the second functional configuration example such as the number of accesses 176 and the determination result 176 are stored.

  The logic simulator 121 is a processing unit that performs a logic simulation using the evaluation program 172 according to the design data 171 with the PA 17a built therein.

  The access number calculation unit 135 is a processing unit that calculates the access number of the logical RAM macro using the design data 171 and the logical evaluation result 173 and stores it in the storage area 170 as the logical access number 176. .

  In the design data 171, a PA 17 a that counts occurrence of Load / store, occurrence of cache miss, and occurrence of MOVE IN / MOVE OUT is designed as a circuit. A cache miss rate is obtained based on the number of times a cache miss has occurred, and the load / store count, the cache miss rate, and the number of MOVE IN / MOVE OUT to the lower memory are included in the logic evaluation result 173 as PA information, It is output and stored in the storage area 170.

  Next, processing for determining waste of RAM access performed by the processing units 121, 135, and 126 described above will be described. FIG. 5 is a flowchart for explaining a second processing example for determining waste of RAM access. FIG. 5 shows a processing example in the second functional configuration example shown in FIG.

  In FIG. 5, the logic simulator 121 receives design data 171 containing the PA 17 a stored in the storage area 170 and an evaluation program 172, executes a logic simulation according to the design data 171, and shows a logic indicating the result. The evaluation result 173 is stored in the storage area 170 (step S31). When the logic simulation is executed by the logic simulator 121, the load / store count, the cache miss rate, and the MOVE IN / MOVE OUT count counted by the PA 17a are extracted. Therefore, the data is included in the logic evaluation result 173. .

  After executing the logic simulation, the access count calculation unit 135 acquires the load / store count, cache miss rate, and MOVE IN / MOVE OUT count related to the RAM macro from the logic evaluation result 173 (step S32).

  Then, the access number calculation unit 135 reads the design data 171 from the storage area 170 to acquire the RAM configuration information, and based on the acquired RAM configuration information, the Load / store related to the RAM macro acquired in step S <b> 32. The number of accesses (read / write) to the logical RAM macro is calculated using the number of times, the cache miss rate, and the number of MOVE IN / MOVE OUT (step S33). A logical access number 176 indicating the calculated number of accesses (read / write) to the logical RAM macro is stored in the storage area 170.

  Thereafter, the waste power presence / absence determination unit 126 reads the actual access number 175 from the storage area 170 and sets the actual access number M of the RAM macro (step S34). In addition, the waste power presence / absence determining unit 126 reads the logical access number 176 from the storage area 170 and sets it as the logical RAM macro access number N (step S35).

  Then, the waste power presence / absence determination unit 126 determines whether or not the access number M is greater than the access number N, and outputs and stores the determination result 176 in the storage area 170 (step S35).

  Next, a calculation example of the RAM access count in the memory system 200 as shown in FIG. 6 will be described. FIG. 6 is a diagram illustrating a configuration example of a memory system. In FIG. 6, the memory system 200 is a hierarchical memory system including an L1 cache and an L2 cache.

  The RAM constituting the L1 cache is divided for each way 1 to way n, the tag RAM and the data line RAM are integrated, and has a configuration in which line data can be read at a time. A set of tags and line data having the same index is set as one set.

  The address memory 61 has a tag indicating a predetermined upper bit of the address, an index for designating a data line, and a byte offset.

  Each way 1 to way n is composed of a valid bit indicating validity / invalidity of the data line, a tag indicating a predetermined higher bit of the address, and a data line storing data for each index.

  Each comparison unit 62 corresponding to each way 1 to way n compares the tag in the address memory 61 with the tag specified by the index of each way 1 to way n. Each AND circuit 62 corresponding to each way 1 to way n outputs a logical product of the effective bit designated by the index of the corresponding way and the comparison result of the comparison unit 62.

  The OR circuit 64 outputs a logical sum of outputs from all the AND circuits 62, and indicates a data hit or miss. The n: 1 multiplexer 65 selects a way according to the output from each AND circuit 62, and outputs the data of the data line designated by the index.

  The buffer 66 is a memory for temporarily storing data when data is written and read between the L1 cache and the L2 cache.

  In this memory system 200, the write method of the L1 cache is the write back method. The L1 cache is an n-way set associative method.

  The processing according to the present embodiment does not necessarily require the RAM to be divided for each way in the L1 cache, and can also be applied to a configuration in which the tag RAM and the data RAM are separated. Even if it is the structure which can read a part of, it is applicable.

  Next, an application example of a method for determining the presence or absence of wasted power will be described using the above-described memory system 200 as an example.

(Procedure 1) Equivalent to step S21 in FIG. 3 and step S31 in FIG. 5 By executing a logic simulation according to the design data 171 using the evaluation program 172, the number of accesses M to the RAM constituting the L1 cache To get. The number of reads M (R1) and the number of writes M (W1) are acquired for each access type. In this embodiment, the read access to the RAM constituting the L1 cache to be counted is the total value to the RAM for the number of ways constituting the L1 cache. The same applies to write access.

(Procedure 2) Corresponds to step S11 in FIG. 3 and step S31 in FIG. 5 The number of load / store times by performance evaluation simulation using the evaluation program 172 or logic simulation according to the design data 171 incorporating the PA 17a , The cache miss rate, and the number of MOVE IN / MOVE OUT through the buffer 66 from the L2 cache to the L1 cache is counted. The performance evaluation result 174 or the logic evaluation result 173 including the counted number is stored in the storage area 170.

(Procedure 3) Corresponds to steps S12 and S13 in FIG. 3 and steps S32 and S33 in FIG. 5 and theoretically based on the number of times counted in the procedure 2 described above and the configuration information of the memory system 200 obtained from the design data 171. The number of accesses N to the RAM constituting the cache is calculated. The number of reads M (R1) and the number of writes M (W1) are acquired for each access type. The calculation method is shown in the following procedure with reference to FIG. FIG. 7 is a diagram for explaining a calculation method (procedure 3) in the application example.

  Consider the following case for L1 cache operation. In the case of load to the L1 cache of (a), (b), and (c), the store is (d), (e), and (f). FIG. 8 shows the operation of the L1 cache corresponding to (a) to (f) of FIG. With reference to FIGS. 7 and 8, the calculation method (procedure 3) will be described in detail from (a) to (f) in correspondence with FIGS. 7 and 8.

(A) When L1 cache is hit by load, initial read access to the RAM constituting the L1 cache is sufficient. The CPU 69 acquires data from the L1 cache.

  The number of operations is one for the initial read access. As shown in FIG. 6, since the L1 cache is composed of n ways, in the case of load, the tag information is read and at the same time the n way data lines are read at the same time. Based on the information shown, the required data is selected by the multiplexer. At that time, since n-way RAMs constituting the L1 cache are accessed once at the same time, n read accesses (1 * n (way)) are required in the initial stage.

(B) When a load misses in the L1 cache First, the initial read access at the time of L1 cache hit / miss determination is required n times. Next, it is necessary to read data from the L2 cache and write it to the data line to be rewritten in the corresponding L1 cache. When the old data of the data line to be rewritten is clean (or empty), the old data can be overwritten, so the CPU 69 writes new data to the data line to be rewritten from the L2 cache with one MOVE IN. .

  The number of operations is n times of initial read access and one time of write access by MOVE IN. When there is a miss in the L1 cache, the data brought from the L2 cache is directly transferred to the load order destination (processor or the like) and is usually written to the L1 cache. This is because the data is likely to be used soon. The same applies to (c) below.

(C) When L1 cache is missed by load First, initial read access at the time of L1 cache hit / miss determination is required n times. Next, it is necessary to read data from the L2 cache and write it to the data line to be rewritten in the corresponding L1 cache. When the old data of the data line to be rewritten becomes dirty, the CPU 69 writes the old data once to the L2 cache with MOVE OUT, and then writes the new data read from the L2 cache to the data line to be rewritten.

  However, assuming that the old data is stored in the buffer 66 by the initial read access and the MOVE OUT is written from the buffer 66 to the L2 cache instead of from the L1 cache, one read access by the MOVE OUT to the L1 cache is assumed. Is ignored.

  The number of operations is n times of initial read access and one time of write access by MOVE IN. Since the data read at the time of hit / miss determination of the L1 cache is stored in the buffer 66 and written back to the L2 cache, one read access by MOVE OUT to the L1 cache is ignored.

(D) When L1 cache is hit in store In the L1 cache hit / miss determination, the initial read access to the RAM constituting the L1 cache is required n times. After that, when the store data is written by the CPU 69, one write access to the target way is performed.

  The number of operations is n times of initial read access and one time of write access by writing store data. The store data is merged with the data read at the time of hit / miss determination of the L1 cache and written back to the L1 cache.

(E) When the L1 cache misses in the store First, in the L1 cache hit / miss determination, the initial read access to the RAM constituting the L1 cache is required n times. Thereafter, the CPU 69 stores the data of the corresponding data line in the buffer 66, updates the location corresponding to the store data, and writes it in the L1 cache. When the old data of the data line to be written in the L1 cache is clean, it is not necessary to write the old data back to the L2 cache.

  The number of operations is n times of initial read access and one time of write access by writing store data. In the case of the Store, the data existing in the data line that becomes the MOVE IN of the L1 cache from the L2 cache is temporarily stored in the buffer 66, and the store data part is updated and written to the L1 cache. Data writing is counted as one write access. Therefore, one write access by the MOVE IN to the L1 cache is ignored.

(F) When the L1 cache misses in the store First, in the L1 cache hit / miss determination, the initial read access to the RAM constituting the L1 cache is required n times. Thereafter, the CPU 69 stores the data of the corresponding data line in the buffer 66, updates the location corresponding to the store data, and writes it in the L1 cache. When the old data of the line to be written in the L1 cache becomes dirty, it is necessary to write the old data back to the L2 cache with MOVE OUT.

  The number of operations is n times of initial read access and one time of write access by writing store data. Since the data read at the time of hit / miss determination of the L1 cache is stored in the buffer 66 and written back to the L2 cache, one read access by MOVE OUT to the L1 cache is ignored. In the case of Store, since data existing in the data line that becomes MOVE IN of the L1 cache from the L2 cache is temporarily stored in the buffer 66 and the store data portion is updated and written to the L1 cache, Writing MOVE IN data is counted as one write access. Therefore, one write access by the MOVE IN to the L1 cache is ignored.

  Based on the access information related to the RAM described above, variables are set as follows.

-Set Load count to variable L-Set store count to variable S-Set L1 cache store miss rate to MW 1%-Set MOVE IN count to L1 cache to MI1-L1 cache And set the number of MOVE OUT times for MO1 to MO1 and in memory system 200 for that n-way L1 cache,
The theoretical number of read accesses for the L1 cache is
N (R1) = n × (L + S) (1)
Calculated by The theoretical number of write accesses for the L1 cache is
N (W1) = S + MI1−S × MW1% (2)
Calculated by

(Procedure 4) Corresponds to Steps S22 to S24 in FIG. 3 and Steps S34 to S36 in FIG. 5. The logical read access count N (R1) and the logical write access count which are obtained as the number of accesses of the RAM macro and calculated by the above-described calculation formulas (1) and (2) of (f) in (Procedure 3). Compare with N (W1).

  By judging whether M (R1)> N (R1) or not, if M (R1)> N (R1), there is a useless read access to the RAM constituting the L1 cache. Judgment can be made.

By judging whether or not M (W1)> N (W1), if M (W1)> N (W1), there is a useless write access to the RAM constituting the L1 cache. Judgment can be made.

  The method of determining the presence of useless access related to the L1 cache according to the configuration of the L1 cache and the L2 cache has been described. However, the access between the L2 cache and the lower-level memory can also be performed using the same method as described above. Unnecessary access can be extracted.

  As described above, in this embodiment, the logical value of the minimum necessary number of accesses to the RAM is determined (steps S12, S13, and S23 in FIG. 3 or S32, S33, and S34 in FIG. 5), and the logical simulation is performed. The actual number of accesses to the RAM is compared (S24 in FIG. 3 or S36 in FIG. 5).

  Therefore, even in a memory system having a hierarchical structure, it is possible to determine whether or not there is useless access in the entire memory system by extracting the number of MOVE IN / MOVE OUT times in the lower memory. When it is determined that useless access exists, it can be determined that useless power is consumed.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The following additional notes are further disclosed with respect to the embodiment including the above examples.
(Appendix 1)
Using frequency information related to access to target data in the memory according to the access to the memory, obtained by the first simulation using the evaluation program for evaluating the semiconductor integrated circuit stored in the storage area Calculating means for calculating the logical access count;
Using the evaluation program, acquisition means for acquiring the actual number of accesses to the memory by a second simulation according to design data of the semiconductor integrated circuit stored in the storage area;
A low-power design support apparatus for a semiconductor integrated circuit, comprising: a waste power determination unit that determines that there is waste power in the memory when the actual access number is larger than the logical access number.
(Appendix 2)
Using the evaluation program, having a performance evaluation simulator for executing the first simulation,
The low-power design support apparatus according to appendix 1, further comprising a logic simulator that executes the second simulation according to the design data using the evaluation program.
(Appendix 3)
The design data has an event counter;
Using the evaluation program, and having a logic simulator for executing the first simulation including the second simulation according to design data having the event counter,
The number information is extracted by operating the event counter by the first simulation,
The low-power design support apparatus according to appendix 1, wherein the acquisition unit acquires the actual number of accesses from the first simulation.
(Appendix 4)
The low-power design support apparatus according to any one of appendices 1 to 3, wherein the number information includes a load / store number, a cache miss rate, and a MOVE IN / MOVE OUT number.
(Appendix 5)
The low-power design support apparatus according to any one of appendices 1 to 4, wherein the memory is a cache memory having a hierarchical structure.
(Appendix 6)
The number of accesses is the number of read accesses and the number of write accesses to the memory,
The low power design support according to any one of appendices 1 to 5, wherein the waste power determination unit determines whether or not there is useless power in the memory for each of the number of read accesses and the number of write accesses. apparatus.
(Appendix 7)
Using frequency information related to access to target data in the memory according to the access to the memory, obtained by the first simulation using the evaluation program for evaluating the semiconductor integrated circuit stored in the storage area Calculate the number of logical accesses,
Using the evaluation program, the actual number of accesses to the memory is obtained by a second simulation according to design data of the semiconductor integrated circuit stored in the storage area,
A low-power design support method for a semiconductor integrated circuit, in which a computer determines that the memory has wasted power when the actual access count is larger than the logical access count.
(Appendix 8)
Using frequency information related to access to target data in the memory according to the access to the memory, obtained by the first simulation using the evaluation program for evaluating the semiconductor integrated circuit stored in the storage area Calculate the number of logical accesses,
Using the evaluation program, the actual number of accesses to the memory is obtained by a second simulation according to design data of the semiconductor integrated circuit stored in the storage area,
When the actual access count is larger than the logical access count, a program for causing a computer to determine that there is wasted power in the memory and causing the computer to function as a low power design support device for a semiconductor integrated circuit A stored computer-readable storage medium.

11 CPU
12 memory unit 13 display unit 14 output unit 15 input unit 16 communication unit 17 storage device 18 driver 19 storage medium 61 address memory 62 comparator 63 AND circuit 64 OR circuit 65 n: 1 multiplexer 66 buffer 100 low power design support device 121 logic Simulator 123 Performance evaluation simulator 125 Access count calculation section 126 Waste power presence / absence determination section 170 Storage area 171 Design data 172 Evaluation program 173 Logic evaluation result 174 Performance evaluation result 175 Actual access count 176 Logical access count 177 Determination result

Claims (5)

Using frequency information related to access to target data in the memory according to the access to the memory, obtained by the first simulation using the evaluation program for evaluating the semiconductor integrated circuit stored in the storage area Calculating means for calculating the number of logical reads and the number of logical writes ;
Using the evaluation program, an acquisition means for acquiring an actual read count and an actual write count to the memory by a second simulation according to design data of the semiconductor integrated circuit stored in the storage area; ,
If the actual read times greater than the logical read count, or, if the actual write times larger than the logical write times, and wasteful power determination means for determining a wasteful power is in the said memory A low-power design support apparatus for a semiconductor integrated circuit, comprising: Using the evaluation program, having a performance evaluation simulator for executing the first simulation,
The low-power design support apparatus according to claim 1, further comprising a logic simulator that executes the second simulation according to the design data using the evaluation program. The design data has an event counter;
Using the evaluation program, and having a logic simulator for executing the second simulation including the first simulation according to design data having the event counter,
The number information is extracted by operating the event counter by the second simulation,
The low-power design support apparatus according to claim 1, wherein the acquisition unit acquires the actual number of accesses from the second simulation. The number information includes load / store number, cache miss rate, MOVE
The low power design support apparatus according to any one of claims 1 to 3, further comprising an IN / MOVE OUT count. Using frequency information related to access to target data in the memory according to the access to the memory, obtained by the first simulation using the evaluation program for evaluating the semiconductor integrated circuit stored in the storage area And calculate the logical read count and logical write count,
Using the evaluation program, the second simulation according to the design data of the semiconductor integrated circuit stored in the storage area is used to obtain the actual number of reads and the actual number of writes to the memory,
If the actual number of reads is greater than the logical number of reads, or if the actual number of writes is greater than the logical number of writes , the computer executes a determination that there is wasted power in the memory A low power design support method for a semiconductor integrated circuit.

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