JP5605142B2 - Detection device and electronic device - Google Patents

Description

The present invention, concerning detection device and an electronic apparatus.

  Electronic devices such as cellular phones and car navigation systems incorporate a gyro sensor for detecting physical quantities such as angular velocity. This gyro sensor is used for, for example, camera shake correction, posture control, GPS autonomous navigation, and the like.

JP-A-8-18396

  In such a sensor detection apparatus, there is a problem that a clock signal in which the phase relationship with the signal from the sensor is adjusted may be required to detect the signal from the sensor at a desired timing.

  For example, the phase adjustment of the signal can be performed by a phase adjustment circuit using a high-pass filter or the like (for example, Patent Document 1). However, in a phase adjustment circuit using a high-pass filter or the like, there are problems that the gain decreases as a large adjustment angle is obtained, or that it is difficult to obtain a high-precision adjustment angle due to manufacturing variation.

  According to some aspects of the present invention, it is possible to provide a phase adjustment circuit, a detection device, an electronic device, and the like that can adjust the phase of a signal with high accuracy.

  One aspect of the present invention is a phase main adjustment low-pass filter having a frequency characteristic in which a first signal having a frequency fin is input and a phase delay angle at the frequency fin is X degrees (X ≧ 0), and the low-pass filter. A second signal based on the output signal from the filter is input, and has a frequency characteristic in which the phase advance angle at the frequency fin is Y degrees (Y ≧ 0), and the Y degree is smaller than the X degree. And a high-pass filter for fine phase adjustment to be set.

  According to one aspect of the present invention, the phase at the frequency fin is mainly adjusted by the low-pass filter. Then, the phase advance angle Y degree of the high-pass filter is set to a value smaller than the phase delay angle X degree of the low-pass filter, so that the phase at the frequency fin is finely adjusted by the high-pass filter. Thereby, the phase of the signal can be adjusted with high accuracy. That is, it is possible to suppress a change in the phase adjustment angle with respect to a change in the cutoff frequency of the low-pass filter or the high-pass filter.

  In one aspect of the present invention, the amplifier includes an amplifier circuit that amplifies an output signal from the low-pass filter and outputs the amplified signal as the second signal to the high-pass filter, the low-pass filter being a passive It may be a filter.

  In this way, the output signal whose amplitude has been reduced by the main adjustment of the phase by the passive low-pass filter can be amplified by the amplifier circuit. Thereby, for example, the amplitude of a signal input to a subsequent circuit such as a delay adjustment circuit described later can be amplified to an appropriate amplitude.

  In one aspect of the present invention, a delay adjustment circuit including a plurality of delay elements that delay the output signal from the high-pass filter may be included.

  In the aspect of the invention, the delay adjustment circuit may adjust the delay time of the output signal from the high pass filter to adjust the phase of the output signal of the phase adjustment circuit with respect to the first signal. Good.

  In this way, the phase of the output signal of the phase adjustment circuit with respect to the first signal can be adjusted by the delay adjustment circuit. Thus, even when the phase adjustment angle by the low-pass filter or the high-pass filter changes, the delay adjustment circuit can absorb the change.

  In one aspect of the present invention, the low-pass filter is a passive filter composed of a resistor element and a capacitor, and the amplifier circuit is a normal amplifier circuit composed of an operational amplifier and a resistor element. The filter is a passive filter composed of a resistance element and a capacitor, and the delay adjustment circuit performs phase adjustment by selecting and outputting one of the output signals of each delay circuit of the plurality of delay circuits. May be.

  In this way, the low-pass filter for main phase adjustment, the high-pass filter 230 for fine phase adjustment, the amplification circuit for amplifying the output signal from the low-pass filter, and the delay adjustment circuit for adjusting the delay time of the output signal from the high-pass filter Is feasible.

  In the aspect of the invention, the phase adjustment angle in the delay adjustment circuit may be an angle equal to or less than the Y degree.

  In one embodiment of the present invention, the X degree may be an angle of 80 degrees or more and 90 degrees or less, and the Y degree may be an angle of 0 degrees or more and 10 degrees or less.

  This makes it possible to reduce the change in the phase adjustment angle with respect to the change in the cutoff frequency of the low-pass filter or the high-pass filter. In addition, since the phase adjustment angle in the delay adjustment circuit is set to Y degrees or less, the layout area of the delay adjustment circuit can be reduced.

  According to another aspect of the present invention, a first signal for phase main adjustment having a frequency characteristic in which a first signal having a frequency fin is input and a phase advance angle at the frequency fin is X2 degrees (X2 ≧ 0). A high-pass filter and a second signal based on an output signal from the first high-pass filter are input, and has a frequency characteristic in which a phase advance angle at the frequency fin is Y2 degrees (Y2 ≧ 0), and the Y2 degrees May include a second high-pass filter for fine phase adjustment that is set to a value smaller than X2 degrees.

  According to another aspect of the present invention, the phase at the frequency fin is mainly adjusted by the first high-pass filter. Then, the phase advance angle Y2 degrees of the second high-pass filter is set to a value smaller than the phase advance angle X2 degrees of the first high-pass filter, so that the phase at the frequency fin is finely adjusted by the second high-pass filter. The Thereby, the phase of the signal can be adjusted with high accuracy. That is, it is possible to suppress changes in the phase adjustment angle with respect to changes in the cutoff frequency of the first high-pass filter and the second high-pass filter.

  According to still another aspect of the present invention, a driving circuit for driving a sensor device, a detection circuit to which an output signal from the sensor device is input, and a signal from the driving circuit are input as the first signal. The phase adjustment circuit according to any one of the above, which outputs a clock signal based on the first signal to the detection circuit.

  In another aspect of the present invention, the detection circuit includes a charge-voltage conversion circuit that converts an output signal from the sensor device into a charge-voltage converter, and an A / D converter that performs an A / D conversion on an output signal from the charge-voltage conversion circuit. A D conversion circuit, and the A / D conversion circuit may sample a signal based on an output signal of the charge-voltage conversion circuit based on the clock signal based on the first signal.

  In another aspect of the invention, the sensor device may be a gyro sensor.

  Still another embodiment of the present invention relates to an electronic apparatus including the detection device according to any one of the above.

FIG. 1A and FIG. 1B are a first comparative example of the present embodiment. 2A and 2B are a second comparative example of the present embodiment. 2 is a configuration example of a phase adjustment circuit of the present embodiment. 3 is a detailed configuration example of a phase adjustment circuit according to the present embodiment. Explanatory drawing about the phase adjustment angle of the 1st structural example. FIG. 6A shows an example of frequency characteristics of the low-pass filter. FIG. 6B shows an example of frequency characteristics of the high-pass filter. 2 shows a second configuration example of a phase adjustment circuit according to the present embodiment. Explanatory drawing about the phase adjustment angle of a 2nd structural example. A detailed configuration example of a delay adjustment circuit. The structural example of a detection apparatus. FIG. 11A shows an example of a signal waveform of the A / D conversion circuit. FIG. 11B shows a signal waveform example of the phase adjustment circuit. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example First, a comparative example of this embodiment will be described. As will be described later with reference to FIGS. 10 to 11B, since the A / D conversion circuit 100 samples the desired signal included in the signals VS1 and VS2 from the sensor device 10, the phase is 90 degrees with respect to the desired signal. A shifted clock signal CK is required. Since the desired signal has the same phase as the signal VD2 in the drive circuit 40, it is necessary to generate the clock signal CK having a phase shifted by 90 degrees from the signal VD2 in FIG. Since the sampling timing in the A / D conversion circuit 100 affects the detection sensitivity, highly accurate phase adjustment is necessary.

  However, when a large adjustment angle close to 90 degrees is obtained, there is a problem that the gain decreases or it is difficult to obtain a high-precision adjustment angle due to manufacturing variation. This point will be described with reference to FIGS. 1 (A) to 2 (B).

  FIG. 1A shows a first comparative example of this embodiment. This phase adjustment circuit includes a high-pass filter HA and a delay circuit DA. The high pass filter HA is a primary passive filter, and a sine wave having a frequency fin is input to the high pass filter HA as the input signal VI. The delay circuit DA is composed of a delay buffer such as an inverter, and converts the output signal of the high-pass filter HA into a clock signal CK.

  FIG. 1B shows the frequency characteristics of the high-pass filter HA. As indicated by A1 in FIG. 1B, in order to turn the phase of the input signal VI close to 90 degrees, the cut-off frequency fc needs to be larger than the frequency fin. Then, as shown in A2, in order to approach 90 degrees, it is necessary to set the cutoff frequency to a higher frequency fc 'as shown in A3.

  However, as indicated by A4, when the cut-off frequency is increased, the gain of the high-pass filter HA decreases, and a signal having a sufficient amplitude is not input to the delay circuit DA. Therefore, there are problems such that the clock signal CK is not output and a through current is generated.

  On the other hand, in order not to reduce the gain too much, a method of shifting the phase by about 85 degrees with the high pass filter HA and adjusting the remaining 5 degrees with the delay circuit DA is conceivable.

  However, in this method, since the temperature dependence of the delay by the delay circuit DA is large, the accuracy of phase adjustment deteriorates due to a temperature change. Another problem is that the layout area of the delay circuit DA increases depending on the frequencies of the signals VS1 and VS2 from the sensor device 10. For example, in the case of a crystal vibration type gyro sensor, the frequency of the signals VS1 and VS2 is assumed to be about 50 kHz. In this case, since a delay of 56 ns per degree is required, a very large delay circuit is required.

  FIG. 2A shows a second comparative example of the present embodiment. This phase adjustment circuit includes high-pass filters HB1 and HB2 and a comparator CPB. The high pass filters HB1 and HB2 are first order high pass filters having cutoff frequencies fc1 and fc2, respectively. The comparator CPB converts the output signal HAQ of the high pass filter HA into a clock signal CK.

  FIG. 2B shows frequency characteristics of the high-pass filters HB1 and HB2. Assume that the cutoff frequencies fc1 and fc2 are set to the same frequency as the frequency fin of the input signal VI as indicated by B1 in FIG. Then, as shown in B2, it is possible to rotate the phase by 45 degrees + 45 degrees = 90 degrees as shown in B3 without lowering the gain as compared with the first comparative example described above.

  However, as shown in B4, since the phase change is large with respect to the change in the cut-off frequencies fc1 and fc2, the phase adjustment angle greatly changes due to manufacturing variations of the resistance elements and capacitors that determine the cut-off frequencies fc1 and fc2. End up.

2. Phase Adjustment Circuit FIG. 3 shows a configuration example of the phase adjustment circuit of the present embodiment that can solve the above-described problems. This phase adjustment circuit includes a low-pass filter 210, an amplification circuit 220 (gain adjustment circuit), a high-pass filter 230, and a delay adjustment circuit 240 (delay circuit). In this configuration example, the low-pass filter 210 mainly adjusts the phase, and the high-pass filter 230 finely adjusts the phase, thereby enabling highly accurate phase adjustment.

  In this specification, the phase delay means that the phase of the output signal is temporally delayed with respect to the phase of the input signal, and the phase advance means that the phase of the output signal is temporally relative to the phase of the input signal. Represents progress to In the drawings, the phase delay angle is expressed as a negative angle, and the phase advance angle is expressed as a positive angle.

  Further, in this specification, the fine adjustment of the phase represents adjusting the phase with an adjustment angle smaller than the adjustment angle in the main adjustment. For example, the adjustment is performed from 0 degree to 45 degrees with respect to the main adjustment from 45 degrees to 90 degrees, or the phase is adjusted at an adjustment angle equal to or less than 1/5 of the adjustment angle in the main adjustment.

  The low-pass filter 210 receives a sine wave input signal VI having a frequency fin (in a broad sense, an input signal including a fin sine wave signal). The low-pass filter 210 delays the phase at the frequency fin and performs the main adjustment of the phase adjustment performed by the phase adjustment circuit. Specifically, the clock signal CK is delayed by 90 degrees with respect to the signal VI (voltage signal), and the low-pass filter 210 rotates the phase by an angle larger than at least 45 degrees. Desirably, the low-pass filter 210 delays the phase at the frequency fin by 80 degrees to 90 degrees.

  The amplifier circuit 220 amplifies the amplitude of the signal LQ from the low pass filter 210. That is, the amplifier circuit 220 amplifies the signal whose amplitude is reduced by the gain of the low-pass filter 210 and adjusts the amplitude of the signal input to the delay adjustment circuit 240.

  The high pass filter 230 advances the phase at the frequency fin and performs fine adjustment of the phase adjustment performed by the phase adjustment circuit. Specifically, the high-pass filter 230 performs adjustment by advancing the phase that the phase adjustment circuit has delayed too much with respect to the target phase of 90 degrees. Alternatively, the high-pass filter 230 advances the phase so that the target phase is 90 degrees, including the phase delayed by a circuit preceding the phase adjustment circuit (for example, an I / V conversion circuit 42 described later in FIG. 10). Make it. Desirably, the high-pass filter 230 advances the phase at the frequency fin by 0 degrees to 10 degrees.

  The delay adjustment circuit 240 further finely adjusts the phase of the signal HQ from the high pass filter 230 and outputs a clock signal CK having a frequency fin. Specifically, the delay adjustment circuit 240 delays the edge timing of the clock signal CK and delays the phase of the clock signal CK with respect to the input signal VI. The phase adjustment angle of the delay adjustment circuit 240 may be an angle fixed in advance, an angle fixed selectively from a plurality of adjustment angles, or a selectable variable angle. .

  Here, the phase of the clock signal CK with respect to the input signal VI is a phase difference between the phase defined in the input signal VI and the phase defined in the clock signal CK. For example, when the amplitude of the input signal VI is a, it is assumed that VI = a · sin (2πfin + θ). Further, the rising edge of the clock signal CK is assumed to have a phase of 0 degree, and one period corresponds to the phase 2π. In this case, if there is a rising edge of the clock signal CK at 2πfin + θ = 0 °, the phase difference is 0 °, and if there is a rising edge of the clock signal CK at 2πfin + θ = −90 °, the phase delay is 90 °.

  According to the above configuration example, by providing the low-pass filter 210 for phase main adjustment and the high-pass filter 230 for phase fine adjustment, as described later in FIG. Accurate phase adjustment is possible. Further, the provision of the amplifier circuit 220 makes it possible to ensure the amplitude of the signal input to the delay adjustment circuit 240.

3. Detailed Configuration Example of Phase Adjustment Circuit FIG. 4 shows a detailed configuration example of the above-described phase adjustment circuit. The phase adjustment circuit includes a low-pass filter 210, an amplification circuit 220, a high-pass filter 230, and a delay adjustment circuit 240.

  The low-pass filter 210 is a primary passive low-pass filter. Specifically, the low-pass filter 210 includes a resistance element RL and a capacitor CL, and the cutoff frequency is set by the resistance value of the resistance element RL and the capacitance value of the capacitor CL. Resistive element RL is provided between input node NI and node NLQ, and capacitor CL is provided between node NLQ and a ground node (reference voltage node in a broad sense).

  The amplifier circuit 220 is a forward amplification circuit that forward-amplifies the input signal LQ. Specifically, the amplifier circuit 220 includes an operational amplifier OP and resistance elements R1 and R2, and the gain is set by the resistance values of the resistance elements R1 and R2. The signal LQ from the low-pass filter 210 is supplied to the positive terminal (first terminal) of the operational amplifier OP. The resistance element R1 is provided between the negative terminal (second terminal) of the operational amplifier OP and the node NGQ, and the resistance element R2 is provided between the node NGQ and the ground node. The output terminal of the operational amplifier OP outputs a signal GQ to the node NGQ.

  The high pass filter 230 is a primary passive high pass filter. Specifically, the high pass filter 230 includes a resistance element RH and a capacitor CH, and the cutoff frequency is set by the resistance value of the resistance element RH and the capacitance value of the capacitor CH. Capacitor CH is provided between node NGQ and node NHQ, and resistance element RH is provided between node NHQ and the ground node.

  Next, phase adjustment performed by the above-described phase adjustment circuit will be described in detail with reference to FIGS. In the following, a case where a phase adjustment circuit is applied to the detection device 30 described later in FIG. 10 will be described as an example, and the phase of the clock signal CK is delayed by 90 degrees with respect to the input signal IFD of the drive circuit 40.

  As shown in FIG. 5, for example, it is assumed that the phase is delayed by 5 degrees by the I / V conversion circuit 42. In this case, the low-pass filter 210 performs the main adjustment by delaying the phase by 85 degrees, the amplification circuit 220 delays the phase by 5 degrees, the high-pass filter 230 performs the fine adjustment by advancing the phase by 6.5 degrees, and the delay adjustment circuit 240. Adjusts to delay the phase by 1.5 degrees. With these adjustments, the phase adjustment circuit delays the phase of the clock signal CK by 90 degrees.

  FIG. 6A shows an example of frequency characteristics of the low-pass filter 210, and FIG. 6B shows an example of frequency characteristics of the high-pass filter 230. As indicated by D1 in FIG. 6A, the cut-off frequency fcL of the low-pass filter 210 is set so that the phase delay at the frequency fin is 85 degrees. At this time, as indicated by D2, the gain of the low-pass filter 210 at the frequency fin is about −20 dB. The gain of the amplifier circuit 220 is set to 20 dB, for example.

  As indicated by D3 in FIG. 6B, the cutoff frequency fcH of the high-pass filter 230 is set so that the phase lead at the frequency fin is 6 degrees. At this time, as indicated by D4, the gain of the high-pass filter 230 at the frequency fin is about −0.5 dB.

  According to the above embodiment, as indicated by D1 in FIG. 6A, the frequency fin is set in a frequency range in which the phase change is small with respect to the change in the cutoff frequency fcL. Therefore, even if the cut-off frequency fcL varies due to manufacturing variations of the resistance element RL and the capacitor CL, the change in the phase adjustment angle can be reduced compared to the second comparative example. Further, as indicated by D3 in FIG. 6B, the change in the phase adjustment angle can be similarly reduced in the high-pass filter 230 as compared with the second comparative example.

  Further, as shown in FIG. 5, since the adjustment angle by the delay adjustment circuit 240 is smaller than that in the first comparative example, changes in delay time due to temperature changes can be suppressed as compared with the first comparative example. Further, the layout area of the delay adjustment circuit 240 can be reduced as compared with the first comparative example. In addition, since the manufacturing variation of the phase adjustment angle of the filter is reduced as described above, the phase adjustment range of the delay adjustment circuit 240 can be reduced (for example, −3 ° to 0 ° centered at −1.5 °). Therefore, the layout area of the delay adjustment circuit 240 can be reduced.

  Now, as described above in the comparative example, in the phase adjustment using a filter or the like, it is difficult to obtain a high-precision adjustment angle due to manufacturing variations or the like because the gain decreases as a large adjustment angle is obtained. There is a problem that there is.

  In this regard, as shown in FIG. 3, the phase adjustment circuit 50 of the present embodiment includes a low-pass filter 210 for main phase adjustment and a high-pass filter 230 for fine phase adjustment. The low-pass filter 210 has a frequency characteristic in which the first signal VI having the frequency fin is input and the phase delay angle at the frequency fin is X degrees (X ≧ 0). The high-pass filter 230 receives the second signal GQ based on the output signal LQ from the low-pass filter 210, and has a frequency characteristic in which the phase advance angle at the frequency fin is Y degrees (Y ≧ 0). This phase advance angle Y degree is set to a value smaller than the phase delay angle X degree of the low-pass filter 210.

  As a result, it is possible to perform phase adjustment with high accuracy while suppressing the influence of manufacturing variation and the like. That is, by setting X degree> Y degree, the main phase adjustment is performed by the low-pass filter 210, and the fine phase adjustment is performed by the high-pass filter 230. As a result, as described above with reference to FIG. 6A and the like, the change in the phase adjustment angle becomes small with respect to the variation in the cutoff frequency, and the phase can be adjusted with high accuracy.

  In addition, by providing the low-pass filter 210, even when the input signal VI includes a high-frequency component such as a beard, it is possible to suppress unnecessary pulses due to the high-frequency component from being output to the clock signal CK. For example, in the detection apparatus 30 to be described later with reference to FIG. 10, the sensor device 10 is driven by the rectangular wave drive signal VD, and therefore the signals ISP and ISM from the sensor device 10 include a whisker due to the edge of the rectangular wave. May be. Even in such a case, it is possible to remove the whiskers in this embodiment.

  Further, by providing the high pass filter 230, the DC component of the input signal VI can be cut. For example, in the detection device 30, the DC offset voltage from the I / V conversion circuit 42 may be input to the phase adjustment circuit 50. In the present embodiment, since the delay adjustment circuit 240 outputs the clock signal CK based on the signal from which the DC offset voltage is cut, a change in the duty of the clock signal CK due to the DC offset voltage can be suppressed.

  The phase adjustment circuit of this embodiment includes an amplifier circuit 220 as shown in FIG. The amplifier circuit 220 amplifies the output signal LQ from the low-pass filter 210 and outputs the amplified signal to the high-pass filter 230 as the second signal GQ. The low-pass filter 210 is a passive filter.

  In this way, even if the passive low-pass filter 210 performs the main phase adjustment, the signal LQ can be amplified even if the amplitude of the output signal LQ decreases. Thereby, compared with the above-mentioned first comparative example, a signal having a sufficient amplitude can be supplied to the delay adjustment circuit 240, and it is possible to suppress a through current from flowing through the delay element. Further, by providing the amplifier circuit 220, the high-pass filter 230 can be configured simply because the high-pass filter 230 in the subsequent stage can be driven even if it is a passive filter.

  Further, the phase adjustment circuit of the present embodiment includes a delay adjustment circuit 240 as shown in FIG. As will be described later with reference to FIG. 9, the delay adjustment circuit 240 includes a plurality of delay elements BF1 to BFj that delay the output signal HQ from the high-pass filter 230. Specifically, the delay adjustment circuit 240 adjusts the delay time of the output signal HQ from the high-pass filter 230 to adjust the phase of the output signal CK of the phase adjustment circuit with respect to the first signal VI.

  In this way, even when the phase adjustment angle by the low-pass filter 210 or the high-pass filter 230 varies due to manufacturing variations or the like, the delay adjustment circuit 240 can absorb the variations and perform accurate phase adjustment. it can. Accordingly, as will be described later with reference to FIG. 11A and the like, the detection timing of the desired signal can be adjusted with high accuracy, so that the accuracy of sensing such as angular velocity by the sensor device can be improved. Further, as described above with reference to FIG. 6A and the like, the phase adjustment range of the delay adjustment circuit 240 can be reduced by reducing the manufacturing variation of the phase adjustment angle of the filter. Therefore, the layout area of the delay adjustment circuit 240 can be reduced.

  In the present embodiment, as shown in FIG. 4, the low-pass filter 210 is a passive filter composed of a resistance element RL and a capacitor CL. The amplifier circuit 220 is a non-inverting amplifier circuit composed of an operational amplifier OP and resistance elements R1 and R2. The high pass filter 230 is a passive filter composed of a resistance element RH and a capacitor CH. As will be described later with reference to FIG. 9, the delay adjustment circuit 240 performs phase adjustment by selecting and outputting one of the output signals DS1 to DSj of the delay circuits of the plurality of delay circuits BF1 to BFj.

  In this way, the phase main adjustment low-pass filter 210, the phase fine adjustment high-pass filter 230, the amplification circuit 220 that amplifies the signal LQ, and the delay adjustment circuit 240 that adjusts the delay time of the clock signal CK as described above. Is feasible.

  In the present embodiment, the phase adjustment angle in the delay adjustment circuit 240 is desirably an angle of Y degrees or less. The phase delay angle X degree of the low-pass filter 210 is desirably an angle of 80 degrees or more and 90 degrees or less, and the phase advance angle Y degree of the high-pass filter 230 is an angle of 0 degrees or more and 10 degrees or less. It is desirable.

  In this way, as described above with reference to FIG. 6A and the like, it is possible to reduce the change in the phase adjustment angle with respect to the change in the cutoff frequency of the low-pass filter 210 and the high-pass filter 230. In addition, by setting the phase adjustment angle in the delay adjustment circuit 240 to Y degrees or less, the layout area of the delay elements BF1 to BFj can be reduced.

4). Second Configuration Example of Phase Adjustment Circuit In the above embodiment, the main phase adjustment is performed using the low-pass filter. However, in the present embodiment, the main phase adjustment may be performed using the high-pass filter. FIG. 7 shows a second configuration example as a configuration example of the phase adjustment circuit in this case. The phase adjustment circuit shown in FIG. 7 includes a first high-pass filter 250, an amplifier circuit 220, a second high-pass filter 230, and a delay adjustment circuit 240.

  The high-pass filter 250 receives a sine wave input signal VI (voltage signal) having a frequency fin. The high-pass filter 250 advances the phase at the frequency fin and performs the main adjustment of the phase adjustment performed by the phase adjustment circuit. Specifically, the high-pass filter 250 rotates the phase by an angle larger than at least 45 degrees out of 90 degrees adjusted by the phase adjustment circuit. Desirably, the high pass filter 250 advances the phase at the frequency fin by 80 degrees to 90 degrees. The high pass filter 250 includes a capacitor CH1 and a resistance element RH1.

  The amplifier circuit 220 amplifies the signal whose amplitude is reduced by the gain of the high-pass filter 250 and adjusts the amplitude of the signal input to the delay adjustment circuit 240. The amplifier circuit 220 includes an operational amplifier OP and resistance elements R1 and R2.

  The high pass filter 230 advances the phase at the frequency fin and performs fine adjustment of the phase adjustment performed by the phase adjustment circuit. Specifically, the high-pass filter 230 rotates the phase by an angle smaller than 45 degrees out of 90 degrees adjusted by the phase adjustment circuit. Desirably, the high-pass filter 230 advances the phase at the frequency fin by 0 degrees to 20 degrees. The high pass filter 230 includes a capacitor CH2 and a resistance element RH2.

  FIG. 8 shows an example of the phase adjustment angle in the second configuration example. In the following description, a case where a phase adjustment circuit is applied to the detection device 30 described later in FIG. 10 will be described as an example, and the phase of the clock signal CK is advanced by 90 degrees with respect to the input signal IFD of the drive circuit 40.

  As shown in FIG. 8, for example, the phase is delayed by 5 degrees by the I / V conversion circuit 42. In this case, the high-pass filter 250 advances the phase by 87 degrees to perform the main adjustment, the amplifier circuit 220 delays the phase by 5 degrees, the high-pass filter 230 advances the phase by 14.5 degrees, and performs the fine adjustment, and the delay adjustment circuit 240 adjusts to delay the phase by 1.5 degrees. With these adjustments, the phase adjustment circuit advances the phase of the clock signal CK by 90 degrees. In this example, the gain of the high-pass filter 230 is about −30 dB, and the amplifier circuit 220 performs amplification of 25 to 30 dB.

  According to the above embodiment, the phase adjustment circuit includes the first high-pass filter 250 for phase main adjustment and the second high-pass filter 230 for fine phase adjustment. The high-pass filter 250 has a frequency characteristic in which the first signal VI having the frequency fin is input and the phase advance angle at the frequency fin is X2 degrees (X2 ≧ 0). The high pass filter 230 receives the second signal GQ based on the output signal HQ1 from the high pass filter 250, and has a frequency characteristic in which the phase advance angle at the frequency fin is Y2 degrees (Y2 ≧ 0). The phase advance angle Y2 degrees by the high-pass filter 230 is set to a value smaller than the phase advance angle X2 degrees by the high-pass filter 250.

  In this way, by providing the first high-pass filter 250 for phase main adjustment and the second high-pass filter 230 for phase fine adjustment, the influence of manufacturing variations is suppressed as in the first configuration example. High-accuracy phase adjustment and area reduction of the delay adjustment circuit are possible.

  In the above embodiment, the low-pass filter 210 shown in FIG. 4 and the high-pass filter 250 shown in FIG. 7 are composed of passive filters and the active amplifier circuit 220 is provided. However, the present embodiment is not limited to this. . That is, the low-pass filter 210 and the high-pass filter 250 may be configured by an active filter capable of amplifying without providing the amplifier circuit 220.

5. Delay Adjustment Circuit FIG. 9 shows a detailed configuration example of the delay adjustment circuit 240 described above. The delay adjustment circuit 240 includes a delay circuit 241 and a selection circuit 242.

  The delay circuit 241 converts a sine wave signal HQ having a frequency fin into a clock signal, and outputs a plurality of clock signals DS1 to DSj (j is a natural number) with edge timings sequentially delayed. Specifically, the delay circuit 241 includes a plurality of buffer circuits BF1 to BFj. The buffer circuits BF1 to BFj sequentially delay the edge timing of the clock signal and output the clock signals DS1 to DSj to the first to jth nodes TP1 to TPj (first to jth taps).

  The selection circuit 242 selects any one of the clock signals DS1 to DSj and outputs the selected clock signal as the clock signal CK. Specifically, the selection circuit 242 selects the clock signals DS1 to DSj based on the set value SPD from the adjustment register 243. This adjustment register 243 is included in, for example, the detection device 30 described later in FIG. In the present embodiment, the selection is not limited to the selection by the adjustment register 243. For example, the clock signals DS1 to DSj may be selected at the time of manufacturing by laser trimming or the like.

6). Detection Device FIG. 10 shows a configuration example of a detection device to which the above-described phase adjustment circuit is applied. The detection device 30 includes a drive circuit 40, a phase adjustment circuit 50, and a detection circuit 60, and detects a desired signal included in a signal from the sensor device 10. Here, the detection device 30 is not limited to the configuration shown in FIG. 10, and various modifications such as omitting some of the components or adding other components are possible.

  The sensor device 10 is a physical quantity transducer such as a gyro sensor. For example, as a gyro sensor, a vibration-type angular velocity sensor that detects angular velocity from Coriolis force caused by rotation of a vibrator such as a piezoelectric element, or an angular acceleration sensor that detects angular acceleration from changes in capacitance or inertial force. Etc. can be adopted. In the following, a case where the sensor device 10 is a vibration type gyro sensor will be described as an example, but the present embodiment is not limited to this.

  Here, the physical quantity transducer is an element for converting a physical quantity (a quantity representing the degree of property of an object, the unit of which is defined) into another physical quantity. As physical quantities to be converted, in addition to Coriolis force, force such as gravity, acceleration, and mass can be considered. Further, the physical quantity obtained by the conversion may be a voltage or the like in addition to the current.

  The drive circuit 40 outputs a drive signal VD (drive voltage, drive current) to drive the sensor device 10 and receives a feedback signal IFD (output current) from the sensor device 10. The drive circuit 40 thus forms an oscillation loop and excites the sensor device 10.

  The detection circuit 60 receives the detection signals ISP and ISM (differential current signals) from the sensor device 10 driven by the drive signal VD, and detects a desired signal from the detection signals ISP and ISM. The desired signal is a signal representing a rotation direction and a rotation speed with respect to the detection axis of the sensor device 10, for example, a signal representing a Coriolis force generated by the rotation of the sensor device 10.

  More specifically, the drive circuit 40 includes an I / V conversion circuit 42 (current-voltage conversion circuit; an amplifier circuit in a broad sense), a high-pass filter 44, and a comparator 46.

  The I / V conversion circuit 42 amplifies the feedback signal IFD from the sensor device 10. Specifically, the I / V conversion circuit 42 amplifies the feedback signal IFD, which is a current signal, converts the feedback signal IFD into a voltage signal, and outputs the converted signal VD2.

  The high pass filter 44 performs a high pass filter process on the signal VD2 from the I / V conversion circuit 42 and outputs a processed signal VD3. The high pass filter 44 cuts the DC offset component of the signal VD2.

  The comparator 46 binarizes the signal VD3 from the high-pass filter 44 that is a sine wave, and supplies the rectangular wave signal after the binarization process to the sensor device 10 as the drive signal VD.

  The phase adjustment circuit 50 receives the signal VD2 from the I / V conversion circuit 42 of the drive circuit 40, shifts the phase of the signal VD2, and generates a clock signal CK. The phase adjustment circuit 50 outputs the clock signal CK to the A / D conversion circuit 100 of the detection circuit 60.

  The detection circuit 60 includes a Q / V conversion circuit 70 (charge-voltage conversion circuit; an amplifier circuit in a broad sense) and an A / D conversion circuit 100.

  The Q / V conversion circuit 70 converts the detection signals ISP and ISM, which are current signals from the sensor device 10, into a charge voltage by a differential amplifier, and uses the converted voltage signals VS1 and VS2 as differential outputs as an A / D conversion circuit. 100 is output. For example, the Q / V conversion circuit 70 includes an operational amplifier OPD and capacitors CF1 and CF2.

  The A / D conversion circuit 100 performs A / D conversion of the signals VS1 and VS2 from the Q / V conversion circuit 70 based on the clock signal CK from the phase adjustment circuit 50, and outputs the converted digital signal ADQ. .

  Next, the relationship between the phase adjustment by the phase adjustment circuit 50 and the sampling timing by the A / D conversion circuit 100 will be described with reference to FIGS. 11A and 11B.

  As shown in FIG. 11A, the differential signal (VS1-VS2) from the Q / V conversion circuit 70 includes a desired signal that is a detection target signal and an unnecessary signal that is a non-detection target signal. . The desired signal is a signal including information on the angular velocity sensed by the sensor device 10, and the amplitude represents the magnitude of the angular velocity. Therefore, as indicated by E1, the angular velocity is detected by sampling the peak value of the sine wave of the desired signal. This sampling is performed at the timing of the falling edge (or rising edge) of the clock signal CK, and the phase of the clock signal CK is adjusted to adjust this edge timing.

  Further, as shown in E2, the unnecessary signal that is not to be detected is 90 degrees out of phase (orthogonal) with respect to the desired signal, and therefore can be removed by sampling at the falling edge of the clock signal CK. It is. This unnecessary signal is caused by mechanical vibration leakage of the vibration type gyro sensor, and is caused by imbalance of the shape of the vibrator.

  As shown in FIG. 11B, the phase of the input signal VD2 to the phase adjustment circuit 50 is a signal in phase with the desired signal (in the example of FIG. 5, the phase difference is 5 degrees). This phase relationship is determined by, for example, the phase relationship between the drive signal VD and the detection signals ISP and ISM, the circuit characteristics of the I / V conversion circuit 42, the circuit characteristics of the Q / V conversion circuit 70, and the like. The phase adjustment circuit 50 performs adjustment to shift the phase of the clock signal CK by 90 degrees (85 degrees in the example of FIG. 5 described above) with respect to the phase of the signal VD2, and the A / D conversion circuit 100 samples the desired signal. Adjust timing.

  According to the above embodiment, the detection apparatus 30 includes the drive circuit 40 that drives the sensor device 10, the detection circuit 60 that receives the output signals ISP and ISM from the sensor device 10, and the phase adjustment circuit 50. Then, the signal VD2 from the drive circuit 40 is input to the phase adjustment circuit 50 as the first signal VI, and the phase adjustment circuit 50 sends the clock signal CK based on the first signal VI to the detection circuit 60. Output.

  More specifically, the detection circuit 60 includes a charge / voltage conversion circuit (Q / V conversion circuit 70) that converts the output signals ISP and ISM from the sensor device into a charge voltage, and an output signal VS1 and VS1 from the charge / voltage conversion circuit. It has an A / D conversion circuit 100 for A / D converting VS2. Then, the A / D conversion circuit 100 samples signals based on the output signals VS1 and VS2 of the charge-voltage conversion circuit based on the clock signal CK.

  In this way, as described above with reference to FIG. 11A and the like, the edge timing of the clock signal CK is adjusted by the phase adjustment circuit 50, so that the peak value of the desired signal included in the signal (VS1-VS2). Can be accurately sampled. Thereby, the detection accuracy of the angular velocity represented by the amplitude of the desired signal can be improved.

  In the above embodiment, the case where the signals VS1 and VS2 themselves are A / D converted as signals based on the output signals VS1 and VS2 of the charge-voltage conversion circuit has been described, but the present embodiment is not limited to this. In other words, in the present embodiment, another circuit is provided between the charge-voltage conversion circuit and the A / D conversion circuit 100, and signals from other circuits are output as signals based on the output signals VS1 and VS2 of the charge-voltage conversion circuit. D conversion may be performed.

  In the above-described embodiment, the case where the desired signal is directly A / D converted by the phase-adjusted clock signal CK has been described. However, the present embodiment is not limited to this. For example, when detecting a desired signal by synchronous detection, the phase adjustment circuit 50 of the present embodiment may be applied to adjust the phase of the clock signal for synchronous detection according to the phase relationship with the desired signal.

7). Electronic Device FIG. 12 shows a configuration example of an electronic device to which the detection device 30 is applied. This electronic apparatus includes a sensor device 10, a detection device 30 (an integrated circuit device in a broad sense), a processing unit 510, a storage unit 520, a wireless circuit 530, and an antenna 540. Note that the electronic apparatus of the present embodiment is not limited to the configuration shown in FIG. 12, and various modifications such as omitting some of the components or adding other components are possible.

  In this electronic apparatus, the sensor device 10 detects various physical quantities (force, acceleration, mass, etc.). Then, the physical quantity is converted into a current (charge), a voltage or the like and output as a detection signal. The detection device 30 receives the detection signal from the sensor device 10 and performs detection and A / D conversion of the detection signal. The processing unit 510 receives digital data from the detection device 30 and performs signal processing on the digital data. The storage unit 520 stores digital data from the detection device 30 and digital data from the processing unit 510. The radio circuit 530 performs modulation processing on the digital data from the detection device 30 and the processing unit 510 and transmits the digital data to an external device (an electronic device on the other side) using the antenna 540. The antenna 540 may be used to receive data from an external device, perform ID authentication, control the sensor device 10, and the like.

  According to the above configuration example, various electronic devices including a smoke sensor, an optical sensor, a human sensor, a pressure sensor, a biological sensor, a gyro sensor, and the like can be realized. In addition, an electronic device such as an IC tag (RF tag) used for RFID (Radio Frequency Identification) that performs writing and reading of data without contact using wireless communication can be realized.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (gain adjustment circuit, delay adjustment circuit, gyro sensor, etc.) described together with different terms (amplifier circuit, delay circuit, sensor device, etc.) having a broader meaning or the same meaning at least once The different terms can be used anywhere in the book or drawing. Further, the configuration and operation of the phase adjustment circuit, the detection device, the electronic device, and the like are not limited to those described in the present embodiment, and various modifications can be made.

10 sensor devices, 30 detection devices, 40 drive circuits, 42 I / V conversion circuits,
44 high-pass filter, 46 comparator, 50 phase adjustment circuit,
60 detection circuit, 70 Q / V conversion circuit, 100 A / D conversion circuit,
210 low-pass filter, 220 amplifier circuit, 230 high-pass filter,
240 delay adjustment circuit, 241 delay circuit, 242 selection circuit,
243 adjustment register, 250 high-pass filter, 510 processing unit,
520 storage unit, 530 wireless circuit, 540 antenna,
ADQ digital signal, BF1 to BFj, 1st to jth buffer circuits,
CH, CL, CH1, CH2 capacitors, CK clock signal,
CPB comparator, DS1 to DSj output signal,
DS1 to DSj 1st to jth clock signals, IFD feedback signal,
ISP, ISM detection signal, OP operational amplifier,
R1, R2, RH, RH1, RH2, RL resistance elements,
TP1 to TPj 1st to jth nodes, VD drive signal, VI input signal,
X phase delay angle, Y phase advance angle,
fc, fc1, fc2, fcH, fcL Cutoff frequency, fin frequency

Claims (9)

A drive circuit for driving the sensor device;
A phase adjustment circuit that receives a signal from the drive circuit as a first signal and outputs a clock signal based on the first signal;
A charge-voltage conversion circuit that converts an output signal from the sensor device into a charge-voltage, and
An A / D conversion circuit that samples an output signal from the charge-voltage conversion circuit based on the clock signal and performs A / D conversion;
Including
The phase adjustment circuit includes:
Is the first signal of frequency fin is input, a low-pass filter for phase main adjustment having a frequency characteristic that the phase delay angle becomes X degrees in the frequency fin,
A second signal based on the output signal from the low-pass filter is input, has a frequency characteristic in which the phase advance angle at the frequency fin is Y degrees, and the Y degree is set to a value smaller than the X degree. High-pass filter for fine phase adjustment,
Have
The X degree is
An angle of 80 degrees or more and 90 degrees or less,
The Y degree is
A detection device having an angle of 0 ° to 10 ° . In claim 1,
The phase adjustment circuit includes:
An amplification circuit that amplifies the output signal from the low-pass filter and outputs the amplified signal as the second signal to the high-pass filter;
The low pass filter is
A detection device characterized by being a passive filter. In claim 2,
The phase adjustment circuit includes:
A detection apparatus comprising a delay adjustment circuit having a plurality of delay elements for delaying an output signal from the high-pass filter. In claim 3,
The delay adjustment circuit is
A detection apparatus that adjusts a delay time of an output signal from the high-pass filter to adjust a phase of an output signal of the phase adjustment circuit with respect to the first signal. In claim 4,
The low pass filter is
It is a passive filter composed of a resistance element and a capacitor,
The amplifier circuit is
It is a forward rotation amplification circuit composed of an operational amplifier and a resistance element,
The high-pass filter is
It is a passive filter composed of a resistance element and a capacitor,
The delay adjustment circuit is
A detection apparatus that performs phase adjustment by selecting and outputting one of the output signals of each delay circuit of the plurality of delay circuits. In any of claims 3 to 5,
The phase adjustment angle in the delay adjustment circuit is
A detection apparatus having an angle of Y degrees or less. A drive circuit for driving the sensor device;
A phase adjustment circuit that receives a signal from the drive circuit as a first signal and outputs a clock signal based on the first signal;
A charge-voltage conversion circuit that converts an output signal from the sensor device into a charge-voltage, and
An A / D conversion circuit that samples an output signal from the charge-voltage conversion circuit based on the clock signal and performs A / D conversion;
Including
The phase adjustment circuit includes:
It is input first signal frequency fin, a first high-pass filter for phase main adjustment having a frequency characteristic which the phase advances angle becomes X2 degrees in the frequency fin,
A second signal based on the output signal from the first high-pass filter is input, and has a frequency characteristic in which the phase advance angle at the frequency fin is Y2 degrees, and the Y2 degrees is smaller than the X2 degrees. A second high-pass filter for fine phase adjustment to be set;
Have
The X2 degrees is
An angle of 80 degrees or more and 90 degrees or less,
Y2 degrees is
A detection device having an angle of 0 ° to 20 ° . In any one of Claims 1 thru | or 7 ,
The sensor device is
A detection device characterized by being a gyro sensor. An electronic apparatus comprising a detection device according to any one of claims 1 to 8.

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