JP5604995B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor element is soldered onto a substrate via Pb-free solder.

  Conventionally, the general manufacturing method of this kind of semiconductor device is as follows (for example, refer patent document 1). A solder made of Pb-free solder not containing Pb is mounted on a substrate such as a heat sink or a wiring board, and the solder is melted to form a solder. Thereafter, a rectangular plate-shaped semiconductor element made of silicon is mounted on the soldering solder, and soldering is performed by reflowing the soldering solder. Thus, a semiconductor device is completed.

JP-A-3-230864

  However, unlike conventional Sn—Pb solder containing Pb, the wettability of Pb-free solder is poor, and it is difficult for the entire bonding surface of the semiconductor element to wet. For this reason, a phenomenon that the solder between the substrate and the semiconductor element does not exist at the end of the semiconductor element, particularly at the four corners, a so-called solder drawing phenomenon occurs.

  For example, in the case where a wire bonding pad is provided at a corner of a semiconductor element, when solder pulling occurs at this corner, the bottom of the corner is not supported by solder and becomes a hollow bond, resulting in a semiconductor. There are concerns about element damage and wire bonding strength reduction. In addition, the occurrence of solder shrinkage means that the non-wetting area is increased, and there is a concern about an increase in thermal resistance and consequently a temperature rise of the semiconductor element.

  The present inventor made a prototype based on a conventional manufacturing method and examined the solder shrinkage. FIGS. 6A and 6B are process diagrams showing a method for manufacturing a semiconductor device as a prototype performed by the present inventor. FIGS. 6A, 6B, and 6C are schematic cross-sectional views, and FIG. It is a top view.

  Here, as a typical soldering method, Su-0.7% Cu-0.06% Ni solder is used as solder J30 made of Pb-free solder, and Ni plating (thickness 2.5) is used as a substrate on the joint surface. The heat sink 20 made of Mo or Cu having a thickness of about ~ 5.5 μm was used.

  Then, solder J30 in a solder foil state is placed on the heat sink 20 (see FIG. 6 (a)), hydrogen reflow is performed to form solder J30 as a welcome solder (see FIG. 6 (b)). The semiconductor element 10 was placed on the solder J30, and hydrogen reflow was performed again to connect the heat sink 20 and the semiconductor element 10 to form a semiconductor device (see FIGS. 6C and 6D).

  Here, as shown in FIG. 6B, when the solder J30 is melted in the soldering solder forming step, the solder J30 is shrunk due to the strength of the surface tension of the solder J30, and the solder as the soldering solder at the end of the reflow. The shape of J30 is a mountain shape having a high center and a low end.

  Therefore, when the semiconductor element 10 is placed thereon, as shown in FIG. 6B, only the center of the solder J30 is in contact with the bonding surface of the semiconductor element 10, but the end of the solder J30 is bonded to the semiconductor element 10. There will be no contact with the surface.

  By subsequent hydrogen reflow, the solder J30 is pushed by the semiconductor element 10 and the solder thickness becomes uniform up to the vicinity of the end of the semiconductor element 10, but the solder J30 below the end of the semiconductor element 10 is low, and FIG. As shown in c) and (d), soldering occurs without contacting the semiconductor element 10. This soldering is particularly noticeable at the corner 11 of the semiconductor element 10.

  Here, simply, in order to increase the amount of solder, it is conceivable to increase the area of the solder J30, that is, the area of the solder foil.

  However, in this case, when the completed semiconductor device is further soldered to another substrate or the like, the solder J30 between the heat sink 20 and the semiconductor element 10 is remelted and the semiconductor element 10 on the heat sink 20 is soldered to the solder J30. There is a risk that the position will change by moving and rotating the top. If the area of the solder J30 is large, the positional displacement distance of the semiconductor element 10 is correspondingly increased. Therefore, it can be said that it is not preferable to increase the area of the solder J30.

  In any case, conventionally, there has been no method for reliably bringing the molten solder into contact with the entire bonding surface of the semiconductor element in the soldering method for performing the soldering.

  The present invention has been made in view of the above problems, and in a method of manufacturing a semiconductor device in which a semiconductor element is soldered onto a substrate via Pb-free solder, the entire bonding surface of the semiconductor element is melted. An object of the present invention is to make sure that solder is brought into contact with the semiconductor element and prevent the occurrence of solder at the end of the semiconductor element.

In order to achieve the above object, in the invention described in claim 1, the solder (30) is placed from the substrate (20) side more than the low-temperature solder layer (31) made of Pb-free solder and the low-temperature solder layer (31). It is assumed that a high-temperature solder layer (32) made of Pb-free solder having a high melting point and having a flat joint surface with the semiconductor element (10) is laminated. When soldering, the high-temperature solder layer (32) is joined. In order to maintain the flatness of the surface, the high-temperature solder layer (32) is in a solid state, and a first melting step is performed in which the low-temperature solder layer (31) is melted as a whole. The semiconductor element (20) is mounted on the joint surface of (32), and then a second melting step is performed in which the high-temperature solder layer (32) is melted together with the low-temperature solder layer (31) and soldered . , Solder In 30), towards the high temperature solder layer (32) is characterized by a thicker than low temperature solder layer (31).

  According to this, in the first melting step, the low-temperature solder layer (31) on the substrate (20) side is melted, but the high-temperature solder layer (32) thereon is flatness of the joint surface with the semiconductor element (10). Therefore, when the semiconductor element (10) is mounted, the upper surface of the solder (30) is ensured to be flat. Moreover, since the low temperature solder layer (31) has sufficient wettability with the high temperature solder layer (32), the low temperature solder layer (31) spreads over the entire high temperature solder layer (32).

  If the semiconductor element (10) is mounted on the solder (30) in this state, the semiconductor element (10) is attached to the upper surface of the flat solder (30), that is, the flat joint surface of the high-temperature solder layer (32). In addition, since the second melting step is performed in this state, the molten solder (30) is wetted and spread over the entire bonding surface of the semiconductor element (10). Is done.

Therefore, according to the present invention, the molten solder (30) is reliably brought into contact with the entire bonding surface of the semiconductor element (10), and the occurrence of solder shrinkage is prevented at the end of the semiconductor element (10). Can do. In the present invention, in the solder (30), since the high temperature solder layer (32) is thicker than the low temperature solder layer (31), the thickness of the high temperature solder layer (32) can be secured. In the first melting step, even if the low-temperature solder layer (31) is in a molten state, it is easy to ensure the flatness of the joint surface of the high-temperature solder layer (32), and in the first melting step, the high-temperature solder layer ( Even if part of 32) melts, it is easy to ensure the flatness of the joint surface of the high-temperature solder layer (32).

Furthermore, in the invention according to claim 2 , in the method of manufacturing a semiconductor device according to claim 1 , the solder (30) is transferred from the substrate (20) side to the low-temperature solder layer (31) and the high-temperature solder layer (32). In addition, on the joint surface of the high-temperature solder layer (32), a Pb-free solder having a melting point lower than that of the high-temperature solder layer (32) and thinner than that of the low-temperature solder layer (31) is formed. 2 in which the second low-temperature solder layer (33) is laminated, and in the first melting step, the second low-temperature solder layer (33) is also completely melted, and then the second low-temperature solder layer (33) 33), the semiconductor element (10) is mounted on the joint surface of the high-temperature solder layer (32), and in the subsequent second melting step, the low-temperature solder layer (31), the high-temperature solder layer (32), and the second All of the low-temperature solder layer (33) of By, and performs soldering.

  According to this, in the first melting step, the second low-temperature solder layer (33) is in a molten state, but since it is the thinnest layer, the flatness of the joint surface of the high-temperature solder layer (32) is impaired. That is avoided as much as possible. In the second melting step, the joining surface of the high-temperature solder layer (32) and the semiconductor element (10) are joined through the second low-temperature solder layer (33) that is melted first. The adhesion between the flat bonding surface of the layer (32) and the semiconductor element (10) is improved.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect , the solder (30) has a rectangular plate shape corresponding to the semiconductor element (10), and the semiconductor element ( An extended portion (a portion of the solder (30) extended from the corner of the solder (30) corresponding to the corner (11) of 10) so as to protrude outside the side of the solder (30) ( 30a) is provided.

  According to this, since the amount of solder (30) in the portion located at the corner (11) of the semiconductor element (10) in the solder (30) can be locally increased, the corner of the semiconductor element (10) can be increased. This is preferable in terms of preventing the occurrence of solder shrinkage in the portion (11).

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

It is process drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. It is a schematic sectional drawing which shows the mode of generation | occurrence | production of the solder void by the conventional general soldering method. It is a schematic sectional drawing which shows the mode of generation | occurrence | production of the solder void in 1st Embodiment. It is process drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device as a trial manufacture which this inventor performed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(First embodiment)
FIG. 1 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Here, in FIG. 1, the process proceeds in the order of (a), (c), and (e), and finally the semiconductor device shown in (e) is completed, and (b) is in (a). FIG. 4D is an enlarged view of part A, and FIG. 5D is an enlarged view of part B in FIG.

  In the semiconductor device of this embodiment, as shown in FIG. 1E, a rectangular plate-like semiconductor element 10 made of silicon is soldered onto a substrate 20 via a solder 30 made of Pb-free solder. . Here, the planar shape of the semiconductor element 10 and the substrate 20 can be the same as that shown in FIG. 6D, for example.

  Specifically, examples of the semiconductor element 10 include an IC chip and a power element made of a silicon semiconductor formed by a general semiconductor process, and examples of the substrate 20 include a heat sink, a lead frame, and a wiring board. Here, the heat sink 20 is made of Mo, Cu, or the like.

  Further, the entire bonding surface (the lower surface in FIG. 1E) which is a surface bonded to the solder 30 in the semiconductor element 10 and the bonding surface which is a surface bonded to the solder 30 in the heat sink 20 (FIG. 1). A metal layer for soldering (not shown) is formed on the entire upper surface in (e). This metal layer is typically a Ti / Ni / Au film or the like.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. This manufacturing method includes a soldering process in which the semiconductor element 10 is soldered onto the heat sink 20 via a solder 30 made of Pb-free solder.

  In the present embodiment, as described above, a metal layer for soldering such as a Ti / Ni / Au film (not shown) is formed on the entire bonding surface of the semiconductor element 10 and the entire bonding surface of the heat sink 20. As long as these joint surfaces come into contact with the solder 30, the solder wettability is good.

  First, as shown in FIGS. 1A and 1B, the solder 30 is mounted on the joint surface of the heat sink 20. At this time, the solder 30 is formed by laminating a low-temperature solder layer 31 made of Pb-free solder and a high-temperature solder layer 32 made of Pb-free solder having a melting point higher than that of the low-temperature solder layer 31 from the heat sink 20 side.

  Further, the high-temperature solder layer 32 has a flat joint surface (the upper surface in FIGS. 1A and 1B) with the semiconductor element 10. The two solder layers 31 and 32 have a rectangular shape with the same size and the same planar shape.

  Specifically, the two layers 31 and 32 are rectangular slightly larger than the semiconductor element 10, and when the semiconductor element 10 and the solder 30 are overlapped, the solder 30 slightly extends from the entire outer periphery of the semiconductor element 10. (For example, about 0.1 mm) is set to a size that protrudes. The two layers 31 and 32 may have the same thickness or different thicknesses, but it is preferable that the high temperature solder layer 32 is thicker than the low temperature solder layer 31.

  The solder 30 having such a laminated structure is formed as follows. First, two types of solder foils having different compositions to be the low temperature solder layer 31 and the high temperature solder layer 32 are prepared. Here, in the case of a solder having a plurality of metal components, a plurality of types of metal particles are mixed with a predetermined composition and rolled to produce a foil.

  Then, these two types of foils are brought into contact with each other and heated below the melting temperature of the both foil members, so that some of the components (for example, Sn) in both foils diffuse to each other, whereby both foils The solder 30 having a laminated structure is completed by bonding.

  If an oxide film is formed on the surface of the solder foil, the metal may not be diffused. For example, it is necessary to perform the production in hydrogen + nitrogen and not mix oxygen. Further, the solder 30 having the present laminated structure may be produced by producing a solder foil on the high temperature side and immersing one side of the foil in a solder bath on the low temperature side.

  Specific examples of these low-temperature solder layer 31 and high-temperature solder layer 32 include Sn-0.7% Cu foil having an eutectic point of melting point: 227 ° C. as the low-temperature solder layer 31. Examples of the layer 32 include Sn-4.5% Cu-2% Ni foil having a eutectic point of melting point: 310 ° C.

  Further, the thickness of the entire solder 30 is the same as that of a conventional general solder. For example, when the thickness of the solder 30 in the above specific example of this embodiment is 80 μm, the low-temperature solder layer 31 is formed. The thickness of the Sn-0.7% Cu foil is about 30 μm, and the thickness of the Sn-4.5% Cu-2% Ni foil that becomes the high-temperature solder layer 32 is about 50 μm.

  Thus, the solder 30 having the two-layer structure is disposed on the joining surface of the heat sink 20 and soldering is performed. First, the first melting step shown in FIGS. 1C and 1D is performed. In this first melting step, the high temperature solder layer 32 is in a solid state while maintaining the flatness of the joint surface of the high temperature solder layer 32, while the low temperature solder layer 31 is in a molten state.

  The first melting step will be specifically described. The heat sink 20 on which the solder 30 is mounted is placed in an oven or the like, and the ambient temperature is a temperature equal to or higher than the melting point of the low temperature solder layer 31 and lower than the melting point of the high temperature solder layer 32. And Based on one specific example described above, hydrogen reflow is performed at 250 ° C., for example.

  If it does so, Sn-0.7% Cu which is the low-temperature solder layer 31 will fuse | melt, and will get wet on the joint surface of the heat sink 20. FIG. On the other hand, Sn-4.5% Cu-2% Ni, which is the high-temperature solder layer 32, does not melt at 250 ° C. and is in a solid state. Since the melted Sn-0.7% Cu is also wetted with Sn-4.5% Cu-2% Ni, the thickness of Sn-0.7% Cu does not change.

  That is, Sn-0.7% Cu which is the low-temperature solder layer 31 is sufficiently wetted with the Sn-4.5% Cu-2% Ni which is the high-temperature solder layer 32 and the heat sink 20, so that both of these It is restrained from above and below, and does not become a mountain shape as in the past. Therefore, Sn-0.7% Cu soldering that is solidified at a reduced temperature is substantially eliminated.

  Thereafter, a semiconductor element mounting step for mounting the semiconductor element 20 on the upper surface of the solder 30, that is, the bonding surface of the high-temperature solder layer 32 is performed. At this time, since the bonding surface of the high-temperature solder layer 32 is a flat surface, the entire bonding surface of the semiconductor element 10 including the corner portion 11 is in contact with the bonding surface of the high-temperature solder layer 32.

  Subsequently, a second melting step is performed in which the high-temperature solder layer 32 is melted together with the low-temperature solder layer 31 to perform soldering. That is, in the second melting step, both the two layers 31 and 32 between the semiconductor element 10 and the heat sink 20 are reflowed.

  The second melting step will be specifically described. The heat sink 20 on which the semiconductor element 10 and the solder 30 are mounted is placed in an oven or the like, and the ambient temperature is set to a temperature equal to or higher than the melting point of the high-temperature solder layer 32. Based on the specific example described above, hydrogen reflow is performed at 340 ° C., for example.

  Then, both the two layers 31 and 32, that is, the entire solder 30 are melted and then solidified by cooling, and the soldering is completed. Since the solder 30 melted in contact with the entire heat sink 20 and the joining surface of the semiconductor element 10, no soldering occurs, and a good fillet is formed as shown in FIG.

  Thus, the semiconductor device of this embodiment is completed. The completed solder 30 is configured as an alloy in which the components of the low-temperature solder layer 31 and the high-temperature solder layer 32 are mixed together.

  As described above, according to the manufacturing method of the present embodiment, in the first melting step, the low-temperature solder layer 31 on the heat sink 20 side is melted, but the high-temperature solder layer 32 thereon is a bonding surface with the semiconductor element 10. Since the solid state is maintained so as to maintain the flatness, the upper surface of the solder 30 ensures the flatness when the semiconductor element 10 is mounted. Further, the low temperature solder layer 31 wets and spreads over the entire high temperature solder layer 32 due to sufficient wetting with the high temperature solder layer 32.

  Since the semiconductor element 10 is mounted on the solder 30 in this state, the entire bonding surface of the semiconductor element 10 can be brought into contact with the flat bonding surface of the high-temperature solder layer 32. Since the melting step 2 is performed, a state in which the melted solder 30 wets and spreads over the entire bonding surface of the semiconductor element 10 is realized.

  Therefore, according to the present embodiment, the molten solder 30 is surely brought into contact with the entire bonding surface of the semiconductor element 10, and the soldering at the end including the four corners 11 of the rectangular semiconductor element 10 is prevented. Occurrence can be prevented.

  Further, as described above, in the manufacturing method of the present embodiment, it is desirable that the high temperature solder layer 32 is thicker than the low temperature solder layer 31 in the solder 30. According to this, since the thickness of the high temperature solder layer 32 can be ensured, it is easy to ensure the flatness of the joint surface of the high temperature solder layer 32 even if the low temperature solder layer 31 is in a molten state in the first melting step. Even if a part of the high-temperature solder layer 32 is melted, there is an advantage that it is easy to ensure the flatness of the joint surface of the high-temperature solder layer 32.

  Therefore, as shown in the above specific example, Sn-0.7% Cu foil is about 30 μm, and Sn-4.5% Cu-2% Ni foil is about 50 μm. When the% Cu foil is melted, the Sn-4.5% Cu-2% Ni foil restrains Sn-0.7% Cu and keeps the planar shape.

  Moreover, according to the manufacturing method of this embodiment, there is an advantage also about a solder void. FIG. 2 is a schematic cross-sectional view showing a state of generation of solder voids by a soldering method using a conventional general solder.

  When the conventional soldering method is applied, if there is a portion where the solder 30 is not partially wetted on the joint surface of the heat sink 20, when the semiconductor element 10 is mounted there, it becomes a void K (see FIG. 2).

  In particular, as shown in FIG. 2, when the portion where the solder 30 does not get wet is in the central portion of the solder 30 (near the top of the mountain-shaped solder 30), in the reflow after mounting the semiconductor element 10 on the tower, the solder 30 At the same time, the gas surrounded by the solder 30 and the semiconductor element 10 becomes the void K and is crushed. Since the semiconductor element 10 is directly above, the void K cannot escape to the outside and spreads sideways, so that the void K becomes large.

  On the other hand, FIG. 3 is a schematic cross-sectional view showing how solder voids are generated in the present embodiment, (a) and (b) show a semiconductor element mounting step, and (c) and (d) show a second state. The state after completion | finish of a melting process is shown. In FIG. 3, (b) is an enlarged view of part C in (a), and (d) is an enlarged view of part D in (c). In the present embodiment, the low-temperature solder layer 31 is melted in the first melting step, and the high-temperature solder layer 32 is in a solid state.

  That is, in the present embodiment, the void K is generated in the portion of the low-temperature solder layer 31 in the thickness direction of the solder 30 and is not a void over the entire thickness direction of the solder 30 as in the prior art. The size of the void K is smaller than the conventional one. Thus, in this embodiment, there exists an advantage that the size of a solder void can be made small.

  In addition, as the solder 30 used for the manufacturing method of the present embodiment, the low-temperature solder layer 31 shown in the above specific example is Sn-0.7% Cu, and the high-temperature solder layer 32 is Sn-4.5% Cu-2. The combination is not limited to the% Ni foil, and other combinations may be used.

  For example, the low-temperature solder layer 31 is Sn-3.5% Ag, Sn-3% Ag-0.5% Cu, Sn-0.7% Cu-0 on the phase diagram assuming that the eutectic point is the melting point. 0.06% Ni, Sn-8% Zn, etc., and 100% Sn (melting point: 232 [deg.] C.) may be mentioned as a melting point that is not a eutectic point.

  On the other hand, as the high temperature solder layer 32, Sn-6% Cu-3% Ni, Zn-5% Al, etc. are mentioned as those having eutectic points as melting points on the phase diagram, and melting points are not eutectic points. Sn-2% Co, Sn-1 to 2% Ge, Sn-2 to 3% Mn, Sn-30 to 50% Au, Sn-10 to 20% Ag, Sn-17 to 25% Sb, etc. Is mentioned.

  In addition, as a solder, the composition whose eutectic point is the melting point changes from the solid phase to the liquid phase at the eutectic temperature, so that it is better for the solder joint of this embodiment. That is, it is preferable to use the low-temperature solder layer 31 and the high-temperature solder layer 32 that have a eutectic point at the melting point.

  A composition whose eutectic point is not the melting point is solidified through a solid-liquid mixed state in which the solid phase and the liquid phase are mixed from the melting point. Therefore, for example, when the high-temperature solder layer 32 is such, the solder of the high-temperature solder layer 32 can be used in the first melting step even if the temperature is higher than the melting point of the low-temperature solder layer 31 and lower than the melting point of the high-temperature solder layer 32. Some of them (for example, Sn) may melt.

  However, the amount of the component in the high temperature solder layer 32 that melts at the reflow temperature of the low temperature solder layer 31 is small, and the high temperature solder layer 32 is large so as to maintain the flatness of the joint surface of the high temperature solder layer 32, that is, the upper surface of the solder 30. Since the portion is in a solid state, there is no problem.

(Second Embodiment)
FIG. 4 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Here, in FIG. 4, the process proceeds in the order of (a), (c), and (e), and finally the semiconductor device shown in (e) is completed, and (b) is in (a). FIG. 4D is an enlarged view of a portion E, and FIG. 4D is an enlarged view of a portion F in FIG.

  Whereas the solder 30 used in the manufacturing method in the first embodiment has a two-layer structure, the present embodiment is different in that the solder 30 has a three-layer structure. The point will be described mainly.

  As shown in FIGS. 4A and 4B, the solder 30 is mounted on the joint surface of the heat sink 20. At this time, in the present embodiment, the solder 30 is formed by laminating the low-temperature solder layer 31 and the high-temperature solder layer 32 from the heat sink 20 side. A three-layer structure in which low-temperature solder layers 33 are stacked is used. Hereinafter, the low-temperature solder layer 31 on the heat sink 20 side is referred to as a first low-temperature solder layer 31.

  Here, the second low-temperature solder layer 33 is made of Pb-free solder having a melting point lower than that of the high-temperature solder layer 32 and is thinner than the first low-temperature solder layer 31. Specifically, the second low-temperature solder layer 33 can be selected from the solder materials used for the first low-temperature solder layer 31 shown in the first embodiment. The first low-temperature solder layer 31 and the second low-temperature solder layer 33 may be made of the same material or different materials.

  Further, when the thicknesses of the first low-temperature solder layer 31 and the high-temperature solder layer 32 are the thicknesses of the specific example shown in the first embodiment, the thickness of the second low-temperature solder layer 33 is, for example, 10 μm. The following is assumed. Such a three-layer solder 30 can be produced by metal diffusion or the like, similar to the case of the two-layer 31 and 32 solders.

  And after arrangement | positioning of the solder 30, also in this manufacturing method, the 1st fusion | melting process shown by FIG.4 (c), (d) is performed. In this first melting step, both the first low-temperature solder layer 31 and the second low-temperature solder layer 33 are made while the high-temperature solder layer 32 is in a solid state so as to maintain the flatness of the joint surface of the high-temperature solder layer 32. Is in a molten state.

  At this time, the melted second low-temperature solder layer 33 at the uppermost part of the solder 30 has a mountain shape, but since the thickness thereof is thin, it becomes very gentle, so that the joint surface of the high-temperature solder layer 32 is flat. Performing sex is prevented as much as possible.

Thereafter, a semiconductor element mounting step is performed. Here, the semiconductor element 10 is mounted on the bonding surface of the high-temperature solder layer 32 via the second low-temperature solder layer 33. Then, the second melting step is performed. Here, all the three layers 31 to 33 are melted and heated by heating to all the melting temperatures of the three layers 31 to 33 at this time. Although the second low-temperature solder layer 33 exists between the joint surfaces of the semiconductor element 10 and the high-temperature solder layer 32, as described above, the mountain shape is very gentle. The entire joint surface is in contact with the second low-temperature solder layer 33.

  Therefore, also in this manufacturing method, as shown in FIG. 4E, the molten solder 30 is reliably brought into contact with the entire bonding surface of the semiconductor element 10, and solder is attracted at the end of the semiconductor element 10. Bonding that is prevented from occurring is performed, and the semiconductor device can be completed.

  Thus, according to the manufacturing method of the present embodiment, in the first melting step, the second low-temperature solder layer 33 is in a molten state, but is the thinnest layer. It is avoided as much as possible to impair the flatness.

  In the second melting step, the joining surface of the high-temperature solder layer 32 and the semiconductor element 10 are joined via the second low-temperature solder layer 33 that is melted first. The adhesion between the surface and the semiconductor element 10 is improved.

(Third embodiment)
FIG. 5 is a process chart showing a plan view of a method for manufacturing a semiconductor device according to the third embodiment of the invention. In this embodiment, the planar shape of the solder 30 is changed in the first embodiment. By spreading the solder outside the four corners of the rectangular plate-shaped solder 30, the four corners The place where soldering is prevented is different.

  Also in the manufacturing method of the present embodiment, the solder 30 is mounted on the joint surface of the heat sink 20 as shown in FIG. At this time, the solder 30 has a rectangular plate shape corresponding to the semiconductor element 10 as in the first embodiment. However, in this embodiment, the solder 30 further corresponds to the corner 11 of the semiconductor element 10. It is assumed that the extended portion 30 a is provided at the corner portion of 30.

  The expanded portion 30 a is a portion in which a part of the solder 30 is expanded at the corner portion of the solder 30 so as to protrude outward from the side of the solder 30. Here, the extended portion 30a has a shape protruding in a rectangular shape, but is not limited to this as long as it protrudes outward from the side of the solder 30, and may be, for example, a shape protruding in a circular shape.

  And after arrangement | positioning of this solder 30, also in this manufacturing method, the 1st fusion | melting process shown by FIG.5 (b) is performed. This first melting step may be performed in the same manner as in the first embodiment. Thereafter, if a semiconductor element mounting step is performed, and then the second melting step is performed in the same manner as described above, the semiconductor device of this embodiment is completed as shown in FIG.

  According to the manufacturing method of the present embodiment, the same effects as those of the first embodiment can be obtained, and the amount of the solder 30 in the portion of the solder 30 located at the corner 11 of the semiconductor element 10 by the extended portion 30. Therefore, a more preferable effect can be exhibited in terms of preventing the occurrence of solder shrinkage at the corners 11 of the semiconductor element 10.

  In the present embodiment, a part of the solder 30 only needs to be the extended portion 30a. Therefore, in addition to the first embodiment, the solder 30 having the three-layer structure as in the second embodiment can be used. Of course, it can be applied in combination.

DESCRIPTION OF SYMBOLS 10 Semiconductor element 11 Corner | angular part of semiconductor element 20 Heat sink as board | substrate 30 Solder 30a Expansion part 31 Low temperature solder layer 32 High temperature solder layer 33 2nd low temperature solder layer

Claims (3)

In the method of manufacturing a semiconductor device in which a rectangular plate-shaped semiconductor element (10) made of silicon is soldered onto a substrate (20) via a solder (30) made of Pb-free solder,
From the substrate (20) side, the solder (30) is made of a low-temperature solder layer (31) made of Pb-free solder, Pb-free solder having a melting point higher than that of the low-temperature solder layer (31), and the semiconductor element (10). ) And a high-temperature solder layer (32) having a flat joint surface,
At the time of the soldering, the high-temperature solder layer (32) is entirely in the solid state while the high-temperature solder layer (32) is in a solid state so as to maintain the flatness of the joint surface of the high-temperature solder layer (32). Performing a first melting step to a molten state,
Thereafter, mounting the semiconductor element (20) on the joint surface of the high-temperature solder layer (32),
Subsequently, a second melting step of performing soldering by melting the high temperature solder layer (32) together with the low temperature solder layer (31) is performed ,
In the solder (30), the high temperature solder layer (32) is thicker than the low temperature solder layer (31) . The solder (30) is formed by laminating the low-temperature solder layer (31) and the high-temperature solder layer (32) from the substrate (20) side, and further, the solder of the high-temperature solder layer (32) A second low-temperature solder layer (33) made of Pb-free solder having a melting point lower than that of the high-temperature solder layer (32) and thinner than the low-temperature solder layer (31) is laminated on the joint surface,
In the first melting step, the second low-temperature solder layer (33) is also in a state where the whole is melted,
Thereafter, the semiconductor element (10) is mounted on the joint surface of the high-temperature solder layer (32) via the second low-temperature solder layer (33),
In the subsequent second melting step, the low-temperature solder layer (31), the high-temperature solder layer (32), and the second low-temperature solder layer (33) are all melted and soldered. A method for manufacturing a semiconductor device according to claim 1 . The solder (30) has a rectangular plate shape corresponding to the semiconductor element (10), and the corner of the solder (30) corresponding to the corner (11) of the semiconductor element (10) to claim 1 or 2, characterized in that it is assumed that the solder (30) is enhanced some portion of the solder said edges so as to protrude outward from the (30) extension (30a) is provided The manufacturing method of the semiconductor device of description.

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