JP5603974B2 - Imaging system - Google Patents

Description

  The present invention relates to an imaging system.

  In recent years, there has been an increasing demand for processing image signals acquired at high speed in an imaging system as the number of pixels of the imaging apparatus increases. In order to meet such a demand, a technique has been proposed in which an A / D conversion unit that has been provided outside the imaging apparatus is provided in each column of the pixel array inside the imaging apparatus. Such an imaging apparatus is called a column AD type imaging apparatus. Hereinafter, a column AD type imaging apparatus will be specifically described with reference to the drawings.

  The conventional imaging system S1 includes an imaging device 700, an A / D conversion unit 4, a timing signal generation circuit 5, and a signal processing unit 7, as shown in FIG.

  The imaging device 700 photoelectrically converts an object image formed on the imaging surface to generate an analog image signal, and supplies the analog image signal to the signal processing unit 7. The timing signal generation circuit 5 supplies a timing signal to the A / D conversion unit 4 and the signal processing unit 7. The A / D conversion unit 4 performs A / D conversion on the analog image signal in synchronization with the timing signal to generate a digital image signal, and supplies the digital image signal to the signal processing unit 7. The signal processing unit 7 performs image processing on the digital image signal in synchronization with the timing signal, and outputs the processed digital image signal to the subsequent stage.

  On the other hand, as shown in FIGS. 9 and 10, a column AD type in which A / D conversion units 811, 812,... Are provided inside the imaging apparatus 800 and one in each column of the pixel array PA. An imaging system S2 including the imaging apparatus 800 is proposed. According to such a column AD type imaging apparatus 800, pixel signals can be read out at high speed, and the readout signals can be easily calculated.

  Signals are input from the pixels in each column of the pixel array PA to the A / D converters 811, 812,.

JP-A-2005-311487

  In the imaging apparatus 800 shown in FIGS. 9 and 10, all of the plurality of A / D conversion units 811... Are driven. As a result, power consumption for driving the plurality of A / D converters 811,... Increases, and the plurality of A / D converters 811,. In this case, the characteristics of the imaging device 800 may be deteriorated.

  For example, it is said that the dark current of a photodiode included in each pixel of the pixel array PA of the imaging device 800 generally increases twice as the temperature rises by 8 ° C. It is also well known that pixel pattern defects due to fixed pattern noise and dark current due to dark current variations in photodiodes have temperature characteristics and increase at higher temperatures.

  That is, when a plurality of A / D converters (a plurality of A / D converters) 811,... Generate heat, pixel pattern defects due to fixed pattern noise and dark current due to dark current variation of the photodiode increase. . Thereby, the image quality characteristic of the image according to the image signal acquired by the imaging device 800 may be deteriorated.

  An object of the present invention is to provide an imaging system capable of reducing heat generation by a plurality of A / D conversion means.

An imaging system according to a first aspect of the present invention includes a pixel array in which a plurality of pixels are arrayed in a row direction and a column direction, a row selection unit that selects a row in the pixel array, and the row selection unit selects Reading means for reading out and outputting signals of a plurality of pixels in a row, adding means for adding signals of pixels in two or more columns in the pixel array, and a plurality of A provided in each column of the pixel array An imaging device that includes an A / D conversion unit and a transfer unit that transfers a signal of a pixel in each column in the pixel array to the A / D conversion unit; Signal processing means for processing the image signal output from the signal processing means to generate image data; first addition processing in which the adding means adds signals of pixels in two or more columns in the pixel array; and the adding means 2 or more As well as switching control in accordance with one of the signal processing unit without adding the signals of pixels of the second addition processing for adding signals of the pixels of two or more columns to the frame rate of the image signal, the plurality Among the A / D conversion means, the A / D conversion means for transferring the pixel signals in the pixel array by the transfer means is driven, and the pixel signals in the pixel array are not transferred by the transfer means. And a control means for controlling the conversion means so as not to be driven .

  According to the present invention, heat generation by a plurality of A / D conversion means can be reduced.

1 is a configuration diagram of an imaging system S100 according to a first embodiment of the present invention. 1 is a configuration diagram of an imaging apparatus 100. FIG. FIG. 9 is a timing waveform diagram showing the operation of the imaging apparatus 100. The block diagram of imaging system S200 which concerns on 2nd Embodiment of this invention. FIG. 6 is a timing waveform diagram showing the operation of the imaging apparatus 200. The block diagram of imaging system S300 which concerns on 3rd Embodiment of this invention. FIG. 10 is a timing waveform diagram showing the operation of the imaging apparatus 300. The figure for demonstrating background art. The figure for demonstrating background art. The figure for demonstrating subordinate background art.

  An imaging system S100 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of an imaging system S100 according to the first embodiment of the present invention.

  The imaging system S100 includes an optical system 3, a mechanical shutter 2, an imaging device 100, a timing signal generation circuit 5, a drive circuit 6, a signal processing unit (signal processing means) 7, an image memory 8, a recording circuit 10, a display circuit 12, and An image display device 11 is provided. The imaging system S100 includes a system control unit (control unit) 13, a ROM 14, and a RAM 15.

  The optical system 3 includes a lens and a diaphragm. The optical system 3 forms an image set to an appropriate brightness on the imaging surface of the imaging apparatus 100.

  The mechanical shutter 2 is provided between the optical system 3 and the imaging device 100 on the optical path, and adjusts the amount of light (exposure time) guided to the imaging device 100 after passing through the optical system 3. Here, when the imaging apparatus 100 has an electronic shutter function, the mechanical shutter 2 and the electronic shutter may be used together to ensure a necessary exposure time.

  The imaging device 100 converts an image of a subject formed on the imaging surface (pixel array PA) into an analog image signal. The imaging apparatus 100 reads the analog signal from the pixel array PA, and A / D converts the read analog signal to generate a digital image signal. Then, the imaging apparatus 100 outputs the digital image signal.

  The timing signal generation circuit 5 supplies a timing signal to the drive circuit 6 and the signal processing unit 7. Thereby, the drive circuit 6 and the signal processing unit 7 operate in synchronization with the timing signal.

  The drive circuit 6 drives the optical system 3, the mechanical shutter 2, and the imaging device 100 in synchronization with the timing signal. The drive circuit 6 includes a supply unit (supply means) 6a (see FIG. 2). The supply unit 6a receives a signal of a pixel in the pixel array PA (see FIG. 2) from a plurality of A / D conversion units 111 and the like (see FIG. 2) by a signal transfer gate described later in one line period. Supply power to the / D converter. In one line period, the supply unit 6a supplies power to an A / D conversion unit to which a signal of a pixel in the pixel array PA is not input by a signal transfer gate described later among a plurality of A / D conversion units 111 and the like (see FIG. 2). Do not supply.

  The signal processing unit 7 performs arithmetic processing such as various corrections on the digital image signal in synchronization with the timing signal to generate image data. The arithmetic processing such as various corrections includes, for example, image processing such as color conversion, white balance, and gamma correction, resolution conversion processing, and image compression processing. This image data is supplied to the image memory 8, the display circuit 12, the system control unit 13, the recording circuit 10, and the like. The signal processing unit 7 is, for example, a signal processing circuit. The signal processing unit 7 also extracts information from the image signal and image data generated during the signal processing, such as information about the spatial frequency of the image, the average value of the designated area, the data amount of the compressed image, and the like. The information is output to the system control unit 13. Further, the signal processing unit 7 receives the image data read from the recording medium 9 by the recording circuit 10, and when the image data is a compressed image, the signal processing unit 7 performs an image expansion process on the image data and performs image memory processing. 8 is supplied.

  The signal processing unit 7 may output the image data without compressing it.

  The image memory 8 is connected to the signal processing unit 7 and stores image data output from the signal processing unit 7. The image memory 8 is used for temporarily storing an image signal being subjected to signal processing or for storing image data which is an image signal subjected to signal processing.

  The recording circuit 10 is an interface for connecting the recording medium 9. The recording medium 9 is detachably connected to the recording circuit 10. Thus, the image data output from the signal processing unit 7 is recorded on the recording medium 9 via the recording circuit 10. The recording circuit 10 converts the image data into data suitable for the recording medium 9 (for example, file system data having a hierarchical structure) and records the data on the recording medium 9. In addition, the recording circuit 10 outputs information such as the type and free capacity of the recording medium 9 to the system control unit 13. The recording circuit 10 reads out image data from the recording medium 9 and outputs it to the signal processing unit 7.

  The display circuit 12 converts the image data output from the signal processing unit 7 into an analog signal for display, and supplies the analog signal to the image display device 11. The analog signal for display is, for example, an NTSC analog signal.

  The image display device 11 displays an image corresponding to the image data based on the analog signal. That is, the image display device 11 functions as an electronic viewfinder. The image display device 11 is an LCD device, for example.

  The system control unit 13 controls the entire imaging system S100.

  For example, the system control unit 13 controls the imaging device 100 and the signal processing unit 7 as follows. When the frame rate of an image signal output by a later-described readout unit of the imaging device 100 is equal to or higher than a threshold, the later-described addition unit of the imaging device 100 adds the signals of pixels in two or more columns. Like that. When the frame rate of the image signal output from the reading unit of the imaging apparatus 100 is smaller than the threshold, the system control unit 13 does not add the signals of the pixels in two or more columns without the addition unit of the imaging apparatus 100. 7 adds the signals of pixels in two or more columns.

  The ROM 14 is a non-volatile storage for storing a program describing a control method executed by the system control unit 13, control data such as parameters and tables used when executing the program, and correction data such as defective pixel information. Memory.

  The RAM 15 is a volatile memory that transfers and stores the program, control data, and correction data stored in the ROM 14 and is used when the system control unit 13 controls the imaging system.

  Next, the configuration of the imaging apparatus 100 will be described with reference to FIG. FIG. 2 is a configuration diagram of the imaging apparatus 100.

  The imaging apparatus 100 includes a pixel array PA, a row selection unit (row selection unit) 120, and a readout unit (readout unit) 140.

  In the pixel array PA, a plurality of pixels A11,... Are arranged in the row direction and the column direction. Each pixel A11,... Includes a photodiode (not shown). The dark current of a photodiode is generally said to increase by a factor of 2 with a temperature increase of 8 ° C. In addition, fixed pattern noise due to dark current variations of photodiodes and pixel signal defects due to dark current have temperature characteristics and increase as the temperature increases. FIG. 2 exemplarily shows a case where the pixel array PA includes pixels A11 to B24 of 4 rows and 4 columns.

  The row selection unit 120 selects one row in the pixel array PA. For example, the row selection unit 120 supplies selection signals φSEL1 to φSEL4 for selecting each row such as the pixel A11 in the pixel array PA to the pixels A11 and the like via the row selection lines CL1 to CL4. The row selection unit 120 sequentially activates the selection signals φSEL1 to φSEL4 to sequentially select each row such as the pixel A11 in the pixel array PA. The row selection unit 120 is, for example, a vertical scanning circuit for scanning the pixel array PA in the vertical direction.

  The reading unit 140 selects each column from a plurality of pixels in the row selected by the row selection unit 120 in one line period after the row selection unit 120 selects one row and selects the next row. The pixels are sequentially read out and output.

  Specifically, the reading unit 140 includes preamplifiers 101 to 104, signal transfer gates M11 to M14, signal holding capacitors CT1 to CT4, signal transfer gates (transfer means) M21 to M24, and signal holding capacitors CH1 to CH4. The reading unit 140 includes an addition unit (addition unit) 141, a plurality of A / D conversion units (a plurality of A / D conversion units) 111 to 114, and a horizontal scanning circuit 203.

  The preamplifiers 101 to 104 are connected to the pixels A11 and the like in each column of the pixel array PA via column signal lines RL1 to RL4. The preamplifiers 101 to 104 amplify signals of the pixel A11 and the like transmitted via the column signal lines RL1 to RL4.

  The signal transfer gates M11 to M14 are switches for transferring the signals amplified by the preamplifiers 101 to 104 to the signal holding capacitors CT1 to CT4. The signal transfer gates M11 to M14 transfer the signals of the pixels in each column in the pixel array to the A / D converters 111 to 114. The signal transfer gates M11 to M14 are, for example, MOS transistors, and are turned on when an active signal is supplied to the gates to transfer the signals to the signal holding capacitors CT1 to CT4.

  The signal holding capacitors CT1 to CT4 temporarily hold the transferred signal.

  The signal transfer gates M21 to M24 are switches for transferring the signals held in the signal holding capacitors CT1 to CT4 to the signal holding capacitors CH1 to CH4.

  The signal holding capacitors CH1 to CH4 temporarily hold the transferred signal.

  The addition unit 141 is provided between the pixel array PA and the plurality of A / D conversion units 111 and the like, and adds signals of the pixels A11 and the like of two or more columns in the pixel array PA. Specifically, the addition unit 141 includes a horizontal addition gate M31 and a horizontal addition gate M32. The horizontal addition gate M31 is, for example, a MOS transistor, and transfers a signal held in the signal holding capacitor CT3 to the signal holding capacitor CH1 when an active signal is supplied to the gate. Accordingly, the horizontal addition gate M31 adds the signal held in the signal holding capacitor CT1 and the signal held in the signal holding capacitor CT3, and holds the added result in the signal holding capacitor CH1. The horizontal addition gate M32 is, for example, a MOS transistor, and when an active signal is supplied to the gate, the signal held in the signal holding capacitor CT4 is transferred to the signal holding capacitor CH2. Thereby, the horizontal addition gate M32 adds the signal held in the signal holding capacitor CT2 and the signal held in the signal holding capacitor CT4, and holds the addition result in the signal holding capacitor CH2.

  The plurality of A / D conversion units 111 to 114 are provided in each column in the pixel array PA. Each A / D conversion unit 111 to 114 A / D converts the signal (analog signal) held by the signal holding capacitors CH1 to CH4 to generate a digital signal. Each A / D converter 111-114 outputs the digital signal to the signal processor 7 (see FIG. 1).

  Here, in one line period, the supply unit 6a supplies the power supply φAD1 to the A / D conversion unit to which the pixel signal in the pixel array PA is input among the plurality of A / D conversion units 111 to 114. In one line period, the supply unit 6a does not supply the power supply φAD2 to an A / D conversion unit that does not receive a pixel signal in the pixel array PA among the plurality of A / D conversion units 111 to 114.

  The horizontal scanning circuit 203 sequentially supplies active signals to the signal transfer gates M21 to M24, and sequentially transfers the signals held by the signal holding capacitors CT1 to CT4 to the signal holding capacitors CH1 to CH4.

  As described above, the reading unit 140 performs A / D conversion on the pixel signals in the pixel array PA using the A / D conversion unit supplied with power from the supply unit 6a, and outputs a digital image signal.

  Next, the operation of the imaging apparatus 100 will be described with reference to FIG. FIG. 3 is a timing waveform diagram illustrating the operation of the imaging apparatus 100.

  At timing T0, the row selection unit 120 supplies an active selection signal φSEL1 to the pixel array PA, and selects the pixels A11, B11, A21, and B21 in the row of the pixel A11. Thereby, one line period LT1 starts.

  At timing T1, signals φM11 to φM14 supplied to the signal transfer gates M11 to M14 become active. As a result, the signals amplified by the preamplifiers 101 to 104 are transferred to the signal holding capacitors CT1 to CT4.

  At timing T2, the signals φM11 to φM14 become non-active. Thereby, the transfer of the signals amplified by the preamplifiers 101 to 104 to the signal holding capacitors CT1 to CT4 is completed.

  At timing T3, the row selection unit 120 changes the selection signal φSEL1 from the active level to the non-active level, and the selection of the row of the pixel A11 is completed.

  At timing T4, the signals φM21 and φM22 supplied to the signal transfer gates M21 and M22 are activated. Further, the signals φM31 and φM32 supplied to the horizontal addition gates M31 and M32 of the adding unit 141 are also activated. As a result, the signal held in the signal holding capacitor CT1 and the signal held in the signal holding capacitor CT3 are added and held in the signal holding capacitor CH1. The signal held in the signal holding capacitor CT2 and the signal held in the signal holding capacitor CT4 are added and held in the signal holding capacitor CH2. As a result, a signal obtained by adding the signals of the columns of the pixels A11 to A14 and the signals of the columns of the pixels A21 to A24 is input to the A / D conversion unit 111. A signal obtained by adding the signals of the columns of the pixels B11 to B14 and the signals of the columns of the pixels B21 to B24 is input to the A / D conversion unit 112.

  On the other hand, the signals φM23 and φM24 supplied to the signal transfer gates M23 and M24 remain inactive. That is, no signal is transferred to the signal holding capacitors CH3 and CH4, and no signal of the pixel in the pixel array PA is input to the A / D converters 113 and 114.

  At timing T5, the signals φM21, φM22, φM31, and φM32 become non-active. Thereby, the transfer of the signal to the signal holding capacitors CH1 and CH2 is completed.

  At timing T6, the supply unit 6a supplies the power supply φAD1 to the A / D conversion units 111 and 112 to which the pixel signals in the pixel array PA are input among the plurality of A / D conversion units 111 to 114. That is, the supply unit 6a supplies the active signal φAD1 to the A / D conversion units 111 and 112 as a power source. As a result, the A / D converters 111 and 112 A / D convert and output the signals held in the signal holding capacitors CH1 and CH2. On the other hand, the supply unit 6a does not supply the power supply φAD2 to the A / D conversion units 113 and 114 to which the pixel signals in the pixel array PA are not input among the plurality of A / D conversion units 111 to 114. That is, supply unit 6a keeps signal φAD2 in a non-active state.

  At timing T7, the supply unit 6a changes the signal φAD1 from an active level to a non-active level. Thereby, the supply unit 6a completes the supply of power to the A / D conversion units 111 and 112.

  At timing T8, the row selection unit 120 changes the selection signal φSEL1 from an active level to a non-active level. Thereby, the one line period LT1 is completed. In addition, the row selection unit 120 supplies an active selection signal φSEL2 to the pixel array PA, and selects the pixels A12, B12, A22, and B22 in the row of the pixel A12. As a result, the next one-line period LT2 starts.

  According to the present embodiment, since the unused A / D conversion units 113 and 114 are stopped, the power for driving the plurality of A / D conversion units 111 to 114 can be reduced. Thereby, the heat_generation | fever by the some A / D conversion parts 111-114 can be reduced. As a result, it can suppress that the characteristic of the imaging device 100 falls.

  For example, since heat generation by the plurality of A / D conversion units 111 to 114 can be reduced, the dark current of the photodiodes included in each pixel A11 and the like of the pixel array PA can be reduced. For this reason, it is possible to reduce defects in pixel signals due to fixed pattern noise and dark current due to dark current variation of the photodiode. Thereby, it can suppress that the image quality characteristic of the image according to the image signal acquired by the imaging device 100 falls.

  In recent years, the number of pixels in an imaging device has been increasing. Thus, it can be said that the power saving effect according to the present embodiment increases as the number of pixels of the imaging device increases. In addition, when the imaging apparatus is continuously driven at a high speed for a long time (that is, when an output signal is acquired at a frame rate equal to or higher than a threshold) as in the case of moving image output, the temperature rise of the imaging apparatus is particularly significant. . Therefore, it can be said that the effect of preventing image quality deterioration according to the present embodiment is great.

  As described above, according to the present embodiment, even when the imaging apparatus is continuously driven at a high speed when outputting a moving image (when an image signal is acquired at a frame rate equal to or higher than a threshold value), an image with good image quality is obtained. Can be obtained.

  Further, the reduction in power consumption of the image pickup apparatus extends the life of the power supply unit (battery or the like) of the image pickup system, so that it is possible to drive for a longer time and increase the number of shootable times.

  Next, an imaging system S200 according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a configuration diagram of an imaging system S200 according to the second embodiment of the present invention. In FIG. 4, illustration of parts unnecessary for description is omitted. Below, it demonstrates centering on a different point from 1st Embodiment, and abbreviate | omits description about the same part. In addition, the operations related to the columns of the pixels B11 to B14 and the columns of the pixels B21 to B24 in the pixel array PA are the same as the operations related to the columns of the pixels A11 to A14 and the columns of the pixels A21 to A24.

  As illustrated in FIG. 4, the imaging system S200 is different from the first embodiment in that the imaging system S200 includes an imaging device 200 and a drive circuit 206.

  The imaging apparatus 200 includes a reading unit 240. The reading unit 240 includes an adding unit 241. Adder 241 includes horizontal addition gate M43 in addition to horizontal addition gate M31. As shown in FIG. 5, the horizontal addition gate M31 and the horizontal addition gate M43 are alternately turned on every one line period LT201, LT202,. FIG. 5 is a timing waveform diagram showing the operation of the imaging apparatus 200.

  The drive circuit 206 includes a supply unit 206a. As shown in FIG. 5, the supply unit 206a alternately supplies power supplies φAD1, φAD2 to the A / D conversion unit 111 and the A / D conversion unit 113 for each line period LT201, LT202,. That is, the A / D conversion unit to which power is supplied from the supply unit 206a and the A / D conversion unit to which power is not supplied from the supply unit 206a are different for each line period LT201, LT202,.

  Specifically, as shown in FIG. 5, the operation of the imaging apparatus 200 is different from the first embodiment in the following points.

  At the timing T204b of the one line period LT202 following the one line period LT1, the signal φM23 supplied to the signal transfer gate M23 becomes active. Further, the signal φM43 supplied to the horizontal addition gate M43 of the adder 241 is also activated. As a result, the signal held in the signal holding capacitor CT1 and the signal held in the signal holding capacitor CT3 are added and held in the signal holding capacitor CH3. As a result, a signal obtained by adding the signal of the columns of the pixels A11 to A14 and the signal of the columns of the pixels A21 to A24 is input to the A / D conversion unit 113.

  On the other hand, the signal φM21 supplied to the signal transfer gate M21 remains inactive. That is, no signal is transferred to the signal holding capacitor CH1, and no pixel signal in the pixel array PA is input to the A / D converter 111.

  At timing T205b, the signals φM23 and φM43 become non-active. Thereby, the transfer of the signal to the signal holding capacitor CH3 is completed.

  At timing T206b, the supply unit 206a supplies the power supply φAD2 to the A / D conversion unit 113 to which the pixel signals in the pixel array PA are input among the plurality of A / D conversion units 111 to 114. That is, the supply unit 6a supplies the active signal φAD2 to the A / D conversion unit 113 as a power source. As a result, the A / D converter 113 performs A / D conversion on the signal held in the signal holding capacitor CH3 and outputs the signal. On the other hand, the supply unit 206a does not supply the power supply φAD1 to the A / D conversion unit 111 to which the pixel signal in the pixel array PA is not input among the plurality of A / D conversion units 111 to 114. That is, supply unit 206a keeps signal φAD1 in a non-active state.

  At timing T207b, the supply unit 206a changes the signal φAD2 from an active level to a non-active level. Thereby, the supply unit 206a completes the supply of power to the A / D conversion unit 113.

  Note that the A / D converter that is supplied with power by the supply unit 206a and the A / D converter that is not supplied with power by the supply unit 206a include a plurality of one-line periods (four one-line periods in FIG. 4). It may be different for each frame period.

  Next, an imaging system S300 according to a third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a configuration diagram of an imaging system S300 according to the third embodiment of the present invention. In FIG. 6, illustration of parts unnecessary for description is omitted. Below, it demonstrates centering on a different point from 1st Embodiment, and abbreviate | omits description about the same part. In addition, the operations related to the columns of the pixels B11 to B14 and the columns of the pixels B21 to B24 in the pixel array PA are the same as the operations related to the columns of the pixels A11 to A14 and the columns of the pixels A21 to A24.

  As illustrated in FIG. 6, the imaging system S300 is different from the first embodiment in that the imaging system S300 includes an imaging device 300 and a system control unit 313.

  The imaging apparatus 300 includes a pixel array PA300 and a readout unit 340.

  In the first read mode, the pixel array PA300 includes read columns (first columns) A11 to A14 and B11 to B14 from which signals are read from the pixels, and non-read columns (second columns) from which signals are not read from the pixels. ) A21 to A24, B21 to B24. The first read mode is, for example, a thinning read mode. In the pixel array PA300, signals are read from the pixels A11 to B24 in all columns in the second readout mode. The second read mode is, for example, a normal mode.

  The reading unit 340 includes signal transfer gates M313 and M314. The signal transfer gates M313 and M314 are not turned on in the one-line period LT301 in the first read mode. That is, in the first readout mode, the readout unit 340 reads out signals from pixels in the readout column in the pixel array PA and does not read out signals from pixels in the non-readout column in the pixel array PA. At this time, the readout unit 340 reads out and outputs the signals of the pixels in some columns from the plurality of pixels in the row selected by the row selection unit 120. In addition, the reading unit 340 reads signals from pixels in all columns in the pixel array PA in the second reading mode. At this time, the readout unit 340 reads out and outputs the signals of the pixels in all the columns from the plurality of pixels in the row selected by the row selection unit 120.

  The system control unit 313 controls the imaging device 300 and the signal processing unit 7 so as to switch between the first readout mode and the second readout mode according to a predetermined condition.

  For example, the system control unit 313 controls the imaging device 300 and the signal processing unit 7 as follows. When the frame rate of the image signal read by the reading unit 340 of the imaging device 300 is equal to or higher than the threshold, the system control unit 313 reads the pixel signal of the non-reading column when the imaging device 300 operates in the first reading mode. Make sure they are not released. When the frame rate of the image signal to be read is smaller than the threshold, the system control unit 313 reads the signals of the pixels in all the columns by operating the imaging apparatus 300 in the second reading mode, and the signal processing unit 7 does not read The signal of the pixel corresponding to the column is invalidated.

  Specifically, as shown in FIG. 7, the operation of the imaging apparatus 300 differs from the first embodiment in the following points. FIG. 7 is a timing waveform diagram illustrating the operation of the imaging apparatus 300.

  At timing T301, the signals φM11 and φM12 supplied to the signal transfer gates M11 and M12 are activated. As a result, the signals amplified by the preamplifiers 101 and 102 are transferred to the signal holding capacitors CT1 and CT2. On the other hand, the signals φM313 and φM314 supplied to the signal transfer gates M313 and M314 remain inactive.

  At timing T302, the signals φM11 and φM12 become non-active. Thereby, the transfer of the signals amplified by the preamplifiers 101 and 102 to the signal holding capacitors CT1 and CT2 is completed.

  In the pixel array PA300, in the first readout mode, readout rows (A11, B11), (A13, B13) from which signals are read from the pixels and non-readout rows (A21, B21) in which signals are not read from the pixels. , (A23, B23). That is, the pixel array PA300 may be thinned out not only in column units but also in row units in the first readout mode.

  Next, another modified example will be described. There are still image mode and moving image mode in the imaging mode of the imaging system. The still image mode includes a mode for recording information as it is captured (hereinafter referred to as RAW), a mode for recording an ornamental image (hereinafter referred to as JPG) generated from the RAW, and a mode for recording both RAW and JPG. is there. In addition, JPG has a large size that is the resolution as it is shot, and a small size that reduces the data capacity by reducing the resolution.

  In the RAW recording mode, it is necessary to read out signals of all the pixels from the pixel array of the imaging device. In addition, when generating a small size JPG in a mode in which both RAW and JPG are recorded, it is necessary to add RAW pixel signals by processing such as digital addition. In these cases, all the column A / Ds are used to read out all the pixel signals from the imaging device, and the read image signals are digitally added by the signal processing unit. That is, when the system control unit receives an instruction for operating in these modes from the user, the signals of all the pixels in the pixel array PA are read even if the frame rate of the output image signal is equal to or higher than the threshold value. The image pickup apparatus may be controlled as described above.

  On the other hand, when the system control unit receives an instruction for operating in a mode other than these from the user, the addition unit of the imaging device adds signals of pixels in two or more columns regardless of the frame rate. Also good. Alternatively, regardless of the frame rate, the system control unit operates in the second readout mode so that the signals of the pixels in all columns are read out, and the signal processing unit outputs the pixel signals corresponding to the non-readout columns. You may make it invalidate. As a result, the number of pixels included in the image signal, that is, the amount of data can be reduced, so that the image signal can be processed at high speed.

6a, 206a Supply unit 100, 200, 300 Imaging device 120 Row selection unit 140, 240, 340 Reading unit 141, 241 Addition unit PA, PA300 Pixel array S100, S200, S300 Imaging system

Claims (3)

A plurality of pixels pixel array arranged in rows and columns, and row selection means for selecting a row in the pixel array, and reads and outputs the signals of a plurality of pixels in a row in which the row selecting means has selected Reading means, adding means for adding signals of pixels in two or more columns in the pixel array, a plurality of A / D conversion means provided in each column of the pixel array, and each column in the pixel array the signals of the pixels comprises a transfer means for transferring to said a / D converting means, and an imaging device for acquiring an image signal by imaging an object image,
Signal processing means for processing image signals output from the imaging device to generate image data;
A first addition process in which the adding means adds signals of pixels in two or more columns in the pixel array; and the signal processing means adds two or more signals without adding the signals of pixels in two or more columns. One of the second addition processes for adding the signals of the pixels in the column in accordance with the frame rate of the image signal , and the transfer means among the plurality of A / D conversion means. Control means for driving the A / D conversion means to which the pixel signal in the pixel array is transferred, and controlling so that the transfer means does not drive the A / D conversion means to which the pixel signal in the pixel array is not transferred ,
An imaging system comprising:   When the frame rate of the image signal is equal to or higher than a threshold, the control means controls the addition means to execute a first addition process for adding signals of pixels in two or more columns, When the frame rate is smaller than the threshold value, the addition unit of the imaging device does not add the signals of the pixels of two or more columns, and the signal processing unit adds the signals of the pixels of two or more columns. The imaging system according to claim 1, wherein the imaging system is controlled to execute. A power supply unit configured to supply power to the plurality of A / D conversion units; and when the first addition process is performed by the control unit, the addition unit among the plurality of A / D conversion units The added signal supplies power to the A / D converter that is transferred by the transfer unit, and the signal added by the adder is not supplied to the A / D converter that is not transferred by the transfer unit. the imaging system of claim 1 or 2, wherein the controller controls the supply means.

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