JP5601821B2 - Thin film transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device, an electro-optical display device such as an organic electroluminescence (abbreviation: EL) display device, a thin film transistor used for a semiconductor device such as a semiconductor component, and a manufacturing method thereof.

  As a pixel switching element of a liquid crystal display device, a thin film transistor (abbreviation: TFT) using a thin film semiconductor layer is used. TFTs are also used in other electro-optical display devices such as organic EL display devices. The TFT is manufactured, for example, according to the procedure described below.

  First, a gate electrode material is formed on a substrate by sputtering, and patterned by photolithography and etching to form a gate electrode. Thereafter, a silicon nitride (SiN) film that becomes a gate insulating film, an amorphous silicon film that becomes an i-type semiconductor, and an N-type that becomes an N-type semiconductor by a plasma chemical vapor deposition (abbreviation: CVD) method. An amorphous silicon film is formed. Next, an electrode material to be a source electrode and a drain electrode is formed by sputtering and patterned by photolithography and etching to form a source electrode and a drain electrode. Thereafter, the N-type amorphous silicon film in the region between the source electrode and the drain electrode is removed by dry etching. Next, a desired resist pattern is formed by photolithography and unnecessary portions are removed by etching. Thereafter, a SiN film serving as a protective film is formed by plasma CVD. Through the above procedure, an inverted stagger type TFT using an amorphous silicon film as a silicon thin film in a channel part (hereinafter sometimes referred to as “channel part silicon thin film”) to be an i-type semiconductor is formed.

  TFTs are used not only for pixel switching elements but also for driving circuits such as source drivers and gate drivers. In order to realize a narrow frame and cost reduction of a display device such as a liquid crystal display device and an organic EL display device, a display device in which a driving circuit using TFTs is formed on the same glass substrate as a pixel portion has been developed. Yes.

  Since a large driving voltage is continuously applied to the TFT in the driving circuit for a long time as compared with the TFT used as the pixel switching element, the electrical characteristics are greatly deteriorated. Therefore, a method of manufacturing a TFT having higher stability by forming a microcrystalline silicon film by a plasma CVD method as a channel part silicon thin film in the TFT in the drive circuit has been proposed.

  A TFT using a microcrystalline silicon film as a channel portion silicon thin film (hereinafter sometimes referred to as “microcrystalline silicon TFT”) has a TFT using an amorphous silicon film as a channel portion silicon thin film (hereinafter referred to as “amorphous silicon”). There is an advantage that the change over time in the threshold voltage (Vth) generated by continuing to apply a voltage to the gate of the TFT is small compared to the case of “TFT” in some cases.

  On the other hand, the microcrystalline silicon TFT has the following problems. Since the band gap of microcrystalline silicon is narrower than the band gap of amorphous silicon, in the microcrystalline silicon TFT, when a reverse bias voltage is applied to the gate, the microcrystalline silicon film and the N-type amorphous film thereon are applied. Hole injection by band-to-band tunneling at the interface with the porous silicon film tends to occur. Therefore, there is a problem that the leakage current increases.

  Patent Documents 1 and 2 disclose techniques for suppressing the leakage current. In the thin film transistors disclosed in Patent Documents 1 and 2, an amorphous silicon film is sandwiched between a microcrystalline silicon film and an N-type amorphous silicon film, thereby forming an N-type amorphous silicon film. The band gap mismatch at the interface is reduced and the leakage current is suppressed. In the thin film transistors disclosed in Patent Documents 1 and 2, a silicon nitride film or a silicon oxide film is used as a gate insulating film in contact with the microcrystalline silicon film.

Japanese Patent Laying-Open No. 2005-167051 JP 2005-322845 A

  In a microcrystalline silicon TFT, when a silicon nitride film is used as a gate insulating film in contact with a microcrystalline silicon film, a so-called hot carrier (abbreviation: HC) that occurs when a large drain voltage and a gate voltage are continuously applied simultaneously. There is a problem that deterioration becomes large.

  For example, in a gate drive circuit, since a large drain voltage and gate voltage are simultaneously applied to some TFTs in the drive circuit, the electrical characteristics of the TFT deteriorate as HC deterioration. When the HC deterioration increases, there arises a problem that the life of the circuit operation is shortened. In addition, in order to ensure a margin for circuit operation, the size of the TFT becomes large, and there is a problem that a narrow frame cannot be realized.

  The above-described HC degradation in the microcrystalline silicon TFT occurs when hot carriers are injected into the silicon nitride film, which is a gate insulating film, when a large drain voltage and gate voltage are simultaneously applied. Therefore, HC degradation can be suppressed by applying a silicon oxide film having a high blocking effect of hot carrier injection to the gate insulating film.

  When a silicon oxide film is used as the gate insulating film of a microcrystalline silicon TFT, since there are few nuclei for crystal growth on the surface of the silicon oxide film, an attempt is made to form microcrystalline silicon on the silicon oxide film by plasma CVD. Microcrystalline silicon grows in an island shape. Along with this, a large amount of voids called voids are generated, which causes a problem that the on-characteristics of the TFT are extremely lowered. When the on-characteristics of the TFT are extremely lowered, a display failure due to insufficient writing of the TFT used for the pixel switching element and an operation failure due to insufficient writing of the TFT in the drive circuit occur.

  Table 1 summarizes the electrical characteristics of the TFT when a silicon nitride film is used as the gate insulating film in contact with the microcrystalline silicon film described above and when a silicon oxide film is used. As shown in Table 1, when a silicon nitride film is used as the gate insulating film, the on-characteristics are good, and the Vth shift with respect to the gate voltage stress, that is, the change with time of the threshold voltage (Vth) is small. HC deterioration is large. When a silicon oxide film is used as the gate insulating film, the Vth shift and HC deterioration with respect to the gate voltage stress are small, but the on-state characteristics are extremely lowered.

  An object of the present invention is to provide a thin film transistor in which a change in threshold voltage with time and hot carrier deterioration are as small as possible, and a decrease in on-state characteristics is as small as possible, and a method for manufacturing the same.

The thin film transistor of the present invention includes a gate electrode provided on an insulating substrate, a gate insulating film provided on the gate electrode, a microcrystalline silicon provided on the gate insulating film and in contact with the gate insulating film An active layer including a film; and a source electrode and a drain electrode provided on the active layer, wherein the gate insulating film includes a silicon oxide film provided in contact with the microcrystalline silicon film, a portion in contact with the microcrystalline silicon film, the microcrystalline silicon film composition formula SiO x _(x is the number of less than 2 1.2 or higher) have a composition represented by, included in the active layer, deposited It is formed by crystallizing characterized Rukoto in.

The thin film transistor manufacturing method of the present invention includes a step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film including a silicon oxide film on the gate electrode, and a step of forming on the gate insulating film. forming an active layer comprising a microcrystalline silicon film, on said active layer, and forming a source electrode and a drain electrode, in the step of forming a pre-Symbol gate insulating film, at least of the silicon oxide film In the step of forming the silicon oxide film and forming the active layer so that the upper part has a composition represented by a composition formula SiO _x (x is a number greater than or equal to 1.2 and less than 2), A silane gas is formed on the silicon oxide film having a composition represented by a composition formula SiO _x (x is a number of 1.2 or more and less than 2) and having oxygen vacancies as crystal growth nuclei on the upper surface. And water The microcrystalline silicon film is formed so as to be in contact with the silicon oxide film by depositing a silicon film with the growth of microcrystalline silicon by plasma chemical vapor deposition using a mixed gas containing an elementary gas. It is characterized by that.

According to the thin film transistor of the present invention, the gate insulating film is a silicon oxide film and is in contact with the microcrystalline silicon film of the active layer. The microcrystalline silicon film is formed by crystallization during film formation. The portion of the silicon oxide film in contact with the microcrystalline silicon film has a composition represented by the composition formula SiO _x (x is a number greater than or equal to 1.2 and less than 2), so that the microcrystalline silicon film of the silicon oxide film is formed. The power surface can be brought into a state in which oxygen vacancies as crystal growth nuclei are sufficiently present. As a result, a microcrystalline silicon film can be grown at a high density on the silicon oxide film, so that a microcrystalline silicon film having excellent crystallinity can be formed, and a decrease in on characteristics due to voids can be suppressed. .

  Since the active layer is formed including this microcrystalline silicon film, a change in the threshold voltage with time can be suppressed to be smaller than in the case where the microcrystalline silicon film is not included. In addition, since the gate insulating film includes a silicon oxide film, hot carrier injection into the gate insulating film can be prevented and hot carrier deterioration can be suppressed. Therefore, it is possible to realize a thin film transistor in which a change in threshold voltage with time and hot carrier deterioration are as small as possible, and a decrease in on-state characteristics is as small as possible.

According to the method for manufacturing a thin film transistor of the present invention, at least the upper part of the silicon oxide film constituting the gate insulating film has a composition represented by the composition formula SiO _x (x is a number of 1.2 or more and less than 2). Thus , the upper surface, which is the surface on which the microcrystalline silicon film of the silicon oxide film is to be formed, can be brought into a state where oxygen vacancies that are crystal growth nuclei are sufficiently present. Along with the growth of microcrystalline silicon by plasma chemical vapor deposition using a mixed gas containing silane gas and hydrogen gas on a silicon oxide film in which oxygen vacancies as crystal growth nuclei exist on the upper surface. By depositing the silicon film, the microcrystalline silicon film is formed so as to be in contact with the silicon oxide film. Therefore, the microcrystalline silicon film can be grown at a high density on the silicon oxide film, and the microcrystalline silicon film having excellent crystallinity can be obtained. A crystalline silicon film can be formed. Accordingly, a decrease in on-characteristic due to voids can be suppressed, and an active layer including a gate insulating film including a silicon oxide film and a microcrystalline silicon film can be provided.

  By configuring the gate insulating film so as to include the silicon oxide film, hot carrier injection into the gate insulating film can be prevented, so that hot carrier deterioration can be suppressed. By configuring the active layer so as to include the microcrystalline silicon film, it is possible to suppress a change in the threshold voltage with time compared to the case where the microcrystalline silicon film is not included. Therefore, it is possible to manufacture a thin film transistor in which a change in threshold voltage with time and deterioration of hot carriers are as small as possible, and a decrease in ON characteristics is as small as possible.

It is a top view which shows the structure of TFT array board | substrate 20 provided with TFT1 in the 1st Embodiment of this invention. It is a top view which shows the structure of the pixel part 21 of the TFT substrate 20 shown in FIG. It is sectional drawing seen from cut surface line AA of FIG. 2, BB, CC. 6 is a cross-sectional view showing a state at a stage where the formation of the SiO _x film 52 is completed. 6 is a cross-sectional view showing a state where patterning of a microcrystalline silicon film 62, an i-type amorphous silicon film 63, and an N-type amorphous silicon film 61 is completed. FIG. FIG. 6 is a cross-sectional view showing a state at a stage where the formation of the TFT channel portion 46 is completed. FIG. 10 is a cross-sectional view showing a state where formation of a pixel drain contact hole 47, a gate terminal portion contact hole 48, and a source terminal portion contact hole 49 is completed. FIG. 6 is a cross-sectional view showing a state in which pattern formation of a transparent pixel electrode 43, a gate terminal pad 44, and a source terminal pad 45 is completed. 5 is a cross-sectional view showing a state where a disconnection failure has occurred in the gate terminal pad 44. FIG. Is a graph showing the SiO _x composition dependence of on-current of the microcrystalline silicon TFT in the first embodiment of the present invention. It is a graph which shows the microcrystal silicon film thickness dependence of the off current of the microcrystal silicon TFT in the 1st Embodiment of this invention. It is a top view which shows the structure of 21 A of pixel parts of TFT substrate 20A in the 2nd Embodiment of this invention. It is sectional drawing seen from cut surface line AA, BB, CC of FIG. FIG. 6 is a cross-sectional view showing a state at a stage where the formation of a low silicon oxide (SiO _x ) film 52 is completed. 6 is a cross-sectional view showing a state where patterning of the microcrystalline silicon film 70, the i-type amorphous silicon film 63, and the N-type amorphous silicon film 61 is completed. FIG. Is a graph showing the SiO _x composition dependence of on-current of the microcrystalline silicon TFT of the second embodiment of the present invention. It is a graph which shows the microcrystal silicon film thickness dependence of the off current of the microcrystal silicon TFT in the 2nd Embodiment of this invention.

<First Embodiment>
FIG. 1 is a plan view showing a configuration of a TFT array substrate 20 including a TFT 1 according to the first embodiment of the present invention. FIG. 2 is a plan view showing the configuration of the pixel portion 21 of the TFT substrate 20 shown in FIG. FIG. 3 is a cross-sectional view taken along section lines AA, BB, and CC in FIG. In FIG. 3, cross-sectional views viewed along the cutting plane lines AA, BB, and CC in FIG. 2 are shown side by side.

  In the present embodiment, as the TFT array substrate 20, an active matrix type TFT array substrate (hereinafter sometimes referred to as "TFT substrate") for a liquid crystal display device using liquid crystal as a display element, more specifically, a gate driver is incorporated. The TFT substrate will be described as an example. The TFT substrate 20 includes a pixel unit 21 and a gate driver unit 22. Although not shown in FIG. 1, the TFT 1 is formed in the pixel portion 21 and the gate driver portion 22. In the pixel unit 21, a plurality of TFTs 1 are arranged in a matrix. A gate line 33 and a source line 40 are formed in the pixel portion 21. The gate wiring 33 and the source wiring 40 are electrically connected to each TFT 1. Since the TFT 1 formed in the pixel portion 21 and the TFT 1 formed in the gate driver portion 22 have the same configuration, the TFT 1 formed in the pixel portion 21 will be described below as a representative.

  As shown in FIG. 3, the TFT substrate 20 includes a transparent insulating substrate 31, a gate electrode 32, a gate wiring 33, a gate terminal portion 34, an auxiliary capacitance electrode 35, a gate insulating film 36, an active layer 37, a source electrode 38, and a drain. The electrode 39, the source wiring 40, the source terminal portion 41, the interlayer insulating film 42, the transparent pixel electrode 43, the gate terminal pad 44 and the source terminal pad 45 are configured. The gate electrode 32, the gate insulating film 36, the active layer 37, the source electrode 38, the drain electrode 39 and the interlayer insulating film 42 constitute the TFT 1.

  The transparent insulating substrate 31 is made of a light-transmitting insulating material such as glass and plastic. At least a gate electrode 32, a gate wiring 33, a gate terminal portion 34, and an auxiliary capacitance electrode 35 are formed on the transparent insulating substrate 31, specifically, on a surface portion on one side in the thickness direction of the transparent insulating substrate 31. Yes. The gate electrode 32, the gate wiring 33, the gate terminal portion 34, and the auxiliary capacitance electrode 35 are formed of a metal film made of a metal material. The gate wiring 33 is electrically connected to the gate electrode 32. The gate terminal portion 34 is electrically connected to the gate wiring 33. An image scanning signal is input to the gate terminal unit 34 from the gate driver unit 22.

  In the vicinity of the gate electrode 32, an active layer 37 that is a component of the TFT 1 is provided via a gate insulating film 36. The active layer 37 includes a channel layer 60 and an N-type semiconductor layer 61. The N-type semiconductor layer 61 is realized by an N-type amorphous silicon film made of amorphous silicon to which an N-type impurity is added. Hereinafter, the N-type semiconductor layer 61 may be referred to as an N-type amorphous silicon film 61.

  The channel layer 60 is a non-doped semiconductor layer to which no impurity is added. The channel layer 60 is a silicon semiconductor layer, and includes a non-doped microcrystalline silicon film 62 to which no impurity is added and a non-doped amorphous silicon film to which no impurity is added (hereinafter referred to as “i-type amorphous silicon film”). 63). In the present embodiment, the channel layer 60 is a silicon semiconductor layer having a two-layer structure of a microcrystalline silicon film 62 and an i-type amorphous silicon film 63. Here, the “microcrystalline silicon film” refers to a silicon film that exhibits a mixed phase of a crystalline phase and an amorphous phase.

  The microcrystalline silicon film 62 is provided on the gate electrode 32 with the gate insulating film 36 interposed therebetween. In other words, the microcrystalline silicon film 62 is provided on a portion of the gate insulating film 36 that covers the gate electrode 32, specifically, on a surface portion on one side in the thickness direction of the gate insulating film 36 that covers the gate electrode 32. It is done. That is, the microcrystalline silicon film 62 is provided in contact with the gate insulating film 36. The i-type amorphous silicon film 63 is provided on the microcrystalline silicon film 62, specifically, on the surface portion on one side in the thickness direction of the microcrystalline silicon film 62. The N-type amorphous silicon film 61 is provided on the i-type amorphous silicon film 63, specifically, on the surface portion on one side in the thickness direction of the i-type amorphous silicon film 63.

  The gate insulating film 36 includes a first gate insulating film 50 and a second gate insulating film 53. The first gate insulating film 50 is formed on the transparent insulating substrate 31, specifically, on the surface portion on one side in the thickness direction of the transparent insulating substrate 31, the gate electrode 32, the gate wiring 33, the gate terminal portion 34 and the auxiliary capacitance electrode. 35 so as to cover 35. In the present embodiment, the first gate insulating film 50 is a silicon nitride film made of silicon nitride (SiN). The second gate insulating film 53 is provided on the first gate insulating film 50, specifically, on the surface portion on one side in the thickness direction of the first gate insulating film 50. The second gate insulating film 53 is a silicon oxide film made of silicon oxide.

  Thus, in this embodiment, the gate insulating film 36 has a two-layer structure of the silicon nitride film that is the first gate insulating film 50 and the silicon oxide film that is the second gate insulating film 53. The gate insulating film 36 is in contact with the gate electrode 32 with a silicon nitride film as the first gate insulating film 50, and is in contact with the microcrystalline silicon film 62 in the active layer 37 with a silicon oxide film as the second gate insulating film 53.

The second gate insulating film 53, the composition ratio of silicon dioxide (SiO ₂₎ film 51 made of silicon dioxide (SiO _2), and an oxygen atom of silicon oxide (O) and silicon atom (Si) (O / Si) is And a low silicon oxide film (hereinafter also referred to as “SiO _x film”) 52 made of silicon oxide having a composition formula SiO _x of less than 2 and x of less than 2. In the present embodiment, the SiO _x film 52 has a composition ratio (O / Si) between oxygen atoms (O) and silicon atoms (Si) of 1.2 or more and less than 2, that is, _{x in} the composition formula SiO x is 1. It consists of silicon oxide which is 2 or more and less than 2. The SiO _x film 52 constitutes the upper part of the second gate insulating film 53 that is in contact with the microcrystalline silicon film 62, specifically, the surface part on one side in the thickness direction of the second gate insulating film 53. Therefore, in this embodiment, the portion of the silicon oxide film that is the second gate insulating film 53 that is in contact with the microcrystalline silicon film 62 has a composition represented by the composition formula SiO _x (x is a number greater than or equal to 1.2 and less than 2). Have

  The source electrode 38 and the drain electrode 39 are directly electrically connected to the N-type amorphous silicon film 61. The source electrode 38 and the drain electrode 39 are formed of a metal film made of a metal material. The N-type amorphous silicon film 61 is partly removed from the channel layer 60 and separated into a source layer 61 a that is in contact with the source electrode 38 and a drain layer 61 b that is in contact with the drain electrode 39. Yes. As described above, the TFT 1 of this embodiment is a so-called channel-etched bottom gate thin film transistor in which the source layer 61 a and the drain layer 61 b are directly patterned on the channel layer 60. A thin film transistor having a bottom-gate structure is also referred to as an inverted staggered thin film transistor.

  A region formed by separating the source electrode 38 and the drain electrode 39 and further removing a part of the N-type amorphous silicon film 61 is referred to as a TFT channel portion 46. That is, the TFT channel portion 46 is separated between the source electrode 38 and the drain electrode 39 and between the source layer 61 a and the drain layer 61 b of the N-type amorphous silicon film 61.

The source wiring 40 is provided on the SiO _x film 52 of the second gate insulating film 53, specifically on the surface portion on one side in the thickness direction of the SiO _x film 52, and is electrically connected to the source electrode 38. The source terminal portion 41 is provided on the SiO _x film 52 of the second gate insulating film 53, specifically on the surface portion on one side in the thickness direction of the SiO _x film 52, and is electrically connected to the source wiring 40. A video signal is input to the source terminal unit 41 from the outside.

  The interlayer insulating film 42 is made of SiN, for example, and is formed so as to cover the entire substrate including the TFT channel portion 46. A pixel drain contact hole 47 that penetrates in the film thickness direction of the interlayer insulating film 42 and reaches the lower drain electrode 39 is formed in the interlayer insulating film 42. In the interlayer insulating film 42, a gate terminal contact hole 48 that penetrates in the film thickness direction of the interlayer insulating film 42 and reaches the lower gate terminal portion 34 is formed. Further, in the interlayer insulating film 42, a source terminal portion contact hole 49 that penetrates in the film thickness direction of the interlayer insulating film 42 and reaches the lower source terminal portion 41 is formed.

  The transparent pixel electrode 43 is electrically connected to the drain electrode 39 through the pixel drain contact hole 47. The gate terminal pad 44 is electrically connected to the gate terminal portion 34 through the gate terminal portion contact hole 48. The source terminal pad 45 is electrically connected to the source terminal portion 41 through the source terminal portion contact hole 49.

  The TFT substrate 20 configured as described above is used in a liquid crystal display device. In the liquid crystal display device, a TFT substrate 20 and a counter substrate (not shown) provided with a color filter for color display and a counter electrode are bonded together with a predetermined gap called a cell gap, and liquid crystal is injected into the gap. And is manufactured by sealing. The TFT substrate 20 is not limited to a liquid crystal display device, and may be used for other semiconductor devices such as an optical display device for display applications.

  Next, a manufacturing method of the TFT 1 in the first embodiment of the present invention will be described. In the present embodiment, a manufacturing method of the TFT substrate 20 using the manufacturing method of the TFT 1 will be described. 4 to 8 are views for explaining a manufacturing method of the TFT substrate 20 according to the first embodiment of the present invention. 4 to 8 show a portion that becomes the pixel portion 21 of the TFT substrate 20 as in FIG. 3. 4 to 8 correspond to cross-sectional views taken along section lines AA, BB, and CC in FIG.

FIG. 4 is a cross-sectional view showing a state where the formation of the SiO _x film 52 is completed. First, after a transparent insulating substrate 31 made of a light-transmitting insulating material such as glass and plastic is cleaned using a cleaning liquid or pure water, a metal film (hereinafter referred to as “metal film” in some cases) is formed on the transparent insulating substrate 31. A). Thereafter, the metal film is patterned by the first photolithography process to form the gate electrode 32, the gate wiring 33, the gate terminal portion 34, and the auxiliary capacitance electrode 35.

Next, a silicon nitride film is formed as the first gate insulating film 50 so as to cover the gate electrode 32, the gate wiring 33, the gate terminal portion 34, and the auxiliary capacitance electrode 35. Next, after a silicon dioxide (SiO ₂ ) film 51 is formed on the first gate insulating film 50, a low silicon oxide (SiO _x ) film 52 is formed on the SiO ₂ film 51. In this way, the second gate insulating film 53 made of the silicon oxide film is formed, and the gate insulating film 36 including the first gate insulating film 50 and the second gate insulating film 53 is formed. The film thickness of the second gate insulating film 53, that is, the total film thickness of the SiO ₂ film 51 and the SiO _x film 52 is selected to be 100 nm or less.

The SiO ₂ film 51 and the SiO _x film 52 are formed as follows. The SiO ₂ film 51 is a plasma CVD apparatus. For example, the substrate temperature is 200 to 400 ° C., the pressure is 100 to 200 Pa, the frequency is 13.56 MHz, the power density is 0.1 W / cm ² , and the SiH ₄ gas is used. It can be formed by depositing with a flow rate of 90 sccm and an N ₂ O gas flow rate of 220 sccm. Here, sccm (Standard cc per minute) is a unit representing a gas flow rate (cc / min), and the volume of the gas flowing per minute is converted into a state of 0 ° C. and 1 atm (101325 Pa). Represents the gas flow rate.

SiO _x film 52, after forming the SiO ₂ film 51, a plasma CVD apparatus used for formation of the SiO ₂ film 51, a continuous while maintaining the vacuum, for example, a substrate temperature of 200 to 400 ° C., the pressure 100 ˜200 Pa, frequency is set to 13.56 MHz, power density is set to 0.1 to 0.5 W / cm ² , SiH ₄ gas flow rate is set to 130 sccm, and N ₂ O gas flow rate is set to 220 sccm. be able to.

As described above, the SiO ₂ film 51 and the SiO _x film 52 can be separately formed by changing the flow rate ratio of the SiH ₄ gas and the N ₂ O gas. Specifically, the ratio of the flow rate of SiH ₄ gas to the flow rate of N ₂ O gas (SiH ₄ / N ₂ O) is about 90/220 = 0.40, that is, the flow rate of SiH ₄ gas is the flow rate of N ₂ O gas. The SiO ₂ film 51 can be formed by depositing at about 0.40 times the thickness. Further, the ratio of the flow rate of SiH ₄ gas to the flow rate of N ₂ O gas (SiH ₄ / N ₂ O) is about 100/220 to 160/220 = 0.45 to 0.73, that is, the flow rate of SiH ₄ gas is set to N _2. By depositing at a flow rate of about 0.45 to 0.73 times the flow rate of O gas, it is possible to form the SiO _x film 52 where _{x in} the composition formula SiO x is 1.2 or more and less than 2.

FIG. 5 is a cross-sectional view showing a state where patterning of the microcrystalline silicon film 62, the i-type amorphous silicon film 63, and the N-type amorphous silicon film 61 is completed. After formation of the SiO _x film 52, on the SiO _x film 52, a microcrystalline silicon film 62 serving as a semiconductor active film, the i-type amorphous silicon film 63 is an amorphous silicon film of non-doped, N-type impurity N-type amorphous silicon film 61, which is an amorphous silicon film to which is added, is sequentially formed in this order. The microcrystalline silicon film 62 is formed in contact with the SiO _x film 52.

The microcrystalline silicon film 62 is formed by a mixed gas of silane (SiH ₄ ) gas and hydrogen (H ₂ ) gas. Specifically, the microcrystalline silicon film 62 is a plasma CVD apparatus, for example, a substrate temperature of 200 to 400 ° C., a pressure of 100 to 150 Pa, a frequency of 13.56 MHz, and a power density of 0.1 W / cm ^2, and a flow rate ratio of SiH ₄ gas and H ₂ gas, 200 to 300 in the ratio of the flow rate of SiH ₄ gas to the flow rate of H ₂ gas (SiH ₄ / H _2), i.e., the flow rate of H ₂ gas 1 In this case, it can be formed by depositing the SiH ₄ gas at a flow rate of 200 to 300.

  After the formation of the N-type amorphous silicon film 61, the microcrystalline silicon film 62, the i-type amorphous silicon film 63, and the N-type amorphous silicon film 61 are formed by the second photolithography process. Patterning is formed into a shape to be an element. In this manner, an active layer 37A including the channel layer 60 including the microcrystalline silicon film 62 and the i-type amorphous silicon film 63 and the N-type amorphous silicon film 61 is formed on the gate insulating film 36. In the active layer 37A formed here, the N-type amorphous silicon film 61 is separated into the source layer 61a and the drain layer 61b in the step shown in FIG. 6 to be described later, and the active layer 37 shown in FIG. It becomes.

  FIG. 6 is a cross-sectional view showing a state at a stage where the formation of the TFT channel portion 46 is completed. After the active layer 37A is formed as described above, a metal film, for example, an aluminum (Al) alloy film, which becomes the source electrode 38 and the drain electrode 39 is covered so as to cover the entire one side in the thickness direction of the substrate including the active layer 37A. Form a film. Thereafter, the metal film and the underlying N-type amorphous silicon film 61 are patterned by a third photolithography process to form the source electrode 38, the drain electrode 39, the source wiring 40, and the source terminal portion 41, The N-type amorphous silicon film 61 is separated into a source layer 61a and a drain layer 61b. Thus, the TFT channel portion 46 is formed and the active layer 37 shown in FIG. 3 is formed. In this manner, the source electrode 38 and the drain electrode 39 are formed on the active layer 37.

  FIG. 7 is a cross-sectional view showing a state where the formation of the pixel drain contact hole 47, the gate terminal portion contact hole 48, and the source terminal portion contact hole 49 has been completed. After the TFT channel portion 46 is formed as described above, the interlayer insulating film 42 is formed as a passivation film so as to cover the entire one side in the thickness direction of the substrate including the TFT channel portion 46. For example, a SiN film is formed as the interlayer insulating film 42.

  Thereafter, the interlayer insulating film 42 is patterned by a fourth photolithography process. Thus, the pixel drain contact hole 47 that reaches the surface of the drain electrode 39 through the interlayer insulating film 42, the gate terminal contact hole 48 that reaches the surface of the gate terminal portion 34 through the interlayer insulating film 42, and the interlayer At least a source terminal contact hole 49 that penetrates the insulating film 42 and reaches the surface of the source terminal 41 is formed. The pixel drain contact hole 47, the gate terminal portion contact hole 48, and the source terminal portion contact hole 49 can be simultaneously formed by one photolithography process.

  FIG. 8 is a cross-sectional view showing a state where the pattern formation of the transparent pixel electrode 43, the gate terminal pad 44, and the source terminal pad 45 is completed. The transparent pixel electrode 43, the gate and the gate are formed so as to cover the entire one side in the thickness direction of the substrate including the inner surfaces of the pixel drain contact hole 47, gate terminal contact hole 48 and source terminal contact hole 49 formed as described above. A transparent conductive film to be the terminal pad 44 and the source terminal pad 45 is formed. As the transparent conductive film, for example, an indium oxide (Indium Tin Oxide; abbreviation: ITO) film to which tin is added is formed.

  Next, the transparent conductive film is patterned by a fifth photolithography process. Thus, the transparent pixel electrode 43 is formed so as to be electrically connected to the lower drain electrode 39 via the pixel drain contact hole 47. Further, a pattern of the gate terminal pad 44 that is electrically connected to the lower gate terminal portion 34 through the gate terminal portion contact hole 48 is formed. Further, a pattern of source terminal pads 45 that are electrically connected to the source terminal portion 41 in the lower layer through the source terminal portion contact hole 49 is formed. The above-described procedure completes the TFT substrate 20 shown in FIG. 3 that is preferably used as a liquid crystal display device.

  The completed TFT substrate 20 may be heat-treated at a temperature of about 200 to 350 ° C. As a result, electrostatic charges and stress accumulated in the entire TFT substrate 20 can be removed or alleviated. Further, the electrical specific resistance of the metal film constituting the gate electrode 32, the source electrode 38, the drain electrode 39, etc. can be lowered. Therefore, the TFT characteristics can be improved and stabilized. Although the manufacturing method of the TFT 1 in the pixel portion 21 has been described in the present embodiment, the TFT is formed in the gate driver portion 22 simultaneously with the formation of the TFT 1 in the pixel portion 21.

As described above, according to the present embodiment, the portion of the silicon oxide film that is the second gate insulating film 53 (hereinafter sometimes referred to as the silicon oxide film 53) in contact with the microcrystalline silicon film 62 is the composition formula SiO _x. The low silicon oxide (SiO _x ) film 52 has a composition represented by (x is a number from 1.2 to less than 2). That is, the silicon oxide film 53 is formed so that a portion in contact with the microcrystalline silicon film 62 has a composition represented by a composition formula SiO _x (x is a number of 1.2 or more and less than 2). As a result, the surface of the SiO _x film 52, which is the surface on which the microcrystalline silicon film 62 of the silicon oxide film 53 is to be formed, can be brought into a state where oxygen vacancies serving as crystal growth nuclei exist.

Since the microcrystalline silicon film 62 is formed in contact with the SiO _x film 52, the microcrystalline silicon film 62 can be grown at a high density on the silicon oxide film 53, and the microcrystalline silicon film 62 having excellent crystallinity can be obtained. Can be formed. As a result, it is possible to provide the gate insulating film 36 including the silicon oxide film 53 and the active layer 37 including the microcrystalline silicon film 62 while suppressing a decrease in the on-characteristic due to the void. By configuring the gate insulating film 36 so as to include the silicon oxide film 53, hot carrier injection into the gate insulating film 36 can be prevented, so that hot carrier deterioration can be suppressed. In addition, by configuring the active layer 37 so as to include the microcrystalline silicon film 62, it is possible to suppress a change in the threshold voltage with time compared to the case where the microcrystalline silicon film 62 is not included. Accordingly, it is possible to realize a TFT 1 in which the change in threshold voltage with time and hot carrier deterioration are as small as possible and the on-characteristic deterioration is as small as possible.

  As described above, the microcrystalline silicon TFT which is the TFT 1 of the present embodiment has little deterioration with respect to a large driving voltage while ensuring sufficient on-characteristics. Therefore, by using the TFT 1 of this embodiment, a long-life liquid crystal display device can be realized without causing display failure and circuit operation failure due to insufficient writing of the TFT.

Table 2 shows the film formation conditions of the silicon oxide film, the composition and refractive index of the silicon oxide film deposited under the film formation conditions, and the crystallization rate of the microcrystalline silicon film deposited on the silicon oxide film. Show the relationship. In Table 2, in the case where a silicon oxide film is deposited by changing the flow rate (sccm) of SiH ₄ gas and the flow rate (sccm) of N ₂ O gas in a plasma CVD apparatus, oxygen atoms (O) in the silicon oxide film are deposited. The composition ratio x, that is, the value of x in the composition formula SiO _x , the refractive index n of the silicon oxide film, and the crystallization rate (%) of the microcrystalline silicon film deposited on the silicon oxide film are shown together. Table 2 also shows the crystallization rate of the microcrystalline silicon film to which argon (Ar) is added in the second embodiment of the present invention, which will be described later, as an Ar addition crystallization rate (%).

As shown in Table 2, when the flow rate of the SiH ₄ gas increases, the refractive index n of the silicon oxide film increases and the composition ratio x of oxygen atoms (O) decreases. This is because when the flow rate of SiH ₄ gas increases, the ratio of silicon atoms (Si) in the silicon oxide film increases and the refractive index increases. Therefore, in the manufacturing process of the silicon oxide film according to the present embodiment and the second embodiment of the present invention described later, a silicon oxide film is used instead of the value of the composition ratio x of oxygen atoms (O) in the silicon oxide film. The silicon oxide film may be controlled using the value of the refractive index n. It is not important whether the silicon oxide film is controlled by the composition ratio x of oxygen atoms (O) or the refractive index n, and it is important to improve the crystallization rate of the microcrystalline silicon film.

  As shown in Table 2, the crystallinity of the microcrystalline silicon film is such that the composition ratio x of oxygen atoms (O) in the silicon oxide film is smaller than 2.0, in other words, the refractive index n of the silicon oxide film. Increases slightly even if it is a little larger than 1.46. The reason for this will be described.

It is known that the α-quartz crystal lattice which is stable at 573 ° C. or less is a regular hexagon having a side of 4.9 mm. That is, when viewed α quartz from the plane, an area of one unit cell of the crystal lattice, the 62.38Å ^2. The silicon oxide film formed in this embodiment is also considered on the assumption that it forms such an α-quartz crystal. When the composition ratio x of oxygen atoms (O) is 1.99, there are 99 SiO _{2 and} 1 SiO, that is, one oxygen vacancy exists in 100 silicon oxide molecules. This is equal to that there is one oxygen vacancy 100 per unit lattice, in terms of area, that there is one oxygen vacancy on 6238Å ² = 62.38nm every ^two is 100 times the area of the unit cell be equivalent to. This oxygen deficiency functions as a crystal growth nucleus.

On the other hand, in the microcrystalline silicon film, the size of the obtained microcrystal is about 10 to 50 nm in diameter. The area when the crystallite having a diameter of 30 nm is viewed in plan is 706.9 nm ² , and the area when the crystallite having a diameter of 10 nm is viewed in plan is 78.5 nm ² . Comparing these values with the above-described formation area of oxygen vacancies as crystal growth nuclei in the silicon oxide film, even when the composition ratio x of oxygen atoms (O) in the silicon oxide film is 1.99, the density is sufficient. It can be seen that crystal growth nuclei are formed. When the composition ratio x of oxygen atoms (O) is 1.99, the refractive index n of the silicon oxide film is 1.462.

  Accordingly, when the composition ratio x of oxygen atoms (O) in the silicon oxide film is smaller than 2.0 or the refractive index n of the silicon oxide film is larger than 1.46, as described above, microcrystalline silicon. The crystallization rate of the film is greatly improved.

From the above, in this embodiment, the composition ratio x of oxygen atoms (O) in the low silicon oxide (SiO _x ) film 52 is less than 2. In terms of the refractive index n, in this embodiment, the refractive index n of the low silicon oxide (SiO _x ) film 52 is set to a value exceeding 1.46. Actually, considering the conditions under which practically sufficient reproducibility and uniformity can be obtained from the accuracy of gas flow rate control of SiH ₄ and N ₂ O, the composition ratio x of oxygen atoms (O) in the SiO _x film 52 Is preferably 1.9 or less, more specifically 1.89 or less, and the refractive index n of the SiO _x film 52 is preferably 1.48 or more.

When the composition ratio x of oxygen atoms (O) in the low silicon oxide (SiO _x ) film 52 becomes less than 1.2, or when the refractive index n of the SiO _x film 52 exceeds 1.7, the microcrystalline silicon film 62 However, since the defect level density in the SiO _x film 52 is increased and hot carrier deterioration is increased, a long-life liquid crystal display device cannot be obtained. Therefore, the composition ratio x of the oxygen atoms (O) in the SiO _x film 52 is preferably 1.2 or more, the refractive index n of SiO _x film 52 is preferably 1.7 or less.

From the above, in the present embodiment, the SiO _x film 52 is configured to have a composition represented by the composition formula SiO _x (x is a number of 1.2 or more and less than 2). Expressed by the refractive index n, the SiO _x film 52 may be configured such that the refractive index n exceeds 1.46 and is 1.7 or less.

Expressed by the refractive index n, the portion of the silicon oxide film that is the second gate insulating film 53 that is in contact with the microcrystalline silicon film 62 has a refractive index n exceeding 1.46 and not more than 1.7 (1.46 <n ≦ 1.7) Even in the case of the low silicon oxide (SiO _x ) film 52, SiO having a composition represented by the composition formula SiO x (where x is a number of 1.2 or more and less than 2) The same effect as that of the _x film 52 can be achieved.

In this embodiment, the value of the refractive index n with respect to the composition ratio x of oxygen atoms (O) in the silicon oxide film is slightly larger than the values in the literature and the like. This is because in the present embodiment, nitrogen atoms (N) from N ₂ O gas are mixed in the silicon oxide film. It is necessary to always calibrate the value of the refractive index n using a quartz substrate made of perfect SiO _{2 or the} like. In the present embodiment, the quartz substrate, which is perfect SiO ₂ , was calibrated with a composition x of 2.0 and a refractive index n of 1.46.

As an example, a silicon dioxide (SiO ₂ ) film 51 and a low silicon oxide (SiO _x ) film 52 constituting a silicon oxide film as the second gate insulating film 53 were formed using a plasma CVD apparatus. The SiO ₂ film 51 was formed with a SiH ₄ gas flow rate of 90 sccm and an N ₂ O gas flow rate of 220 sccm. The SiO _x film 52 was formed with a SiH ₄ gas flow rate of 130 sccm and an N ₂ O gas flow rate of 220 sccm. Both the SiO ₂ film 51 and the SiO _x film 52 were formed at a substrate temperature of 300 ° C., a pressure of 150 Pa, and a power density of 0.2 W / cm ² .

With respect to the formed SiO ₂ film 51 and SiO _x film 52, the value of x in the composition formula SiO _x , that is, the composition ratio x of oxygen atoms (O) was measured by X-ray photoelectron spectroscopy (abbreviation: XPS). And measured. The refractive index n was measured using spectro-elipsometory using a helium-neon (He—Ne) laser having an oscillation wavelength of 633 nm as a light source. The composition ratio x of oxygen atoms (O) in the SiO ₂ film 51 was 2.0, and the refractive index n was 1.46. The composition ratio x of oxygen atoms (O) in the SiO _x film 52 was 1.54, and the refractive index n was 1.55.

FIG. 9 is a cross-sectional view showing a state in which a disconnection failure has occurred in the gate terminal pad 44. In the present embodiment, as described above, the film thickness of the silicon oxide film as the second gate insulating film 53, that is, the total film thickness of the SiO ₂ film 51 and the SiO _x film 52 is 100 nm or less is selected. When the thickness of the silicon oxide film 53 is large, the silicon oxide film 53 protrudes at the gate terminal portion 34 as shown in FIG. 9 due to the difference in etching rate. As a result, a disconnection failure is likely to occur in the gate terminal pad 44.

Thickness of the silicon oxide film 53, i.e., where the formation of the SiO ₂ film 51 and the SiO _x film 52 the total thickness of the SiO ₂ film 51 and the SiO _x film 52 as 100nm or less, disconnection was not confirmed. At this time, the thickness of the SiO ₂ film 51 was 80 nm, and the thickness of the SiO _x film 52 was 20 nm. From the above results, in the present embodiment, as described above, the total thickness of the silicon oxide film as the second gate insulating film 53, that is, the thickness of the SiO ₂ film 51 and the SiO _x film 52 is calculated. The film thickness is 100 nm or less. Thereby, disconnection failure of the gate terminal pad 44 can be prevented.

Hereinafter, the effect of the low silicon oxide (SiO _x ) film 52 was verified. Immediately after the microcrystalline silicon film 62 is formed, the case where the SiO _x film 52 is formed after the silicon dioxide (SiO ₂ ) film 51 is formed and the case where the SiO _x film 52 is not formed. The surface photograph was observed using a scanning electron microscope (abbreviation: SEM, manufactured by Hitachi, Ltd., S-806).

The SiO ₂ film 51 is a plasma CVD apparatus, the substrate temperature is set to 300 ° C., the pressure is set to 150 Pa, the power density is set to 0.2 W / cm ² , the flow rate of SiH ₄ gas is set to 90 sccm, and the flow rate of N ₂ O gas is set. It was formed as 220 sccm. The SiO _x film 52 is a plasma CVD apparatus, the substrate temperature is set to 300 ° C., the pressure is set to 150 Pa, the power density is set to 0.2 W / cm ² , the flow rate of SiH ₄ gas is set to 130 sccm, and the flow rate of N ₂ O gas is set. It was formed as 220 sccm. The microcrystalline silicon film 62 was deposited by a plasma CVD apparatus at a substrate temperature of 250 ° C., a pressure of 150 Pa, and a flow rate ratio (SiH ₄ / H ₂ ) of SiH ₄ gas to H ₂ gas of 300.

The sample microcrystalline silicon in which the SiO _x film 52 was not formed grew in an island shape, and many voids were observed. On the other hand, the microcrystalline silicon of the sample on which the SiO _x film 52 was formed grew at a high density and uniformly, and almost no voids were observed.

Further, with respect to these samples, the crystallization rate of the microcrystalline silicon film 62 was measured using a Raman spectrometer (manufactured by JASCO, MRS-3100). The crystallization rate of the sample in which the SiO _x film 52 was not formed was 40%. On the other hand, in the sample in which the SiO _x film 52 was formed, a crystallization rate of 60% was obtained.

Further, after forming the SiO ₂ film 51, and the case of forming the SiO _x film 52, for the case of not forming the SiO _x film 52, to prepare a microcrystalline silicon TFT respectively, the gate voltage - drain Current characteristics were measured. The measured TFT channel width is 25 μm and the channel length is 4 μm. From the measurement results, when the SiO _x film 52 is formed, the drain current is about 3.5 times larger when the drain voltage is applied 10 V than when the SiO _x film 52 is not formed. It was confirmed that it was obtained. From this, it was found that when the SiO _x film 52 was formed, good on characteristics were obtained.

Further, microcrystalline silicon TFTs were produced by changing the composition of the SiO _x film 52, and the gate voltage-drain current characteristics were measured. From the measurement results, the dependence of the on-current, which is the drain current when a drain voltage of 10 V is applied and a gate voltage of 20 V, on the composition of the SiO _x film 52 (hereinafter sometimes referred to as “SiO _x composition dependence”). Evaluated. FIG. 10 is a graph showing the SiO _x composition dependence of the on-current of the microcrystalline silicon TFT in the first embodiment of the present invention. In FIG. 10, the vertical axis represents the on-current (Ion (x = 2.0) of a microcrystalline silicon TFT manufactured using a silicon oxide film having x of 2.0 in the composition formula SiO _x instead of the SiO _x film 52. )), The on-current value Ion / Ion (x = 2.0) normalized, and the horizontal axis represents the composition of the SiO _x film 52. In FIG. 10, the composition of the SiO _x film 52 is represented by the value of x in the composition formula SiO _x , that is, the composition ratio (O / Si) of oxygen atoms (O) to silicon atoms (Si).

From FIG. 10, it can be seen that the on-current increases when the composition ratio x of oxygen atoms (O) in the SiO _x film 52 is smaller than 2.0, and increases as the composition ratio x of oxygen atoms decreases. This, as the composition ratio x of the oxygen atoms in the SiO _x film 52 is reduced, increasing the crystal growth nuclei in which oxygen defects in SiO _x film 52, whereby, in order to microcrystalline silicon film 62 is grown at a high density is there.

In addition, microcrystalline silicon TFTs in which the thickness of the microcrystalline silicon film 62 was changed by 10 nm from 10 nm to 70 nm were manufactured, and gate voltage-drain current characteristics were measured. The composition ratio x of oxygen atoms in the SiO _x film 52 was 1.54. From the measurement results, the off-current (Imin), which is the minimum value of the drain current when a drain voltage of 10 V is applied, depends on the thickness of the microcrystalline silicon film 62 (hereinafter referred to as “microcrystalline silicon thickness dependence”). Evaluated). The gate voltage at which the drain current is minimized differs depending on the TFT.

  FIG. 11 is a graph showing the microcrystalline silicon film thickness dependence of the off-state current of the microcrystalline silicon TFT according to the first embodiment of the present invention. In FIG. 11, the vertical axis represents the off-current value Imin / Imin (50 nm) normalized by the TFT off-current (Imin (50 nm)) with a microcrystalline silicon film thickness of 50 nm, and the horizontal axis represents the microscopic silicon. The film thickness (nm) of the crystalline silicon film 62 is shown.

  Even when the thickness of the microcrystalline silicon film 62 is reduced, the on-current is constant, but the off-current varies depending on the thickness of the microcrystalline silicon film 62 as shown in FIG. When the film thickness of the microcrystalline silicon film 62 was between 70 nm and 30 nm, the minimum value of the off current tended to decrease as the film thickness was reduced. However, even when the thickness of the microcrystalline silicon film 62 was reduced to 30 nm or less, the minimum value of the off current was not so small and showed a saturation tendency. From this, it can be seen that by setting the thickness of the microcrystalline silicon film 62 to 30 nm or less, the leakage current can be reduced without reducing the on-characteristics.

  Therefore, the film thickness of the microcrystalline silicon film 62 is preferably 30 nm or less. Since the microcrystalline silicon film 62 has high hole mobility, the off-resistance in the channel direction is low, which causes an increase in leakage current. By making the thickness of the microcrystalline silicon film 62 relatively small, specifically, 30 nm or less, the resistance in the channel direction can be increased, so that leakage current can be reduced.

  In the present embodiment, the gate insulating film 36 is a silicon nitride film (hereinafter referred to as nitridation) that is a first gate insulating film 50 interposed between the gate electrode 32 and a silicon oxide film that is the second gate insulating film 53. A silicon film 50 in some cases), and has a stacked structure of the silicon nitride film 50 and the silicon oxide film 53. Since the relative dielectric constant of the silicon oxide film is 1.46, whereas the relative dielectric constant of the silicon nitride film is 2.0, the gate insulating film 36 is replaced with the silicon nitride film 50 and the silicon oxide film 53 as described above. As a result, the dielectric constant of the gate insulating film 36 is increased as compared with the case where the gate insulating film is formed only by the silicon oxide film. For this reason, when compared with the same film thickness, the on-state current can be increased in the stacked structure as compared with the case where the gate insulating film is formed of only the silicon oxide film. Therefore, the performance of the TFT 1 can be improved without increasing the thickness of the gate insulating film 36.

  In the present embodiment, the active layer 37 includes an i-type amorphous silicon film 63 provided over the microcrystalline silicon film 62, and the channel layer 60 includes the microcrystalline silicon film 62 and the i-type amorphous silicon film. A laminated structure with the silicon film 63 is provided. Thus, the N-type amorphous silicon film 61 can be formed on the channel layer 60 while suppressing the band gap mismatch. Therefore, when a reverse bias voltage is applied to the gate electrode 32, hole injection due to interband tunneling can be prevented between the microcrystalline silicon film 62 and the N-type amorphous silicon film 61. Leakage current can be suppressed.

<Second Embodiment>
FIG. 12 is a plan view showing the configuration of the pixel portion 21A of the TFT substrate 20A according to the second embodiment of the present invention. 13 is a cross-sectional view taken along section lines AA, BB, and CC in FIG. In the TFT substrate 20A of the present embodiment, the configuration other than the microcrystalline silicon film 62 of the TFT substrate 20 in the first embodiment is the same as that of the TFT substrate 20 in the first embodiment. Only different parts will be described, the same reference numerals are given to the same components, and the common description will be omitted.

The TFT substrate 20A of the present embodiment includes a TFT 2 having the same configuration as the TFT 1 included in the TFT substrate 20 of the first embodiment. The TFT 2 of this embodiment includes a microcrystalline silicon film 70 containing argon (Ar) as a microcrystalline silicon film constituting the channel layer 71 of the active layer 72. The TFT 2 in this embodiment includes a microcrystalline silicon film 70 containing Ar instead of the microcrystalline silicon film 62 provided in the TFT 1 in the first embodiment described above. The microcrystalline silicon film 70 contains argon in a portion in contact with the low silicon oxide (SiO _x ) film 52 constituting the second gate insulating film 53, more specifically in the entire microcrystalline silicon film 70.

  Next, the manufacturing method of TFT2 in the 2nd Embodiment of this invention is demonstrated. Since the manufacturing method of TFT2 in this Embodiment is similar to the manufacturing method of TFT2 in 1st Embodiment, description is abbreviate | omitted about the same process. In the present embodiment, a manufacturing method of the TFT substrate 20A using the manufacturing method of the TFT 2 will be described. 14 and 15 are diagrams for explaining a manufacturing method of the TFT substrate 20A in the second embodiment of the present invention. 14 and 15 show a portion to be the pixel portion 21A of the TFT substrate 20A, as in FIG. 14 and 15 correspond to cross-sectional views taken along section lines AA, BB, and CC in FIG.

FIG. 14 is a cross-sectional view showing a state where the formation of the low silicon oxide (SiO _x ) film 52 is completed. As in the first embodiment, the transparent insulating substrate 31 such as a glass substrate is first cleaned using a cleaning liquid or pure water, and then a metal film is formed on the transparent insulating substrate 31. Thereafter, the metal film is patterned by a first photolithography process to form the gate electrode 32, the gate wiring 33, the gate terminal portion 34, and the auxiliary capacitance electrode 35. Next, after forming the first gate insulating film 50 so as to cover the gate electrode 32, the gate wiring 33, the gate terminal portion 34, and the auxiliary capacitance electrode 35, the second gate insulating film is formed on the first gate insulating film 50. A silicon dioxide (SiO ₂ ) film 51 and a low silicon oxide (SiO _x ) film 52 to be 53 are formed. The composition ratio x of oxygen atoms (O) in the SiO _x film 52 is, for example, 1.54. The total film thickness of the SiO ₂ film 51 and the SiO _x film 52 is selected to be 100 nm or less.

FIG. 15 is a cross-sectional view showing a state where patterning of the microcrystalline silicon film 70, the i-type amorphous silicon film 63, and the N-type amorphous silicon film 61 is completed. Next, on the SiO _x film 52, there are a microcrystalline silicon film containing Ar (hereinafter sometimes referred to as “Ar-containing microcrystalline silicon film”) 70 and a non-doped amorphous silicon film to be a semiconductor active film. An i-type amorphous silicon film 63 and an N-type amorphous silicon film 61 which is an amorphous silicon film to which an N-type impurity is added are sequentially formed in this order.

The microcrystalline silicon film 70 is formed by a plasma CVD method using a mixed gas containing SiH ₄ gas, H ₂ gas, and Ar gas, in this embodiment, a mixed gas of SiH ₄ gas, H ₂ gas, and Ar gas. Form a film. The microcrystalline silicon film 70 is formed by a plasma CVD method at a flow rate ratio (SiH ₄ / H ₂ / Ar) of SiH ₄ gas, H ₂ gas, and Ar gas of 1: 150: 150 to 300, that is, SiH ₄ gas. When the flow rate is 1, the flow rate of H ₂ gas is 150, the flow rate of Ar gas is 200 to 300, the pressure is 100 to 150 Pa, the power density is 0.05 to 0.2 W / cm ² , and the film is formed. It can be formed by depositing at a temperature of 200 to 300 ° C.

  Thereafter, similarly to the first embodiment, an Ar-containing microcrystalline silicon film 70, an i-type amorphous silicon film 63, and an N-type amorphous silicon film 61 are formed by a second photolithography process. The active layer 72A is formed by patterning into a shape that is a constituent element of the TFT2. In the active layer 72A formed here, the N-type amorphous silicon film 61 is separated into the source layer 61a and the drain layer 61b in a later step, thereby forming the active layer 72 shown in FIG. Since the subsequent manufacturing steps are the same as those in the first embodiment described above, description thereof will be omitted. As described above, the TFT substrate 20A including the TFT 2 shown in FIG. 13 is manufactured.

As described above, according to the present embodiment, the microcrystalline silicon film 70 is formed by a mixed gas containing SiH ₄ gas, N ₂ O gas, and Ar gas. Accordingly, the crystallinity of the microcrystalline silicon film 70 can be increased and the crystallization rate can be improved, so that the on-characteristics of the TFT 2 can be improved.

In this embodiment, the thickness of the silicon oxide film as the second gate insulating film 53, that is, the total thickness of the SiO ₂ film 51 and the SiO _x film 52 is selected to be 100 nm or less. When the thickness of the silicon oxide film 53 is large, the silicon oxide film 53 protrudes from the gate terminal portion 34 due to the difference in etching rate as shown in FIG. As a result, a disconnection failure is likely to occur in the gate terminal pad 44.

Thickness of the silicon oxide film 53, i.e., where the formation of the SiO ₂ film 51 and the SiO _x film 52 the total thickness of the SiO ₂ film 51 and the SiO _x film 52 as 100nm or less, disconnection was not confirmed. At this time, the thickness of the SiO ₂ film 51 was 80 nm, and the thickness of the SiO _x film 52 was 20 nm. From the above results, in this embodiment, as described above, the film thickness of the silicon oxide film as the second gate insulating film 53, that is, the total film thickness of the SiO ₂ film 51 and the SiO _x film 52 is determined. 100 nm or less. Thereby, disconnection failure of the gate terminal pad 44 can be prevented.

Hereinafter, the effect of the microcrystalline silicon film 70 containing Ar was verified. Microcrystalline silicon film 70 containing Ar, using a mixed gas of Ar gas to SiH ₄ gas and H ₂ gas as a source gas, by a plasma CVD method, SiH ₄ gas, H ₂ gas, Ar gas The flow rate ratio (SiH ₄ / H ₂ / Ar) was 1: 150: 150, the pressure was 150 Pa, the power density was 0.06 W / cm ² , and the film formation temperature was 300 ° C. At this time, when the element distribution in the depth direction of the formed TFT channel portion 46 was examined using a secondary ion mass spectrometer (abbreviation: SIMS, manufactured by CAMECA, IMS-6F), Ar was detected in the microcrystalline silicon film 70.

  Moreover, about the case where Ar is contained in mixed gas, and the case where it is not contained, immediately after forming a microcrystalline silicon film, a surface photograph is used using SEM (made by Hitachi, Ltd., S-806). Observed. In both the sample not containing Ar and the sample containing Ar, microcrystalline silicon grew at a high density and uniformly, and almost no voids were observed.

  Furthermore, the crystallization rate of these samples was measured using a Raman spectroscopic device (manufactured by JASCO, MRS-3100). The crystallization rate of the sample not containing Ar was 60%. On the other hand, a crystallization rate of 67% was obtained in the sample containing Ar.

The reason why the crystallization rate is improved by containing Ar in the mixed gas can be explained as follows. In a crystal growth process in which a silicon film is formed with a mixed gas of SiH ₄ gas and H ₂ gas, an amorphous silicon film (a-Si film) and a microcrystalline silicon film are deposited simultaneously. If the mixed gas contains a large amount of H ₂ gas, a large amount of hydrogen atoms (H) decomposed in the plasma cut weak silicon bonds (Si—Si bonds) in the amorphous silicon film, and Si and Combined, SiH ₄ (gas) is removed from the film. That is, when a large amount of H ₂ gas is present in the mixed gas, more microcrystalline silicon films grow than amorphous silicon films. The effect of hydrogen atoms breaking weak silicon bonds in the amorphous silicon film becomes more prominent as the film forming temperature is lower. When Ar gas is further mixed with this mixed gas, since Ar has a mass larger than that of H, the action of breaking weak silicon bonds in the amorphous silicon film becomes larger than that of H, so that the crystallinity is better. A microcrystalline silicon film with a high conversion rate can be formed.

  Furthermore, when Ar gas is mixed, the action of breaking weak silicon bonds occurs even at higher temperatures. That is, the microcrystalline silicon film 70 can be deposited at a higher temperature. In the example of the first embodiment described above, when forming the microcrystalline silicon film 62, the film forming temperature is 250 ° C., but in the example of the present embodiment, the film forming temperature is 300 ° C. When Ar gas was mixed, the growth rate of the microcrystalline silicon film was improved 1.5 times as compared with the case where Ar gas was not mixed. Therefore, when Ar gas is mixed, not only the crystallization rate is improved but also the throughput is improved.

Further, microcrystalline silicon TFTs in which Ar was contained in the microcrystalline silicon film 70 were manufactured by changing the composition of the SiO _x film 52, and the gate voltage-drain current characteristics were measured. From the measurement results, the dependence on the composition of the SiO _x film 52, that is, the dependence on the SiO _x composition, was evaluated with respect to the on-current that is the drain current when the drain voltage was applied at 10 V and the gate voltage was applied at 20 V.

FIG. 16 is a graph showing the SiO _x composition dependency of the on-current of the microcrystalline silicon TFT according to the second embodiment of the present invention. In FIG. 16, the vertical axis represents the on-current (Ion (x = 2.0) of the microcrystalline silicon TFT manufactured using a silicon oxide film having x of 2.0 in the composition formula SiO _x instead of the SiO _x film 52. )), The on-current value Ion / Ion (x = 2.0) normalized, and the horizontal axis represents the composition of the SiO _x film 52. In FIG. 16, the composition of the SiO _x film 52 is represented by the value of x in the composition formula SiO _x , that is, the composition ratio (O / Si) of oxygen atoms (O) to silicon atoms (Si).

FIG. 16 shows that the on-current increases when the composition ratio x of oxygen atoms (O) in the SiO _x film 52 becomes smaller than 2.0, and increases as the composition ratio x of oxygen atoms becomes smaller.

Further, the result shown in FIG. 16 was compared with the result in the case where Ar was not contained in the microcrystalline silicon film 62 shown in FIG. As a result, when Ar is contained in the microcrystalline silicon film 70, 1.05 times when the composition ratio x of oxygen atoms (O) in the SiO _x film 52 is 1.98, compared with the case where Ar is not contained. When the composition ratio x is 1.54, the value is 1.51 times, and when the composition ratio x is 1.20, the value is 1.65 times, confirming that the on-current is improved from 1.05 times to 1.65 times. It was done.

Further, microcrystalline silicon TFTs in which the thickness of the microcrystalline silicon film 70 containing Ar was changed by 10 nm from 10 nm to 70 nm were manufactured, and the gate voltage-drain current characteristics were measured. The composition ratio x of oxygen atoms in the SiO _x film 52 was 1.54. From the measurement results, the dependency on the film thickness of the microcrystalline silicon film 70, that is, the dependency on the microcrystalline silicon film thickness, was evaluated for the off-state current (Imin) that is the minimum value of the drain current when a drain voltage of 10 V was applied. The gate voltage at which the drain current is minimized differs depending on the TFT.

  FIG. 17 is a graph showing the microcrystalline silicon film thickness dependence of the off-state current of the microcrystalline silicon TFT according to the second embodiment of the present invention. In FIG. 17, the vertical axis represents a value Imin / Imin (50 nm) normalized by the off-current (Imin (50 nm)) of the TFT in which the thickness of the microcrystalline silicon film 70 is 50 nm, and the horizontal axis represents the microcrystal. The film thickness (nm) of the silicon film 70 is shown.

  As in the first embodiment, the on-state current is constant even when the thickness of the microcrystalline silicon film 70 containing Ar is reduced, but the off-state current is small as shown in FIG. It varies depending on the film thickness of the crystalline silicon film 70. When the film thickness of the microcrystalline silicon film 70 was between 70 nm and 30 nm, the minimum value of the off current tended to decrease as the film thickness was reduced. However, even when the thickness of the microcrystalline silicon film 70 was reduced to 30 nm or less, the minimum value of the off current was not so small and showed a saturation tendency. From this, it can be seen that by setting the thickness of the microcrystalline silicon film 70 to 30 nm or less, the leakage current can be reduced without reducing the on-characteristics.

  Therefore, the thickness of the microcrystalline silicon film 70 is preferably 30 nm or less. Since the microcrystalline silicon film 70 has high hole mobility, the off-resistance in the channel direction is small, which causes an increase in leakage current. By making the thickness of the microcrystalline silicon film 70 relatively small, specifically, 30 nm or less, the resistance in the channel direction can be increased, so that leakage current can be reduced.

  Further, the result shown in FIG. 17 was compared with the result in the case where Ar was not contained in the microcrystalline silicon film 62 shown in FIG. As a result, it was found that when Ar was contained in the microcrystalline silicon film 70, the off-state current was slightly increased as compared with the case where Ar was not contained. More specifically, the off-current increases by 0.9% when the thickness of the microcrystalline silicon film 70 is 50 nm, increases by 6.3% when the thickness is 30 nm, and increases when the thickness is 10 nm. It was found to increase by 10.0%. This is considered to be because Ar makes a defect in the microcrystalline silicon film 70, but there is no problem because the increase rate is 10% at the maximum.

  As described above, the microcrystalline silicon TFT, which is the TFT 2 of the present embodiment, is deteriorated with respect to a large driving voltage while ensuring a larger ON characteristic as compared with the TFT 1 of the first embodiment described above. Few. Therefore, by using the TFT 2 of this embodiment, a long-life liquid crystal display device can be realized without causing display failure and circuit operation failure due to insufficient writing of the TFT.

  Further, in this embodiment, since the microcrystalline silicon film 70 can be formed at a higher speed than in the first embodiment, throughput can be improved and manufacturing cost can be reduced.

Further, in the present embodiment, when the composition ratio x of oxygen atoms (O) in the low silicon oxide (SiO _x ) film 52 becomes less than 1.2 or when the refractive index n exceeds 1.7, the above-mentioned first Compared with the first embodiment, the crystallization rate of the microcrystalline silicon film 70 is further improved. Specifically, as shown in Table 2 above, when Ar is not added, the crystallization rate is 66% or more, whereas when Ar is added, the crystallization rate is 74% or more. It becomes. However, since the defect level density in the SiO _x film 52 increases and hot carrier deterioration increases, a long-life liquid crystal display device cannot be obtained. Therefore, the composition ratio x of the oxygen atoms (O) in the SiO _x film 52 is preferably 1.2 or more, the refractive index n of SiO _x film 52 is preferably 1.7 or less.

Each above-mentioned embodiment is only illustration of this invention, and can change a structure within the scope of the present invention. For example, in each of the above-described embodiments, the gate insulating film 36 includes the silicon nitride (SiN) film 50 that is the first gate insulating film and the silicon oxide film that is the second gate insulating film 53, specifically, silicon dioxide ( Although composed of the SiO ₂ ) film 51 and the low silicon oxide (SiO _x ) film 52, the gate insulating film 36 is not limited to this. For example, without providing the SiO ₂ film 51, x in SiO _x constitutes a second gate insulating film 53 at less than 2 lower silicon oxide (SiO _x) film 52 alone, only the SiN film 50 and the SiO _x film 52 The gate insulating film 36 may be configured. As described above, the second gate insulating film 53 may not include the SiO ₂ film 51, but is configured to include the SiO ₂ film 51 from the viewpoint of preventing hot carrier injection into the gate insulating film 36. It is preferable.

The second gate insulating film 53 has a laminated structure of the SiO ₂ film 51 and the SiO _x film 52 in each of the above-described embodiments, but is not limited to this, and may be formed of a single layer film, for example. Good. When the second gate insulating film 53 is formed of a single layer film, at least a portion in contact with the microcrystalline silicon films 62 and 70 has a composition represented by the composition formula SiO _x (x is a number of 1.2 or more and less than 2). Or a refractive index greater than 1.46 and 1.7 or less. For example, in the second gate insulating film 53, the composition ratio x of oxygen atoms (O) decreases from the first gate insulating film 50 side toward the microcrystalline silicon films 62 and 70 side, and the microcrystalline silicon films 62 and 70. It may be configured to be 1.2 or more and less than 2 at the part in contact with. The second gate insulating film 53 has a refractive index that increases from the first gate insulating film 50 side toward the microcrystalline silicon films 62 and 70 and is in contact with the microcrystalline silicon films 62 and 70. It may be configured to be larger than or equal to 1.7 or less.

  In each of the above-described embodiments, the manufacturing method of the channel etch type TFT has been described. However, even the etch stopper type TFT can be manufactured in the same manner.

  1, 2 Thin film transistor (TFT), 20, 20A TFT substrate, 21, 21A Pixel portion, 22 Gate driver portion, 31 Transparent insulating substrate, 32 Gate electrode, 33 Gate wiring, 34 Gate terminal portion, 35 Auxiliary capacitance electrode, 36 Gate insulating film, 37, 72 Active layer, 38 Source electrode, 39 Drain electrode, 40 Source wiring, 41 Source terminal part, 42 Interlayer insulating film, 43 Transparent pixel electrode, 44 Gate terminal pad, 45 Source terminal pad, 46 TFT channel Part, 47 pixel drain contact hole, 48 gate terminal part contact hole, 49 source terminal part contact hole, 50 first gate insulating film (silicon nitride film), 51 silicon dioxide film, 52 low silicon oxide film, 53 second gate insulation Membrane, 60,71 channel layer, 61 N Type semiconductor layer (N-type amorphous silicon film), 61a source layer, 61b drain layer, 62 microcrystalline silicon film, 63 i-type amorphous silicon film, and 70 argon (Ar) -containing microcrystalline silicon film.

Claims (7)

A gate electrode provided on an insulating substrate;
A gate insulating film provided on the gate electrode;
An active layer provided on the gate insulating film and including a microcrystalline silicon film provided in contact with the gate insulating film;
A source electrode and a drain electrode provided on the active layer,
The gate insulating film includes a silicon oxide film provided in contact with the microcrystalline silicon film,
Wherein the portion in contact with the microcrystalline silicon film of the silicon oxide film, the composition formula SiO x _(x is a number less than 2 1.2 or higher) have a composition represented by,
The microcrystalline silicon film included in the active layer, a thin film transistor, wherein Rukoto formed and crystallized during the formation. The silicon oxide film includes a portion in contact with the microcrystalline silicon film, and a low silicon oxide film having a composition represented by the composition formula SiO _x (x is a number of 1.2 or more and less than 2), and the low oxidation is arranged under the silicon film, thin film transistor according to claim 1, characterized in Rukoto that having a stacked structure of a silicon dioxide film having a composition represented by the composition formula SiO _2.   The gate insulating film further includes a silicon nitride film interposed between the gate electrode and the silicon oxide film, and has a stacked structure of the silicon nitride film and the silicon oxide film. 3. The thin film transistor according to 1 or 2.   The active layer further includes an amorphous silicon film provided on the microcrystalline silicon film, and has a stacked structure of the microcrystalline silicon film and the amorphous silicon film. 4. The thin film transistor according to any one of 3 above. Forming a gate electrode on an insulating substrate;
Forming a gate insulating film including a silicon oxide film on the gate electrode;
Forming an active layer including a microcrystalline silicon film on the gate insulating film;
Forming a source electrode and a drain electrode on the active layer ,
In the step of forming a pre-Symbol gate insulating film,
Forming the silicon oxide film so that at least an upper part of the silicon oxide film has a composition represented by a composition formula SiO _x (x is a number of 1.2 or more and less than 2) ;
In the step of forming the active layer,
The silicon oxide film in which the upper portion has a composition represented by the composition formula SiO _x (x is a number of 1.2 or more and less than 2), and oxygen vacancies as crystal growth nuclei exist on the upper surface. The microcrystal is deposited on the silicon oxide film by depositing a silicon film with the growth of microcrystalline silicon by plasma chemical vapor deposition using a mixed gas containing silane gas and hydrogen gas. A method of manufacturing a thin film transistor, comprising forming a silicon film . The step of forming the gate insulating film includes:
Forming a silicon dioxide film having a composition represented by the composition formula SiO ₂ on the gate electrode;
On the silicon dioxide film, by forming a low silicon oxide film having a composition represented by the composition formula SiO _x (x is a number of 1.2 or more and less than 2), the low silicon oxide film and the silicon dioxide are formed. method of manufacturing a thin film transistor according to claim 5, characterized in Rukoto and forming the silicon oxide film having a laminated structure of the film. The method of manufacturing a thin film transistor according to claim 5 or 6, wherein the mixed gas further contains an argon gas .

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