JP5594141B2 - Multi-frequency channel receiving apparatus and method using multiphase discrete processing - Google Patents

Description

(Description of related applications)
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2008-234994 (filed on September 12, 2008), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a communication apparatus, and more particularly to a receiving apparatus and method suitable for reducing the power consumption of a communication apparatus using frequency multiplex transmission and frequency hopping.

  Multi-frequency channel transmission / reception typified by frequency hopping and frequency multiplexing has been adopted as one of the means for responding to the ancient request of transmitting data quickly and remotely regardless of wired or wireless.

  For example, frequency multiplexing represented by wireless OFDM (Orthogonal Frequency Division Multiplexing) is widely used as means for improving the transmission rate while avoiding intersymbol interference caused by transmission.

  When viewed from the receiver, the frequency-multiplexed signal is a combination of a plurality of frequency channels called subcarriers, so that the time waveform becomes complicated and it is difficult to read data directly from the waveform.

  For this reason, a technique is adopted in which after a time waveform is converted into information on the frequency axis, it is decomposed into individual frequency components and demodulated. Since the processing after this time axis → frequency axis conversion needs to be calculated between a large number of sampling points and displayed in a spectrum, and difficult to realize with an analog circuit, it is digitally converted by an AD converter (Analog to Digital Converter). After conversion to a signal, FFT (Fast Fourier Transform) processing is performed by a DSP (Digital Signal Processor).

  The related art will be described below together with the analysis by the present inventors.

  FIG. 1 shows a configuration of a frequency multiplex receiver described in Non-Patent Document 1 in wireless communication. Referring to FIG. 1, in this frequency multiplexing receiver, after receiving a radio signal by an antenna, a signal appropriately amplified by an LNA (Low Noise Amplifier) 101 and an automatic gain control amplifier 102 is IQ (I : In-phase, Q: Quadrature) The detection 103 reduces the frequency to a low band and further decomposes the signal into two signal components on the real side and imaginary side of the complex signal. The signal output from the IQ detection 103 is converted into a digital signal by an AD converter and then input to the guard interval removal 104. In the guard interval removal 104, information from the sampling signal obtained by AD conversion is not read until a certain period of time elapses from the start of the symbol. Remove interference.

  The signal output from the guard interval removal 104 is sent to the FFT (105), and the signal intensity and phase rotation for each subcarrier are calculated by fast Fourier transforming the time waveform. Demapping (demodulation) is performed from the signal strength / phase information of each subcarrier, and the rearrangement of the bit arrangement is performed by deinterleaving. This demapping and deinterleaving is performed by demapping + deinterleaving 106.

  Signal processing in the communication physical layer is completed by performing decoding by a FEC (Forward Error Correction) decoder 107 on the signal that has been rearranged in the demapping + deinterleaving 106.

  In the frequency multiplexing receiver of FIG. 1, digital signal processing called FFT is used to separate a plurality of subcarriers received simultaneously into individual components. For this reason, an AD converter that converts an analog signal into a digital signal is required, and a DSP is required for FFT. Both ADC and DSP require a large circuit area, and require high-speed operation and power consumption according to the amount of arithmetic processing.

  In addition, frequency hopping is widely used as a method of spreading a spectrum over a wide band for the purpose of reducing coherence or increasing interference. In this case, unlike frequency multiplexing in which a plurality of frequencies are received at the same time, it is required to perform communication by switching frequencies in a time division manner, so a frequency synthesizer, so-called synthesizer, is required.

  However, when performing communication at a high data rate, the frequency hopping speed also increases, and the method of applying frequency hopping by switching the frequency division ratio of the phase lock loop does not catch up with the lockup speed and is difficult to use. Become.

  For this reason, when performing communication with a high data rate, especially multi-band OFDM communication using a so-called ultra-wide band (UWB), another configuration is required.

  That is, the frequency is multiplied by a four-phase input of frequency A and a four-phase input of frequency B, and only a frequency A + B or A−B is output (single sideband mixer, abbreviated as “SSB mixer”). Examples of synthesis are increasing due to the progress of UWB circuit technology.

  In the case of the SSB mixer, the multiplication result of the frequency A and the frequency B can be switched from the frequency A + B to AB by switching the order in the four-phase input, for example, 0 degree input and 180 degree input with the selector. For this reason, the frequency can be switched at high speed without being limited by the lockup time of the phase lock loop.

  FIG. 2 is a diagram illustrating a configuration of a high-speed frequency hopping IC disclosed in Patent Document 1 in ultra-wideband communication. 2 corresponds to the above-described frequency synthesizer (synthesizer). A signal 69 generated from the fixed frequency oscillator 32 at a desired frequency 2 × A is converted into a four-phase signal 50 having a half frequency A by the ½ divider 33. On the other hand, a signal of frequency B generated as a digital value by an NCO (numerically controlled oscillator) 35 is converted into a four-phase sine wave 40 (I, IB, Q, QB) as an analog signal by DA converters 37, 38. The

  A four-phase signal 40 of frequency A generated by the numerically controlled oscillator 35 and a four-phase signal 50 of frequency B generated from the fixed frequency oscillator 32 are input to an SSB (Single Side Band) mixer 31 and multiplied. . As a result, it is assumed that a signal of frequency A + B (or frequency AB) is obtained. Here, among the four-phase signals 50 on the numerically controlled oscillator side input to the SSB mixer 31, if Q (90 degree shift clock) and QB (270 degree shift clock) are switched by the phase changeover switch 34, the output frequency will be It can be switched like A-B (or A + B). Since this control does not include feedback, instantaneous switching without a time constant is possible.

  On the receiving side, the output signal of the SSB mixer 31 is multiplied by the LNA (9) output signal and the down-conversion mixer (10), and is dropped to the intermediate frequency signal 64, followed by AD conversion and digital baseband processing in the subsequent stage. Sent.

  As in the example shown in FIG. 2, when high-speed frequency hopping is attempted using the SSB mixer 31 as an analog circuit, the phase relationship between the input four-phase signals, the so-called IQ mismatch (the I component and the Q component) Offset) and mismatch of the differential circuit configuration of the SSB mixer (offset, etc.), not only the desired frequency A + B but also the frequency component of AB that should be removed at the same time. In order to increase the purity of the desired frequency component A + B, it is necessary to compensate for IQ mismatch and SSB mixer circuit mismatch, both of which are performed in the high-frequency analog domain for both control and circuit. High-precision tuning is difficult (analysis by the present inventor).

  In the frequency hopping receiver of FIG. 2, the LNA output signal of the frequency X and the local oscillator circuit output signal of the frequency Y are input to the down-conversion mixer (10), and the XY intermediate frequency signal is obtained. In order to obtain it, the local oscillation circuit must always output the frequency Y.

  In an ultra-wide band receiver that performs frequency hopping over a wide band from 3 GHz to sometimes 10 GHz, a local oscillation circuit must always generate a high-frequency signal near 10 GHz.

  In order to transmit a signal near 10 GHz with low distortion, the CMOS configuration buffer has insufficient bandwidth, and a current mode logic (CML) buffer with low output impedance and improved load driving capability is used. , CML consumes more power than a CMOS configuration because a through current always flows. Furthermore, when an inductor is used to increase the load impedance in the high frequency region and improve the buffer operating band, the circuit area increases, leading to an increase in chip cost (analysis by the present inventor).

  As described above, in both cases of frequency multiplexing and frequency hopping, a communication device that receives a plurality of frequency channels requires a circuit that has a large occupied area and operating power in an LSI, and is particularly high when performing broadband transmission. Accurate analog tuning is required, and digital scalable control is difficult.

JP 2007-295066 A

IEEE Std 802.11a-1999 “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specialties, High-speed Physical Layer 5”. 24 “The Design of CMOS Radio-Frequency Integrated Circuits” (TH Lee, 2nd Edition) p. 433-p. 434 “RF Microelectronics” (B. Razavi) p. 147-p. 149

  The analysis of the related art according to the present invention is summarized as follows.

  The frequency division multiplexing (OFDM) receiver disclosed in Non-Patent Document 1 and the like has an effect of obtaining resistance to waveform distortion and circuit generation noise caused by long-distance transmission, but reduces chip cost and consumption. It is difficult to reduce power.

  The reason for this is that by calculating the information of each frequency channel, that is, the amplitude and phase rotation of each subcarrier by fast Fourier transform processing, not only demodulation but also waveform degradation due to multipath fading that occurred during transmission is highly accurate. However, since fast Fourier transform is performed by digital signal processing, a process of converting the received analog signal into a digital signal by an A / D converter is essential. This fast Fourier transform requires multistage multiplication processing and occupies a circuit area. Further, the A / D converter occupies the circuit area, and it is necessary to increase the sampling frequency as the communication band is expanded, resulting in an increase in power consumption.

  In Patent Document 1, high-speed frequency hopping is possible, but analog tuning is necessary to ensure frequency purity, and power consumption is increased to handle high-frequency signals.

  The reason is that the output frequency is changed by switching the SSB mixer input, which is an analog circuit. Therefore, the purity of the output frequency is affected by analog elements such as the differential circuit mismatch of the SSB mixer. This is because it is necessary. Moreover, in order to advance the signal processing of the receiving circuit such as a down-conversion mixer, it is necessary to supply a high frequency signal in the vicinity of the carrier wave to the receiving circuit, and an increase in power consumption is unavoidable.

  On the other hand, as a reality in applications, it is required to provide a low-power wireless chip that can achieve wideband communication, interference resistance improvement, and coherence reduction by multi-frequency channel transmission at low cost.

  For this reason, it is important to reduce power consumption and chip cost by using a new circuit technology. (As described above, in the conventional configuration, power consumption is reduced by an A / D converter, DSP, and analog circuit elements. It was difficult to reduce the chip cost).

  An object of the present invention is to suppress an increase in area and power in a receiving apparatus that receives a received frequency hopping or frequency multiplexed multi-frequency channel signal, and reduces the area for handling high-frequency signals without using analog tuning. Then, a scalable digital control is introduced to provide a low power / area saving receiver and method.

  The invention disclosed in this document is generally configured as follows in order to solve the above problems.

  In one aspect of the present invention, a predetermined number of frequencies (N: N is a positive integer greater than or equal to 2) (f1, f2,..., FN) are input simultaneously or in time division as electrical signals. A receiving device that samples each frequency component of the predetermined number of frequencies (f1, f2,..., FN) with respect to an input signal at a predetermined sampling frequency (fs (x)). A plurality of discrete filters juxtaposed with each other, and a clock distribution system for supplying a clock group of a predetermined frequency (fc) whose phases are spaced apart from each other as clocks for sampling by the discrete filters to the discrete filters Is provided.

  In one aspect of the present invention, at least one of the plurality of discrete filters samples a plurality of frequency components at a predetermined frequency and then converts the frequency component to a predetermined frequency; A filter function for removing frequency components by calculation between sampled signals is provided.

  In one form of this invention, the anti-aliasing filter which removes a folding | turning signal is provided in the front | former stage with respect to at least 1 said discrete filter among these discrete filters.

  In one aspect of the present invention, the discrete filter samples at a frequency that is an integral multiple of the predetermined frequency (fc) of the clock from the clock distribution system as the sampling frequency (fs (x)).

  In one embodiment of the present invention, each of the clock distribution system and a plurality of the discrete filters are provided with a selector, and the plurality of selectors are activated / stopped in synchronization with an activation signal input thereto, You may make it receive the several frequency input by a time division.

  In one aspect of the present invention, the selector uses a part of clocks of a predetermined combination or all clocks of the clock group from the clock distribution system based on the activation signal in the discrete filter. The plurality of sampling clocks may be supplied to the discrete filter.

  In one form of the present invention, the discrete filter receives the input signal in common, and a plurality of sample and hold circuits are controlled by a plurality of sampling clocks whose phases are equally spaced. And an analog selector that sequentially selects the hold outputs of the plurality of sample and hold circuits and outputs them as one signal.

In another aspect of the present invention, a predetermined number (a plurality) of predetermined frequencies are input as electric signals simultaneously or in time division,
For the input signal, each frequency component of the predetermined number of frequencies is sampled at a predetermined sampling frequency with a plurality of discrete filters juxtaposed with each other,
As a clock for performing sampling by the discrete filter, a clock group having a predetermined frequency whose phases are separated from each other by a predetermined interval is supplied from the clock distribution system to the discrete filter.
A receiving method including the above steps is provided.

  According to the present invention, in a receiving apparatus that receives a received frequency hopping or multi-frequency channel signal that has been subjected to frequency multiplexing, an increase in area and power is suppressed, and an area that handles high-frequency signals without using analog tuning is provided. Reduce and introduce scalable digital control to achieve low power and area saving.

It is a figure which shows the structure of the OFDM receiver described in the nonpatent literature 1. FIG. It is a figure which shows the structure of the frequency hopping IC described in patent document 1. FIG. It is a figure which shows the structure of the 1st Example of this invention. It is a figure explaining the frequency arrangement | positioning in 1st Example of this invention. (A), (B) is a figure which shows the structure and operation | movement of the discrete filter 1 in the 1st Example of this invention. (A), (B) is a figure which shows the structure and operation | movement of the discrete filter 2 in the 1st Example of this invention. It is a figure which shows the structure of the 2nd Example of this invention. It is a figure explaining the frequency arrangement | positioning in the 2nd Example of this invention. (A), (B) is a figure which shows the structure and operation | movement of the discrete filter 1 in the 2nd Example of this invention. (A), (B) is a figure which shows the structure and operation | movement of the discrete filter 2 in the 2nd Example of this invention. (A), (B) is a figure which shows the frequency characteristic of the discrete filter 2 in the 2nd Example of this invention. It is a figure which shows the structure of the 3rd Example of this invention. It is a figure explaining the frequency arrangement | positioning in the 3rd Example of this invention. (A), (B) is a figure which shows the frequency characteristic of the discrete filter 1 in the 3rd Example of this invention. (A), (B) is a figure which shows the frequency characteristic of the discrete filter 2 in the 3rd Example of this invention.

1 Local Oscillator 4 OFDM Processing Unit 5 Modulator 6 High Output Power Amplifier (HPA)
7 Transmission / reception switch 8 Antenna 9 Low noise amplifier (LNA)
10 Mixer (down converter)
11 Communication control unit (communication processing unit)
30 DDS
31 SSB Mixer 32 Fixed Frequency Oscillator 33 1/2 Divider 34 Phase Switch 35 NCO (Numerically Controlled Oscillator)
36 Accumulator
37, 38 DAC (digital / analog converter)
40 4 phase sine wave 50 4 phase signal 64 Intermediate frequency signal 69 Signal 101 LNA
102 Automatic gain control amplifier 103 IQ detection 104 Guard interval removal 105 FFT
106 Demapping + Deinterleaving 107 FEC Decoder 108 Automatic Frequency Control / Clock Recovery 100 Wireless Transmission / Reception Device (Communication Device) 100
301 Discrete filter 1
302 Discrete filter 2
303 0 degree shift clock 304 90 degree shift clock 305 180 degree shift clock 306 270 degree shift clock 307 Clock distribution system 308 Selector 1
309 Start signal 1
310 Selector 2
311 Start signal 2
401 Channel 1 (frequency 2.2 GHz)
402 channel 2 (frequency 4.2 GHz)
403 Intermediate frequency (frequency 200 MHz)
501 Sample and hold circuit 1
502 Sample hold circuit 2
503 Analog selector 1
504 Sampling switch 505 Sampling capacity 601 Sample hold circuit 3
602 Sample and hold circuit 4
603 Sample and hold circuit 5
604 Sample and hold circuit 6
605 Analog selector 2
701 Discrete filter 1
702 Discrete filter 2
703 0-degree shift clock 704 90-degree shift clock 705 180-degree shift clock 706 270-degree shift clock 707 Clock distribution system 708 Antialias filter 901 Sample hold circuit 1
902 Sample and hold circuit 2
903 Analog selector 1
904 Sampling switch 1001 Sample and hold circuit 3
1002 Sample and hold circuit 4
1003 Sample and hold circuit 5
1004 Sample and hold circuit 6
1005 Analog selector 2
1202 0 degree shift clock 1203 45 degree shift clock 1204 90 degree shift clock 1205 135 degree shift clock 1206 180 degree shift clock 1207 225 degree shift clock 1208 270 degree shift clock 1209 315 degree shift clock 1210 120 degree shift clock 1211 240 degree shift clock 1212 Discrete filter 1
1213 Discrete filter 2

  According to the present invention, a clock distribution system in which a multiphase clock is transmitted and a part of or all clocks of the clock distribution system are driven, and each frequency component of a plurality of frequency components is subjected to frequency conversion and filtering by discrete time processing. A discrete filter for processing is provided, and frequency conversion or unnecessary component removal for the frequency channel is performed in combination with a discrete filter driven by a multiphase clock.

  In one embodiment of the present invention, referring to FIG. 3, a receiving apparatus in which a predetermined number (N) of predetermined frequencies (f1... FN) (for example, N = 2) are input as electric signals in a time division manner. The discrete filter 1 (301) and the discrete filter 2 (302) juxtaposed with each other with respect to the input signal are provided. When the selector 1 (308) is activated in the discrete filter 1, the input signal is transferred to the clock distribution system. (307) sequentially sampled and held by the clock group (303, 305), serialized (multiplexed into one output) and output. In the discrete filter 2, when the selector 2 (310) is activated, the input signal Are sequentially sampled and held by a four-phase clock (303 to 306), serialized and output. In the slot of channel 1 for frequency hopping, selector 1 is activated and In Le 2 slot selector 2 is started.

  Alternatively, in another aspect of the present invention, the discrete filter commonly receives a frequency multiplexed signal (FDM signal) in which a plurality of frequency components are multiplexed as the input signal. An antialiasing filter (708 in FIG. 7) that removes aliasing of frequency components different from the target band in the discrete filter may be provided, and at least one discrete filter that inputs a signal processed by the antialiasing filter may be provided. . The discrete filter receives a plurality of clocks of a predetermined combination from the clock group from the clock distribution system (707) or all clocks of the clock group as the plurality of sampling clocks used in the discrete filter. . At least one or all of the plurality of discrete filters may be configured to remove a frequency component different from the frequency component to be processed in the discrete filter (in this case, an anti-aliasing filter is unnecessary).

  Conventionally, a high-frequency signal in the vicinity of a carrier wave generated by a voltage-controlled oscillator or the like is frequency-converted by analog control to switch the output frequency and supply it to the receiving circuit. Power operability can be obtained.

  Furthermore, according to the present invention, the frequency multiplicity and the channel arrangement can be changed in a scalable manner by taking advantage of the characteristics of the multiphase clock. For example, if the 4-phase clock is doubled to 8 phases, the same effect as when the operation speed is doubled can be obtained.

  Also, the image band at the time of frequency conversion can be removed using multiphase complex discrete processing, and a high-density frequency multiplexed signal with a narrow channel interval can be received.

  A description will be given below in connection with specific examples. In the following examples, the present invention is not limited to the examples given in these examples, such as specific values of frequencies.

<First embodiment>
FIG. 3 is a diagram showing the configuration of the first exemplary embodiment of the present invention. FIG. 1 shows a main configuration of a multi-frequency channel receiver. Below, the structure which receives a frequency hopping signal especially is demonstrated. It is not limited to either wired communication or wireless communication. In the following embodiments, the number of frequencies (channels), the frequency band, the filter characteristics, and the like are merely for illustrative purposes and should not be understood as limiting the present invention.

  Referring to FIG. 3, among the discrete filter 1 (301) and the discrete filter 2 (302) for inputting the received signal, and 0-degree and 180-degree shift clocks among the four-phase shift clocks, the activation signal 1 (309) is input. ) Is controlled to start and stop, and at the time of startup, selector 1 (308) that inputs 0-degree and 180-degree shift clock to discrete filter 1 (301) and four-phase shift clock (303 to 306) are input to start signal 2 (311) controls start / stop, and includes a selector 2 (310) that inputs a four-phase shift clock (303 to 306) to the discrete filter 2 (302) at the time of startup.

  For example, as shown in FIG. 4, the frequency hopping signal processed by the receiver shown in FIG. 3 includes two frequency components of channel 1 (401) having a frequency of 2.2 GHz and channel 2 (402) having a frequency of 4.2 GHz. It is assumed that it is sent in time division and spread spectrum. Assume that the intermediate frequency (403) to be output is 200 MHz.

  The received signal is simultaneously input to the discrete filter 1 (301) and the discrete filter 2 (302) placed in parallel.

  The discrete filter 1 (301) is driven by a two-phase clock of a 1 GHz CMOS level 0-degree shift clock 303 and a 180-degree inverted CMOS level 180-degree shift clock 305.

  The discrete filter 1 (301) is connected to only the two-phase shift clocks (303, 305) among the four-phase shift clocks (303 to 306) constituting the clock distribution system 307.

  The discrete filter 2 (302) is a two-phase signal shifted to a 90-degree shift clock 304 and a 270-degree shift clock 306 in addition to the two-phase shift clocks (303, 305) for driving the discrete filter 1 (301). 4 phase clocks (303 to 306) are added. The discrete filter 2 (302) is connected to all the four-phase shift clocks (303 to 306) constituting the clock distribution system 307.

  The reason why the frequency of the shift clock per phase is 1 GHz is that the CMOS logic buffer has a frequency band in which clock distribution is possible without using a current mode logic (CML) buffer. The clock buffer (not shown) of the clock distribution system 307 is configured by CMOS logic, and circuit stop / start by gated control is easier than current mode logic.

  A selector 1 (308) is arranged between the clock distribution system 307 and the discrete filter 1 (301).

  The selector 1 (308) selects whether the clock supply to the discrete filter 1 (301) is continued or stopped by the activation signal 1 (309).

  Similarly, a selector 2 (310) is arranged between the clock distribution system 307 and the discrete filter 2 (302). The selector 2 (310) selects whether the clock supply to the discrete filter 2 (302) is continued or stopped by the activation signal 2 (311).

  The discrete filter 1 (301) outputs a signal of channel 1 (401) down-converted to 200 MHz having an intermediate frequency (403).

  From the discrete filter 2 (302), the signal of the channel 2 (402) which is also down-converted to the intermediate frequency (403) is output.

  In the configuration shown in FIG. 2 as a comparative example, in order to obtain an intermediate frequency of 200 MHz from a received signal having a frequency of 4.2 GHz, a clock of up to 4 GHz is supplied to a local oscillator (not shown) (mixer (down converter) in FIG. 2). 10).

  On the other hand, in this embodiment, since only a clock with a frequency of 1 GHz is required, the operation band of a clock buffer (not shown) constituting the clock distribution system 307 can be reduced, and the buffer input load is also reduced. Even if the number of clock phases increases, the clock distribution system 307 as a whole consumes less power than the configuration of FIG.

That is, assuming that the clock buffer load (capacitive load) of the configuration of FIG. 2 is C1, the clock frequency is f, the clock buffer load in the configuration of this embodiment of FIG. 3 is C2, and the clock frequency is f / 4, both are CMOS logic. If the power supply voltage is equal to V,
The power consumption in the case of the configuration of FIG. 2 is C1 × f × V × V
The power consumption in the case of the configuration of FIG. 3 is C2 × (f / 4) × V × V × 4 = C2 × f × V × V
It becomes.

  Since C1> C2, the buffer power consumption of this embodiment is smaller than the buffer power consumption in the configuration of FIG.

  In the configuration of FIG. 2, when current mode logic is used instead of CMOS logic, a through current from the power source to GND always flows, and this difference in power consumption is further increased.

  In the present embodiment, since all the clock distribution systems (307) can be configured by CMOS logic including the selector 1 (308) and the selector 2 (310), like the SSB mixer 31 in FIG. The output frequency purity is not affected by analog elements such as differential mismatch.

  Next, in addition to the configuration example of FIG. 3 and the frequency arrangement of FIG. 4, the operation when the multi-frequency channel receiver of this embodiment receives a frequency hopping signal will be described in detail. Here, in the case of wireless communication, a radio signal as an electromagnetic wave flying in space is converted into an electric signal in an antenna or the like, and is amplified to a strength suitable for the operation of the receiving circuit of this embodiment by a low noise amplifier. Shall be handled. The configuration of FIG. 3 is located in the down converter (10) at the rear stage of the LNA 9, referring to FIG.

  In the case of wired communication, a signal in which signal degradation caused by a transmission line is compensated to a value suitable for the operation of the receiving circuit in FIG. 3 by an input buffer or an equalizer is handled.

  In order to simplify the description, only two frequency channels, channel 1 and channel 2, are subjected to frequency hopping. However, in this embodiment, the number of hopping channels is not limited to two. is there.

  The frequency hopping signals (received signals in FIG. 3) subjected to spectrum spread in channel 1 (401) and channel 2 (402) are input to discrete filter 1 (301) and discrete filter 2 (302) arranged in parallel. The However, since it is a frequency hopping method, channel 1 (401) and channel 2 (402) are not input simultaneously, and channel 1 (401) or channel 2 (402) is not time-divided (separate slot). Either one is input in common to the discrete filter 1 (301) and the discrete filter 2 (302).

  In the slot receiving channel 1 (401), the start signal 1 (309) causes the shift clock to reach the discrete filter 1 (301) from the clock distribution system (307). It connects to the discrete filter 1 (301) via the selector 1 (308). In this slot, since channel 2 (402) is not received, the selector 2 prevents the shift clock from reaching the discrete filter 2 (302) from the clock distribution system (307) by the activation signal 2 (311). 2 (310) is controlled to avoid unnecessary power consumption in the discrete filter 2 (302).

  In the slot that receives channel 1 (401), down-conversion is performed in the discrete filter 1 (301) from the frequency 2.2 GHz of channel 1 (401) according to the timing relationship defined by the multiphase clock. 4 intermediate frequency (403) is converted to 200 MHz.

  FIG. 5A is a diagram showing a configuration of the discrete filter 1 (301) of FIG. FIG. 5B is a diagram showing the received signal and the timing waveforms of the 0 ° and 180 ° shift clocks 303 and 305.

  Referring to FIG. 5A, the discrete filter 1 (301) includes a sample and hold circuit 1 (501) driven by a 0 degree shift clock 303 and a sample and hold circuit 2 driven by a 180 degree shift clock 305. (502) Further, the analog selector 1 (503) which selects the output of the sample and hold circuit 1 (501) and the output of the sample and hold circuit 2 (502) according to the 0 degree shift clock 303 and outputs an intermediate frequency signal. And. The sample and hold circuit (501, 502) includes a sampling switch (504) and a sampling capacitor (505). The sampling switch (504) is turned on when, for example, the clock is logic “1”, and the sampling capacitor is used for the received signal. (505) is charged and turned off when the clock is logic "0", and the sampling capacitor (505) holds the received signal voltage immediately before the sampling switch (504) is turned off. Although omitted in FIG. 5A for simplicity, it is needless to say that the sample-and-hold circuit may include a buffer circuit such as a voltage follower that outputs a terminal voltage of the capacitor.

  In the sample and hold circuit 1 (501), when the logic level of the 0-degree shift clock is “1”, the sampling switch 504 is turned on, and the potential difference applied by the sampling capacitor 505 follows the input waveform (sampling mode). ).

  Further, when the logic level of the 0-degree shift clock 303 is “0”, the sampling switch 504 is turned off, and the sampling capacitor 505 holds the voltage of the received signal at the terminal voltage (hold mode). For this reason, the sampling capacitor 505 stores the voltage value of the received signal when the logic level of the 0-degree shift clock 303 transitions from “1” to “0”, and holds the memory until the logic level returns to “1”. It will be. That is, the input waveform of the discrete filter 1 (301) is sampled at the falling position of the 0-degree shift clock 303.

  Similarly, in the sample and hold circuit 2 (502), the input waveform of the discrete filter 1 (301) is sampled at the falling position of the 180-degree shift clock 305.

  In the analog selector 1 (503) that performs the selection operation with the 0-degree shift clock 303, the sample / hold circuit 1 (501) and the sample / hold circuit 2 (502) are sampled and matched so as to match the hold mode period. If the output voltages of the hold circuit 1 (501) and the sample hold circuit 2 (502) are selected and output, sampling signals sampled at the falling positions of both the 0 degree shift clock 303 and the 180 degree shift clock 305 are obtained. Will be obtained.

  That is, the analog selector 1 (503) selects the output of the sample and hold circuit 1 (501) and outputs the sample and hold circuit during the period when the logic level of the 0 degree shift clock 303 inputted as the selection signal is “0”. 1 (501) hold mode value is output.

  The analog selector 1 (503) selects the output of the sample-and-hold circuit 2 (502) and outputs the sample-and-hold circuit 2 while the logic level of the 0-degree shift clock 303 inputted as the selection signal is “1”. The value of the hold mode (502) is output. As a result, both sampled values are output at the falling positions of the 0-degree shift clock 303 and the 180-degree shift clock 305, respectively.

  The selection operation in the analog selector 1 (503) is a so-called “serialization” process in which the hold values of the sample and hold circuits 1 (501) and 2 (502) inputted in parallel are serially output. The same serialization is performed in the process in the discrete filter 2 (302) described later. That is, the analog selector 1 (503) functions as a multiplexer that selects and time-multiplexes the outputs of the sample and hold circuits 1 (501) and 2 (502).

  In this embodiment, since the frequency of both the 0-degree shift clock and the 180-degree shift clock is 1 GHz, the input waveform is sampled at the sampling frequency of 2 GHz as a result of being sampled at the falling positions of both clocks. .

  If a 2.2 GHz channel 1 signal is sampled at a sampling frequency of 2 GHz, a signal down-converted to 200 MHz can be obtained according to the principle of the sampling mixer. For details of the sampling mixer, refer to the description in Non-Patent Document 2.

  Next, the reception of channel 1 ends, and in the slot where channel 2 is received, the discrete filter 2 (302) decreases from the frequency 4.2 GHz of channel 2 (402) according to the timing relationship defined by the 4-phase clock. Conversion is performed and the intermediate frequency is converted to 200 MHz.

  FIG. 6A is a diagram illustrating a configuration of the discrete filter 2 (302). FIG. 6B is a diagram illustrating timing waveforms of the reception signal and the 0-degree shift clock 303 to 270-degree shift clock 306 in FIG.

The discrete filter 2 (302) is
A sample and hold circuit 3 (601) driven by a 0 degree shift clock 303;
A sample and hold circuit 4 (602) driven by a 90-degree shift clock 304;
A sample and hold circuit 5 (603) driven by a 180-degree shift clock 305;
A sample and hold circuit 6 (604) driven by a 270 degree shift clock 306;
Analog selector 2 (605) for selecting the output of each of the sample and hold circuits 3, 4, 5 and 6 according to the selection operation defined by the 0 degree shift clock 303 and the 90 degree shift clock 304 and outputting an intermediate frequency signal When,
It has.

  Here, in the sample and hold circuit 3 (601), the operation of sampling the input signal of the channel 2 at the falling position of the 0-degree shift clock 303 is the same as that of the discrete filter 1 (301).

  For the other sample / hold circuits 4 (602), 5 (603), and 6 (604), the input signal of the channel 2 at the falling position of the 90 ° shift clock 304, the 180 ° shift clock 305, and the 270 ° shift clock 306. Is sampled. Similarly to the discrete filter 1 (301), the hold mode values obtained by the sample-and-hold circuits 3, 4, 5, and 6 are serialized by the analog selector 2 (605), and the discrete filter 2 ( 302).

  In the discrete filter 2 (302), as a result of sampling at the falling positions of the 1 GHz 0 degree shift clock 303, 90 degree shift clock 304, 180 degree shift clock 305, and 270 degree shift clock 306, the input waveform is It is sampled at a sampling frequency of 4 GHz.

  If the 4.2 GHz channel 2 signal is sampled at 4 GHz, a signal down-converted to 200 MHz according to the principle of the sampling mixer can be obtained as in the case of the discrete filter 1.

  The operation in the discrete filter 2 is continued in the slot that receives the channel 2 and returns to the operation of the slot that receives the channel 1 as soon as the reception slot of the channel 2 is completed.

  However, this is an operation when the reception slot of channel 1 and the reception slot of channel 2 are alternately repeated.

  When randomly hopping between a plurality of slots, the activation signal 1 (309) and the activation signal 2 (311) are not alternately set to logic “1”, but randomly set to logic “1”. Programmed. In this case, it can be realized without changing the configuration of FIGS. 5 and 6.

  Next, the function and effect of this embodiment will be described.

  In the conventional configuration, when receiving a frequency hopping signal, a local oscillator that outputs a high-frequency clock near the carrier frequency is required. However, according to this embodiment, a local oscillator that outputs a high-frequency clock near the carrier frequency is used. It is unnecessary.

  That is, according to the present embodiment, it is possible to realize an equivalent process by including the sampling mixer driven by the multiphase clock. As a result, a large area buffer for driving the high-frequency clock is not necessary, and low power is realized.

  Further, by combining the discrete processing by the sampling mixer and multiphase clock distribution and adopting a configuration in which the multiphase clock distribution destination is switched by the selector, a circuit with a CMOS logic configuration can be realized. As a result, analog circuit elements such as an SSB mixer can be reduced, and tuning can be avoided.

  Furthermore, in the description of the configuration and operation described above, the clock distribution system is configured with a four-phase clock. However, when sampling at 8 GHz is desired, a total of four phases of 45 degrees, 135 degrees, 225 degrees, and 315 degrees is also added. This is possible by configuring a clock distribution system with eight phases and performing the same multiphase sampling mixer processing. Thus, there is an effect that scalable function expansion is facilitated.

<Second embodiment>
Next, a second embodiment of the present invention will be described. In the first embodiment, a frequency hopping signal input in a time division manner in the reception of a plurality of frequency channels has been dealt with. In this embodiment, a so-called frequency multiplexed signal (FDM) in which a plurality of frequency channels are input simultaneously. The structure in the case of receiving (signal) is demonstrated. Only the differences from the first embodiment will be described below.

FIG. 7 is a diagram showing the configuration of the second exemplary embodiment of the present invention. Referring to FIG. 7, the second embodiment is different from the first embodiment in that
(A) In the first embodiment, selectors 1 and 2 (308 and 310) are disposed between the clock distribution system (307) and the discrete filters 1 and 2 (301 and 302), respectively. In the second embodiment, no selector is provided between the clock distribution system (707) and the discrete filters 1 and 2 (701, 702).
(B) In the second embodiment, the anti-aliasing filter 1 (708) is arranged in the previous stage of the discrete filter 1 (701).

  In the second embodiment of the present invention, the frequency multiplexed signal processed by the receiver has two frequency components of a channel 1 having a frequency of 2.5 GHz and a channel 2 having a frequency of 4.5 GHz as shown in FIG. It is assumed that it has been sent and multiplexed. Assume that the intermediate frequency to be output is 500 MHz.

  The received frequency multiplexed signal (received signal) is simultaneously input to discrete filter 1 (701) and discrete filter 2 (702) placed in parallel. Prior to input to discrete filter 1 (701), Unlike the input to the discrete filter 2 (702), it passes through the anti-aliasing filter 1 (708).

  The discrete filter 1 (701) is connected to only two phases among the 1 GHz four-phase shift clocks 703 to 706 forming the clock distribution system (707), and the discrete filter 2 (702) is a four-phase shift clock. 703 to 706 are all connected. Since this is the same as in the first embodiment, description thereof is omitted.

  The discrete filter 1 (701) outputs a channel 1 signal down-converted to an intermediate frequency of 500 MHz, and the discrete filter 2 (702) outputs a channel 2 signal that is also down-converted to an intermediate frequency. .

  7 and 8, as in FIGS. 3 and 4 of the first embodiment, the frequency multiplicity is set to 2 in order to simplify the description. However, in the present invention, the number of multiplicity is 2. Of course, the present invention is not limited to the above, and is applicable to multiplicity other than 2.

  Comparing the configuration of this embodiment shown in FIG. 7 with the configuration shown in FIG. 1, in this embodiment, channels 1 and 2 of frequency multiplexed signals can be used without using an AD converter or a DSP that performs FFT. Are separated and output. For this reason, the area of the receiving circuit can be reduced.

  Next, the operation of the second embodiment of the present invention will be described. Hereinafter, operations different from those of the first embodiment will be described with reference to FIGS.

  Also in the second embodiment of the present invention, a plurality of frequency channels of channel 1 and channel 2 are received, but each is input simultaneously. For this reason, the discrete filter 1 (701) that receives the channel 1 has a filter characteristic that removes the channel 2, and the discrete filter 2 (702) that receives the channel 2 has a filter characteristic that removes the channel 1. have.

  In the discrete filter 1 (701), the component of the frequency 4.5 GHz that the channel 2 has is removed, and down conversion is performed from the frequency 2.5 GHz that the channel 1 has according to the defined timing relationship of the multiphase clock. It is converted to an intermediate frequency of 500 MHz.

  FIG. 9A is a diagram illustrating a configuration of the discrete filter 1 (701). FIG. 9B is a diagram showing the reception signal of FIG. 9A and the timing waveforms of the 0 ° and 180 ° shift clocks 703 and 705. The discrete filter 1 (701) outputs the outputs of the sample and hold circuit 1 (901) and the sample and hold circuit 2 (902) connected in parallel, and the sample and hold circuit 1 (901) and the sample and hold circuit 2 (902). A receiving analog selector 1 (903) is provided. The sample-and-hold circuit 1 (901) and the sample-and-hold circuit 2 (902) are received signals when the sampling switch 904 is turned on / off by the 0-degree and 180-degree shift clocks 703 and 705, and when the sampling switch 904 is on. A sampling capacitor is provided which is charged and holds accumulated charges (voltage) when the sampling switch 904 is off.

  Since discrete filter 1 (701) performs sampling in two phases of 0 degree shift clock 703 and 180 degree shift clock 705, the signal of channel 1 is sampled at a sampling frequency of 2 GHz as in the operation in the first embodiment. Will do. As a result, an intermediate frequency signal of 500 MHz is output according to the principle of the sampling mixer.

  However, according to the sub-sampling principle, sampling is performed in the same manner even with a harmonic component of 2 GHz. In this example, even with a sampling frequency of 2 GHz, channel 2 with a frequency of 4.5 GHz can be sampled, and the resulting frequency is 500 MHz due to frequency folding. In this case, when channel 1 and channel 2 are sampled simultaneously at 2 GHz, both outputs have the same frequency of 500 MHz and overlap in the same phase, and the signal component disappears.

  For this reason, it is necessary to place the anti-aliasing filter 1 (708) before the discrete filter 1 (701) to avoid such overlap. In other words, if the anti-aliasing filter 1 (708) has a characteristic of removing at least a component of frequency 4.5 GHz, the component of the channel 2 is removed at the time when it is input to the discrete filter 1 (701). Will be. As a result, only the channel 1 is output from the discrete filter 1 (701).

  Next, the discrete filter 2 (702) performs down-conversion according to the timing relationship defined by the multiphase clock from the frequency 4.5 GHz that the channel 2 has, and the component of the frequency 2.5 GHz that the channel 1 has. It is removed and converted to an intermediate frequency of 500 MHz.

FIG. 10A is a diagram illustrating a configuration of the discrete filter 2 (702). FIG. 10B is a diagram illustrating timing waveforms of the received signal and the 0-degree shift clock 703 to 270-degree shift clock 706 in FIG.

  Referring to FIG. 10A, the discrete filter 2 (702) includes sample and hold circuits 3, 4, 5, 6 (1001, 1002, 1003, 1004) connected in parallel, sample hold circuits 3, 4, An analog selector 2 (1005) for receiving outputs of 5 and 6 (1001, 1002, 1003, 1004) is provided. The sample and hold circuits 3, 4, 5, 6 (1001, 1002, 1003, 1004) are a sampling switch that is turned on / off by a 0 to 270 degree shift clock 703 to 706, and a received signal when the sampling switch is on. And a sampling capacitor that holds the accumulated charge (voltage) when the sampling switch is off.

  Here, after sampling is performed according to the timing relationship defined by the four-phase shift clock, the operation until the down-conversion to the intermediate frequency according to the principle of the sampling mixer is performed in the discrete filter 2 (302 of the first embodiment). ) Operation is the same.

  At this point, since both the channel 1 and channel 2 components are included in the down-converted discrete-time signal, it is necessary to remove the channel 1 component thereafter.

  When channel 1 is sampled at 4 GHz, the signal obtained is 1.5 GHz (4 GHz-2.5 GHz), and when channel 2 is similarly sampled at 4 GHz, the signal obtained is 500 MHz.

  For this reason, the discrete filter 2 can output only the channel 2 by performing a filtering process that removes at least 1.5 GHz on the signal obtained by sampling.

  In the discrete filter 2 (702), since the Nyquist frequency is 2 GHz, as shown in FIG. 11 (B), if normalized by the Nyquist frequency (= 2 GHz) and there is a zero point at a part of 0.75, Desired properties are obtained. The filter transfer function H (z) for obtaining this characteristic is as follows.

H (z) = 1 + √2 (1 / z) + (1 / z ² ) (1)

  The zero point of H (z) exists at exp (± j3π / 4) = (− 1 ± j) / √2 as shown in FIG.

  The discrete filter 2 (702) can output only the channel 2 if the calculation based on the transfer function is performed between the hold values obtained by sampling with the four-phase clock.

In the present embodiment, in order to enable simultaneous reception of a plurality of frequency channels, an anti-aliasing filter 1 (708) is provided, and further, filtering processing is performed in the discrete filter 2 (702). In addition, in the discrete filter 2 (702), the filter function of the transfer function of Expression (1) (Y (z) = (1 + √2z ⁻¹ + z ⁻² ) X with respect to the hold value obtained by sampling with a four-phase clock. (Z)) can be implemented using any known configuration such as a SCF (switched capacitor filter). The filter output Y (N) (N is an integer indicating a sampling point) is a current sample value X (N) and a value √2 · X (N−1) obtained by multiplying the previous sample value by a coefficient √2. It is obtained by voltage-adding the previous sample value X (N−2). The coefficient (1: √2: 1) may be set according to the ratio of the sampling capacitance values.

  In this embodiment, by adopting multiphase discrete processing, it is possible to reduce the operating frequency per clock distribution system and reduce the power consumption. Multiple frequency channel reception is possible without using a circuit that requires a chip internal area and power consumption such as a PLL and an AD converter, and scalable frequency control is possible by changing the number of clock phases.

  Next, the effect of the present embodiment will be described.

  In this embodiment, a frequency multiplexed signal (FDM signal) can be received by adding a circuit block such as an anti-aliasing filter to the first embodiment. However, frequency hopping and frequency multiplexing have different purposes such as the former avoiding interference and the latter improving communication speed.

<Third embodiment>
Next, a third embodiment of the present invention will be described. In the second embodiment, the case where the frequency interval between channels is wide among the reception of frequency multiplexed signals is taken as an example, but in this embodiment, the case where the channel interval is arranged at a narrower interval is taken. An application example will be described. In the following, differences from the second embodiment will be described. FIG. 12 is a diagram showing the configuration of the third embodiment of the present invention. Referring to FIG. 12, a discrete filter 1 (1212) and a discrete filter 2 (1213) are provided, and the discrete filter 1 (1212) includes 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, and 270 degrees. 315 degrees 8-phase shift clock 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209 is input, and discrete filter 2 (1213) is a 3-phase shift clock of 0 degrees, 120 degrees, and 240 degrees. 1202, 1210, and 1211 are input.

  As shown in FIG. 13, the frequency multiplexed signal processed by the receiver is frequency-multiplexed by simultaneously transmitting two frequency components of channel 1 having a frequency of 1.5 GHz and channel 2 having a frequency of 2.5 GHz. Shall. Assume that the intermediate frequencies to be output are all 500 MHz.

  In the second embodiment, the clock distribution system 707 has four phases. In this embodiment, the 45-degree shift clock 1203, the 135-degree shift clock 1205, the 225-degree shift clock 1207, and the 315-degree shift clock. Six phases of 1209, 120 degree shift clock 1210, and 240 degree shift clock 1211 are added to form a total of 10 phases. That is, in this embodiment, the number of phases of the clock distribution system is increased from 4 phases to 10 phases.

  The discrete filter 1 (1212) for selecting the channel 1 includes a 0 degree shift clock, a 45 degree shift clock, a 90 degree shift clock, a 135 degree shift clock, a 180 degree shift clock, a 225 degree shift clock, a 270 degree shift clock, An 8-phase clock of 315 degree shift clock is connected.

  The discrete filter 2 (1213) is connected to a three-phase clock of 0 degree shift clock, 120 degree shift clock, and 240 degree shift clock.

  In the present embodiment, it is not necessary to dispose anti-aliasing filters before the discrete filters 1 (1212) and 2 (1213). The other configuration is the same as that of the second embodiment.

  Next, the operation of the third embodiment of the present invention will be described. Hereinafter, operations different from those of the second embodiment will be described with reference to FIGS. In the third embodiment, it is assumed that a frequency multiplexed signal that simultaneously receives channel 1 and channel 2 is handled.

  In the discrete filter 1 (1212), the component of the frequency 2.5 GHz that the channel 2 has is removed, and the down conversion is performed according to the timing relationship defined by the 8-phase clock from the frequency 1.5 GHz that the channel 1 has, It is converted to an intermediate frequency of 500 MHz.

  Note that sampling is performed according to the timing relationship defined by the falling position of the multiphase clock input to the discrete filter 1 (1212), and down-conversion is performed according to the principle of the sampling mixer. 6 is the same as the first embodiment described with reference to FIG. 6 and the second embodiment described with reference to FIGS. In this embodiment, since the number of clock phases is 10, the timing waveform diagram is omitted.

  In this embodiment, unlike the operation of the discrete filter 1 (701) in the second embodiment, the sampling frequency in the discrete filter 1 (1212) is a timing relationship between two phases of 0 degree shift clock and 180 degree shift clock. Note that 2 is defined as 2 GHz.

  When the channel 1 of 1.5 GHz and the channel 2 of 2.5 GHz are sampled at a sampling frequency of 2 GHz, the signals having the opposite phases but the same down-converted to 500 MHz are obtained.

  This is a state where a so-called image frequency is mixed, and these two down-converted signals are the filters of the transfer function H (z) of the equation (1) described in the second embodiment, that is, A filter whose coefficients of z are all real numbers cannot be removed. This is because a filter whose coefficients of z are all real numbers has a symmetric transfer function between the positive frequency axis and the negative frequency axis, and therefore cannot distinguish image frequencies having the same absolute value of the frequency and having opposite phases. This is because both the desired frequency and the image frequency give the same processing.

  In order to remove the image frequency component by making the transfer function asymmetric between the positive frequency axis and the negative frequency axis, it is necessary to introduce complex discrete processing.

  Because of this complex discrete processing, a signal sampled by an orthogonal clock shifted by 90 degrees with respect to the sampling clock is required.

  However, since the sampling frequency in the discrete filter 1 (1212) is 2 GHz formed by a two-phase clock of 1 GHz, the orthogonal clock is handled by being delayed by 45 degrees with respect to 1 GHz. (A clock that is 45 degrees out of phase at 1 GHz is 90 degrees in 2 GHz, that is, an orthogonal clock).

  In the discrete filter 1 (1212), it is necessary to remove the channel 2 in order to select the desired channel 1, but since the Nyquist frequency of the discrete filter 1 (1212) is 1 GHz, as shown in FIG. If the channel 2 frequency of 2.5 GHz is normalized with the Nyquist frequency and there is a zero point at the 0.5 point, the desired characteristics can be obtained. The filter transfer function H (z) for obtaining this characteristic is given by the following equation (2).

  H (z) = (1 / z) + j (2)

The zero of the transfer function H (z) in equation (2) is at z = j (see FIG. 14A). Formula (2)
Filter processing (Y (z) = (z ⁻¹ + j) X (z)), the filter output Y (N) (where N is an integer representing a sampling point) is the current sample value X (N) Is the value obtained by adding the previous sample value X (N−1) to the value obtained by rotating 90 ° on the complex plane (X (z) = x1 + jx2 is jX (z) = − x2 + jx1). .

  The discrete filter 1 (1212) can output only the channel 1 if the calculation based on the transfer function is performed between the hold values obtained by sampling with the 8-phase clock.

  It has been shown that, by taking the above operation procedure, the discrete filter 1 (1212) can remove unwanted components of the frequency multiplexed signal using complex polyphase discrete processing.

  Next, in the discrete filter 2 (1213), the frequency 1.5 GHz component of the channel 1 is removed, and the down conversion is performed from the frequency 2.5 GHz of the channel 2 according to the timing relationship defined by the multiphase clock. Is converted to an intermediate frequency of 500 MHz. As in the description of the discrete filter 1 (1212), the timing waveform diagram is omitted.

Since the discrete filter 2 (1213) is driven by a three-phase clock (1202, 1210, 1211), the sampling frequency is 3 GHz and the Nyquist frequency is 1.5 GHz. Therefore, the channel 1 to be removed is down-converted to a band centered on DC after sampling, as shown in FIG.
H (z) = 1− (1 / z) (3)
If the signal component near DC is removed through the high-pass filter expressed by the following equation, only the desired channel 2 component is selected and output.

The zero point of the transfer function (3) is at z = 1 (see FIG. 15A). That is, in the filter processing (Y (z) = (1−z ⁻¹ ) X (z)) of Expression (3), the filter output Y (N) (where N is an integer representing a sampling point) is A value obtained by subtracting the previous sample value X (N−1) from the previous sample value X (N) becomes a high pass for removing the DC component.

  Next, the function and effect of this embodiment will be described.

  By increasing the number of phases of the clock distribution system, it is possible to process a frequency multiplexed signal in which channels are arranged symmetrically from the sampling frequency of each discrete filter.

  Further, by adding not only four-phase and eight-phase clocks but also 120-degree shift clocks and 120-degree shift clocks, the types of sampling frequencies that can be realized increase, and an anti-aliasing filter need not be used.

  Further, by combining the anti-aliasing filter used in the second embodiment and the clock distribution system used in the present embodiment, a more complicated frequency channel arrangement of three or more channels is possible.

  It should be noted that the disclosures of the above-mentioned patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

Claims (20)

A receiving device in which a predetermined number (a plurality) of predetermined frequencies are input simultaneously or in time division as an electric signal,
For the input signal, each frequency component of the predetermined number of frequencies is sampled at a predetermined sampling frequency, and a plurality of discrete filters juxtaposed with each other;
As a clock for sampling with the discrete filter, a clock distribution system for supplying a clock group of a predetermined frequency whose phases are separated from each other by a predetermined interval to the discrete filter;
With
A receiving apparatus comprising: an antialiasing filter that removes a folding signal at a preceding stage of at least one of the plurality of discrete filters .   At least one of the plurality of discrete filters is configured to sample the plurality of frequency components at a predetermined frequency and then convert the frequency component to a predetermined frequency and a frequency signal other than the desired frequency component between the sampled signals. The receiving apparatus according to claim 1, further comprising: a filter function for removing by the calculation.   The receiving device according to claim 1, wherein the discrete filter samples at a frequency that is an integral multiple of the predetermined frequency of the clock from the clock distribution system. A receiving device in which a predetermined number (a plurality) of predetermined frequencies are input simultaneously or in time division as an electric signal,
For the input signal, each frequency component of the predetermined number of frequencies is sampled at a predetermined sampling frequency, and a plurality of discrete filters juxtaposed with each other;
As a clock for sampling with the discrete filter, a clock distribution system for supplying a clock group of a predetermined frequency whose phases are separated from each other by a predetermined interval to the discrete filter;
With
A selector is provided between the clock distribution system and the plurality of discrete filters,
The plurality of selectors are started / stopped in synchronization with a start signal inputted to each,
A receiving apparatus that receives a plurality of frequencies input in a time division manner. The discrete filter receives a frequency hopped signal as the input signal,
Based on the activation signal, said selector for connecting to said discrete filter corresponding to the received frequency is started, the selector connected to said discrete filter that do not correspond to the reception frequency is stopped, it claim 4, wherein Receiver. The discrete filter receives the input signal in common, and a plurality of sample and hold circuits in which a sample mode and a hold mode are controlled by a plurality of sampling clocks whose phases are equally spaced,
An analog selector for sequentially selecting the hold outputs of the plurality of sample and hold circuits and outputting them as one signal;
With
The selector provided between the clock distribution system and the discrete filter , based on the activation signal, a plurality of clocks of a predetermined combination of clocks from the clock distribution system or the clock The receiving apparatus according to claim 4 , wherein all clocks of a clock group are supplied to the discrete filter as the plurality of sampling clocks used in the discrete filter. A receiving device in which a predetermined number (a plurality) of predetermined frequencies are input simultaneously or in time division as an electric signal,
For the input signal, each frequency component of the predetermined number of frequencies is sampled at a predetermined sampling frequency, and a plurality of discrete filters juxtaposed with each other;
As a clock for sampling with the discrete filter, a clock distribution system for supplying a clock group of a predetermined frequency whose phases are separated from each other by a predetermined interval to the discrete filter;
With
The plurality of discrete filters commonly receive a frequency multiplexed signal obtained by multiplexing a plurality of frequency components as the input signal,
Among the plurality of discrete filters, at least one discrete filter that includes an anti-aliasing filter that removes aliasing of a frequency component different from a target band of the discrete filter, and inputs a signal processed by the anti-aliasing filter, in the preceding stage A receiving apparatus comprising: The plurality of discrete filters commonly receive a frequency multiplexed signal obtained by multiplexing a plurality of frequency components as the input signal,
At least one discrete filter of the plurality of discrete filter is removed in the different frequency components the discrete filter and the frequency component to be processed, it claimed in any one of claims 1 to 3, wherein Receiver. 9. The receiving apparatus according to claim 8 , wherein at least one of the plurality of discrete filters removes an undesired component of the frequency-multiplexed signal using complex discrete processing. The discrete filter receives the input signal in common by a plurality of sampling clocks whose phases are equally spaced, and a sample mode and a hold mode are controlled by a plurality of sampling clocks whose phases are equally spaced A sample and hold circuit,
An analog selector for sequentially selecting the hold outputs of the plurality of sample and hold circuits and outputting them as one signal;
With
The discrete filter receives a plurality of clocks of a predetermined combination of the clock groups from the clock distribution system or all clocks of the clock group as the plurality of sampling clocks used in the discrete filter. the receiving apparatus according to any one of claims 7 to 9, characterized in that. A predetermined number (a plurality) of predetermined frequencies are input simultaneously or time-divisionally as electrical signals,
For the input signal, each frequency component of the predetermined number of frequencies is sampled at a predetermined sampling frequency with a plurality of discrete filters juxtaposed with each other,
As a clock for sampling by the discrete filter, a clock group having a predetermined frequency whose phases are separated from each other by a predetermined interval is supplied from the clock distribution system to the discrete filter .
For at least one of said discrete filter, receiving method thereof in front of the anti-aliasing filter to supply a signal obtained by removing an aliasing signal, it is characterized by one of said plurality of discrete filter. In at least one of the plurality of discrete filters,
A mixer process for sampling the plurality of frequency components at a predetermined frequency and converting the sample to a predetermined frequency;
The receiving method according to claim 1 1, the frequency components of the desired non executes a filtering process for removing the operation between the sampled signals, characterized in that. Wherein the discrete filter The receiving method according to claim 1 1 or 12 wherein said sampled at said predetermined integer multiple of the frequency of the clock from the clock distribution system, it is characterized. A predetermined number (a plurality) of predetermined frequencies are input simultaneously or time-divisionally as electrical signals,
For the input signal, each frequency component of the predetermined number of frequencies is sampled at a predetermined sampling frequency with a plurality of discrete filters juxtaposed with each other,
As a clock for sampling by the discrete filter, a clock group having a predetermined frequency whose phases are separated from each other by a predetermined interval is supplied from the clock distribution system to the discrete filter.
The selector between the clock distribution system and the plurality of discrete filters is started / stopped in synchronization with a start signal input to each, and receives a plurality of frequencies input in a time division manner. Reception method. The discrete filter receives a frequency hopped signal as the input signal,
Based on the activation signal, said selector for connecting to said discrete filter corresponding to the received frequency is started, the selector is stopped to be connected to the discrete filter that do not correspond to the reception frequency, it to claims 1-4, characterized in The receiving method described. The plurality of discrete filters commonly receive a frequency multiplexed signal obtained by multiplexing a plurality of frequency components as the input signal,
At least one discrete filter of the plurality of discrete filter is removed in the different frequency components the discrete filter and the frequency component to be processed, the method of reception according to claim 1 1, wherein the. At least one discrete filter among the plurality of discrete filters is characterized in that a signal processed by an anti-aliasing filter that removes aliasing of frequency components different from the band targeted by the discrete filter is input to the preceding stage. The receiving method according to claim 16 . The reception method according to claim 16 , wherein at least one of the plurality of discrete filters removes an undesired component of the frequency-multiplexed signal using complex discrete processing. 12. The discrete filter receives a part of clocks or all clocks of a predetermined combination in the clock group from the clock distribution system as clocks for performing the sampling. 18. The reception method according to any one of items 1 to 17. Comprising first and second discrete filters juxtaposed with each other for receiving a received signal;
The first discrete filter is:
A first group of sample and hold circuits that respectively sample and hold the received signals in response to a first group of clocks having different phases supplied from a clock distribution system;
A first multiplexing circuit that multiplexes and serially outputs a plurality of signals held by the first group of sample and hold circuits;
With
The second discrete filter is:
A second group of sample and hold circuits that respectively sample and hold the received signals in response to a second group of clocks having different phases supplied from the clock distribution system;
A second multiplexing circuit for multiplexing and serially outputting a plurality of signals held by the second group of sample and hold circuits;
A first selector that inputs the first group of clocks from the clock distribution system and that is activated and stopped in synchronization with a first activation signal that is input;
A second selector that inputs the second group of clocks from the clock distribution system and that is activated and stopped in synchronization with the input second activation signal;
With
In the slot of the first channel of frequency hopping, the first selector is activated, the second selector is deactivated, and the first group of clocks from the clock distribution system is transmitted via the first selector. Supplied to the first discrete filter;
In the slot of the second channel, the second selector is activated, the first selector is deactivated, and the second group of clocks from the clock distribution system passes through the second selector . A receiving apparatus that is supplied to a discrete filter.

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