JP5588469B2 - Substrate processing equipment - Google Patents

Description

  The present invention includes a processing block including a coating processing unit and a development processing unit for a plurality of substrates stacked, an exposure block including an exposure processing unit for a substrate, and an interface block connecting the processing block and the exposure block. The present invention relates to a substrate processing apparatus provided.

  Generally, in a semiconductor manufacturing process, for example, there is a photolithography process in which a photoresist is applied on a substrate such as a semiconductor wafer, the resist film is exposed according to a predetermined circuit pattern, and developed to form a circuit pattern. Done. In this photolithography process, a substrate processing apparatus in which an exposure apparatus is connected to a coating / development processing apparatus is usually used.

  As a conventional substrate processing apparatus of this type, a substrate after coating and a substrate after exposure are connected to an interface block that transports the substrate between a processing block having a coating / developing processing unit and an exposure block having an exposure processing unit. Is provided with a buffer unit that waits, a substrate storage unit that stores a substrate carried in and out of the exposure block, and a substrate transfer robot that transfers the substrate (for example, see Patent Document 1).

  In the device described in Patent Document 1, a first substrate transfer robot is disposed on the processing block side of the interface block, and a second substrate transfer robot is disposed on the exposure block side. The substrate after coating is transported to the first buffer unit and the first substrate housing unit, the substrate is transported to the exposure block by the second substrate transport robot, and the substrate after exposure is transported to the second buffer unit, Describes a technique for transporting an exposed substrate received from a second buffer unit to a processing block by a substrate transport robot.

Japanese Patent Laying-Open No. 2009-158925 (paragraph 0033, FIG. 4)

  However, in the technique described in Patent Document 1, since the substrate transport robot is arranged on the processing block side and the exposure block side, the space occupied by the substrate transport robot is widened, which may increase the size of the apparatus. In addition, since the first substrate transport robot is responsible for transporting the substrate after coating into the interface block and transporting the substrate after exposure to the processing block, throughput is reduced when processing a large number of substrates continuously. There is a concern about the decline.

  Further, in the exposure apparatus that constitutes the exposure block, the arrangement of the substrate delivery unit may not be constant due to the exposure process, and if the substrate transport robot that delivers the substrate to the exposure block is arranged on the exposure block side There is a possibility that it cannot correspond to the arrangement of the board transfer section.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a substrate processing apparatus capable of reducing the size of the apparatus and improving the throughput, and adapting to the arrangement of the substrate delivery portions of different exposure apparatuses. To do.

In order to solve the above-described problems, a first substrate processing apparatus of the present invention includes a processing block including a coating processing unit and a development processing unit for a plurality of stacked substrates, and an exposure block including a substrate exposure processing unit. And an interface block connected to the processing block and connecting the processing block and the exposure block, the interface block is a first mounting for mounting the substrate after coating. A shelf unit for stacking a substrate mounting unit, a second mounting unit for mounting a substrate before development, a buffer unit for waiting the substrate, and a substrate cooling unit, and both sides of the shelf unit. A first substrate transport mechanism and a second substrate transport formed such that a substrate can be transferred to the unit, and one of the substrates can be transferred to the exposure block. Comprising a structure, a by one of the substrate transport mechanism of the first and second substrate transport mechanism, a substrate after coating, and received from the first placement unit, and conveyed to the buffer section, and the other The substrate received from the buffer section by the substrate transport mechanism is transported to the substrate cooling section and the exposure block, and the substrate received from the exposure block is transported to the second placement section by the one substrate transport mechanism. It is formed so that it may convey (Claim 1).

The second substrate processing apparatus of the present invention includes a processing block including a plurality of substrate coating processing units and a development processing unit, and a substrate exposure processing unit, as in the first substrate processing apparatus. Assuming a substrate processing apparatus comprising an exposure block provided, and an interface block connected to the processing block and connecting the processing block and the exposure block, the interface block places a substrate on which the coated substrate is placed. An upper shelf unit that stacks a first placement unit, a second placement unit that places a substrate before development, a buffer unit that waits for the substrate, and a first substrate delivery unit; and vertically below the upper shelf unit A lower shelf unit that is biased and that stacks the second substrate transfer unit and the substrate cooling unit, and is disposed on one of both sides of the upper shelf unit and the lower shelf unit. A first substrate transport mechanism that is formed so that a substrate can be delivered to the shelf unit; and the other one on both sides of the upper shelf unit and the lower shelf unit. A second substrate transport mechanism that is formed so as to be able to deliver a substrate and a substrate that can be delivered to the lower shelf unit, and can be transported to and received from the exposure block. And a third substrate transport mechanism to be formed (claim 2 ).

3. The substrate processing apparatus according to claim 2 , wherein the first substrate transport mechanism, the second substrate transport mechanism, and the third substrate transport mechanism share the transport process back and forth, and the substrate after coating is transferred to the first substrate transport mechanism. In order from the mounting unit, the buffer unit, the second substrate transfer unit, the substrate cooling unit, the substrate transferred to the exposure block, and the substrate received from the exposure block are transferred to the first substrate transfer unit and the first substrate transfer unit. preferably formed so as to convey to the second mounting portion (claim 3).

In this case, the first substrate transport mechanism transports the coated substrate from the first placement unit to the buffer unit and the first substrate transfer unit in order, and the second substrate transport mechanism. The substrate received from the first substrate transfer unit is transferred to the substrate cooling unit, and the substrate received from the substrate cooling unit is transferred to the exposure block by the third substrate transfer mechanism, and the exposure is performed. The substrate received from the block is transferred to the second substrate transfer unit, and the substrate received from the second substrate transfer unit is transferred to the second placement unit by the second substrate transfer mechanism. It is preferable to form it as follows (claim 4 ).

The third substrate processing apparatus of the present invention is similar to the first and second substrate processing apparatuses, and includes a processing block including a plurality of substrate coating processing units and a development processing unit, and substrate exposure. Assuming a substrate processing apparatus comprising an exposure block having a processing section and an interface block connected to the processing block and connected to the processing block, the interface block mounts a substrate after coating. A shelf unit for stacking a first placement unit to be placed, a second placement unit for placing a substrate before development, a first and second buffer unit for waiting the substrate, a substrate cooling unit, and a substrate delivery unit; A first process of laminating a peripheral exposure unit disposed on one of both sides of the shelf unit and removing an unnecessary coating film on the periphery of the substrate by exposure and a pre-exposure cleaning unit cleaning the substrate before exposure shelf A second processing shelf unit that is disposed on the other side of the knit and on both sides of the shelf unit and that stacks a plurality of post-exposure cleaning units that clean the exposed substrate, the shelf unit, and the first process. A first upper substrate transport mechanism and a first lower substrate transport which are arranged on a vertical line between the shelf units and are formed so that substrates can be delivered to the shelf unit and the first processing shelf unit, respectively. A mechanism is disposed on a vertical line between the shelf unit and the second processing shelf unit, and is formed to be capable of delivering a substrate to the shelf unit and the second processing shelf unit, respectively. The upper substrate transport mechanism and the second lower substrate transport mechanism are provided (claim 5 ).

6. The substrate processing apparatus according to claim 5 , wherein the first upper substrate transfer mechanism, the first lower substrate transfer mechanism, the second upper substrate transfer mechanism, and the second lower substrate transfer mechanism are moved forward and backward. In order to share the substrate after coating, the first buffer unit, the peripheral exposure unit, the second buffer unit, the pre-exposure cleaning unit, the substrate cooling unit, and the like, in order from the first mounting unit. transported to the exposure block, a substrate received from the exposure block, preferably formed so as to convey the post-exposure cleaning unit and to said second mounting portion (claim 6).

In this case, the first upper substrate transport mechanism transports the coated substrate sequentially from the first placement unit to the first buffer unit, the peripheral exposure unit, and the second buffer unit, and The substrate received from the second buffer unit by the first lower substrate transfer mechanism is transferred to the pre-exposure cleaning unit and the substrate cooling unit, and is received from the substrate cooling unit by the second lower substrate transfer mechanism. The substrate is transported to the exposure block, and the second upper substrate transport mechanism is formed so that the substrate received from the exposure block is transported to the post-exposure cleaning unit and the second placement unit. (Claim 7 ).

According to the first aspect of the present invention, the interface block includes first and second placement units for placing the coated substrate or the exposed substrate, a buffer unit for waiting the substrate, a substrate cooling unit, and a substrate. Arranged on both sides of the shelf unit that stacks the delivery unit and the shelf unit, each can deliver the substrate to the shelf unit, and one of them can deliver the substrate to the exposure block By providing the first substrate transport mechanism and the second substrate transport mechanism, the space occupied by the shelf unit and the substrate transport mechanism arranged in the interface block can be reduced. Further, by disposing the first substrate transport mechanism and the second substrate transport mechanism on both sides of the shelf unit, the substrate can be transferred in accordance with the position of the substrate transfer portion in the exposure block.

  In addition, the first substrate transport mechanism and the second substrate transport mechanism share the transport process back and forth, and the coated substrates are sequentially transferred from the first placement unit to the buffer unit, the substrate cooling unit, and the exposure block. The substrate can be efficiently transported by transporting the substrate received from the exposure block to the second placement unit.

According to invention of Claims 2-4 , the 1st and 2nd mounting part which mounts the board | substrate after application | coating or the board | substrate before image development, the buffer part which waits for a board | substrate, and a 1st board | substrate delivery part are provided. The upper shelf unit to be stacked, the lower shelf unit that is disposed to be deviated from vertically below the upper shelf unit, and the second substrate delivery unit and the substrate cooling unit are stacked, and the upper shelf unit and the lower shelf unit are sandwiched between The first substrate transport mechanism is arranged on one of the both sides and is formed so that the substrate can be transferred to the upper shelf unit, and the other on both sides of the upper shelf unit and the lower shelf unit. A second substrate transport mechanism that is formed so that the substrate can be delivered to the lower shelf unit; and a substrate that can be delivered to the lower shelf unit; Formed for transport and receipt That a third substrate transfer mechanism, by having a upper shelf unit disposed to the interface block, it is possible to reduce the occupied space of the lower shelf unit, and the first to third substrate transfer mechanism. Further, by arranging the first to third substrate transport mechanisms on both sides of the upper shelf unit and the lower shelf unit, it is possible to deliver the substrate in correspondence with the arrangement position of the substrate delivery unit in the exposure block. .

  Further, the first substrate transport mechanism, the second substrate transport mechanism, and the third substrate transport mechanism share the transport process back and forth, and the substrates after coating are sequentially arranged from the first placement section to the buffer section, The substrate is transferred to the first substrate transfer unit, the substrate cooling unit, and the exposure block, and the substrate received from the exposure block is transferred to the first substrate transfer unit and the second placement unit, thereby efficiently transferring the substrate. It can be carried out.

According to invention of Claims 5-7 , an interface block is the 1st and 2nd mounting part which mounts the board | substrate after application | coating or the board | substrate before image development, and the 1st, 2nd to make a board | substrate wait. A shelf unit that stacks the buffer unit, the substrate cooling unit, and the substrate delivery unit, and a peripheral exposure unit that is disposed on one of both sides of the shelf unit and removes an unnecessary coating film on the periphery of the substrate by exposure, and a pre-exposure unit A first processing shelf unit that stacks a pre-exposure cleaning unit that cleans the substrate and a second post-exposure cleaning unit that is disposed on the other side across the shelf unit and that cleans the substrate after exposure. Are arranged on a vertical line between the shelf unit and the first processing shelf unit, and are formed so as to be able to deliver substrates to the shelf unit and the first processing shelf unit, respectively. Upper substrate transfer mechanism and first A second substrate is arranged on the vertical line between the lower substrate transport mechanism and the shelf unit and the second processing shelf unit, and is formed so as to be able to deliver substrates to the shelf unit and the second processing shelf unit, respectively. By providing the substrate transport mechanism and the second lower substrate transport mechanism, the space occupied by the shelf unit and the substrate transport mechanism arranged in the interface block can be reduced. In addition, the first upper and lower substrate transfer mechanisms and the second upper and lower substrate transfer mechanisms are arranged on both sides of the shelf unit, so that the substrates are transferred according to the position of the substrate transfer portion in the exposure block. Is possible.

According to the invention described in claims 5 to 7 , the peripheral exposure unit, the pre-exposure cleaning unit, and the post-exposure cleaning unit are arranged in the interface block, and the first upper and lower substrate transport mechanisms and the second upper unit are arranged. In addition, by sharing the substrate transport by the lower substrate transport mechanism, it is possible to increase the processing efficiency of the immersion exposure in particular. Further, when any of the first upper and lower substrate transport mechanisms and the second upper and lower substrate transport mechanisms fails, the other substrate transport mechanisms can be substituted to continue the processing.

  According to the substrate processing apparatus of the present invention, the apparatus can be reduced in size and the throughput can be improved. Further, it is possible to provide a substrate processing apparatus that can cope with the arrangement of the substrate transfer portions of different exposure apparatuses.

It is a schematic plan view which shows an example of the substrate processing apparatus which concerns on this invention. It is a schematic perspective view which shows the said substrate processing apparatus. It is a schematic longitudinal cross-sectional view which shows the said substrate processing apparatus. It is a schematic plan view which shows the interface block in this invention. It is a schematic longitudinal cross-sectional view which shows the said interface block. It is a schematic side view which shows the board | substrate conveyance mechanism in this invention. It is a flowchart which shows the conveyance process of the board | substrate in this invention. It is a flowchart which shows the conveyance process of the board | substrate in 1st Embodiment concerning this invention. It is a flowchart which shows the conveyance process of the board | substrate in 2nd Embodiment concerning this invention. It is a flowchart which shows the conveyance process of the board | substrate in 3rd Embodiment concerning this invention. It is a schematic plan view which shows the interface block in 4th Embodiment concerning this invention. It is a schematic longitudinal cross-sectional view which shows the interface block in the said 4th Embodiment. It is a flowchart which shows the conveyance process of the board | substrate in the said 4th Embodiment. It is a schematic plan view which shows the substrate processing apparatus of 5th Embodiment concerning this invention. It is a schematic sectional drawing which shows the interface block in the said 5th Embodiment. It is a flowchart which shows the conveyance process of the board | substrate in the said 5th Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, the configuration of a coating / developing apparatus to which the substrate processing apparatus according to the present invention is applied will be described.

  As shown in FIG. 1, a carrier block S1, a processing block S2, an interface block S3, and an exposure block S4 are connected to the coating / development processing apparatus 1 in order from the carrier block S1 to the exposure block S4.

  In the carrier block S1, the transfer mechanism B takes out the wafer W from the sealed carrier 11 mounted on the mounting table 10 by the transfer arm 20, and transfers it to the processing block S2 adjacent to the carrier block S1. Further, the transfer mechanism B is configured to receive the wafer W after being processed in the processing block S <b> 2 and return it to the carrier 11.

  As shown in FIG. 2, the processing block S2 includes a first block (BCT layer) B1 for performing an antireflection film forming process formed on the lower layer side of the resist film, and a resist liquid coating process. 2nd block (COT layer) B2, 3rd block (TCT layer) B3 for performing the formation process of the antireflection film formed on the upper layer side of the resist film, 4th and 5th for performing the development process The blocks (DEV layers) B4 and B5 are stacked in order from the bottom.

  The first block (BCT layer) B1 and the third block (TCT layer) B3 each include a liquid processing module 30 including three application portions for applying a chemical solution for forming an antireflection film by spin coating. And a heating / cooling processing module 40 for performing pre-processing and post-processing of the processing performed in the liquid processing module 30, the liquid processing module 30, and the heating / cooling processing module 40. Are provided with transfer mechanisms A1 and A3 which are substrate transfer means for transferring the wafer W between them (see FIG. 3).

  The second block (COT layer) B2 has the same configuration except that the chemical solution is a resist solution and a hydrophobic treatment unit is incorporated. On the other hand, for the fourth and fifth processing blocks (DEV layers) B4 and B5, a developing unit is disposed in each of the DEV layers B4 and B5. In the DEV layers B4 and B5, transport mechanisms A4 and A5 for transporting the wafer W to these developing units are provided (see FIG. 3). In addition, shelf units U1 to U4 for stacking the heating / cooling processing modules 40 are provided at portions of the processing block S2 facing the first to fifth blocks B1 to B5 with respect to the transport paths of the transport mechanisms A1 to A5. ing. Further, as shown in FIG. 1 and FIG. 3, the processing block S2 is provided with a shelf unit U5, and between each part of the shelf unit U5, a vertically movable transport mechanism E provided in the vicinity of the shelf unit U5. Thus, the wafer W is transferred.

  In the shelf unit U5, as shown in FIG. 3, delivery units TCP1, TRS3, CPL11, CPL2, BF2, CPL3, BF3, delivery units CPL4, TRS4 are stacked in order from the bottom.

  On the other hand, on the upper part of the COT layer B2, the wafer is placed on the first placement unit TRS-COT for placing the coated wafer W provided on the shelf unit U6 described later from the delivery unit CPL11 provided on the shelf unit U5. A shuttle arm F which is a dedicated conveying means for directly conveying W is provided (see FIG. 3). The wafer W on which the resist film and further the antireflection film are formed is transferred to the transfer unit CPL11 by the transfer mechanism E via the transfer unit BF2 and TRS3, and from here, the first placement of the shelf unit U6 by the shuttle arm F. It is directly conveyed to the part TRS-COT and taken into the interface block S3.

  In the central portion of the interface block S3, a first placement portion TRS-COT for placing the wafer W after application of the resist solution, a second placement portion TRS-DEV for placing the wafer W before development, A shelf unit U6 for stacking a plurality of, for example, four stages of wafer cooling sections ICPL (hereinafter referred to as cooling section ICPL) and a plurality of, for example, two stages of wafer transfer sections TRS, is arranged. In the cooling unit ICPL, the wafer W is cooled to a predetermined temperature, for example, 23 ° C. so as not to affect the overlay accuracy of the exposure apparatus. In addition, although the several buffer part BFA and BFB are shown in the figure, one buffer part may be sufficient.

  A first substrate transport mechanism 60A (hereinafter referred to as the first transport mechanism 60A) and a second substrate transport mechanism 60B (hereinafter referred to as the first transport mechanism 60B) are provided on both sides of the front and back surfaces (X direction) of the apparatus with the shelf unit U6 interposed therebetween. In the following, the second transport mechanism 60B) is disposed to face each other. Here, the first transport mechanism A is disposed on the front side (left side in FIG. 5) of the apparatus, and the second transport mechanism 60B is disposed on the back side (right side in FIG. 5) of the apparatus. Each of the first transfer mechanism 60A and the second transfer mechanism 60B can transfer the wafer W to the shelf unit U6. On the other hand, for example, the first transfer mechanism 60A is provided in the exposure block S4. The wafer W can be transferred to a transfer table (not shown) which is a substrate transfer unit. A filter unit FFU is installed on the ceiling unit U of the interface block S and the first transport mechanism 60A and the second transport mechanism 60B, and the air purified by the filter unit FFU is removed from the interface block S. It is supplied by downflow.

  The first transport mechanism 60A and the second transport mechanism 60B are similarly configured, and are provided on the partition wall 50 side of the interface block S3 and the processing block S2 (see FIGS. 1, 4, and 5). ). Next, the structure of the first transport mechanism 60A and the second transport mechanism 60B will be described as a representative of the first transport mechanism 60A.

  As shown in FIG. 6, the first transport mechanism 60A includes a lifting platform 62 slidably mounted on a pair of left and right vertical guide rails 61 disposed on the partition wall 50 side of the interface block S3 and the processing block S2. The base part 64 mounted on the upper part of the lifting / lowering base 62 via the horizontal rotating part 63, the fork-like arm 65 provided on the base part 64 so as to be movable in the horizontal linear direction, and the lifting / lowering base 62 are lifted and lowered. And an elevating drive mechanism 66. In this case, the elevating drive mechanism 66 includes a drive pulley 66b driven by a drive motor 66a, a driven pulley 66c, and a timing belt 66d spanned between the drive pulley 66b and the driven pulley 66c, and is attached to the timing belt 66d. A lifting platform 62 is connected via a bracket 66e. The lifting drive mechanism 66 may be formed by a ball screw mechanism.

  Each drive unit in the first transport mechanism 60A configured as described above, that is, the drive motor 66a, the horizontal rotation unit 63, and the drive unit of the arm 65 are controlled by the external control unit 110 shown in FIG. It is driven by a signal from the control unit 110.

  The external control unit 110 is built in the control computer 100, and the control computer 100 is provided with a computer-readable storage medium storing software that causes the control computer 100 to execute the control program. The control signal is output to each of the above parts. The control program is stored in a storage medium such as a hard disk, a compact disk, a flash memory, a flexible disk, or a memory card, and is used by being installed in the control computer 100 from these storage media.

  The first and second transport mechanisms 60A and 60B configured as described above move and rotate in the vertical direction (Z direction), the horizontal orthogonal direction (X and Y directions), and the horizontal rotation direction (θ direction). Freely formed. Therefore, the first and second transport mechanisms 60A and 60B are provided with the first placement unit TRS-COT, the second placement unit TRS-DEV, and the buffer units BFA and BFB (hereinafter referred to as the following units) of each layer of the shelf unit U6. The wafer W can be transferred to a plurality of, for example, four stages of cooling units ICPL and a plurality of, for example, two stages of wafer transfer units TRS, and also to a transfer table (not shown) of the exposure block S4. The wafer W can be transferred and received. Accordingly, the first and second transfer mechanisms 60A and 60B share the transfer process of the wafer W back and forth, and the applied wafer W is sequentially transferred from the first placement unit TRS-COT to the buffer unit BF, It is possible to transport the wafer W before development after the exposure received from the exposure block S4 to the cooling unit ICPL and the exposure block S4 to the second placement unit TRS-DEV.

  Next, the transfer process of the wafer W in the interface block S3 will be described with reference to FIGS.

<First Embodiment>
FIG. 8 shows a case where the first transport mechanism 60A is dedicated to transport of the wafer W to the exposure block S4, that is, to carry the wafer W into and out of the exposure block S4. In the first embodiment, when the coated wafer W processed by the coating processing unit of the processing block S2 is loaded and placed on the first placement unit TRS-COT, the second transfer mechanism 60B. However, the wafer W is received from the first placement unit TRS-COT and transferred to the buffer unit BF (S-1), and the wafer W received from the buffer unit BF is transferred to the cooling unit ICPL (S-2). The wafer W cooled to a predetermined temperature by the cooling unit ICPL is received by the first transfer mechanism 60A and transferred to the delivery table (EIF-IN) of the exposure block S4 (S-3). The wafer W subjected to the exposure processing by the exposure apparatus of the exposure block S4 is received from the delivery table (EIF-OUT) of the exposure block S4 by the first transfer mechanism 60A and transferred to the second placement unit TRS-DEV. (S-4). The wafer W transferred to the second placement unit TRS-DEV is developed in the first block (DEV layer) B1 by the transfer mechanism A1 of the processing block S2.

  According to the first embodiment, the wafer W can be carried into and received from the exposure block S4 by the first transfer mechanism 60A corresponding to the case where the delivery table of the exposure block S4 is arranged vertically.

Second Embodiment
FIG. 9 shows a case where the second transport mechanism 60B is dedicated to transport of the wafer W to the exposure block S4, that is, to carry the wafer W into and out of the exposure block S4. In the second embodiment, when the coated wafer W processed by the coating processing unit of the processing block S2 is loaded into the first mounting unit TRS-COT and mounted thereon, the first transfer mechanism 60A. However, the wafer W is received from the first placement unit TRS-COT and transferred to the buffer unit BF (S-1), and the wafer W received from the buffer unit BF is transferred to the cooling unit ICPL (S-2). The wafer W cooled to a predetermined temperature by the cooling unit ICPL is received by the second transfer mechanism 60B and transferred to the delivery table (EIF-IN) of the exposure block S4 (S-3). The wafer W subjected to the exposure processing by the exposure apparatus of the exposure block S4 is received from the delivery table (EIF-OUT) of the exposure block S4 by the second transfer mechanism 60B and transferred to the second placement unit TRS-DEV. (S-4). The wafer W transferred to the second placement unit TRS-DEV is developed in the first block (DEV layer) B1 by the transfer mechanism A1 of the processing block S2.

  According to the second embodiment, the wafer W can be carried into and received from the exposure block S4 by the second transport mechanism 60B in correspondence with the case where the delivery table of the exposure block S4 is arranged vertically.

<Third Embodiment>
FIG. 10 shows a transfer process of the wafer W corresponding to the case where the delivery table of the exposure block S4 is arranged on the left and right of the exposure block S4. In the third embodiment, when the coated wafer W processed by the coating processing unit of the processing block S2 is loaded into and placed on the first mounting unit TRS-COT, the second transfer mechanism 60B. However, the wafer W is received from the first placement unit TRS-COT and transferred to the buffer unit BF (S-1). Next, the first transfer mechanism 60A transfers the wafer W received from the buffer unit BF to the cooling unit ICPL (S-2). The wafer W cooled to a predetermined temperature by the cooling unit ICPL is received by the first transfer mechanism 60A and transferred to the delivery table (EIF-IN) of the exposure block S4 (S-3). The wafer W subjected to the exposure processing by the exposure apparatus of the exposure block S4 is received from the delivery table (EIF-OUT) of the exposure block S4 by the second transfer mechanism 60B and transferred to the second placement unit TRS-DEV. (S-4). The wafer W transferred to the second placement unit TRS-DEV is developed in the first block (DEV layer) B1 by the transfer mechanism A1 of the processing block S2.

  According to the first to third embodiments, the interface block S3 includes the first and second placement units TRS-COT, TRS-DEV, and wafers on which the coated wafer W or the exposed wafer W is placed. The shelf unit U6 for stacking the buffer unit BF for waiting W, the cooling unit ICPL, and the wafer delivery unit TRS and the both sides of the shelf unit U6 are arranged, and each can deliver the wafer W to the shelf unit U6. In addition, one is provided in the interface block S3 by including the first transfer mechanism 60A and the second transfer mechanism 60B formed so that the wafer W can be delivered to the exposure block S4. The space occupied by the shelf unit U6 and the first and second transport mechanisms 60A and 60B can be reduced. Further, by disposing the first transport mechanism 60A and the second transport mechanism 60B on both sides of the shelf unit U6, the wafer W can be transferred in accordance with the position of the transfer table in the exposure block S4. .

  Also, the first transfer mechanism 60A and the second transfer mechanism 60B share the transfer process back and forth, and the coated wafers W are sequentially transferred from the first placement unit TRS-COT to the buffer unit BF and the cooling unit. By transferring the wafer W received from the exposure block S4 to the ICPL and the exposure block S4, the wafer W can be transferred efficiently and the throughput can be improved by transferring the wafer W to the second placement unit TRS-DEV. I can plan.

<Fourth embodiment>
FIG. 11 is a schematic plan view of an interface block S3A in the fourth embodiment of the substrate processing apparatus according to the present invention, and FIG. 12 is a schematic sectional view of the interface block S3A in the fourth embodiment.

  The fourth embodiment is a case where the case where the shelf unit in the interface block and the movement track of the transport mechanism overlap is avoided.

  As shown in FIGS. 11 and 12, the interface block S3A in the fourth embodiment has a first placement unit TRS-COT on which the coated wafer W is placed, and a second substrate on which the substrate before development is placed. The upper shelf unit UA that stacks the placement unit TRS-DEV, the buffer units BFA and BFB that wait for the wafer W, and the first wafer transfer unit TRSA, and the upper shelf unit UA that is biased to the back in the X direction from the vertically lower side. A lower shelf unit UB that is disposed and stacks the second wafer transfer unit TRSB and the cooling unit ICPL.

  Further, as shown in FIGS. 11 and 12, the interface block S3A has one of both sides in the front and back direction (X direction) of the apparatus sandwiching the upper shelf unit UA and the lower shelf unit UB, that is, the front side in the X direction ( A first substrate transfer mechanism 60C (hereinafter referred to as a first transfer mechanism 60C) disposed on the left side in FIG. 12 and capable of transferring the wafer W to the upper shelf unit UA, and an upper shelf unit A second side formed on the other side of the both sides of the UA and the lower shelf unit UB, that is, on the back side in the X direction (right side in FIG. 12), so that the wafer W can be delivered to the lower shelf unit UB. The wafer W is formed so that it can be transferred to the substrate transport mechanism 60D (hereinafter referred to as the second transport mechanism 60D) and the lower shelf unit UB, and the exposure block S4 is provided. Transport and receipt of the wafer W can be the third substrate transfer mechanism 60E that is formed (referred to as a third transfer mechanism 60E below), comprises a by.

  In the fourth embodiment, the first transport mechanism 60C and the second transport mechanism 60D have the same structure as the first and second transport mechanisms 60A and 60B, and are perpendicular to the vertical direction (Z direction) and horizontal. It is formed to be movable and rotatable in the direction (X, Y direction) and the horizontal rotation direction (θ direction). The second transport mechanism 60D is disposed on the side wall 50A on the back surface side of the interface block S3A without being raised or lowered along the vertical guide rail 61 disposed on the partition wall 50 of the processing block S2 and the interface block S3A. The guide rail may be moved up and down along the guide rail and moved and rotated in the horizontal rotation direction (θ direction). With this configuration, the second transport mechanism 60D can be formed to be movable only in the Z, X, and θ directions.

  As shown in FIGS. 11 and 12, the third transport mechanism 60E includes a column base 71 that is movably mounted on mutually parallel horizontal guide rails 70 laid on the bottom of the interface block S3, and the column base. A lifting platform 72 that can be moved up and down by a lifting mechanism (not shown) built in 71, and a horizontal orthogonal direction (X and Y directions) and a horizontal rotation direction by a moving mechanism (not shown) built in the lifting platform 62. And an arm 73 formed to be movable and rotatable in the (θ direction).

  The driving units of the first transport mechanism 60C, the second transport mechanism 60D, and the third transport mechanism 60E configured as described above are controlled by the external control unit 110, and signals from the control unit 110 are transmitted. Driven by.

  Thereby, the first transport mechanism 60C includes the first placement unit TRS-COT, the second placement unit TRS-DEV, the buffer units BFA and BFB (hereinafter referred to as the buffer unit BF) of the upper shelf unit UA. In addition, the wafer W can be delivered to the first wafer delivery unit TRSA. The second transport mechanism 60D can deliver the wafer W to the second wafer delivery unit TRSB and the plurality of cooling units ICPL of the lower shelf unit UB. Further, the third transport mechanism 60E moves to the second wafer transfer unit TRSB of the lower shelf unit UB and the lower portion of the upper shelf unit UA to move to the plurality of cooling units ICPL and transfer blocks of the exposure block S4. The wafer W can be delivered.

  Next, the wafer W transfer process of the fourth embodiment will be described with reference to the flowchart shown in FIG. In the fourth embodiment, when the coated wafer W processed by the coating processing unit of the processing block S2 is loaded into the first mounting unit TRS-COT and mounted thereon, the first transfer mechanism 60C is used. However, the wafer W is received from the first placement unit TRS-COT and transferred to the buffer unit BF (BF-IN) (S-11). Next, the first transfer mechanism 60C receives the wafer W from the buffer unit BF (BF-OUT) and transfers it to the first wafer transfer unit TRSA (S-12). When the wafer W is transferred to the first wafer transfer unit TRSA, the second transfer mechanism 60D receives the wafer W from the first wafer transfer unit TRSA and transfers it to the cooling unit ICPL (S-13). The wafer W cooled to a predetermined temperature by the cooling unit ICPL is received by the third transfer mechanism 60E and transferred to the delivery table (EIF-IN) of the exposure block S4 (S-14). The wafer W subjected to the exposure processing by the exposure apparatus of the exposure block S4 is received from the transfer table (EIF-OUT) of the exposure block S4 by the third transfer mechanism 60E and transferred to the second wafer transfer unit TRSB (S -15). The wafer W transferred to the second wafer transfer unit TRSB is transferred to the second placement unit TRS-DEV by the second transfer mechanism 60D (S-16). The wafer W transferred to the second placement unit TRS-DEV is developed in the first block (DEV layer) B1 by the transfer mechanism A1 of the processing block S2.

  According to the fourth embodiment, the first and second placement units TRS-COT and TRS-DEV for placing the coated wafer W or the undeveloped wafer W, the buffer unit BF for waiting the wafer W, and the first An upper shelf unit UA that stacks one wafer transfer unit TRSA, and a lower shelf unit UB that is deviated from vertically below the upper shelf unit UA and stacks a second wafer transfer unit TRSB and a cooling unit ICPL. The upper shelf unit UA and the lower shelf unit UB are arranged on either side of the front and back sides (X direction) of the apparatus, and the wafer W can be transferred to the upper shelf unit UA. The first transport mechanism 60C is disposed on the other side of the front and back direction (X direction) of the apparatus sandwiching the upper shelf unit UA and the lower shelf unit UB, and the wafer with respect to the lower shelf unit UB. The second transfer mechanism 60D formed so as to be able to deliver W and the lower shelf unit UB are formed so as to be able to deliver the wafer W, and the wafer W can be transferred to and received from the exposure block S4. The upper shelf unit UA, the lower shelf unit UB, and the first, second, and third transport mechanisms 60C disposed in the interface block S3A. , 60D, 60E can be reduced.

  Further, by arranging the lower shelf unit UB so as to be deviated from vertically below the upper shelf unit UA, it is possible to prevent the shelf unit in the interface block S3A and the movement track of the transfer mechanism from overlapping, and the wafer W Transport can be performed efficiently. Further, by arranging the first, second and third transport mechanisms 60C, 60D, 60E on both sides of the upper shelf unit UA and the lower shelf unit UB, it corresponds to the arrangement position of the delivery table in the exposure block S4. Thus, the wafer W can be delivered.

  Further, the first, second, and third transfer mechanisms 60C, 60D, and 60E share the transfer process back and forth, and the coated wafers W are sequentially transferred from the first placement unit TRS-COT to the buffer unit BF. The wafer W is transferred to the first wafer transfer unit TRSA, the cooling unit ICPL, and the exposure block S4, and the wafer W received from the exposure block S4 is transferred to the first wafer transfer unit TRS and the second placement unit TRS-DEVB. As a result, the wafer W can be efficiently transferred, and the throughput can be improved.

<Fifth Embodiment>
FIG. 14 is a schematic plan view in which the substrate processing apparatus according to the fifth embodiment of the present invention is applied to a coating / developing apparatus, and FIG. 15 is a schematic cross-sectional view showing an interface block in the fifth embodiment.

  Since the carrier block S1 and the processing block S2 in the coating / developing apparatus according to the fifth embodiment are the same as those in the first to fourth embodiments, the same portions are denoted by the same reference numerals and the description thereof is omitted.

  As shown in FIGS. 14 and 15, the interface block S3B in the fifth embodiment includes a shelf unit UC arranged at the center of the interface block S3B and a first process arranged on both sides of the shelf unit UC. The first upper substrate transport mechanism 90A (hereinafter referred to as the first upper transport mechanism 90A) disposed between the shelf unit 80A and the second processing shelf unit 80B, and the shelf unit UC and the first processing shelf unit 80A. ) And a first lower substrate transport mechanism 90B (hereinafter referred to as a first lower transport mechanism 90B), and a second upper substrate transport disposed between the shelf unit UC and the second processing shelf unit 80B. A mechanism 90C (hereinafter referred to as a second upper transport mechanism 90C) and a second lower substrate transport mechanism 90D (hereinafter referred to as a second lower transport mechanism 90D) are mainly configured. It is.

  In this case, the shelf unit UC is arranged at the center of the interface block S3B, and the first placement unit TRS-COT on which the coated wafer W is placed, and the second placement on which the wafer W before development is placed. Placement unit TRS-DEV, first and second buffer units BFA, BFB for waiting wafer W, a plurality of, for example, four wafer cooling units ICPL (hereinafter referred to as cooling unit ICPL) for cooling wafer W to a predetermined temperature, for example, 23 ° C. ) And a wafer transfer section TRS.

  The first processing shelf unit 80A is disposed on one side of the X direction across the shelf unit UC, that is, on the front side of the apparatus (left side in FIG. 15), and removes an unnecessary coating film on the periphery of the wafer W by exposure. The peripheral exposure unit WEE and the pre-exposure cleaning unit SRS for cleaning the pre-exposure wafer W are formed in a casing. The second processing shelf unit 80B is disposed on the other side in the X direction across the shelf unit UC, that is, on the back side (right side in FIG. 15) of the apparatus, and a plurality of, for example, 3 for cleaning the wafer W after exposure. It is formed of a casing in which a plurality of post-exposure cleaning parts PIR are stacked.

  The first upper transport mechanism 90A and the first lower transport mechanism 90B are arranged on a vertical line between the shelf unit UC and the first processing shelf unit UC, and the shelf unit UC and the first processing shelf unit 80A, respectively. On the other hand, the wafer W can be transferred. Further, the second upper transport mechanism 90C and the second lower transport mechanism 90D are disposed on the vertical line between the shelf unit UC and the second processing shelf unit 80B, and the shelf unit UC and the second processing shelf, respectively. The wafer W is formed so as to be transferred to the unit 80B.

  According to the substrate processing apparatus of the fifth embodiment configured as described above, the first upper transport mechanism 90A, the first lower transport mechanism 90B, the second upper transport mechanism 90C, and the second lower transport mechanism 90D. Divides the transfer process forward and backward, and sequentially coats the wafer W after coating from the first placement unit TRS-COT, the first buffer unit BFA, the peripheral exposure unit WEE, the second buffer unit BFB, and the pre-exposure cleaning unit. The wafer W transferred to the SRS, the cooling unit ICPL, and the exposure block S4 and received from the exposure block S4 can be transferred to the post-exposure cleaning unit PIR and the second mounting unit TRS-DEV.

  Next, the wafer W transfer process of the fifth embodiment will be described with reference to the flowchart shown in FIG. In the fifth embodiment, the first upper transfer mechanism 90A receives the coated wafer W from the first placement unit TRS-COT and transfers it to the first buffer unit BFA (S-21). The wafer W received from the first buffer unit BFA is transferred to the peripheral exposure unit WEE (S-22). The wafer W transferred to the peripheral exposure unit WEE is removed from the peripheral unnecessary coating film by exposure, and then is received from the peripheral exposure unit WEE by the first upper transfer mechanism 90A and transferred to the second buffer unit BFB. (S-23). Next, the wafer W received from the second buffer unit BFB is transferred to the pre-exposure cleaning unit SRS by the first lower transfer mechanism 90B (S-24). The wafer W cleaned by the pre-exposure cleaning unit SRS is received from the pre-exposure cleaning unit SRS by the first lower transfer mechanism 90B and transferred to the substrate cooling unit ICPL (S-25). Cool to a temperature, for example 23 ° C. Next, the wafer W received from the cooling unit ICPL is transferred to the delivery table EIF-IN of the exposure block S4 by the second lower transfer mechanism 90D (S-26). The wafer W that has been exposed by the exposure apparatus of the exposure block S4 is received from the delivery table EIF-OUT of the exposure block S4 by the second upper transfer mechanism 90C and transferred to the post-exposure cleaning unit PIR (S-). 27). The wafer W cleaned by the post-exposure cleaning unit PIR is received from the post-exposure cleaning unit PIR by the second upper transfer mechanism 90C and transferred to the second placement unit TRS-DEV (S-28). . The wafer W transferred to the second placement unit TRS-DEV is developed in the first block (DEV layer) B1 by the transfer mechanism A1 of the processing block S2.

  According to the fifth embodiment, the peripheral exposure unit WEE, the pre-exposure cleaning unit SRS, and the post-exposure cleaning unit PIR are arranged in the interface block S3B, and the first upper and lower transport mechanisms 90A and 90B and the second upper unit and By sharing the transfer process of the wafer W by the lower transfer mechanisms 90C and 90D, the processing efficiency of the immersion exposure can be particularly improved. Further, when one of the first upper and lower transport mechanisms 90A and 90B and the second upper and lower transport mechanisms 90C and 90D fails, the processing can be continued by substituting the other transport mechanisms. .

<Other embodiments>
In the first to fourth embodiments, the case where the wafer W is delivered to the shelf units U6 and UA and the exposure block S4 arranged in the interface blocks S3 and S3A has been described. However, the first to fourth embodiments are described. Also in the embodiment, for example, a processing shelf unit that stacks a peripheral exposure unit, a pre-exposure cleaning unit, and a post-exposure cleaning unit is arranged in the interface blocks S3 and S3A, and these peripheral exposure unit and pre-exposure cleaning unit are arranged by the substrate transport mechanism. It is also possible to deliver the wafer to the post-exposure cleaning unit.

  Moreover, although the said embodiment demonstrated the case where it applied to a semiconductor wafer, this invention is applicable also to the glass substrate for flat panel displays.

S2 processing block S3, S3A, S3B interface block U6, UC shelf unit UA upper shelf unit UB lower shelf unit TRS-COT first placement unit TRS-DEV second placement unit BF buffer unit BFA first buffer unit BFB Second buffer unit TRS Wafer transfer unit (substrate transfer unit)
TRSA first wafer transfer section (first substrate transfer section)
TRSB second wafer transfer section (second substrate transfer section)
ICPL cooling unit (wafer cooling unit, substrate cooling unit)
WEE peripheral exposure unit SRS Pre-exposure cleaning unit PIR Post-exposure cleaning unit 60A, 60C First transport mechanism (first substrate transport mechanism)
60B, 60D Second transport mechanism (second substrate transport mechanism)
60E Third transport mechanism (third substrate transport mechanism)
80A first processing shelf unit 80B second processing shelf unit 90A first upper transport mechanism (first upper substrate transport mechanism)
90B First lower transport mechanism (first lower substrate transport mechanism)
90C Second upper transport mechanism (second upper substrate transport mechanism)
90D Second lower transport mechanism (second lower substrate transport mechanism)

Claims (7)

A processing block having a coating processing section and a development processing section for a plurality of substrates to be stacked, an exposure block having a substrate exposure processing section, and a processing block connected to the processing block to connect the processing block and the exposure block. A substrate processing apparatus comprising: an interface block;
The interface block above
A shelf unit for stacking a first placement part for placing the substrate after coating, a second placement part for placing the substrate before development, a buffer part for waiting the substrate, and a substrate cooling part ;
A first substrate disposed on both sides of the shelf unit, each of which is capable of delivering a substrate to the shelf unit and one of which is capable of delivering the substrate to the exposure block. A transport mechanism and a second substrate transport mechanism;
Equipped with,
The substrate after coating is received from the first placement unit by one substrate transport mechanism of the first and second substrate transport mechanisms, transported to the buffer unit, and the buffer is transported by the other substrate transport mechanism. The substrate received from the exposure unit is transferred to the substrate cooling unit and the exposure block, and the substrate received from the exposure block is transferred to the second placement unit by the one substrate transfer mechanism. the substrate processing apparatus, characterized in that. A processing block having a coating processing section and a development processing section for a plurality of substrates to be stacked, an exposure block having a substrate exposure processing section, and a processing block connected to the processing block to connect the processing block and the exposure block. A substrate processing apparatus comprising: an interface block;
The interface block above
An upper shelf unit for stacking a first placement part for placing a substrate after application, a second placement part for placing a substrate before development, a buffer part for waiting the substrate, and a first substrate delivery part; ,
A lower shelf unit that is arranged to be deviated from vertically below the upper shelf unit and that stacks the second substrate transfer unit and the substrate cooling unit;
A first substrate transport mechanism that is disposed on one of both sides of the upper shelf unit and the lower shelf unit, and is formed so that a substrate can be delivered to the upper shelf unit;
A second substrate transport mechanism that is disposed on the other side of both sides of the upper shelf unit and the lower shelf unit, and is formed so that a substrate can be delivered to the lower shelf unit;
A third substrate transport mechanism which is formed so as to be capable of delivering a substrate to the lower shelf unit, and capable of transporting and receiving the substrate with respect to the exposure block;
A substrate processing apparatus comprising: The substrate processing apparatus according to claim 2 ,
The first substrate transport mechanism, the second substrate transport mechanism, and the third substrate transport mechanism share the transport process back and forth, and the substrates after coating are placed in order from the first placement section in the buffer section. The second substrate delivery unit, the substrate cooling unit, and the exposure block are transported, and the substrate received from the exposure block is transported to the first substrate delivery unit and the second placement unit. A substrate processing apparatus, which is formed. In the substrate processing apparatus of Claim 2 or 3 ,
The first substrate transport mechanism transports the coated substrates sequentially from the first placement unit to the buffer unit and the first substrate transfer unit, and the second substrate transport mechanism performs the first process. The substrate received from one substrate transfer unit is transported to the substrate cooling unit, and the substrate received from the substrate cooling unit is transported to the exposure block by the third substrate transport mechanism and received from the exposure block. The substrate is transported to the second substrate delivery section, and the substrate received from the second substrate delivery section is transported to the second placement section by the second substrate transport mechanism. A substrate processing apparatus. A processing block having a coating processing section and a development processing section for a plurality of substrates to be stacked, an exposure block having a substrate exposure processing section, and a processing block connected to the processing block to connect the processing block and the exposure block. A substrate processing apparatus comprising: an interface block;
The interface block above
A first placement portion for placing a substrate after coating, a second placement portion for placing a substrate before development, first and second buffer portions for waiting the substrate, a substrate cooling portion, and a substrate delivery portion A shelf unit for stacking,
A first processing shelf disposed on one of both sides of the shelf unit, in which a peripheral exposure unit that removes unnecessary coating films on the periphery of the substrate by exposure and a pre-exposure cleaning unit that cleans the substrate before exposure are stacked. Unit,
A second processing shelf unit which is disposed on the other side of the both sides of the shelf unit and which stacks a plurality of post-exposure cleaning units for cleaning the exposed substrate;
A first upper substrate that is arranged on a vertical line between the shelf unit and the first processing shelf unit, and is formed so that a substrate can be delivered to the shelf unit and the first processing shelf unit, respectively. A transport mechanism and a first lower substrate transport mechanism;
A second upper substrate that is arranged on a vertical line between the shelf unit and the second processing shelf unit, and is formed so that a substrate can be delivered to the shelf unit and the second processing shelf unit, respectively. A transport mechanism and a second lower substrate transport mechanism;
A substrate processing apparatus comprising: The substrate processing apparatus according to claim 5 ,
The first upper substrate transport mechanism, the first lower substrate transport mechanism, the second upper substrate transport mechanism, and the second lower substrate transport mechanism share the transport process back and forth, and the substrate after coating is formed. In order from the first mounting unit, the first buffer unit, the peripheral exposure unit, the second buffer unit, the pre-exposure cleaning unit, the substrate cooling unit, and the exposure block are conveyed to the exposure block. A substrate processing apparatus, wherein the received substrate is formed so as to be conveyed to the post-exposure cleaning unit and the second mounting unit. In the substrate processing apparatus according to claim 5 or 6 ,
The first upper substrate transport mechanism transports the coated substrate sequentially from the first placement unit to the first buffer unit, the peripheral exposure unit, and the second buffer unit. The substrate received from the second buffer unit by the lower substrate transfer mechanism is transferred to the pre-exposure cleaning unit and the substrate cooling unit, and the substrate received from the substrate cooling unit by the second lower substrate transfer mechanism. The substrate is transported to the exposure block, and the second upper substrate transport mechanism is configured to transport the substrate received from the exposure block to the post-exposure cleaning unit and the second placement unit. A substrate processing apparatus.

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