JP5588393B2 - Synchronous rectifier converter and its test system - Google Patents

Description

  The present invention relates to a synchronous rectifier converter using a synchronous rectifier, a test system thereof, and a test method thereof.

  As a method for testing the operation of the overvoltage protection circuit of the power supply device, there is a method in which a volume for generating a variable voltage is mounted and the output voltage of the power supply device is self-raised and tested. In this method, voltage adjustment using an internal volume is necessary, but manual adjustment is generally not appropriate for automatic testing.

  Further, as an operation test method for the overvoltage protection circuit of the power supply device, there is a method of applying an external voltage to the output terminal of the power supply device for testing (see, for example, Patent Document 1). In this method, the voltage applied to the output terminal of the power supply device can be controlled by a computer, and an automatic test can be performed.

  By the way, many synchronous rectifiers are used for commutation elements of AC-DC converters and DC-DC converters. When a synchronous rectifying element is used for the commutation element, the conversion efficiency of the power source can be increased as compared with the case where a diode is used. Generally, an FET is used as the synchronous rectifier element.

Japanese Patent Application Laid-Open No. 5-126887

  Since the FET has a property of flowing a current in both directions, when a high voltage is applied from the outside to the output terminal of the power supply device, a current flows through the FET that is a synchronous rectifier, and the current from the external power supply flows backward. When the current flows backward, the output voltage of the power supply device does not increase, and the operation test of the overvoltage protection circuit becomes difficult.

  The present invention has been made in view of such a situation, and an object of the present invention is to realize an operation test of an overvoltage protection circuit of a power supply device using a synchronous rectifying element by a method of applying an external voltage from an output terminal. To provide technology.

  In order to solve the above problems, a synchronous rectification converter according to an aspect of the present invention includes a transformer that isolates input and output, a switching element connected to a secondary side of the transformer, an LC filter connected to the switching element, A synchronous rectifying element connected to a node between the switching element and the LC filter, an overvoltage protection circuit for detecting an overvoltage by monitoring an output voltage of the synchronous rectifying converter, and for stopping the operation of the synchronous rectifying element A synchronous rectification stop circuit. For example, an FET may be used as the synchronous rectifier element. In that case, the synchronous rectification stop circuit supplies a signal for turning off the FET.

  According to this aspect, the operation test of the overvoltage protection circuit of the synchronous rectification converter can be performed by a method of applying an external voltage from the output terminal of the synchronous rectification converter.

  The synchronous rectification stop circuit includes a first diode that rectifies the input voltage on the secondary side of the transformer, an RC filter that smoothes the voltage rectified by the first diode, a detection circuit that detects an output voltage of the RC filter, May be included. The detection circuit may decrease the gate voltage of the FET according to the decrease in the output voltage.

  The synchronous rectification stop circuit may include a test terminal connected to the gate terminal of the commutation FET. A ground potential may be applied to the test terminal when an overvoltage test is performed by applying a test voltage to the output terminal of the synchronous rectification converter.

  Another aspect of the present invention is a test system for a synchronous rectifier converter. This synchronous rectifier converter test system includes the above-described synchronous rectifier converter, an external power supply device that applies a test voltage to the output terminal of the synchronous rectifier converter, and an overvoltage test device that tests the operation of the overvoltage protection circuit. .

  Yet another embodiment of the present invention is a method for testing a synchronous rectifier converter. In this method, when an overvoltage test is performed by applying a test voltage to the output terminal of the synchronous rectification converter, the operation of the synchronous rectification element is stopped.

  According to the present invention, an operation test of an overvoltage protection circuit of a power supply device using a synchronous rectifying element can be realized by a method of applying an external voltage from an output terminal.

It is a figure which shows the structure of the test system of the synchronous rectification type converter based on a comparative example. It is a figure which shows the structure of the test system of a synchronous rectification type | mold converter based on embodiment of this invention. 1 is a diagram illustrating a configuration of a test system for a synchronous rectification converter according to Embodiment 1. FIG. It is a figure which shows the timing chart for demonstrating operation | movement of the test system of a synchronous rectification type converter based on Example 1. FIG. It is a figure which shows the structure of the test system of the synchronous rectification type converter based on Example 2. FIG.

  FIG. 1 is a diagram illustrating a configuration of a test system 500 for a synchronous rectification converter according to a comparative example. The test system 500 includes a DC-DC converter 100, an external power supply device 200, and an overvoltage test device 300. A DC-DC converter 100 shown in FIG. 1 is a step-down DC-DC converter, and steps down and outputs DC power input from a DC power supply. When an AC power supply is used, a rectifier circuit including a diode bridge circuit or the like is inserted between the AC power supply and the DC-DC converter 100. In this case, the entire circuit including the rectifier circuit is an AC-DC converter.

  A DC-DC converter 100 shown in FIG. 1 is an isolated, full-bridge, and synchronous rectification type converter. The DC-DC converter 100 includes an H bridge circuit, a transformer T1, a first resistor R1, a second resistor R2, a first FET Q1, a second FET Q2, an LC filter, a third resistor R3, a fourth resistor R4, a comparator CP1, and an error amplifying unit 12. And a PWM control unit 11.

  The H bridge circuit includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The high potential side terminals of the first switch S1 and the second switch S2 are connected to a positive input terminal. The low potential side terminals of the third switch S3 and the fourth switch S4 are connected to the negative input terminal. The low potential side terminal of the first switch S1 and the high potential side terminal of the third switch S3 are connected, and the node is connected to one terminal of the primary winding of the transformer T1. The low potential side terminal of the second switch S2 and the high potential side terminal of the fourth switch S4 are connected, and the node is connected to the other terminal of the primary winding of the transformer T1.

  On / off of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 is controlled by the PWM control unit 11. When the PWM control unit 11 controls the first switch S1 and the fourth switch S4 to be on and the second switch S2 and the third switch S3 to be off, a forward current flows through the primary winding of the transformer T1. On the other hand, when the PWM controller 11 controls the first switch S1 and the fourth switch S4 to be turned off and the second switch S2 and the third switch S3 to be turned on, a reverse current flows through the primary winding of the transformer T1. The amount of current flowing through the primary winding of the transformer T1 is determined by the duty ratio controlled by the PWM control unit 11.

  The transformer T1 insulates the input / output (that is, the primary side and the secondary side). A current according to the turn ratio between the primary winding and the secondary winding and the current flowing through the primary winding flows through the secondary winding of the transformer T1. In the configuration shown in FIG. 1, a positive input terminal and a negative input terminal on the secondary side are taken out from two nodes on the secondary winding. Two nodes of the secondary winding are provided at points where voltage is divided at a predetermined voltage dividing ratio.

  The first FET Q1 is connected to the secondary side of the transformer T1. More specifically, an n-channel MOSFET or a power MOSFET is employed for the first FET Q1, the source terminal of the first FET Q1 is connected to the positive input terminal on the secondary side, and the gate terminal thereof is connected via the first resistor R1. It is connected to one end of the secondary winding of the transformer T1, and its drain terminal is connected to the LC filter. The first FET Q1 functions as a switching element that steps down the input voltage on the secondary side.

  The LC filter is connected to the first FET Q1. The LC filter includes an inductor L1 and a first capacitor C1. One end of the inductor L1 is connected to the drain terminal of the first FET Q1, and the other end is connected to the positive output terminal of the DC-DC converter 100. The first capacitor C1 is provided after the inductor L1, and is connected between the positive output terminal and the negative output terminal of the DC-DC converter 100. The LC filter smoothes the output voltage of the DC-DC converter 100.

  The second FET Q2 is connected to a node between the first FET Q1 and the LC filter. More specifically, the second FET Q2 employs an n-channel MOSFET or power MOSFET, the source terminal of the second FET Q2 is connected to the negative input terminal on the secondary side, and the gate terminal thereof is connected via the second resistor R2. The other end of the secondary winding of the transformer T1 is connected, and its drain terminal is connected to a node between the first FET Q1 and the LC filter.

  The second FET Q2 is a synchronous rectification type commutation element. The second FET Q2 is turned on when the first FET Q1 is off. When the second FET Q2 is turned on, the energy stored in the inductor L1 is commutated to the output terminal. Note that the conversion loss of the power supply can be reduced by using an FET instead of a diode as the commutation element.

  The output voltage of the DC-DC converter 100 is input to the error amplifier 12. The error amplifier 12 compares the output voltage with the target voltage, amplifies the error, and outputs the amplified error to the PWM controller 11. When the output voltage is lower than the target voltage, the PWM control unit 11 increases the duty ratio so as to increase the amount of current flowing through the primary winding of the transformer T1. On the other hand, when the output voltage is higher than the target voltage, control is performed so that the amount of current flowing through the primary winding of the transformer T1 is reduced by decreasing the duty ratio. With this feedback control, the output voltage of the DC-DC converter 100 can be stabilized.

  The output voltage of the DC-DC converter 100 is divided by the third resistor R3 and the fourth resistor R4 and is also input to the comparator CP1. The comparator CP1 outputs a significant signal (for example, a high level signal) when the divided voltage exceeds the reference voltage Vref. The comparator CP1 functions as an overvoltage protection circuit. Although not shown, when the DC-DC converter 100 is actually used, when the comparator CP1 detects an overvoltage, the voltage application to the primary winding of the transformer T1 is stopped. Further, an alarm may sound when the comparator CP1 detects an overvoltage.

  When the DC-DC converter 100 is actually used, a load is connected to the output terminal of the DC-DC converter 100, but the external power supply device 200 is connected during the test. The external power supply apparatus 200 applies a test voltage to the output terminal of the DC-DC converter 100. This voltage gradually increases according to the control of the overvoltage test apparatus 300.

  The overvoltage test apparatus 300 is connected to the output terminal of the comparator CP1, and detects the timing at which the output of the comparator CP1 is inverted. The overvoltage test apparatus 300 detects the voltage applied to the output terminal of the DC-DC converter 100 by the external power supply apparatus 200 at this timing. The overvoltage test apparatus 300 can be composed of, for example, a PC and a voltage detection apparatus.

  However, in the test system 500 according to the comparative example, when the voltage applied from the external power supply apparatus 200 to the output terminal of the DC-DC converter 100 is increased, the ON period of the first FET Q1 is shortened, and the ON period of the second FET Q2 is increased. become longer. As a result, the current flows backward through the inductor L1 and the second FET Q2, and the voltage at the output terminal of the DC-DC converter 100 does not rise.

  FIG. 2 is a diagram showing a configuration of a synchronous rectification converter test system 500 according to an embodiment of the present invention. The configuration shown in FIG. 2 is a configuration in which a synchronous rectification stop circuit 20 is added compared to the configuration shown in FIG. The synchronous rectification stop circuit 20 is a circuit for stopping the operation of the synchronous rectification element. In the present embodiment, since the second FET Q2 is used as the synchronous rectification element, the synchronous rectification stop circuit 20 is a circuit that supplies a signal for turning off the second FET Q2. Hereinafter, a specific configuration example of the synchronous rectification stop circuit 20 will be described.

  FIG. 3 is a diagram illustrating a configuration of a test system 500 for a synchronous rectification converter according to the first embodiment. In the first embodiment, the synchronous rectification stop circuit 20 includes a first diode D1, a second diode D2, an RC filter, and a detection circuit M1.

  The anode terminal of the first diode D1 is connected to the positive input terminal on the secondary side, and its cathode terminal is connected to the RC filter. The first diode D1 rectifies the input voltage on the secondary side of the transformer T1. The RC filter includes a fifth resistor R5 and a second capacitor C2. One end of the fifth resistor R5 is connected to the cathode terminal of the first diode D1, and the other end is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the ground. The RC filter smoothes the voltage rectified by the first diode D1.

  The detection circuit M1 is connected to a node between the fifth resistor R5 and the second capacitor C2. The anode terminal of the second diode D2 is connected to a node between the gate terminal of the second FET Q2 and the second resistor R2, and the cathode terminal thereof is connected to the detection circuit M1. The detection circuit M1 detects the output voltage of the RC filter, and reduces the gate voltage of the second FET Q2 in accordance with the decrease in the output voltage. That is, in accordance with the decrease in the output voltage, the voltage at the cathode terminal of the second diode D2 is decreased to draw the current from the gate terminal of the second FET Q2, thereby decreasing the voltage at the gate terminal.

  The detection circuit M1 can be composed of, for example, a comparator and a switch. The switch is inserted between the cathode terminal of the second diode D2 and the ground. The comparator turns on the switch when the output voltage of the RC filter exceeds the reference voltage. As a result, the second diode D2 becomes conductive, the voltage at the gate terminal of the second FET Q2 becomes zero, and the second FET Q2 is turned off.

  FIG. 4 is a timing chart for explaining the operation of the synchronous rectification converter test system 500 according to the first embodiment. When an external voltage is applied from the external power supply device 200 to the output terminal of the DC-DC converter 100, the ON width Ton of the pulse waveform applied to the transformer T1 by the PWM control is narrowed. Accordingly, the ON width Ton of the pulse waveform on the anode side of the second diode D2 connected to the input terminal on the secondary side of the transformer T1 is also narrowed.

  The voltage at the cathode terminal of the first diode D1 is smoothed by an RC filter and converted to a DC voltage. This DC voltage decreases as the ON width Ton decreases. The detection circuit M1 detects the drop in the DC voltage, and pulls the cathode terminal of the second diode D2 to the ground, thereby stopping the operation of the second FET Q2 that is a synchronous rectifier. As a result, the external voltage applied to the output terminal of the DC-DC converter 100 increases without causing a current to flow back through the second FET Q2, and the overvoltage protection circuit can be accurately tested.

  FIG. 5 is a diagram illustrating a configuration of a test system 500 for a synchronous rectification converter according to the second embodiment. In the second embodiment, the synchronous rectification stop circuit 20 includes a second diode D2 and a test terminal. The test terminal is connected to the gate terminal of the second FET Q2 via the second diode D2. More specifically, the anode terminal of the second diode D2 is connected to a node between the gate terminal of the second FET Q2 and the second resistor R2, and its cathode terminal is connected to the test terminal. A ground potential is applied to the test terminal when an overvoltage test is performed by applying a test voltage to the output terminal of the DC-DC converter 100. In the example illustrated in FIG. 5, an example in which the ground potential is applied from the external power supply device 200 is illustrated, but the ground potential may be applied from other than the external power supply device 200. Thereby, operation | movement of 2nd FETQ2 which is a synchronous rectification element can be stopped. Therefore, the external voltage applied to the output terminal of the DC-DC converter 100 rises without causing the current to flow back through the second FET Q2, and the overvoltage protection circuit can be accurately tested.

  As described above, according to the present embodiment, by providing the synchronous rectification stop circuit 20 for stopping the operation of the synchronous rectifier element, an operation test of the overvoltage protection circuit of the power supply device using the synchronous rectifier element is output. The method can be implemented accurately by applying an external voltage from the terminal. Since it is not necessary to manually adjust the voltage by connecting the volume to the input of the error amplifying unit 12, the operation test of the overvoltage protection circuit can be easily executed by an automatic testing machine.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the above-described embodiment, the example in which the full bridge method is adopted as the DC-DC converter 100 has been described. In this respect, a half-bridge method or a push-pull method may be employed. Moreover, you may employ | adopt a forward system and a flyback system. Further, the example using the self-driven first FET Q1 and the second FET Q2 has been described, but the first FET Q1 and the second FET Q2 may be driven by the PWM control unit 11.

  100 DC-DC converter, 11 PWM control unit, 12 error amplification unit, S1 first switch, S2 second switch, S3 third switch, S4 fourth switch, T1 transformer, R1 first resistor, R2 second resistor, Q1 1st FET, Q2 2nd FET, L1 inductor, C1 1st capacitor, R3 3rd resistor, R4 4th resistor, CP1 comparator, 20 Synchronous rectification stop circuit, D1 1st diode, D2 2nd diode, R5 5th resistor, C2 2nd capacity | capacitance, M1 detection circuit, D3 3rd diode, 200 External power supply device, 300 Overvoltage test device, 500 Test system.

Claims (2)

A transformer that isolates the input and output;
A switching element connected to the secondary side of the transformer;
An LC filter connected to the switching element;
An FET connected to a node between the switching element and the LC filter;
An overvoltage protection circuit that detects the overvoltage by monitoring the output voltage of the synchronous rectification type converter;
A synchronous rectification stop circuit for supplying a signal for turning off the FET ,
The synchronous rectification stop circuit is
A first diode for rectifying the input voltage on the secondary side of the transformer;
An RC filter for smoothing the voltage rectified by the first diode;
A detection circuit for detecting an output voltage of the RC filter,
The synchronous rectification type converter , wherein the detection circuit reduces the gate voltage of the FET in response to a decrease in the output voltage . A synchronous rectifier converter according to claim 1 ;
An external power supply for applying a test voltage to the output terminal of the synchronous rectifier converter;
An overvoltage test device for testing the operation of the overvoltage protection circuit;
A test system for a synchronous rectifier converter, comprising:

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