JP5586650B2 - Semiconductor device having drift region and drift control region - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a power semiconductor device having a low on-resistance.

  One important objective in the development of power semiconductor devices is to produce devices that have as high a breakdown voltage characteristic as possible, yet have a low on-resistance and at the same time have the lowest possible switching loss. is there.

  One possibility of reducing the on-resistance of a power semiconductor element having a predetermined withstand voltage characteristic is to use a compensation principle as described in Patent Document 1, Patent Document 2, Patent Document 3, or Patent Document 4, for example. It is.

  One further possibility to reduce the on-resistance of the semiconductor element is to provide a field electrode that is directly insulated from the drift region. This type of element is described in Patent Document 5, Patent Document 6, Patent Document 7, Patent Document 8, or Patent Document 9.

  Patent Document 10 discloses a lateral power MOSFET having a plurality of auxiliary electrodes. The auxiliary electrode is disposed in the drift region of the element, and is insulated from the drift region by a dielectric. The auxiliary electrode is made of semi-insulating polysilicon (SIPOS) or a resistance material, and is connected between the source terminal and the drain terminal of the element. The auxiliary electrode forms a depletion zone (depletion layer) in the drift region when the device is driven to the off state.

  Patent Document 11 discloses a power MOSFET having a resistance layer, and the resistance layer extends along a drift region between the gate electrode and the drain electrode to increase the dielectric strength. “Expand” the electric field in the area.

  Patent Document 12 discloses a lateral high frequency transistor having a drift region extending in the horizontal direction of a semiconductor substrate.

  Patent Document 13 proposes to provide a plurality of field electrodes that are at different potentials along the drift path of the semiconductor element.

US Pat. No. 4,754,310 (Koh) US Pat. No. 5,216,275 (Chen) US Pat. No. 5,438,215 German Patent No. 4,309,764 (Chihoney) US Pat. No. 4,903,189 (Ngo) US Pat. No. 4,941,026 (Temple) US Pat. No. 6,555,873 (Disney) US Pat. No. 6,717,230 (Kohkon) US Pat. No. 6,853,033 (Lian) European Patent Publication No. 1073123 (Yasuhara) British Patent Publication No. 2089118 US Pat. No. 5,844,272 (Sedabeg) US Patent Application Publication No. 2003/0073287 (Kokon)

  An object of the present invention is to provide a semiconductor device, particularly a power semiconductor device, having a drift path / drift region having a low on-resistance.

  The semiconductor element according to the present invention has a drift region and a drift control region made of a semiconductor material in a semiconductor substrate. The drift control region is at least partially disposed adjacent to the drift region. A storage dielectric is disposed between the drift region and the drift control region. In the present semiconductor element, the drift control region functions to control a conductive channel in the drift region along the storage dielectric.

  The present invention will be described in more detail below with reference to the drawings.

The present invention is implemented as a planar MOSFET, and includes a plurality of MOSFET cells and a semiconductor substrate having a plurality of drift control regions arranged in the drift region, the drift region and each drift control region FIG. 2 is a cross-sectional view of a part of a semiconductor element in which a dielectric is disposed. FIG. 3 is a cross-sectional view showing a part of a planar MOSFET having a plurality of drift control regions in which the dielectric extends between two opposing side surfaces of the semiconductor substrate in a vertical direction. It is sectional drawing which shows a part of planar type | mold MOSFET which each said drift control area | region has extended to the source side surface of the said semiconductor base material. Compensation regions adjacent to each of the substrate regions are provided, and intermediate regions doped in a complementary manner to the respective substrate regions are disposed between the compensation regions. FIG. 4 is a cross-sectional view showing a part of a MOSFET according to the present invention in which each drift control region is arranged on the drain side. FIG. 5 is a cross-sectional view showing the MOSFET based on FIG. 4 and showing that a dielectric surrounding each drift control region extends to each intermediate region. A plurality of compensation regions are provided together with a plurality of drift control regions, the plurality of drift control regions are spaced apart from each other in the horizontal direction, and the region below each compensation region is more than the other regions of the semiconductor substrate. FIG. 5 is a cross-sectional view showing a part of a MOSFET having a smaller interval. It is sectional drawing which shows a part of MOSFET which has many each drift control area | regions spaced apart equidistantly in the horizontal direction. 1 shows a part of a semiconductor device according to the invention, implemented as a trench MOSFET, having a plurality of gate electrodes arranged in a plurality of trenches of the semiconductor substrate and having a drift control region arranged under the gate electrodes It is sectional drawing which shows having. FIG. 9 shows a part of the trench MOSFET of FIG. 8, in which each drift control region and the dielectric disposed between each drift control region and the drift region are between the gate electrode and the drift region. It is sectional drawing which shows being spaced apart from the gate insulator arrange | positioned in FIG. A part of the trench MOSFET having each of a plurality of drift control regions is shown, and each of the drift control regions is disposed in a horizontal direction between the gate electrodes, and each of the drift control regions and each of the drifts is arranged. It is sectional drawing which shows that the dielectric material arrange | positioned between a control area | region and the said drift area | region is extended between the mutually opposing surfaces of the said semiconductor base material in the orthogonal | vertical direction. FIG. 9 shows a part of the vertical MOSFET based on FIG. 8, wherein the dielectric disposed between the drift region and the drift control region is air, or two portions where a material having a low dielectric constant is disposed. It is sectional drawing which shows having a layer. 1 shows a portion of a MOSFET having a drift control region, the drift control region being a junction type with a heavily n-type doped connection region adjacent to the drift control region by the source side and the drain side. It is sectional drawing which forms a field effect transistor and shows that this drift control area | region is connected to the said source region via the 1st diode. It is sectional drawing which shows an example of the electron distribution profile of MOSFET by which it is electrically conductive by a prior art. FIG. 13 is a cross-sectional view showing an example of an electron distribution profile of a conducting MOSFET of the present invention based on FIG. 13 is a graph comparing the drain-source current profile of a MOSFET according to the prior art and the drain-source current profile of a MOSFET according to the invention according to FIG. 12 as a function of the drain-source voltage UDS. FIG. 13 shows a portion of the MOSFET of the present invention according to FIG. 12, wherein each drift control region is lightly p-type doped following a heavily p-type doped connection region via a first diode on the source side. FIG. 6 is a cross-sectional view showing that each connection region is connected to each source region by a connection region and connected to each drain region by a p-type doped connection region. FIG. 16 shows a MOSFET according to FIG. 16, in which each source region and each drift control region are connected via a capacitor, and each drift control region and each gate electrode are mutually connected via a second diode. It is a schematic sectional drawing which shows having been connected. FIG. 17B is a schematic cross-sectional view showing a MOSFET as a modification of the MOSFET of FIG. 17A, wherein the drift control region is at least partially coupled to a drain electrode via a tunnel dielectric. FIG. 16 shows a MOSFET based on FIGS. 16 and 17, wherein the MOSFET is connected to the first diode of FIG. 16 and is connected to the second diode and capacitor of FIG. 17A. It is a schematic sectional drawing which shows that the area | region is connected to the drain area | region by the 3rd diode in the drain side. 16 to 18 shows a MOSFET having a circuit configuration based on FIGS. 16 to 18, wherein the drain side diode of FIG. 15 is incorporated in the semiconductor substrate, and the drain region extends below the drift control region. It is a schematic sectional drawing shown. In order to reduce the on-resistance, a semiconductor region implemented as a MOS transistor is shown, and an intermediate region doped at a higher concentration than the drift region is disposed between the drift region and the substrate region. It is a schematic sectional drawing which shows that it exists. FIG. 21 is a schematic cross-sectional view showing an element modified with respect to FIG. 20 and showing that a field electrode is arranged adjacent to the intermediate region doped at a higher concentration. It is sectional drawing which cut | disconnected the element shown to FIG. 20 and FIG. 21 by the cross section II. FIG. 22 is a cross-sectional view showing a modification of the element shown in FIGS. 20 and 21 in a first cross section. FIG. 22 is a cross-sectional view showing a modification of the element shown in FIGS. 20 and 21 in a second cross section (FIG. 23B). FIG. 24 is a cross-sectional view showing a modification of the element shown in FIG. 23. FIG. 25 is a sectional view of the device according to FIG. 24 taken along section III-III ′. It is sectional drawing which shows the semiconductor element implement | achieved as a MOS transistor and the gate electrode is arrange | positioned above a drift control area | region in the perpendicular direction. FIG. 27 is a cross-sectional view showing a modification of the element shown in FIG. 26, wherein the drift control region partially extends to the surface of the semiconductor substrate. It is sectional drawing which shows the semiconductor element which is implement | achieved as a MOS transistor and has a base material area | region adjacent to the said base material area | region and located in a deeper part. It is sectional drawing which shows the MOS transistor which has a Schottky diode between a drain electrode and a drift control area | region. FIG. 30 is a schematic cross-sectional view showing a possible method for realizing the Schottky diode of the device according to FIG. 29; FIG. 30 is a cross-sectional view showing a first modification of the device according to FIG. 29; FIG. 30 is a cross-sectional view showing a second modification of the device according to FIG. 29. FIG. 33 is a schematic cross-sectional view showing a possible manufacturing method of the semiconductor element shown in FIGS. 29 to 32. A semiconductor device realized as a MOS transistor and having a semiconductor region that is complementarily doped with respect to the drain region, and a cross-sectional view showing that the drain electrode of the device is in contact with the semiconductor region. is there. FIG. 34 is a sectional view showing a modification of the element shown in FIG. 34 and showing that a field stop region is arranged between the drift region and the tree device element region doped in a complementary manner to the drift region. It is. FIG. 36 is a cross-sectional view showing a modification of the element shown in FIGS. 34 and 35. FIG. 36 is a cross-sectional view showing another modification of the element shown in FIGS. 34 and 35. FIG. 36 is a cross-sectional view showing still another modification of the element shown in FIGS. 34 and 35. FIG. 36 is a cross-sectional view showing still another modification of the element shown in FIGS. 34 and 35. FIG. 36 is a cross-sectional view showing still another modification of the element shown in FIGS. 34 and 35. FIG. 5 is a cross-sectional view showing a semiconductor element realized as a MOS transistor and having a drift region doped in a complementary manner to the drain region. FIG. 42 is a cross-sectional view showing a modification of the element shown in FIG. 41 and showing that the gate electrode is arranged vertically above the drift control region. FIG. 43 is a cross-sectional view showing a modification of the element shown in FIG. 42. 1 is a schematic cross-sectional view showing a semiconductor device realized as a MOS transistor, in which a tunnel dielectric and a portion of a drift region are disposed between a drift control region and a drain region of the semiconductor device. FIG. 45 is a cross-sectional view showing an element realized as a planar MOS transistor, which is a modification of the element of FIG. 44. FIG. 46 is a cross-sectional view showing a modification of FIG. 45, in which the drift region includes a semiconductor region doped with each other in a complementary manner. FIG. 47 is a cross-sectional view showing a semiconductor element as a modification of the element of FIG. 46. FIG. 48 is a cross-sectional view showing one method step for manufacturing the semiconductor device shown in FIGS. 44 to 47. It is sectional drawing which shows the other method step for manufacturing the said semiconductor element. FIG. 6 is a cross-sectional view showing still another method step for manufacturing the semiconductor device. FIG. 6 is a cross-sectional view showing still another method step for manufacturing the semiconductor device. A semiconductor device realized as a MOS transistor and having a capacitance between the source electrode and the drift control region, the capacitance being incorporated between two conductive layers above the semiconductor substrate. It is sectional drawing shown. It is other sectional drawing of the said semiconductor element. It is a perspective view which shows one possible structure for implement | achieving an electrostatic capacitance in a semiconductor base material. It is a top view which shows the said 1 structure. It is a top view which shows other possible structure for implement | achieving the said electrostatic capacitance. It is a schematic sectional drawing which shows other possible structure for implement | achieving the said electrostatic capacitance. It is sectional drawing which shows other possible structure for implement | achieving the said electrostatic capacitance. It is other sectional drawing which shows the said further another structure. It is sectional drawing which shows other possible structure for implement | achieving the said electrostatic capacitance. It is sectional drawing which shows other possible structure for implement | achieving the said electrostatic capacitance. It is sectional drawing which shows other possible structure for implement | achieving the said electrostatic capacitance. It is a perspective view which shows the semiconductor element implement | achieved as a vertical MOS transistor by which a drain electrode is connected to the drift control area | region in the edge part of a semiconductor base material. FIG. 58 is a perspective view showing a semiconductor element of a modification of the semiconductor element according to FIG. 57. FIG. 58 is a perspective view showing another modification of the semiconductor element of the semiconductor element according to FIG. 57. FIG. 58 is a perspective view showing a semiconductor element of still another modification example of the semiconductor element according to FIG. 57. FIG. 58 is a perspective view showing a semiconductor element of still another modification example of the semiconductor element according to FIG. 57. FIG. 58 is a perspective view showing a semiconductor element of still another modification example of the semiconductor element according to FIG. 57. FIG. 58 is a perspective view showing a semiconductor element of still another modification example of the semiconductor element according to FIG. 57. A MOSFET having a plurality of drift control regions, each drift control region being connected to the drain region via a built-in diode on the drain side, the drift control region extending vertically into the drain region FIG. FIG. 65 is a cross-sectional view showing a MOSFET corresponding to the MOSFET according to FIG. 64, wherein the drift control region is vertically separated from the heavily doped connection region. FIG. 66 is a cross-sectional view of a MOSFET according to the present invention corresponding to the MOSFET according to FIG. 65 and having a strip layout in the plane E-E ′ shown in FIG. 65 extending in a direction perpendicular to the vertical direction. FIG. 3 is a cross-sectional view of a MOSFET according to the present invention having a rectangular cell arrangement in a direction perpendicular to the vertical direction. FIG. 3 is a cross-sectional view in a horizontal direction perpendicular to the vertical direction of a MOSFET according to the present invention having a cell arrangement with a circular cross section. FIG. 4 is a cross-sectional view in the horizontal direction perpendicular to the vertical direction of a MOSFET according to the present invention having a drift region bent and extending in cross section. It is sectional drawing which shows the semiconductor element implement | achieved as a normally-on type MOS transistor. It is sectional drawing which shows the semiconductor element by which the measurement transistor for measuring a load current via this load transistor is arrange | positioned in the cell array of a load transistor. It is sectional drawing which shows the semiconductor element by which the temperature sensor is arrange | positioned in the cell array of a load transistor. FIG. 73 is a perspective view showing a semiconductor element of a modification of the semiconductor element according to FIG. 72. It is sectional drawing which shows the possible edge termination | terminus of the semiconductor element by this invention. It is sectional drawing which shows one modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. It is sectional drawing which shows the other modification of the said edge termination | terminus. A semiconductor which is implemented as a Schottky diode and in which a plurality of the drift control regions are formed in a single crystal and are electrically insulated from the heavily doped connection region of the diode region on the cathode side It is sectional drawing which shows an element. FIG. 87 is a graph showing a diode current profile of the Schottky diode according to FIG. 86 as a line; It is a graph which shows the graph by FIG. 87 logarithmically. FIG. 87 is a cross-sectional view showing the electron distribution of the Schottky diode according to FIG. 86 in the on state. FIG. 6 is a cross-sectional view showing a Schottky diode having a drift control region connected to a cathode electrode of the Schottky diode through a first connection region doped lightly and complementarily to the drift control region. . FIG. 91 is a cross-sectional view based on FIG. 90 showing a Schottky diode in which the first connection region is formed of an intrinsic semiconductor rather than a doped semiconductor material. FIG. 6 is a cross-sectional view showing a Schottky diode having a drift control region that is directly connected to the heavily doped connection region via an intrinsic first connection region. FIG. 5 is a cross-sectional view showing a Schottky diode having at least one drift control region extending to the heavily doped connection region and in contact with the heavily doped connection region. FIG. 6 is a cross-sectional view showing a Schottky diode having a drift control region connected to the heavily doped connection region through a high resistivity resistor layer. FIG. 4 is a cross-sectional view showing a Schottky diode including a drift control region partially insulated from the cathode electrode of the Schottky diode on the cathode side. Based on FIG. 86, the drift control region is a cross-sectional view showing a Schottky diode connected to the anode metal of the Schottky contact of the Schottky diode by a connection layer doped with a low concentration of p-type. FIG. 5 is a cross-sectional view showing a Schottky diode in which the drift control region is connected to the heavily doped connection region through a part of a connection electrode. FIG. 5 is a cross-sectional view showing a Schottky diode connected via a tunnel dielectric to a connection electrode in which the drift control region is in contact with the heavily doped connection region. FIG. 99 is a cross-sectional view of a Schottky diode implemented as a “fused” pin Schottky diode, as a variation of the Schottky diode of FIG. 98. FIG. 99 is a sectional view showing another modification of the Schottky diode of FIG. 98 and showing a Schottky diode in which a single crystal semiconductor layer is arranged between the tunnel dielectric and the connection electrode. FIG. 3 is a cross-sectional view of a semiconductor device implemented as a MOSFET, the drift control region being directly adjacent to the gate electrode on one side and coupled to the drain region via a diode on the other side. FIG. 101 is a cross-sectional view showing a variation of the device of FIG. 101 in which the diode is implemented as a built-in diode. It is sectional drawing which shows the element of the other modification with respect to the element of FIG. FIG. 110 is a cross-sectional view showing an element of a modification of the element of FIG. 102 in which the drift control region is connected to the gate electrode via a contact electrode. FIG. 105 is a cross-sectional view showing an element in which the gate electrode and the drift control region are insulated from each other and the drift control region can be connected to a control potential, which is a modification of the element of FIG. 104. . FIG. 4 is a cross-sectional view illustrating one method step of a method of manufacturing a semiconductor device implemented as a MOSFET, wherein the drift control region is directly adjacent to the gate electrode during individual method steps. It is sectional drawing which shows the other method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. FIG. 6 is a cross-sectional view illustrating one method step of a method of manufacturing another semiconductor device, implemented as a MOSFET, wherein the drift control region is directly adjacent to the gate electrode during individual method steps. It is sectional drawing which shows the other method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. FIG. 5 is a cross-sectional view illustrating one method step of a method of manufacturing yet another semiconductor device, implemented as a MOSFET, wherein the drift control region is directly adjacent to the gate electrode during individual method steps. It is sectional drawing which shows the other method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. FIG. 5 is a cross-sectional view showing a semiconductor device implemented as a MOSFET, including a drift control region directly adjacent to the gate electrode and a multi-layered storage dielectric. FIG. 110 is a cross-sectional view showing an element having a multi-layered storage dielectric as a variation of the element of FIG. 109. A lateral power semiconductor device according to the present invention, implemented as a MOSFET and having a plurality of drift control regions each insulated from a drift region by a storage dielectric, in a semiconductor substrate on which the device is integrated and in a semiconductor substrate It is a top view shown based on various sectional views accumulated on material. It is one sectional drawing of the said horizontal power semiconductor element. It is other sectional drawing of the said horizontal power semiconductor element. It is one perspective view of the said horizontal power semiconductor element. FIG. 2 is a plan view showing a power semiconductor device implemented as a MOSFET and having a drift control region partially separated from the drift region by a tunnel dielectric. It is a perspective sectional view showing a lateral power MOSFET having a drift region and a drift control region based on an SOI substrate. FIG. 6 is a cross-sectional view showing a lateral power semiconductor device implemented as a MOSFET, in which each of the plurality of drift control regions is longer than the entire length of the drift region adjacent to each other and extends in the horizontal direction. FIG. 114B is a cross-sectional view taken along line CC of FIG. 114A showing the horizontal power semiconductor element. It is arrow sectional drawing of the DD line | wire of FIG. 114A which shows the said horizontal power semiconductor element. It is a perspective view which shows the said horizontal power semiconductor element. FIG. 115 is a cross-sectional view showing an element in which a drift control region of the modification according to FIG. 114 is partially disposed adjacent to the base region of the power MOSFET. 114 is a perspective view showing an element in which the gate electrode is realized as a continuous strip-type electrode according to another modification of the element according to FIG. 114. FIG. FIG. 115 is a perspective view showing an element realized based on an SOI substrate according to still another modification example of the element shown in FIG. 114. Schematic showing a part of an element realized as a power MOSFET, wherein the drift control region is coupled to a drain electrode via a first diode and to a source electrode via an incorporated second diode. It is sectional drawing. It is a schematic perspective view which shows a part of element implement | achieved as said power MOSFET. FIG. 4 is a schematic cross-sectional view showing a part of a power MOSFET in which the drift control region is directly coupled to the drain electrode and is coupled to the source electrode via a diode. It is a schematic sectional drawing which shows a part of power MOSFET in which the electrostatic capacitance and the built-in diode are connected between the said drift control area | region and the said source electrode. FIG. 121 is a schematic cross-sectional view showing a modification of the element of FIG. 120 having an external diode. FIG. 121 is a schematic cross-sectional view showing an element in which a further diode is connected between the drift control region and the gate electrode according to another modification of the element of FIG. 120. It is a perspective view which shows a part of semiconductor element which has a drift area | region and a drift control area | region where the electrostatic capacitance is integrated in the area | region of a semiconductor base material. FIG. 124 is a cross-sectional view showing a semiconductor device of a modification of the device according to FIG. 123. FIG. 124 is another cross-sectional view showing a semiconductor element of a modification of the element according to FIG. FIG. 24 is still another cross-sectional view showing a semiconductor device of a modification of the device according to FIG. FIG. 3 is a cross-sectional view showing a lateral power semiconductor device realized as a MOSFET in which a gate electrode is disposed in one trench and an inversion channel controlled by the gate electrode extends in a vertical direction. It is other sectional drawing which shows the said horizontal type power semiconductor element by the EE arrow of FIG. 127A. It is other sectional drawing which shows the said horizontal power semiconductor element by the FF arrow of FIG. 127A. FIG. 128 is a cross-sectional view showing a power MOSFET in which an inversion channel controlled by the gate electrode extends in the horizontal direction as a modification of the MOSFET of FIG. 127. It is other sectional drawing which shows the said power MOSFET by the EE arrow of FIG. 128A. It is other sectional drawing which shows the said power MOSFET by the FF arrow of FIG. 128A. FIG. 6 is a cross-sectional view showing a lateral power MOSFET in which a plurality of gate electrode portions are respectively arranged in the horizontal direction within an extension of a drift control region. FIG. 129 is another cross-sectional view showing the lateral power MOSFET as viewed in the direction of arrows G-G in FIG. 129A. It is other sectional drawing which shows the said horizontal power MOSFET by the HH arrow of FIG. 129A. 1 is a perspective view showing a first exemplary embodiment of a lateral power MOSFET based on an SOI substrate, in which the base region of the power MOSFET is connected to a semiconductor substrate. FIG. FIG. 6 is a perspective view showing a second exemplary embodiment of a lateral power MOSFET based on an SOI substrate, in which the base region of the power MOSFET is connected to a semiconductor substrate. FIG. 6 is a cross-sectional view showing one method step of a possible manufacturing method of a drift control region separated from a drift region by a storage dielectric. It is sectional drawing which shows the other method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is sectional drawing which shows another method step of the said manufacturing method. It is a perspective view which shows the horizontal type power semiconductor element implement | achieved as a Schottky diode. FIG. 4 is a cross-sectional view of a lateral power MOSFET having a drift control region extending in parallel to the surface of a semiconductor substrate and a gate electrode disposed above the surface from different angles. FIG. 134B is another cross-sectional view taken along the line JJ of FIG. 134A in the lateral power MOSFET. FIG. 134B is still another cross-sectional view taken along the line KK of FIG. 134A in the lateral power MOSFET. FIG. 35B is still another cross-sectional view taken along line LL in FIGS. 134B and 134C in the lateral power MOSFET. FIG. 10 is still another cross-sectional view of the lateral power MOSFET. FIG. 135 is a cross-sectional view of an element in which the gate electrode is arranged in one trench, which is a modification of the element in FIG. 134. FIG. 135B is another cross-sectional view of the element taken along line MM in FIG. 135A. FIG. 139 is still another cross-sectional view of the element, taken along line NN in FIG. 135A. FIG. 136 is a cross-sectional view illustrating an element including a plurality of gate electrode portions in which the gate electrode is disposed in an extension part of the drift control region, according to a modification example of the element in FIG. 135. FIG. 136B is another cross-sectional view of the element taken along line OO in FIG. 136A. FIG. 36B is still another cross-sectional view taken along the line PP of FIG. 136A in the element. FIG. 36B is still another cross-sectional view of the element taken along line QQ in FIGS. 136B and 136C. It is sectional drawing which shows one method step of several each method step of the formation method of the connection contact which contacts a some embedded semiconductor region. It is sectional drawing which shows the other method step of each said several method step. It is sectional drawing which shows the further another method step among said each method step of said some. It is sectional drawing which shows the further another method step among said each method step of said some. It is sectional drawing which shows the further another method step among said each method step of said some. It is sectional drawing which shows the further another method step among said each method step of said some. It is a perspective view showing a part of drift region of a power semiconductor element which has a plurality of strip type drift control fields arranged in a power semiconductor element. It is a perspective view which shows further a part of drift region of the power semiconductor element which has several strip type drift control area | regions arrange | positioned in a power semiconductor element. FIG. 139 is a perspective view showing another arrangement as a modification to the arrangement of FIG. 138. 138 is a perspective view showing still another arrangement as another modification to the arrangement shown in FIG. 138. FIG. It is a perspective view which shows a part of drift control area | region of the power semiconductor element which has several strip type drift area | regions arrange | positioned in a power semiconductor element. It is a perspective view which shows a part of drift region of the power semiconductor element which has the some beam type drift control area | region arrange | positioned in a power semiconductor element. It is a perspective view which shows a part of drift region of the power semiconductor element which has a some beam type drift control area | region arrange | positioned in a power semiconductor element. It is a perspective view which shows a part of drift control area | region of the power semiconductor element which has another several beam type drift area | region arrange | positioned in a power semiconductor element. It is a perspective view which shows a part of drift control area | region of the power semiconductor element which has another several beam type drift area | region arrange | positioned in a power semiconductor element. It is a perspective view which shows a part of drift region of the power semiconductor element which is arrange | positioned in a power semiconductor element and has one drift control area | region which has the bent outer periphery. It is a perspective view which shows a part of drift area | region of the other power semiconductor element which is arrange | positioned in a power semiconductor element and has one drift control area | region which has the bent outer periphery.

  In the drawings, unless otherwise indicated, the same reference numerals indicate the same element regions and have the same meaning.

  In an element according to the invention, in one embodiment, the drift region and the drift control region are arranged at least partially next to each other in the semiconductor substrate and separated from each other by a dielectric layer. This region of the dielectric layer that separates the drift region and the drift control region is referred to as an “accumulating dielectric” in the following specification.

  The term “drift region” or “drift path” in the case of a power semiconductor device refers to a semiconductor region in which the reverse voltage is reduced when a reverse voltage is applied to the device, ie, as the reverse voltage increases, It refers to the region where the space charge region extends. The terms “drift region” and “drift path” are also used in particular in unipolar power semiconductor elements such as power MOSFETs or power Schottky diodes, but the terms “n-type base” or “p-type base” Typically, it is used for bipolar parts corresponding to the doping type of the semiconductor region that accepts the reverse voltage. In the following description, the term “drift region” or “drift path” is used in the region for receiving the reverse voltage of the power semiconductor element, without limiting the present invention to unipolar parts.

  The doping of the drift control region is selected, for example, such that the drift control region has at least one semiconductor portion that can be fully depleted in a direction perpendicular to the storage dielectric. This is the same as dopant atoms present in the semiconductor portion can be fully ionized without causing avalanche breakdown when an electric field is present in a direction perpendicular to the storage dielectric. When the device is driven on, the drift control region has a locally significantly increased charge carrier concentration to control the storage channel, that is, in the drift region along the storage dielectric. Serves to control the area. In order to form the channel, a potential difference is required between the drift control region and the drift region. In this case, the type of charge carrier, that is, whether it is an electron or a hole that accumulates along the storage dielectric, is determined by the polarity of the potential difference and can be an undoped region or intrinsic It is not determined by the basic doping of the drift region that can be realized as a region.

  Due to the presence of such a storage channel, the on-resistance of the power semiconductor element is significantly reduced as compared with an element that does not include such a drift control region. With the same on-resistance, the basic doping of the drift region of the device according to the invention can be reduced compared to the basic doping of the drift region of the conventional device, so that the device of the invention It has a higher dielectric strength than that of the element.

  The drift region is capacitively coupled to the drift control region via the storage dielectric so that the storage channel can be formed when the device is driven to an on state. When the device is in an off state, that is, when a space charge region spreads in the drift region, by satisfying the above-specified doping conditions for the drift control region, the drift charge region The effect that the space charge region is expanded also in the control region occurs. The space charge region spreading in the drift control region has the effect that the potential profile in the drift control region follows the potential profile in the drift region. The potential difference or the voltage between the drift region and the drift control region is limited thereby. This voltage limitation allows the use of a thin storage dielectric that effectively produces improved capacitive coupling between the drift control region and the drift region.

  Adjacent to the drift region, an element junction, such as a pn junction or a Schottky junction, can be provided. When a reverse voltage is applied between the drift region and the first element region, the space charge region extends from the junction into the drift region.

  The semiconductor element according to the invention is in particular a unipolar power semiconductor element, for example a power MOSFET or a power Schottky diode. However, in the case of bipolar components such as diodes or IGBTs, drifts consisting of doped or undoped semiconductor material, insulated from the drift region by the storage dielectric and satisfying the doping conditions specified above. It is also possible to provide a control area.

  In the case of a MOSFET, IGBT, or diode, the junction of the element between the first element region and the second element region is a pn junction. The first element region forms a base material region in the case of a MOSFET or IGBT, and forms one of a p-type emitter region and an n-type emitter region in the case of a diode. The second element region forms the drain region in the case of a MOSFET, and forms the emitter region in the case of an IGBT or a diode.

  In the case of a Schottky diode, the junction of the element between the first element region and the drift region is a Schottky contact, and the first element region is made of a Schottky metal. In the case of a Schottky diode, the first element region is an anode region of the Schottky diode and is made of a Schottky metal.

  FIG. 1 is a cross-sectional view illustrating a portion of an exemplary embodiment of a power semiconductor device according to the present invention. The illustrated element is realized as a planar MOSFET and includes a drift region 2, a source region 9, and a base material region 8. The substrate region 8 is disposed between the source region 9 and the drift region 2 and is doped in a complementary manner to the source region 9.

  In order to control the inversion channel in the substrate region 8 between the source region 9 and the drift region 2, a gate electrode 15 is provided, which is dielectrically separated from the semiconductor substrate by a gate dielectric 16. Is electrically insulated. In the illustrated embodiment, the gate electrode is disposed above the surface 101 of the semiconductor substrate 100 and partially reaches the surface 101 from the source region 9 in the horizontal direction r of the semiconductor substrate 100. It extends to the drift region 2. The element further includes a drain region 5 which is adjacent to the drift region 2 and is doped at a higher concentration than the drift region, and the drain region is in contact with the drain electrode 11.

  The drain region 5 of the illustrated device can be realized, for example, by a semiconductor substrate on which an epitaxial layer having basic doping is deposited. In this specification, the drift region 2 is formed by the cross section of the epitaxial layer having the basic doping. Note that in FIG. 1, the scale (ratio) of the actual dimensions of the semiconductor substrate and the epitaxial layer is not reproduced.

  The illustrated MOSFET is n-type conductive, in which case the source region 9, drift region 2 and drain region 5 are n-type doped while the substrate region is p-type doped. . The present invention is naturally applicable to a p-type conductive MOSFET, and the element region of the p-type conductive MOSFET is complementarily doped with respect to the element region of the n-type conductive MOSFET.

  The MOSFET shown in FIG. 1 is realized as a vertical MOSFET. The source region 9, the substrate region 8, the drift region 2, and the drain region 5 of this element are continuously arranged in the vertical (thickness) direction v of the semiconductor substrate 100. When the element is driven in an on state, that is, when a positive voltage is applied between the drain and the source and a suitable driving potential is applied to the gate electrode 15, the current flows between the source and the drain. Flows vertically through the drift region between them. In this element, the base material region 8 and the drain region 5 form a first element region and a second element region, and the drift region 2 is disposed between these element regions. When a reverse voltage is applied between the base material region 8 and the drain region 5, the space charge region spreads from the semiconductor junction between the base material region 8 and the drift region 2 in the drift region 2.

  In the element, at least one drift control region 3 is formed at least partially adjacent to the drift region 2. The element shown in FIG. 1 is provided with a plurality of drift control regions 3 as described above, which are arranged apart from each other in the horizontal direction r of the semiconductor substrate 1. Between each drift control region 3 and the drift region 2, a dielectric layer 4 called an “accumulation dielectric” is disposed. For the following explanation, here, the storage dielectric is directly disposed between the drift region 2 and the drift control region 3, that is, the drift region 2 is directly adjacent to one surface and the other surface is disposed to the other surface. Note that means only the part of the dielectric layer 4 to which the drift control region 3 is immediately adjacent.

  The drift control region 3 is coupled to any one of the load connection potentials of the MOSFET. The load connection potential is a potential present at the drain 5 and / or the source 9 during operation. In the present embodiment, the drift control region 3 is connected to the drain region 5 for this purpose. The drift control region 3 can be connected to the drain region 5 by various methods. In this regard, four different possibilities are illustrated in FIG. First, the drift control region 3 can be connected to the drain electrode 11 through the first heavily doped region 31 having the same conductivity type as the drift control region. In this case, the dielectric layer 4 extends to the drain electrode 11, thereby dielectrically insulating the first connection region 31 and the drain region 5 from each other.

  Depending on the situation, a second connection region 32 that is doped in a complementary manner to the first connection region is arranged between the first connection region 31 and the drain electrode 11 that are heavily doped. Here, the second connection region 32 is doped at a lower concentration than the first connection region 31.

  Further, the drain region 5 may extend to the lower part of the drift control region 3 or to the first connection region 31 adjacent to the drift control region 3. Again, there may be a complementary doped second connection region 32. The second connection region 32 is then disposed between the first connection region 31 and the portion of the drain region 5 that extends to the bottom of the drift control region 3.

  The element according to FIG. 1 is composed of cells and has a number of transistor cells of the same type. Each transistor cell has a source region 9 and a substrate region 8. Each transistor cell is connected in parallel because its source region 9 is connected to a common source electrode 13 and its gate electrode 15 is connected to a common gate connection (not shown). It is connected. In the illustrated device, the drift region 2 is common to all transistor cells. Depending on the realization of the drift control region 3, the drain region 5 may be realized as a continuous semiconductor region common to all transistor cells, or may have a plurality of separated semiconductor parts connected to each other by a drain electrode 11. May be.

  Each individual drift control region 3 is made of a semiconductor material which can be a single crystal. Each drift control region 3 is doped to have at least one semiconductor portion that can be fully depleted in a direction perpendicular to the storage dielectric 4. In the present specification, in particular, those portions of the storage dielectric 4 that extend along the direction of current flow, i.e. in this case, extend in the vertical direction v of the semiconductor substrate, are considered.

  The drift control region has at least one portion, and the at least one portion extends in a direction perpendicular to the current flow direction over the entire dimension of the drift control region, and in the direction It can be completely depleted by the electric field. This is because the dopant in this at least one portion of the drift control region is present when an electric field is present in the horizontal direction relative to the current flow direction (ie, in the illustrated embodiment, in the horizontal direction r of the semiconductor substrate 100). Can be fully ionized without causing avalanche breakdown.

  This condition is met because the net dopant charge in the semiconductor portion is used in the drift control region with respect to that portion of the storage dielectric 4 that dielectrically isolates the semiconductor portion from the drift region 2. This is the case when the dielectric breakdown charge of the semiconductor material to be obtained is lower.

  The drift control region 3 can be doped in particular so that it can be fully depleted as well as partially depleted in a direction perpendicular or horizontal to the current flow direction. is there. The index of the net dopant charge existing in the drift control region and the portion of the storage dielectric 4 extending between the drift region 2 and the drift control region 3 in the current flow direction is used for the drift control region 3. It becomes lower than the dielectric breakdown charge of the semiconductor material.

Any one of the drift control regions shown in FIG. 1 and delimited by the dielectric layer 4 along both sides to the upper end will be considered for the following description. Furthermore, a specific case where each drift control region 3 is uniformly doped is assumed for the following description. In this particular case, the doping condition identified above is the integral of the ionized dopant concentration of the drift control region 3 in the direction r perpendicular to the storage dielectric 4 and is the total “width” of the drift control region 3. In other words, it is considered that the value is smaller than twice the value of the dielectric breakdown charge of the semiconductor material in the drift control region 3. In silicon as a semiconductor material, the dielectric breakdown charge is about 1.2 × 10 ¹² e / cm ² (e indicates the amount of electric charge).

  If one considers the drift control region (not shown in detail) where the drift region separated from the drift control region by the dielectric layer is adjacent to only one side of the uniformly doped drift control region, The fact that the integral of the dopant concentration perpendicular to the dielectric layer is less than the breakdown charge applies to this drift control region. The drift control region as described above can be completely depleted by the electric field existing through the storage dielectric 4.

  The above doping conditions of the drift control region 3 depend on the potential already present in the drift region 2 in the drift control region 3 in the direction of the dielectric layer 4 when the drift control region is doped to a very low concentration. In other words, it is based on the fact that an electric field reaching the dielectric breakdown electric field strength of the semiconductor material in the drift control region 3 cannot be formed.

  The drift control region 3 can be made of the same semiconductor material as the drift region 2 and can have the same doping concentration as the drift region. In the horizontal direction relative to the current flow direction, that is, in the horizontal direction r of the present embodiment, the dimensions of the drift control region are selected such that the conditions already specified for the net dopant charge for the region of dielectric 4 are satisfied.

  It is effective to make the dielectric 4 extremely thin in order to achieve a good storage effect on the charge carriers in the drift region 2 along the storage dielectric, so that the electric field in the drift control region 3 is possible. It is possible to punch through the drift region 2 as well as possible. In this case, the minimum thickness of the dielectric 4 is determined by the potential difference existing between the drift control region 3 and the drift region 2 and the maximum allowable sustained field strength loading of the storage dielectric.

  For a typical sustained potential difference between the drift control region 3 and the drift region 2 that is clearly less than about 100V, and preferably between 5V and 20V, by using silicon dioxide from thermal oxidation as the dielectric, The minimum thickness of the body 4 will be a typical thickness of less than about 500 nm, preferably about 25 nm to about 150 nm.

  The storage dielectric 4 can completely separate the drift control region 3 from the drift region 2, and thus can form a completely closed portion between the drift control region 3 and the drift region 2. is there. In this case, in particular, it is possible to form a dielectric layer that forms the storage dielectric 4 as a so-called tunnel dielectric. This is shown in one of the drift control regions 3 of FIG. 1, and the dielectric on the drift control region 3 is formed as a tunnel dielectric 4 '. This tunnel dielectric will be further described below.

  In the current flow direction, that is, the vertical direction v in the present embodiment, the drift control region 3 is the same as the area of the drift region 2 disposed adjacent to the drift control region 3 in the horizontal direction with respect to the current flow direction. It preferably has doping characteristics. The section extends in the current flow direction (vertical direction v) through the same region as the drift control region 3.

  In the embodiment according to FIG. 1, the drift control region 3 conforms to a grid of cell arrays arranged in the region of the surface 101. Here, each drift control region 3 is arranged between two adjacent substrate regions 8 in the horizontal direction of the semiconductor substrate 1. However, it is not always necessary to adapt to the grid of the cell array. It is therefore possible in particular to select another grid for the drift control region 3 rather than the cell array. That is, in particular, the drift control region 3 can be arranged below the base material region 8 (not shown).

  FIG. 2 is a cross-sectional view showing a further exemplary embodiment of a device according to the invention, implemented as a MOSFET. The element differs from the element according to FIG. 1 in that the drift control region 3 extends to the surface 101 of the semiconductor substrate 1. In the present embodiment, the drift control region 3 is similarly covered with the dielectric layer 4 or the tunnel dielectric 4 ′ that forms the storage dielectric 4 in the surface region.

  FIG. 3 shows a further exemplary embodiment. In FIG. 3, the dielectric layer forming the storage dielectric 4 is adjacent to the drift control region 3 only in the horizontal direction. This is possible when a dielectric or insulator covering the drift control region is deposited on the surface of the semiconductor substrate 1 in the region of the drift control region 3. In the present embodiment, the drift control region 3 is covered by the gate dielectric 16. Accordingly, the drift control region 3 of each cell is electrically insulated from the gate electrode 15 and the source electrode 13 in the region on the surface of the semiconductor substrate 1 (the source side).

  In the device of FIGS. 2 and 3 in which the drift control region 3 extends to the surface of the semiconductor substrate, the drift control region 3 is selectively connected to the drift control region 3 in a complementary manner. It may be connected to the source electrode 13 via 35 and via the tunnel dielectric 4 '. This is shown in the drift control region 3 shown on the far right of FIG.

  In FIG. 4, the compensation region 7 can be provided in the drift region 2 of the MOSFET. The compensation region has the same conductivity type as the substrate regions 8 of the individual cells, but is doped to a lower concentration than these substrate regions. Each compensation region 7 is preferably in contact with one substrate region 8. In the illustrated embodiment, an intermediate region 21 that is more heavily doped than the other regions of the drift region 2 is further arranged in the drift region 2 between the adjacent substrate region 8 and the compensation region 7, The doping of the intermediate region is complementary to the compensation region 7.

  In the exemplary embodiment according to FIG. 4, each drift control region 3 is arranged between the intermediate region 21 and the drain electrode 11. In the present embodiment, the vertical end portion of the drift control region 3 surrounded by the dielectric 4 in the semiconductor substrate is located at a distance from the intermediate region 21.

  As shown in FIG. 5, the drift control region 3 having the dielectric 4 surrounding the drift control region 3 may extend until it contacts the intermediate region 21 or may extend into the intermediate region 21. In this case, the drift control region 3 can also extend to the surface of the semiconductor substrate (not shown).

  FIG. 6 shows a further exemplary embodiment of a MOSFET having a drift control region 3. Here, the plurality of drift control regions 3 coupled to the drain region are non-uniformly arranged in the horizontal direction in the semiconductor substrate 100. In this case, the interval between the plurality of adjacent drift control regions 3 is selected to be smaller than the other regions at a position corresponding to the region of the compensation region 7.

  As shown in FIG. 7, the drift control regions 3 can be separated from each other by an equal distance in the horizontal direction of the semiconductor substrate 100.

  Each exemplary embodiment according to FIGS. 1 to 7 shows a MOSFET having a planar gate electrode. Of course, the principle of the present invention of providing the drift control region 3 can also be used for a trench MOSFET having a vertical gate electrode 15 arranged in one trench. In this case, the drift control region 3 is made of a semiconductor material and insulated from the drift region 2 by a storage dielectric, and the net dopant charge of the drift control region with respect to the portion of the dielectric 4 is less than the dielectric breakdown charge. .

  FIG. 8 is a cross-sectional view showing such a trench MOSFET having a plurality of drift control regions 3. In the case of this element, a source region 9, a substrate region 8 that is complementarily doped with respect to the source region, a drift region 2, and a heavily n-type doped connection region or drain region 5 are provided as a source electrode. 13 to the drain electrode 11 are arranged directly and continuously with each other.

  The trench type MOSFET has a conductive gate electrode 15 made of, for example, a metal or a highly doped polycrystalline semiconductor material (for example, polysilicon). The gate electrode is electrically insulated from other regions of the semiconductor substrate 100 and from the source electrode 13 by a gate dielectric 16, for example a semiconductor oxide.

  The gate electrode 15 is disposed in each of a plurality of trenches extending into the drift region via the source region 9 and the base material region 8.

  The source electrode 13 shorts the source region 9 and the base material region 8 to remove the parasitic bipolar transistor formed by the source region 8, the base material region 9 and the drift region 2 by a known method. Preferably it is formed. For this purpose, in the present embodiment, the source electrode 13 has an electrode area 13 ′. As shown in the right-hand transistor cell of FIG. 8, the electrode section 13 ′ extends vertically through the source region 9 into the substrate region 8.

  As in the exemplary embodiment described above, the drift control region 3 is connected to the drain electrode 11 and thus to the drain region 5 by a first connection region 31 that is heavily n-doped.

  In this case, each drift control region 3 is directly disposed under the plurality of trenches having the gate electrode 15 and is insulated from the drift region 2 by the dielectric 4. In this case, the drift control region 3 having the dielectric 4 extends to a plurality of trenches having the gate electrode 15. However, as shown in FIG. 9, the drift control region 3 having the storage dielectric 4 may be terminated at a distance from a plurality of trenches having the gate electrode 15.

  In the exemplary embodiments according to FIGS. 8 and 9, each drift control region 3 is arranged between the gate electrode 15 and the drain electrode 11, but selectively or additionally adjacent to each other in the horizontal direction. It is also possible to provide further drift control regions which are arranged between the matching gate electrodes 15.

  In the latter case, as shown in FIG. 10, the storage dielectric 4 may extend from the drain side surface 102 of the semiconductor substrate 100 to the source side surface 101 of the semiconductor substrate 100.

  In the exemplary embodiment shown above, the drift control region 3 comprises a drain region 5 (more precisely through the drain electrode 11) and a source region 9 (more precisely through the source electrode 13). ) Are connected to both. In this case, the connection to the drain electrode 11 is made through the first connection region 31, but the connection to the source electrode 13 is made to the third connection region 33 doped with a low concentration and the high concentration. This is done via a p-type doped fourth connection region 34. In this case, the fourth connection region 34 is in contact with the source electrode 13 or is at least conductively connected to the source electrode 13.

  In FIG. 10, the drift control region 3 can extend over the same region as the drift region 2 in the vertical direction v. In this case, the third connection region 33 extends in the vertical direction v over the same region as the base material region 8, and the fourth connection region 34 extends over the same vertical region as the source region. The connection region 31 extends over the same vertical region as the drain region 5.

  In the embodiment according to FIG. 10, the drift control region 3 is connected to the drain electrode 11 and thus to the drain region 5 by a first connection region 31 that is heavily n-type doped. Here, the various possibilities described in connection with FIG. 1 for electrically connecting the drift control region 3 to the drain region 5 are the elements of FIG. 10, the elements of FIGS. It should be noted that the device according to FIG.

  As shown in any one of the transistor cells in the right hand part of FIG. 10, adjacent to the dielectric layer forming the storage dielectric 4 in the substrate region 9 and partly in the source region 8, It is possible to arrange a highly doped p-type doped semiconductor region 17.

  This region 17, hereinafter referred to as the bypass region, forms a very low resistivity bypass for the holes to the source electrode 13, and therefore, especially when the power semiconductor element operates in “avalanche” and “rectification”. Prevent the cell from latching early. This region 17 further prevents a channel that can be controlled by the drift control region 3 from existing between the source region 9 and the drift region 2. Further, the semiconductor region 17 connects the source electrode 13 to the base material region 8 with a low resistance. In addition, the semiconductor region 17 connects the source electrode 13 to the base material region 8 with a low resistance.

  FIG. 11 shows the possibility to reduce the susceptibility of the semiconductor substrate 1 to adverse effects on mechanical stresses that may result from forming the drift control region 3 with the storage dielectric 4 surrounding the drift control region 3. FIG. For this purpose, a dielectric 4 is formed from each dielectric partial layer 4a, 4b, and between these two dielectric partial layers, a gap 4c filled with a compressible medium such as a gas (eg air). Is present.

  In this case, each of the partial layers 4a and 4b of the dielectric 4 can have a shape leaning against each other on the source side, or can be integrally formed on the source side. Further, a net-like portion that can be made of the same material as the partial layers 4a and 4b may be provided between the partial layers 4a and 4b in order to stabilize the partial layers 4a and 4b.

  The MOSFET described based on the various embodiments is configured by applying a suitable driving potential to the gate electrode 15 and between the drain region 5 and the source region 9 or between the drain electrode 11 and the source electrode 13. In the meantime, it is driven to an on state by applying a positive voltage.

  In this case, the potential of the drift control region 3 follows the potential of the drain region 5, and when the drift control region 3 is connected to the drain region 5 via the pn junction (32 and 31 in FIG. 1), The potential of 3 can be lower than the potential of the drain region 5 by the value of the forward voltage of the pn junction. Due to the inevitable electrical resistance of the drift region 2, the potential of the drift region 2 decreases in the direction of the base material region 8.

  As a result, the drift control region 3 is at a higher potential than the drift region 2, and this potential difference increases as the distance from the drain region 5 toward the base material region 8 increases. The potential difference has an effect that a storage region is generated in the drift region 2 adjacent to the storage dielectric 4, and charge carriers (in this case, electrons) are stored in the storage region. Due to the accumulation region, the on-resistance of the element is reduced as compared with the conventional element.

  When a suitable driving potential does not exist in the gate electrode 15 and when a positive voltage exists between the drain and the source, the MOSFET is in an off state. Therefore, the pn junction between the drift region 2 and the substrate region 8 is reverse-biased, and a space charge region is formed in the drift region 2 from the pn junction to the drain region. In this case, the existing reverse voltage is reduced in the drift region 2. This means that the voltage applied to the drift region 2 corresponds to the existing reverse voltage.

  Even in the off state, a space charge region is formed in the vertical direction of the drift control region 3. The space charge region results from the voltage drop in the storage dielectric 4 being limited to a maximum value due to the low concentration doping of the drift control region 3. The storage dielectric 4 forms a capacitance together with the drift control region 3 and the drift region 2, and the following equation is applied to C ′ per unit length of the capacitance.

C ′ = ε ₀ ε _r / d _accu (1)
In this case, ε ₀ indicates the permittivity of the free space, and ε _r indicates the relative permittivity of the dielectric used. This relative dielectric constant is about 4 in the case of silicon dioxide (SiO ₂ ).

  The voltage across the dielectric depends on the charge stored in a known manner.

U = Q '/ C' (2)
Here, Q ′ refers to the charge accumulated for the dielectric portion.

In the off state, the voltage U present in the storage dielectric 4 is limited by the net dopant charge in the drift control region 3. If the net dopant charge in the drift control region 3 for the dielectric portion is less than the dielectric breakdown charge Q _Br , the following equation applies to the voltage U present in the dielectric 4:

U = (Q ′ / C ′) ≦ (Q _Br · d _accu / ε ₀ ε _r ) (3)
As a result, the maximum voltage present in the storage dielectric 4 increases linearly with the thickness d _accu of the storage dielectric 4, and thus increases to a first approximate value of approximately the same strength as its dielectric strength. . The maximum voltage loading of SiO ₂ with an ε _r of about 4 and a thickness of 100 nm is 6.8V, which is significantly less than the allowable continuous loading of such oxides (about 20V). In this case, the breakdown charge is about 1.2 × 10 ¹² / cm ² .

  Accordingly, a space charge region is formed in the drift control region 3 in the off state. The potential profile of the space charge region can differ from the potential profile of the drift region 2 by at most a voltage value that exists in the dielectric 4 and is limited by the low concentration doping of the drift control region 3. In this case, the voltage present in the storage dielectric 4 is usually lower than the breakdown voltage of the storage dielectric 4.

  For the sake of explanation, the drift control region 3 in the above-described element is shown as a region of the same conductivity type as the drift region 2. However, unlike this display, the drift control region 3 may be doped as a semiconductor region that is complementarily doped with respect to the drift region 2 or as an intrinsic semiconductor region.

  The semiconductor elements described above and below are n-type conductive elements, and the majority of charge carriers floating in the drift region 2 are electrons when the elements are driven to an on state. However, the principle of the present invention is not limited to an n-type conductive element, but can also be applied to a p-type conductive element. It is possible to dope complementary to the semiconductor region of the type conductive element.

  In the case of the element described with reference to FIGS. 1 to 9 and 11, the drift control region 3 is connected only to the drain region 5. When the element is in the off state, holes are accumulated in the drift control region 3, and these holes are generated as a result of the electron hole pair generated by heat and do not flow out. Over time, this amount of charge increases until it reaches the maximum allowable field strength of the storage dielectric 4 and destroys the dielectric 4.

  With respect to FIG. 1, such a dielectric breakdown can be avoided by the dielectric layer 4. The dielectric layer 4 partially forms a storage dielectric implemented as a tunnel dielectric 4 '. Even before the storage dielectric 4 reaches the breakdown field strength, as soon as the tunnel dielectric 4 ′ reaches the breakdown field strength, the tunnel dielectric has accumulated charge carriers in the drift region 2. Allows to flow.

Examples of suitable tunnel dielectrics may include layers composed of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or multilayered layers composed of silicon oxide and silicon nitride. A mixed dielectric made of silicon, oxygen, and nitrogen may be used. For example, typical tunneling field strengths are in the range of 1 V / nm to 2 V / nm. For tunnel oxide 4 'having a thickness of 13 nm, this results in a maximum voltage of 13V to 26V. This voltage is higher than the voltage present in the dielectric 4 during normal off-state operation and can be tolerated without problems by the dielectric 4 made of silicon oxide having a thickness of 100 nm.

  In the exemplary embodiment shown in FIG. 1, the tunnel dielectric is disposed at the upper end of the drift control region 3. A particularly effective point is that the accumulated holes facilitate the switching on of the device. This is because the hole facilitates the generation of an accumulation region in the drift region 2 until the difference between the potential of the drift region 2 and the drain region falls below the tunnel voltage value. The excess holes then flow out from the drift control region 3 toward the drain region 5 or the drain electrode 11.

  The tunnel dielectric 4 ′ disposed between the drift control region 3 and the source electrode 13 in FIG. 2 also functions to discharge leakage current generated by thermal charge carrier generation. The pn junction between the drift control region 3 and the complementary doped intermediate region 35 absorbs the reverse voltage that exists between the drift control region 3 and the source electrode. The tunnel dielectric may be adjacent to the source region 9 (not shown).

  FIG. 12 is a cross-sectional view illustrating a further exemplary embodiment of a device according to the present invention implemented as an n-type conductive trench MOSFET. One of the transistor cells of the same number of the above elements is shown in the side sectional view. The element has an element structure of a conventional vertical trench MOSFET 20 and includes a source region 9, a substrate region 8, a drift region 2, a drain region 5, and a gate electrode 15 disposed in the trench. Here, the source electrode 13 is in contact with the source region 9, and the drain electrode 11 is in contact with the drain region 5.

  In this case, the p-type doped substrate region 8 is connected to the source electrode 13 via a high concentration p-type doped bypass region 17, which provides a very low resistivity bypass, Formed in the hole to the source region 9, thus preventing the cell from latching prematurely, particularly when the power semiconductor device is “avalanche” and “rectifier” operation. This region 17 further prevents a channel that can be controlled by the drift control region 3 from existing between the source region 9 and the drift region 2.

  A drift control region 3 is disposed adjacent to the drift region 2, and the drift control region is connected to the drain electrode 11 on the back surface side by a first connection region 31 doped with high concentration n-type. In this element, the drift control region 3 extends in the vertical direction to almost the surface of the semiconductor substrate 1, and is therefore partially disposed adjacent to the substrate region 8. In the direction of the surface, the drift control region 3 is adjacent to a further connection region 133 that is heavily n-doped, and the fourth electrode 19 arranged on the semiconductor substrate 100 is in contact with the connection region. doing. In the present embodiment, the fourth electrode 19 is separated from the source electrode 13.

  The drift control region 3 together with the first connection region 31 and the further connection region 133 forms a junction field effect transistor (JFET), the gate of which shows the substrate region 8 or the bypass region 17. The junction field effect transistors 31, 3, 133 can be switched off by a sufficiently high negative potential of the substrate region 8. In a conventional n-type channel JFET, no dielectric is disposed between the p-type doped gate and the n-type doped channel region. However, the dielectric 4 shown here does not disturb the pinch-off effect.

The dopant concentration in the drift control region 3 can be very low, for example about 10 ¹⁴ cm ⁻³ . Therefore, the pinch-off of the junction field effect transistors 31, 3, 133 has already occurred when the voltage difference between the base material region 8 and the drift control region 3 is several volts.

  In the described element, the drift control region 3 is connected to the source region 9 or the source electrode 13 via the first diode 41. In this case, the anode 41a of the diode 41 is conductively connected to the source region 9 via the source electrode 13, and the cathode 41b is connected to the drift control region 3 or the junction type via the fourth electrode 19. The field effect transistors 31, 3, 133 are conductively connected. There is no need to impose strict requirements on the diode 41 with respect to the leakage current. Because, when the MOSFET is in the off state, the junction field effect transistors 31, 3, 133 are switched off, and it is impossible for current to flow therethrough, so the first diode 41 is high. Having leakage current is not important.

  The first diode 41 can be realized as an external element or can be incorporated into the semiconductor substrate, for example in a monolithic structure or as a polysilicon diode. Further, instead of the first diode 41, a high-resistance resistor or a transistor connected as a diode can be used.

  Note that FIG. 12 shows only a portion of all elements or only one cell. On the left-hand side, there is a further part of the dielectric 4, adjacent to the part, first following a further trench MOSFET structure (not shown). The illustrated MOSFET structure and the further MOSFET structure are formed mirror-symmetrically with respect to a symmetry plane extending in the vertical direction v and a plane perpendicular to the symmetry plane shown.

  The function of the illustrated element will be described below. If a positive operating voltage is present between the drain electrode 11 and the source electrode 13 and a suitable driving potential is present at the gate electrode 15, the element is in an on state. When the element is driven to the on state, the voltage drop between the drain and the source is lower than the reverse voltage of the diode 41, so that the diode 41 is in the off state and the potential of the drift control region 3 is This substantially corresponds to the potential of the drain.

  In the region of the MOSFET structure, the operating voltage drops to the voltage in the path of the drift region 2, whereby the potential in the path of the drift region 2 decreases as the distance from the drain region 5 increases, and the drift control region 3 and the drift region 2 increase by the same amount as the distance from the drain region 5 increases. Charge carriers (electrons in this embodiment) can be accumulated in the drift region 2 along the dielectric 4 by the positive potential of the drift control region 3 with respect to the potential of the drift region 2. This can reduce the on-resistance of the element.

  If the device is off by a gate electrode 15 driven by a suitable method, in the drift region 2 starting from the pn junction, the space charge region expands and the path voltage in the drift region 2 rises. In this case, first, the potential of the drain region 5 or the drain electrode 11 follows the potential of the drift control region 3 by the blocking diode 41. As the potential of the drift control region 3 rises, the junction FET formed by the drift control region 3, the dielectric 4, and the base material region 4 is gradually pinched off and completely turned off. In this region adjacent to the material region, a value different from the potential of the substrate region 8 by the reverse voltage value of the junction FET is maintained. In this case, the junction FET formed in the upper region of the drift control region protects the diode 41 from a voltage that is too high as the drain potential further increases. Here, the voltage for completely pinching off the junction FET is set to be lower than the breakdown voltage of the diode 41.

  As the drain potential further rises, the voltage drop in the drift control region 3 is reduced in the drift region 2 in the lower region, that is, in the region between the heavily doped connection region 31 and the substrate region 8. As the voltage rises in the drift control region 3, the space charge region further expands in the direction of the heavily doped connection region 31.

  In this case, the space charge region spreading in the drift control region 3 and the space charge region spreading in the drift region 2 are the maximum voltage existing in the storage dielectric 4 between the drift control region 3 and the drift region 2. Limit. If the doping of the drift region 2 and the doping of the drift control region 3 are the same, or if the doping characteristics in the current flow direction are the same, the voltage is approximately the turn-off voltage of the junction FET. Within range, usually a few volts, so that the storage dielectric 4 is not subject to high voltage loading and can be designed to be thin accordingly.

  The thin dielectric 4 also has an advantage with respect to accumulating charge carriers in the drift region 2 when the device is driven to the on state. In the constant potential difference between the drift control region 3 and the drift region 2, the thinner the dielectric 4 is, the better this accumulation operation is.

  The advantage of the arrangement according to FIG. 12 is that the current path between each connection electrode or drain electrode 11 and each source electrode 13 of the element exists via a diode 41, via which the drift control region 3 Since the current path charge carriers generated by the heat flow out, the above-described undesired charge carrier accumulation does not occur in the drift control region 3 or in the dielectric 4 in the off state.

  FIGS. 13 and 14 are diagrams comparing the electron distribution of the conventional MOSFET with the electron distribution of the MOSFET according to FIG. 12. In either case, the MOSFET is driven to the on state and the gate voltage is 10V. Both the drain voltage and the source voltage are similarly 10V. FIG. 13 is a diagram showing the electron distribution of the conventional MOSFET, and FIG. 14 is a diagram showing the electron distribution of the MOSFET of FIG.

Each numerical value shown in each of these figures specifies the electron concentration of electrons per cm ³ in each region.

  In this case, in the device of the present invention according to FIG. 14, the region having an electron concentration at least two orders of magnitude higher than the electron concentration of the drift region of the corresponding conventional device according to FIG. It can be seen that the drift region is formed over almost the entire length of the drift region. The high electron concentration is due to the potential of the drift control region. The drift control region is adjacent to the region of the drift region 2 where the electron concentration increases and the potential is higher than the potential of the drift region.

FIG. 15 is a graph showing the characteristic curves 58 and 59 showing the profile of the drain-source current I _DS of the MOSFET as a function of the drain-source voltage U _DS . The corresponding characteristic curve 58 of the MOSFET according to the invention according to FIG. 12 was compared with the characteristic curve 59 showing a MOSFET according to the prior art.

It is noted here that the cross-sectional view obtained for the current flow in the case of the MOSFET according to the present invention is significantly higher than the cross-sectional area of the MOSFET according to the prior art because of the space required for the drift control region. Despite being reduced, the load current I _DS of the MOSFET according to the invention is higher than the drain-source current I _DS of the MOSFET according to the prior art (4 times higher when the drain-source voltage is 4V, When the drain-source voltage is 10V, it is 7 times higher).

  FIG. 16 is a diagram showing a trench MOSFET, which includes the MOSFET according to FIG. 12, the third connection region 33 in which the drift control region 3 is p-doped to a low concentration, and the p-type to a high concentration. The difference is that it is connected to the fourth electrode 19 via a fourth doped region 34 that is type-doped. A two-stage configuration of p-type doped connection regions with a more heavily doped region 34 and a lightly doped region 33 can be optionally selected here. Here, the purpose of the more heavily doped region 34 is to substantially connect the connection electrode 19 to the drift control region 3 and the pn junction, and to the lighter p-type doped region 33. It is to make low resistance connection.

  The device functions in the on-state corresponding to the device described in connection with FIG. 12, and in the case of the device according to FIG. 16, between the drift control region 3 and the respective p-doped regions 33, 34. The pn junction formed between them can already raise the potential of the drift control region above the source potential, that is, higher than the potential of the source electrode 13.

  Further, the MOSFET is in an off state, and a voltage of several tens of volts or several hundreds of volts is present between the drain electrode 11 and the source electrode 13 or in the path of the drift region 2 of the MOSFET structure. It can be assumed that the source electrode 13 is at a reference potential, for example 0V.

  Thereafter, the potential at the fourth electrode 19 becomes higher than the reference potential by an approximate dielectric breakdown voltage value (for example, +15 V) of the first diode 41 at the maximum. The remainder of the reverse voltage, ie the difference between the drain potential and the potential of the fourth electrode 19, is substantially accepted by the lightly doped drift control region 3 and is lightly doped. In the drift control region, a space charge region is formed from a pn junction between the drift control region and each of the p-type doped regions 33 and 34.

  In this case, the space charge region extending in the drift region 2 and the space charge region extending in the drift control region 3 limit the voltage existing in the storage dielectric 4 in the off state. This is because neither the accumulation nor the inversion layer is formed on the storage dielectric 4 in the space charge region.

  The doping of the drift region 2 and the doping of the drift control region 3 are the same, the pn junction between the base region 8 and the drift region 2 in the current flow direction, and the p-type region 33 and the drift control region 3. If the pn junction between and is at the same level, this voltage corresponds to the reverse voltage of the diode 41 at the maximum. The diode 41 causes the p-type region 33 to be at a higher potential than the base material region in the off state.

  The doping of the drift region 2 and the doping of the drift control region 3 can be different, and the voltage loading of the storage dielectric can be greater than the individual doping of these two regions.

  In this case, in the case of the maximum allowable reverse voltage, no avalanche breakdown occurs in the drift control region 3, and in the drift control region 3, the space charge region spreads in the current flow direction. In order to prevent the electric field formed in the direction perpendicular to the flow direction from exceeding the breakdown electric field strength of the semiconductor material, doping of the drift control region 3 is performed by doping conditions in the drift region 2 and insulation of the storage dielectric 4. It is necessary to match the proof stress and the desired dielectric strength of the element.

  Each of the p-type doped semiconductor regions 33 and 34 disposed adjacent to the base region 8 and the heavily doped short circuit region 17 on the drift control region 3 are ( That is, when the potential of each of the regions 33 and 34 is higher than the potential of the base material region 8 by the dielectric breakdown voltage value of the diode 41), in the p-type doped region, the hole is a region of the dielectric 4 Accumulated within.

  Depending on the element in the off state, this part of the structure corresponds to the capacitance charged to the breakdown voltage of the diode. Hereinafter, the capacitance is referred to as storage capacitance. Note that in the case of this element, the diode 41 may optionally be provided. Since the diode 41 promotes charge accumulation in the drift control region 3 when the element is in the off state, it is only necessary to supply a smaller amount of charge even when driven in the on state.

  When the MOSFET switch is turned on, the region of the drift region 2 adjacent to the base material region 8 suddenly drops to a potential lower than the dielectric breakdown voltage of the first diode 41. As a result, holes are extracted from the upper region, that is, the region of the drift control region 3 adjacent to the fourth electrode 19, and move further down, that is, into the region in the direction of the drain electrode 11. These holes cause accumulation of electrons on the opposite side of the dielectric 4, that is, on the side surface of the drift region 2 facing the drift control region 3. Therefore, the electric charge moves from the storage capacitance to the “accumulation capacitance” located deeper.

  The first connection region 31 doped with n-type, together with the second connection region 32 doped with p-type, is connected to the drain region 5 or the drain connection portion 11 from the drift control region 3 while the hole is in the ON state. Is prevented from flowing out. The drift region 2 can be regarded as a control electrode for one hole channel on the side facing the drift region 2 of the heavily doped n-type connection region 31. In order to maintain the accumulation of holes required in the drift control region 3, the formation of the hole channel must be prevented.

  In order to increase the magnitude of the threshold voltage of the channel, the donor concentration in the heavily n-type doped connection region 31 is increased accordingly, or the thickness of the dielectric 2 is increased in the connection region It is preferred to increase locally to a level of 31 (not shown).

  In the present embodiment, it is sufficient that the donor concentration of the first connection region 31 is selected to be particularly high in the region directly adjacent to the dielectric 4 in the horizontal direction. This avoids the formation of hole channels. That is, lower doping may be selected in the remaining region of the connection region 31. In this case, the doping concentration of the connection region 31 does not increase in the vertical direction over the entire width of the connection region 31 in the region adjacent to the dielectric 4, but rather may increase only partially. .

  In the drift region 2, the hole charge for forming the electron accumulation channel on the side facing the drift control region 3 and reducing the loss of the on-state is mostly due to the connection regions 31 and 32 having the corresponding dimensions. Maintained. Only a relatively small portion is lost due to the leakage current of the first diode 41 and due to the subthreshold current flowing through the layer 31 along the dielectric 4.

  Electrons generated by heat can flow out of the drift control region 3 through the configuration having the first connection region 31 and the second connection region 32 during the OFF state.

  Therefore, in the case of the device according to FIG. 16, the holes required for the on-state device in the drift control region 3 are the lower n-doped “storage region” and the upper portion (opposite the drift region 2). Shifts only between the p-type doped "storage regions" 33, 34, so that only a charge shift is performed here, and the drain-source of the device is turned on each time the switch is turned on. There is no need to supply the holes from an electric current. Therefore, the switching loss of the element is minimized.

  The storage capacitance shown in FIG. 16 does not necessarily have to be part of the semiconductor substrate 100 completely. Therefore, in addition to the storage capacitance formed by the substrate region 8, the p-type doped regions 33, 34 and the dielectric, a further static is placed outside the semiconductor substrate. A capacitance may be present.

  A structure having such an additional capacitance 50 is shown in FIG. 17A. Here, the capacitance is schematically shown as a capacitor, and is hereinafter referred to as an external capacitance. The external capacitance can be realized in the semiconductor substrate or outside the semiconductor substrate by any desired method. This further capacitance 50 is connected between the source electrode 13 and the fourth electrode 34, and is therefore connected between the drift control region 3 and the source region 9.

  In the present embodiment, the connection regions 33 and 34 that are doped in a complementary manner with respect to the drift control region 3 are disposed between the drift control region 3 and the fourth connection electrode 19. Forms an internal storage capacitance. When the external capacitance 50 corresponding to the element according to FIG. 12 is present, each of the p-type doped connection regions 33 and 34 having the electric storage property is connected to the heavily doped n-type connection region 33 (FIG. 12). (Not shown). An advantage for each p-type doped connection region 33, 34 is that their leakage current characteristics are more suitable (less).

  In order to make the best use of the on-state loss of the device improved compared to the conventional device, the storage capacitance (even if it is the internal capacitance of FIG. 16 or FIG. The internal and external capacitance of 17A) must be reliably charged when the device is switched on, and the charge lost due to leakage current must then be supplied again.

  The necessity described above can be realized by providing the second diode 42 connected between the gate electrode 15 and the drift control region 3 with reference to FIG. 17A. In this case, the anode 42 a of the diode 42 is connected to the gate electrode 15, and the cathode 42 b is connected to the fourth electrode 19 that is a connection portion of the external capacitance on the side away from the source electrode 13. In order to maintain a sufficient amount of hole-shaped charges shifted in the drift control region 3 while the switch is on, the p-type doped region 34 above the drift control region is It is necessary to have a sufficiently high doping concentration.

  Accordingly, the external capacitance 50 and the second diode 42 may be provided also in the case of the element of FIG. These are indicated by broken lines in FIG.

  When the MOSFET switch is first turned on, the storage capacitance formed by the internal capacitance and / or the external capacitance in the case of the elements of FIGS. To the second diode 42 to be charged. However, the case where it is not already charged by the reverse current due to heat from the drift control region 3 is excluded. In the case where the MOSFET switch is in the ON state, the lost hole is supplied from the gate circuit immediately thereafter. While the storage capacitance and the storage capacitance are dynamically (dynamically) reversed in charge, in a stable state, no current flows from the external control connection, that is, the gate electrode 15, or extremely Only a little current flows.

  A pn junction is provided between the drift control region 3 and the drain electrode 11 so that the storage capacitance does not discharge toward the drain region 5 when the drain potential falls below the drift control region 3 potential. It may be provided. In the case of the device according to FIG. 17A, the pn junction is formed by the n-type doped first connection region 31 adjacent to the drift control region 3 and the lightly doped p-type doped adjacent to the drain electrode 11. 2 connection regions 32.

  In order for the above-described element to function properly, the diode formed by the first connection region 31 and the second connection region 32 needs to have a reverse voltage. The reverse voltage is higher than the maximum allowable gate voltage applied between the gate and source to drive the device to the on state.

  FIG. 17B is a cross-sectional view showing an element modified with respect to FIG. 17A. In the element, the drift control region 3 is connected to the drain electrode 11 via a first connection region 31 that is optionally heavily doped and a tunnel dielectric 4 '. The doping of the first connection region 31 may correspond to, for example, the equivalent of the doping of the drain region 5.

  In the on state, the tunnel dielectric 4 'prevents a plurality of holes accumulated in the drift control region 3 from flowing out toward the drain electrode 11, and in the off state. The tunnel dielectric allows leakage current generated by heat to flow out towards the drain electrode 11. In this case, the dielectric strength of the tunnel dielectric 4 'simply needs to be high enough that the tunnel dielectric can block the gate voltage.

  In the case of the device according to FIG. 17B, a single crystal semiconductor material is arranged on the tunnel dielectric 4 '. Such a device may be formed by growing the semiconductor material on the tunnel dielectric using an epitaxial method. In this case, the drain region 5 represents a substrate on which a tunnel oxide is deposited and an epitaxial layer is further grown thereon. In this case (unlike the element of FIG. 17B), the tunnel dielectric 4 'is arranged between the drift control region 3 and the heavily n-doped drain region 5 (not shown).

  FIG. 18 is a cross-sectional view showing another possibility that can prevent the (hole) storage capacitance from discharging in the direction of the drain region 5. Here, the drift control region 3 is connected to the second electrode 12 via a heavily doped connection region, and the second electrode is separated from the drain electrode 11. A third diode 43 is connected between each of these two electrodes 11 and 12. The third diode can be realized as an external element, the anode 43a of the third diode is connected to the drain electrode 11, and the cathode 43b of the third diode is the second element. It is connected to the electrode 12. The third diode 43 prevents the accumulated capacitance from being discharged toward the drain region 5. In this case, the cutoff capability (withstand voltage) of the third diode 43 needs to be higher than the maximum gate voltage for turning on the MOSFET switch, and lower than the potential difference that can pass through the storage dielectric 4. Also good.

  Initially, when the MOSFET is switched on, the drift control region 3 is charged from the gate circuit to a maximum gate voltage of, for example, 10V. When the MOSFET is switched off, this charge is shifted from the stored capacitance to the storage capacitance. In this case, the storage capacitance needs to be selected so as not to exceed the reverse voltage (for example, 15 V) of the second diode 42. The storage capacitance is preferably 2 to 3 times the storage capacitance between the drift control region 3 and the drift region 2, and the internal capacitance formed by the connection regions 33 and 34 and the bypass region 17. It may be the sum of the electric capacity or the sum of adding any external storage capacitance 50.

  Instead of providing the external storage capacitance 50 outside the element, such a capacitance may be incorporated in an element such as the semiconductor substrate 100, for example. In particular, the storage capacitance is bypassed by the dielectric 4 having a higher dielectric constant and / or by expanding the junction between the hole bypass region 17 and the dielectric 4 (not shown). It is possible to increase towards the region 17.

  In the case of the element according to FIG. 18, in principle, the first diode 41 may be omitted. However, it is possible that excess charge that may occur will flow out of the storage capacitance into the gate circuit. Such an extra charge is generated particularly when the storage capacitance is reversed by the leakage current from the drift control region 3 due to the leakage current from the drift control region 3 during a relatively long OFF state. This is a case where the battery is charged to a voltage.

  Unlike the above-mentioned figure, it is also possible to dope the drift control region 3 in a complementary manner to the drift region 2. That is, in the embodiment according to FIG. 18, it is possible to provide the p-type doped drift control region 3. When the element is turned off, when the space charge region expands in the drift control region 3 from the pn junction between the drift control region 3 and the connection region 31 toward the surface side of the semiconductor substrate 100. At the same time, the space charge region expands in the drift region 2 from the pn junction between the base material region 8 and the drift region 2 toward the back surface side.

  These space charge regions extending from different directions cause a voltage drop in the storage dielectric. Due to the voltage drop, the space charge region has the advantage that in the case of this device, it extends horizontally to the drift region 2 and the drift control region 3. In other words, this creates a compensation effect and allows the drift region 2 to have a higher basic doping concentration for the same dielectric strength.

The doping concentration of the drift region 2 and the doping concentration of the drift control region 3 of the same doping type as the drift region 2 are in a region of the order of 10 ¹⁴ cm ⁻³ , for example. 3 and the doping type are complementary (that is, opposite to each other), the doping concentrations of the drift region 2 and the drift control region 3 can be in the range of 10 ¹⁵ cm ⁻³ to 10 ¹⁶ cm ^−3. .

  FIG. 19 is a cross-sectional view showing yet another possibility for linking the drift control region 3 to the drain region 5. In this case, the drift control region 3 is connected to the drain region 5 not directly via the drain electrode 11 but via the connection regions 31 and 32 that are doped complementarily to each other. This is realized by the fact that the dielectric layer forming the storage dielectric 4 starts from a position spaced from the drain electrode 5 and the drain region 5 extends horizontally below the drift control region 3. Has been.

  In the case of a semiconductor device, in particular as in the case of a power semiconductor device, a plurality of individual cells (here, a plurality of MOSFET cells) are arranged in the same semiconductor substrate and connected in parallel to each other. Is possible. In the case of the element according to the present invention, each two adjacent cells of the element use a common drift control region 3 provided between them.

  In order to detect the voltage present between the load connections of the power semiconductor element, a capacitive voltage divider can be connected between the load connections of the power element to derive a voltage signal at the capacitive voltage divider. Are known. In this case, the value of the voltage signal depends on the existing load path voltage.

  In the power semiconductor device according to the present invention described based on the above embodiments, such a capacitive voltage divider is already connected in parallel to the load path (here, parallel to the drain-source path). In the case of this element, the first electrostatic capacitance is formed by the drift region 2 and the drift control region 3, and the drift region 2 and the drift control region 3 are separated from each other by the storage dielectric 4. .

  The capacitance is shown schematically in FIG. In this case, one connection portion of the capacitance is connected to the drain region 5. The capacitance connected to the source region 9 is the capacitance 50 shown as an external element in FIG. 19, or the connection region 34 that is highly doped, and the substrate region 8 is highly doped. The internal capacitance formed by the connected connection region 17 and the dielectric material in between.

  The center tap of the capacitive voltage divider formed by these two capacitances forms the connection electrode 19 of the drift control region 3. As a result, a signal related to the load path voltage of the power semiconductor element can be extracted directly at this connection 19 in the drift control region 3.

  In order to evaluate the value of the load path voltage, it is also possible to evaluate the absolute value of the potential at the connection portion 19. However, you may evaluate the dynamic behavior of the electric potential in this connection part 19. FIG. Here, the increase in the potential corresponds to the increase in the load path voltage, and the decrease in the potential corresponds to the decrease in the load path voltage.

  20 is a cross-sectional view showing a modification of the vertical power element shown in FIG. In the case of the element, an intermediate region 22 having the same conductivity type as that of the drift region 2 and being doped at a higher concentration than the drift region 2 exists between the base material region 8 and the drift region 2. . This intermediate region 22 extends from the gate dielectric 16 to the storage dielectric 4 in the horizontal direction r of the semiconductor substrate 100.

  The purpose of the intermediate region 22 is that the inversion channel formed in the substrate region 8 along the gate dielectric 16 and the drift region 2 along the storage dielectric 4 when the device is driven to the on state. Increase the lateral conductivity between the storage channel formed in the internal channel or the electrical resistance between the inversion channels arranged at a distance from the storage channel in the horizontal direction r of the semiconductor substrate. It is to reduce.

A path of charge carriers passing through the element between the source region 9 and the drain region 5 is indicated by a broken line in FIG. The doping concentration of the intermediate region 22 is, for example, in the range between 10 ¹⁵ cm ⁻³ and 10 ¹⁷ cm ^−3, and is therefore one to two orders higher than the doping concentration of the drift region 2.

  By providing the doping region of the drift region 2 at the same level and providing the intermediate region 22 that is more highly doped, the number of dopant atoms between the base region 8 and the drain region 5 is increased. Specifically, the dielectric strength of the element is reduced. In order to avoid such a decrease in dielectric strength, the doping concentration of the drift region 2 can be reduced when the intermediate region 22 doped with a higher concentration is provided.

  In order to avoid a reduction in the dielectric strength when providing a more heavily doped intermediate region 22, in FIG. 21, instead of or in addition to reducing the doping concentration of the drift region 2, the field An electrode 23 can be provided.

  The field electrode is disposed adjacent to the more heavily doped intermediate layer 22 and is dielectrically insulated from the intermediate region 22 and the drift region 2 by the dielectric layer 24. In the illustrated exemplary embodiment, the field electrode 23 is directly adjacent to the gate electrode 15 in the vertical direction v of the semiconductor substrate 100. The field electrode 23 is electrically connected to, for example, the source electrode 13 and thus the source potential of the semiconductor element.

  The purpose of the field electrode 23 is to form a space charge region from the pn junction between the substrate region 8 and the more highly doped intermediate region 22 when the semiconductor element is turned off. In some cases, at least a portion of the dopant charge present in the intermediate region 22 is compensated. Therefore, when the above elements have the same dielectric strength, the intermediate region 22 can be doped at a higher concentration than an element that does not include the field electrode 23.

  20 and FIG. 21, the drift control region 3 is connected to the drain region 5 through the connection regions 31 and 32 already described, and through the connection regions 33 and 34 also described above. And connected to the connection electrode 19. Of course, it should be noted that the drift control region may be connected to the drain region 5 and the connection electrode 19 in accordance with the description with reference to FIGS. 12, 17, and 18.

  22 is a cross-sectional view of the element shown in FIGS. 20 and 21 cut by a cross section taken along the line II in FIG. 20 and FIG. In the case of these elements, the gate electrode 15 extends substantially parallel to the drift control region 3 in the horizontal direction of the semiconductor substrate 100. In the case of these devices, the more heavily doped intermediate region 22 shown in FIGS. 20 and 21 is between the inversion channel along the gate electrode 15 and the storage channel along the storage dielectric 4. Increase the transverse conductivity of the.

  FIG. 23A is a cross-sectional view showing an element modified from the elements of FIGS. 20 and 21 in a cross section corresponding to the cross section taken along the line I-I. FIG. 23B shows a cross-sectional view of the device taken along the line II-II shown in FIG. 23A. In the element, each gate electrode 15 or each part of the gate electrode 15 and each part of each base material region or base material region 8 are alternately arranged between two drift control regions 3.

  The cross-sectional view of FIG. 23A shows a heavily doped connection region 17 and source region 9, where the substrate region 8 is here arranged below this connection region 17 and source region 9. The gate electrode 15 is insulated from the substrate region by a gate dielectric 16 and further insulated from the drift control region 3 by a dielectric layer. The gate dielectric 16, the storage dielectric 4, and the dielectric 25 that insulate the gate electrode 15 from the drift control region 3 may be formed of the same material or have the same dielectric characteristics. You may form from a material.

  23A and 23B, the region of the gate dielectric 16 where the inversion channel is formed in the substrate region 8 when the device is driven to an on state, and The region of the storage dielectric 4 in which the storage channel is formed in the drift region 2 extends in directions orthogonal to each other. In the case of this element, the inversion channel formed along the gate dielectric 16 in the upper region of the semiconductor substrate is horizontally aligned with the storage dielectric 4 in the lower region of the semiconductor substrate 100. It extends to the storage channel that is formed.

  In order to prevent the formation of a channel that cannot be switched off in the portion of the substrate region 8 adjacent to the storage dielectric 4, the source region 9 comprises a semiconductor substrate 100 as shown in FIG. 23A. Are arranged so as not to extend to the storage dielectric 4 in the horizontal direction.

  In order to prevent the formation of a channel that cannot be switched off if the source region 9 is intended to extend to the storage dielectric 4 in the horizontal direction of the semiconductor substrate for manufacturing technical reasons, There are various possibilities shown in FIG.

  One possibility is to make the storage dielectric 4 thicker than the rest of the region where the source region 9 extends to the storage dielectric 4. This is illustrated in FIG. 24 by providing an additional dielectric layer 44 directly adjacent to the storage dielectric 4.

  Alternatively, in the region where the dielectric constant of the storage dielectric 4 is such that the source region 9 extends to the storage dielectric 4, the storage channel drifts when the remaining region, particularly when the device is driven to the on state. It is also possible to realize the storage dielectric 4 so as to be lower than in the region formed along the storage dielectric 4 in the region 2.

  Alternatively, the channel stop region 26 may be provided along the storage dielectric 4 adjacent to the substrate region 8 in the vertical direction of the semiconductor substrate 100 between the source region 9 and the drift region 2. The channel stop region 26 is complementary to the source region 9 and is doped at a higher concentration than the base region 8, and extends along the storage dielectric 4 between the source region 9 and the drift region 2. It has a function of preventing the formation of the channel formed and controlled by the drift control region. 25 is a cross-sectional view of the channel stop region 26 taken along the line III-III shown in FIG.

  When the device is driven to the on state, the gate electrode 15 is moved so that the inversion channel formed along the gate dielectric 16 directly transitions into the storage channel formed along the storage dielectric 4. If arranged within the extension of the drift control region 3, the special means for increasing the transverse conductivity as described in connection with FIGS. 21-25 is omitted in FIGS. May be.

  In the case of the elements shown in FIGS. 26 and 27, the gate electrode 15 is disposed above the drift control region 3 in the vertical direction of the semiconductor substrate 100. In order to realize the gate dielectric 16 and the storage dielectric 4, it is possible to provide a common dielectric layer. The common dielectric layer forms a gate dielectric 16 in a region between the gate electrode 15 and the substrate region 8, and forms a storage dielectric 4 in a region between the drift control region 3 and the drift region. To do.

  In this case, the gate electrode 15 and the drift control region 3 are dielectrically isolated from each other by a dielectric, which corresponds to the gate dielectric 16 and / or the storage dielectric 4 in terms of its dielectric properties. May be. According to any one of the possibilities described in connection with FIGS. 12 and 17-19, the drift control region 3 can be coupled to the source electrode 13 or the gate electrode 15. Illustrations of electrical connections or components such as diodes or capacitances that are additionally required depending on the situation have been omitted in FIGS. 26 and 27 for clarity.

  In the case of the device according to FIG. 26, the gate electrode 15 partially covers the region of the drift control region 3 that does not partially reach the surface of the semiconductor substrate 100. Although not shown in detail, the device includes a plurality of areas in which the drift control region 3 extends to and contacts the surface of the semiconductor substrate 100. In a direction perpendicular to the plane of the figure shown, the plurality of areas are offset from this area of the drift control region 3 shown in FIG.

  In the case of the element according to FIG. 27, the gate electrode 15 is formed narrower in the direction perpendicular to the gate dielectric 16 than in the case of the semiconductor element of FIG. , And passes through the side of the gate electrode 15 and extends to the surface of the semiconductor substrate 100 while being insulated from the gate electrode 15 by the dielectric layer. In this region, the above-described intermediate layers or connection layers 33 and 34 can be provided. These are indicated by broken lines in FIG.

  In the case of the element described with reference to FIGS. 26 and 27, the gate electrode 15 is provided in the direct extension of the drift control region 3, and when the element is driven to the OFF state, The inversion channel and the accumulation channel are formed in the transition region between the gate electrode 15 and the drift control region 3 or when the device is driven to the on state when the spike of the electric field spreading in the drift region 2 is formed. It can occur in transition regions between regions.

  Such voltage spikes can cause voltage breakdown before reaching the breakdown voltage in this region of the device. In order to prevent such an unforeseen voltage breakdown, a semiconductor region 81 having the same conductivity type as that of the base region 8 can be provided adjacent to the base region 8 as shown in FIG. . Hereinafter, the semiconductor region 81 is referred to as a base material extension region or a base material extension portion.

  The base material extension region 81 extends to the height of the drift control region 3 in the vertical direction of the semiconductor base material 100, but does not extend to the storage dielectric 4 in the horizontal direction of the semiconductor base material 100. As a result, the substrate extension region does not affect the formation of the storage channel along the storage dielectric 4 when the semiconductor element is driven on, but in the off state the substrate The extension region blocks the region of the drift region 2 between the base material extension region 81 and the storage dielectric 4 from the electric field. This prevents electric field spikes from occurring in this region of the drift region 2 proximate to the storage dielectric 4.

  In the first configuration of the element shown in FIG. 28, the base material extension region is doped at a relatively low concentration. That is, for example, it is doped as much as the substrate region 8 or is soaped at a lower concentration. In this case, the base material extension region supplies a compensation charge for a complementary dopant charge at the upper end of the drift region 2, that is, in the region of the drift region 2 immediately adjacent to the base material extension region 81. When the element is driven to the OFF state, the voltage received in the transition region between the base material extension region 81 and the drift region 2 rises due to the small gradient of the electric field, whereby the electric field is increased. Spikes are avoided.

  In a further configuration, the substrate extension region 81 so that the off-state element locally generates a field strength spike in the region of the substrate extension region 81 to concentrate voltage breakdown in the substrate extension region. Is realized. Concentrating the voltage breakdown on the base material extension region is, for example, a drift region 2 having relatively strong ends as shown in the base material extension region 81 according to FIG. Between pn junctions.

  Furthermore, it is also possible to realize the base material extension region 81 so that the base material extension region 81 extends locally, particularly deeply into the drift region 2. Thereafter, voltage breakdown occurs in a region extending deeply into the drift region 2 of the semiconductor substrate 100. In FIG. 28, a path that extends particularly deep locally in the base material expansion region 81 is indicated by a broken line. In this case, the base material expansion region 81 is doped at a relatively high concentration. That is, for example, it is doped at a higher concentration than the base material region 8.

  The substrate extension region 81 described in connection with FIG. 28 is for an n-type conductive element having an n-type doped drift region 2 (as shown in FIG. 28) and a p-type doped drift region. Can be used in both cases of n-type conductive elements having This will be further described below in connection with FIGS.

  In the case of the power device described with reference to FIGS. 16, 17 and 19, the drain region 5 of the device is connected to the drift control region via a rectifying device (in this case a diode or tunnel dielectric). 3 is connected. 16, 17A and 19, the diode can be formed by a pn junction between two respective connection regions 31, 32, which are complementary to each other. And is arranged adjacent to the drift control region 3 continuously along the back surface direction of the semiconductor substrate 100.

  In FIG. 29, such a pn junction between the drain region 5 or the drain electrode 11 and the drift control region 3 may be replaced with a Schottky junction. In the illustrated element, a Schottky contact is provided between the Schottky metal 64, which is platinum, for example, and the intermediate region 65 doped more heavily than the drift control region 3. This intermediate region 65 is not required to form a Schottky contact, but rather functions as a stop region that prevents holes from flowing out of the drift control region 3 to the drain electrode 11.

  FIG. 30 shows the element according to FIG. 29 in a possible manufacturing method. In this method, a hole stop region 65 is formed, a Schottky metal 64 is deposited on the hole stop region 65, and then ion implantation is performed through the exposed back surface of the semiconductor substrate 100. During this ion implantation, n-type dopant atoms are implanted into the drift region 2 through this back surface of the semiconductor substrate 100.

  Here, the Schottky metal 64 functions as a mask that prevents dopant atoms from being implanted into the drift control region 3. The semiconductor region of the drift region 2 into which the n-type dopant atoms are implanted is indicated by reference numeral 5 'in FIG. The semiconductor element is completed by forming the back side metal film to form the drain electrode 11 and forming the highly doped drain region 5 by the annealing step.

  In the annealing step, the back side region of the semiconductor substrate 100 is heated to electrically activate the dopant atoms implanted in the semiconductor region 5 ′, thereby forming the heavily doped drain region 5. . This drain region 5 simultaneously forms a low resistance electrical contact between the drain electrode 11 and the drift region 2.

  The hole stop region 65 of the element can be formed by various methods.

  First, the hole stop region 65 can be formed in an early step while the drift control region 3 is formed. The drift control region 3 is formed by depositing a semiconductor material on an already existing semiconductor substrate (not shown) by an epitaxial method.

  The arrangement having the hole stop region 65 and the drift control region 3 can be manufactured by the following procedure. First, at the start of this epitaxial method, a more heavily doped layer that will later form the hole stop region 65 is formed, and then a lightly doped semiconductor material that later forms the drift control region 3 is epitaxially formed. Deposit by the method.

  In this case, this epitaxial deposition method is performed in one trench that is bounded on both sides by the storage dielectric. After the etch back, that is, after the substrate is removed, the Schottky metal is formed by depositing a Schottky metal and performing suitable patterning.

  Alternatively, the hole stop region 65 can be formed by performing an ion implantation method masked via the back surface side of the semiconductor substrate 100 according to the drain region 5.

  By heating the back surface side of the semiconductor substrate 100 using a laser beam (laser annealing), dopant atoms implanted to form the hole stop region 65 and / or to form the drain region 5 are used. It is possible to activate.

  FIG. 31 is a cross-sectional view showing another modification of the semiconductor element shown in FIG. This element includes a field stop region 66 in the drift region 2, which is, for example, the same height as the hole stop region 65 and is more highly doped than the drift region 2. The field stop region 66 may be formed by, for example, an ion implantation method and a subsequent annealing process before forming the back side metal film for forming the drain electrode 11.

  In the case of still another modification of the semiconductor device according to the present invention shown in FIG. 32, the semiconductor substrate 100 in the region of the drift region 2 is formed before the back side metal film for forming the drain electrode 11 is formed. Etch back to the height of the more heavily doped semiconductor region 66. This semiconductor region 66 forms the field stop region in the device according to FIG. In this element, the back-side metal film 11 is in direct contact with the semiconductor region 66 that is more highly doped, and this semiconductor region 66 is here between the back-side metal film 11 and the drift region 2. Provides low resistance contact.

  33, the semiconductor structure having the drift control region 3, the storage dielectric 4, and the drift region 2 described in relation to FIGS. 29 to 32 and the region on the surface side of the semiconductor substrate are disposed. Still further device structures can first be formed on a p-doped semiconductor substrate.

The p-type doped semiconductor substrate is to be removed before forming the Schottky metal (64 in FIGS. 29 to 32) and the back side metal film (11 in FIGS. 29 to 32). . The p-type substrate is removed by performing an electrochemical etching method in a basic etching medium such as an aqueous solution of NH ₄ OH, NaOH, or KOH.

  In this case, the voltage source 68 applies a voltage between the semiconductor substrate 67 and the epitaxial layer deposited on the semiconductor substrate, thereby electrochemically etching back the p-type substrate. During this etch back process, the current supplied from the voltage source 68 is measured by the current measuring unit 69.

  Here, it is used that the flowing current rapidly rises when the substrate 67 is completely etched back and then the etching medium invades the n-type doped epitaxial layer. In this method, the flowing current functions as an etching control body, and the etching is terminated when the current reaches the n-type doped epitaxial layer and rapidly increases.

  The described method includes a step of removing the p-type substrate 67 by an electrochemical etching method, and can be controlled better than a chemical removal process or a mechanical removal process. Here, the described method may be combined with such a process. In this case, an electrochemical method in which the semiconductor substrate 67 is first chemically or mechanically thinned and then accurate end point control is possible. I do.

  FIG. 34 is a cross-sectional view illustrating an exemplary embodiment of a power device according to the present invention. The device is improved with respect to its switch-on operation, switch-off operation, and overcurrent operation compared to the semiconductor device described above. In the case of this element, a semiconductor region 27 that is doped complementarily to the drift region 2 is provided adjacent to the drift region 2, and the semiconductor region 27 together with the drain region 5 is provided with the drain electrode 11. It is connected to the.

  The p-type semiconductor region 27 extends across the entire width of the drift region 2 between the two drain regions 5 in the horizontal direction. The drift region 2 exists between the storage dielectrics 4 of the two drift control regions 3 adjacent to both sides of the drift region 2. In this element, the drift control region 3 is connected to the drain electrode 11 through a diode formed by the connection regions 31 and 32.

  However, in order to connect the drift control region 3 to the drain electrode 11, any one of the other possibilities described above, in particular a method of providing a Schottky diode, may be used.

  The effect of the p-type region 27 on the function of the p-type region 27 or the function of the semiconductor element will be described below.

  For the sake of explanation, first, an off-state semiconductor element is assumed. As described above, in the off-state element, the space charge region expands under the control of the drift region 2 in the drift region 2 and the drift control region 3. Thereafter, if the device is driven on, first, an inversion channel is formed along the gate dielectric 16 in the substrate region 8 so that charge carriers are transferred from the source region 9 to the inversion. It flows out into the drift region 2 through the channel.

  At the beginning of this driving operation, in the drift region 2, the storage channel is not yet formed, so that the charge carriers are distributed almost evenly and in the direction of the drain region 5 through the drift region. Flowing into. In this case, the storage channel is formed in the drift region 2 because the voltage drop in the drift region 2 is within a range necessary for forming such a storage channel along the storage dielectric 4. This is only the case when the potential difference between 3 and the drift region 2 drops.

  In this element, at the beginning of the switch-on operation, the p-type region 27 adjacent to the drift region 2 promotes the reduction of the voltage existing in the drift region 2, thereby causing the operation leading to the formation of the storage channel. Accelerate.

  This effect occurs because the drift region 2 is filled with charge carriers by the p-type region 27. In the device according to FIG. 34, the storage channel along the storage dielectric 4 also extends to the drain region 5 through each part of the p-type region 27 extending to the storage dielectric 4. Thus, there is a shunt for the p-type doped region 27 in the switched-on state, i.e. after the storage channel has been formed.

  In this device, the majority of the charge carriers then flow into the drain region 5 via the inversion channel along the gate dielectric 16 and the storage channel along the storage dielectric 4. Therefore, when the device is switched on, the backside emitter formed by the p-type region 27 is no longer effective.

The magnitude of the p-type doping concentration of the p-type region 27 can vary over a wide range. This is at least 1 × 10 ¹⁷ cm ⁻³ or more, but may be more highly doped.

  The lateral extension of the p-type region 27 needs to be designed so that the vertical conductivity in the drain region 5 is kept high. That is, when the element has a rated current, the conductivity is such that the voltage drop in the drain region 5 is smaller than the diode threshold value of the pn junction formed by the p-type region 27 and the drift region 2. Need to be designed to hold.

The extension of the p-type region 27 in the vertical direction is relatively unimportant. The spread needs to be at least about 10 ¹³ cm ⁻² , for example, so that the p-type dose in the vertical direction is required for good emitter characteristics. This corresponds to a vertical dimension of 1 μm for a p-type doping of 10 ¹⁷ cm ⁻³ .

  FIG. 35 is a cross-sectional view showing a modification of the semiconductor element shown in FIG. In the case of this element, a field stop region 28 having the same conductivity type as that of the drift region 2 is arranged upstream of the p-type region 27. The field stop region 28 is more highly doped than the drift region 2 and extends in the horizontal direction between the two storage dielectrics 4 forming the boundary shown in the horizontal direction in the drift region 2. ing.

  FIG. 36 is a cross-sectional view showing a further modification of the semiconductor element shown in FIG. In the case of this element, the dimension of the p-type region 27 in the vertical direction of the semiconductor substrate 100 corresponds to the dimension of the drain region 5. As a result, since the p-type region 27 does not extend to the storage dielectric 4 in the horizontal direction of the semiconductor substrate, the drift region 2 is directly adjacent to the drain region 5 in the region of the storage dielectric 4. Matching.

  In FIG. 37 showing a modification of the element shown in FIG. 36, the field stop region 28 is directly adjacent to the drain region 5 and the p-type region 27. Alternatively, the field stop region 28 may be disposed apart from the drain region 5 and the p-type region 27 as shown in FIG. In the case of this element, a part of the drift region 2 exists between the field stop region 28 and the drain region 5 or between the field stop region 28 and the p-type region 27.

  FIG. 39 is a cross-sectional view showing a further modification of the semiconductor element shown in FIG. In the case of this element, since the dimension of the p-type region 27 in the vertical direction is smaller than the dimension of the drain region 5, the p-type region 27 is concave with respect to the drain region 5 in the surface direction of the drain electrode. It is depressed.

  40 shows the device according to FIG. 39 further having a field stop region 28 arranged upstream of the drain region and p-type region 27. FIG.

  FIG. 41 is a cross-sectional view showing a further exemplary embodiment of a power semiconductor device according to the present invention, which includes a drift region 2, a drift control region 3, and a drift region 2 and a drift control region 3. The storage dielectric 4 is disposed between the two.

  The illustrated element is realized as an n-type conductive MOSFET comprising an n-type doped source region 9 and an n-type doped drain region 5, which MOSFET is at least partially p-type doped. The drift region 2 is also provided. For the sake of clarity, the connection of the drift control region 3 to the drain region 5, the source region 9, and possibly the gate electrode 15 is not shown in detail in FIG. Connecting the drift control region 3 to these semiconductor regions can be done using any one of the possibilities described above.

  When the element is driven to be on, that is, when a positive voltage is applied between the drain region 5 and the source region 9 and a suitable driving potential is applied to the gate electrode 15, In the p-type doped drift region 2, an inversion channel is formed along the storage dielectric 4. Therefore, in this element, the storage dielectric 4 has a function of “inverted dielectric”. However, for simplicity, the term “storage dielectric” is also used herein for the dielectric. An inversion channel is formed in the drift region 2 doped with p-type along the dielectric.

  In the illustrated element, the gate electrode 15 is disposed away from the drift control region 3 in the horizontal direction r of the semiconductor substrate 100. Therefore, when the device is driven to the on state, it forms along the inversion channel formed along the gate dielectric 16 in the substrate region 8 and along the storage dielectric 4 in the p-type drift region 2. The inverted channels to be applied are spaced apart from each other in the horizontal direction.

  In order to bridge this, an n-type doped intermediate region 22 is arranged between the substrate region 8 and the p-type drift region 2, and the intermediate region is in the transverse direction between these two channels. The first step is to enable electron flow between each of these two channels.

  FIG. 42 is a cross-sectional view showing a modification of the element shown in FIG. In the case of this element, the gate electrode 15 is disposed above the drift control region 3 in the vertical direction v of the semiconductor substrate. In the case of this element, the p-type drift region 2 is directly adjacent to the p-type doped substrate region 8.

Also in the element shown in FIG. 42, neither the interconnection of the drift control region 3 to the drain region 5 and the source region 9 nor the interconnection of the drift control region 3 to the gate electrode 15 is shown in detail. This interconnection can be made by any of the methods described above. The doping concentration of the p-type drift region 2 is, for example, in the range of 10 ¹⁴ cm ⁻³ to 5 × 10 ¹⁵ / cm ⁻³ , which is therefore significantly lower than the doping concentration of the substrate region 8.

  In the case of the element shown in FIG. 41, a region 29 doped with p-type at a higher concentration may optionally be provided between the drift region 2 and the intermediate region 22 extending in the transverse direction. The purpose of the p-type region 29 is to reduce the electric field strength below the substrate region 8 and the gate electrode 15 when the device is driven to the off state.

Further, optionally, a semiconductor region 45 doped with a low concentration n-type may be provided in the p-type drift region 2 along the storage dielectric 4, in which the element is driven to an ON state. A storage channel is formed. The doping concentration of the region 45 is, for example, in the range of 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁶ cm ⁻³ , and the horizontal width / dimension of the region is, for example, between 0.2 μm and 2 μm. Within range.

  This very thin n-type doped semiconductor region 45 has a small impact on the off-state operation of the device, but provides an improved switch-on operation. This is because there is usually a conductive channel for the majority of charge carriers along the storage dielectric 4. The n-type region 45 extends from the n-type conductive intermediate region 22 to the drain region 5 in the vertical direction. Such an n-type region may also be provided in the case of the element according to FIG.

  In the case of this element, the n-type region extends from the substrate region 8 to the drain region 5. In the case of the device according to FIG. 42, the gate electrode 15 and the drift control region 3 are arranged vertically in the vertical direction, and the dimensions of such a long and lightly doped n-type region 45 are as follows: Only the gate electrode 15 in the direction is determined to extend to the height of the drift control region 3 through the dielectric that separates the gate electrode 15 and the drift control region 3. This bridges the area in the p-type drift region 2 between the inversion channel formed along the gate dielectric 16 and the storage channel extending along the storage dielectric 4 when the device is on. Can be connected.

  FIG. 43 is a cross-sectional view showing a modification of the element shown in FIG. In the case of this element, the p-type drift region 2 is provided with a p-type doped region 29 having a higher concentration adjacent to the p-type drift region 2, and this region 29 is an electric field loaded in the upper region of the drift region 2. Has the function of reducing the strength.

  Between this higher concentration p-type doped region 29 and the substrate region 8, a lower concentration n-type doped region 22 is provided. This region 22 has the function of “bridging” the semiconductor region between the gate dielectric 16 and the region along the storage dielectric 4.

  In the substrate region 8, an inversion channel is formed along the gate dielectric 16 when the device is driven on, and along the storage dielectric 4 when the device is driven on. A storage channel is formed. Of course, it should be noted that the doping of the p-type region 29 is so high that the channel is pinched off along the storage dielectric 4.

  It should be noted that the drift control region 3 for realizing an n-type conductive semiconductor element does not necessarily have to be n-type doped. As clearly shown in FIGS. 41 to 43, the drift control region 3 may be selectively p-type doped at a low concentration, or may be an intrinsic semiconductor. This applies to all power semiconductor elements of the present invention described above and below.

  FIG. 44 is a cross-sectional view illustrating a further exemplary embodiment of a power semiconductor device according to the present invention. The illustrated element is realized as a vertical n-type conductive MOSFET. In the case of this element, the drift control region 3 is arranged only partially adjacent to the drift region 2. That is, the drift control region 3 does not completely extend along the drift region 2 in the vertical direction v of the semiconductor substrate 100.

  In the case of the illustrated element, the drift control region 3 is disposed in the upper region of the semiconductor substrate 100 so as to be spaced apart from the drain region 5, and a part of the drift region 2 is part of the drift control region 3 and drain region 5. It is arranged between.

  In the case of the illustrated element, the drift control region 3 is dielectrically insulated from the drift region 2 by the storage dielectric 4 in the horizontal direction r of the semiconductor substrate. In the vertical direction of the semiconductor substrate, a tunnel dielectric 4 ′ exists between the drift control region 3 and the drift region 2, and the tunnel dielectric is connected to the “hot reverse current” and “ It is possible to distribute the “displacement current”.

  The drift control region 3 is connected to the source region 9 and possibly the gate electrode 15 by the heavily doped connection region 34 and the diode and capacitance (shown in broken lines) using the method described above. It may be connected.

  The element according to FIG. 44 is based on the basic structure of a trench MOSFET, in which a drift control region 3 is additionally provided along the drift region 2. In the case of this trench MOSFET, the gate electrode 15 is disposed in one trench extending into the semiconductor substrate starting from the surface 101. In the case of this element, the inversion channel in the substrate region 8 is formed between the source region 9 arranged in the region of the surface 101 in the vertical direction and the drift region 2 adjacent to the substrate region 8 in the vertical direction. Arranged between.

  FIG. 45 is a cross-sectional view showing a modification of the element shown in FIG. The element shown in FIG. 45 is based on the basic structure of a planar MOSFET. In the case of the illustrated device, the gate electrode 15 is disposed on the surface 101 of the semiconductor substrate 100 and is insulated from the semiconductor substrate 100 by the gate dielectric 16. In the horizontal direction r of the semiconductor substrate 100, the gate electrode 15 extends to the storage dielectric 4 that extends in the vertical direction v within the semiconductor substrate 100.

  However, the gate electrode 15 may already terminate in the horizontal direction before reaching the storage dielectric 4 (not shown), but in the horizontal direction the drift region 2 extending from the source region 9 to the surface 101 in the horizontal direction. It needs to extend to a part.

  In the case of the illustrated device, in the on state, an inversion channel is formed in the horizontal direction in the substrate region 8 between the source region 9 and the portion of the drift region 2 extending to the surface 101. Further, the substrate region 8 is formed so as to surround the source region 9 in the horizontal direction and the vertical direction of the semiconductor substrate 100.

  FIG. 46 is a diagram showing one element modified with respect to FIG. In the case of this element, the drift region 2 comprises two respective semiconductor parts doped differently. Each of these differently doped semiconductor portions is adjacent to the storage dielectric 4 in the region between the first lightly doped semiconductor portion 91 and the drift control region 3 and drain region 5, A second, more heavily doped semiconductor portion 92.

  In the case of this element, compensation regions 93 and 94 that are complementarily doped with respect to the drift region 2 are provided. The first region 93 of the compensation region is disposed adjacent to the lightly doped drift region portion 91 in the horizontal direction of the semiconductor substrate, and the second region 94 of the compensation region is horizontal. In the direction r, it is arranged adjacent to the more heavily doped drift region portion 92. In this case, the doping concentration of the first compensation region portion 93 is lower than the doping concentration of the second compensation region portion 94.

  In FIG. 46, the drift region 2 can be realized such that a part of the drift region portion 92 that is more highly doped is disposed between the compensation region portion 94 and the drain region 5. The compensation region portions 93 and 94 are directly adjacent to each other in the vertical direction v of the semiconductor substrate. Furthermore, the first compensation region portion 93 is directly adjacent to the substrate region 8 in the vertical direction v.

  The purpose of each compensation region portion 93, 94 when the device is driven to the off state is to compensate the n-type dopant atoms in the drift region 2 by the p-type dopant atoms in each compensation region portion 93, 94. It is. This compensation effect occurs particularly in the lower region of the semiconductor substrate, where the more highly doped drift region portion 92 and the more highly doped compensation region portion 94 are adjacent to each other. In the case where the drift region has the same dielectric strength as an element that does not have a corresponding compensation region, the drift region can be more heavily doped due to the compensation effect described above, resulting in a reduction in on-resistance. Is invited.

  FIG. 47 is a cross-sectional view showing a modification of the element shown in FIG. 46, in which the compensation region portion 93 doped to a lower concentration has a higher concentration in the horizontal direction of the semiconductor substrate. Smaller than the doped compensation region portion 94. In the case of this device, the lightly doped compensation region portion 93 is less useful for compensating for dopant atoms in the lightly doped drift region portion 91, but substantially Rather, it serves to connect the more heavily doped compensation region portion 94 to the substrate region 8.

  In the following, method steps for manufacturing a semiconductor structure used in the device according to FIGS. 44 to 47 will be described with reference to FIGS. 48A to 48D. In the semiconductor structure, the drift control region 3 is arranged only partially adjacent to the drift region 2.

  In this method, a semiconductor substrate is used first. The semiconductor substrate will later form the drain region 5 of the semiconductor element. Subsequently, a semiconductor layer 2 ′ is deposited on the semiconductor substrate by an epitaxial method, and the semiconductor layer forms a part of the drift region 2 after the semiconductor element.

  In order to realize an n-type conductive power element, the semiconductor substrate 5 can be n-type doped and the epitaxial layer 2 ′ can be n-type doped or p-type doped. Thereafter, a tunnel dielectric 4 'is partially deposited on the epitaxial layer 2'.

  The tunnel dielectric has a function of separating the drift control region 3 and the drift region 2 later. The formation of the tunnel dielectric 4 'is realized, for example, by depositing a suitable dielectric layer over the entire area and then selectively removing the dielectric layer by using an etching method. FIG. 48A is a cross-sectional view showing the results of the method steps described above.

  In FIG. 48B, a further epitaxial layer 2 ″ is then deposited on the first epitaxial layer 2 ′ and the tunnel dielectric 4 ′. To grow.

  In FIG. 48C, a trench 110 is etched from the surface 101 of the semiconductor substrate 100 after the deposition of the second epitaxial layer 2 ″. The trench reaches the height of the tunnel dielectric 4 ′ in the vertical direction, In the horizontal direction, it extends to the tunnel dielectric 4 ', which is then filled with a material suitable for realizing the storage dielectric 4. The result of this filling is shown in Fig. 48D. The body may be, for example, a thermal semiconductor oxide (for example, silicon oxide in the case of the semiconductor substrate 100 made of silicon) that may be formed when the semiconductor substrate 100 is heated.

  In the case of this semiconductor structure, the second epitaxial layer is delimited by two trenches 110 (only one trench is shown in FIG. 48C) in the horizontal direction and delimited by the tunnel dielectric 4 ′ in the vertical direction. A part of the layer 2 ″ forms a later drift control region 3, and the remaining region of this second epitaxial layer 2 ″ forms a part of the later drift region 2.

  After the method steps for manufacturing the semiconductor structure having the drift region 2, the drift control region 3, and the storage dielectric 4 described with reference to FIGS. 48A to 48D, the surface 101 of the semiconductor substrate is formed. Basically, further known method steps for realizing the transistor structure in the region are followed, namely the method steps for forming the source region 9, the substrate region 8, the gate electrode 15 and the gate dielectric 16.

  It is possible to dope the above-mentioned epitaxial layers 2 ′, 2 ″ to different concentrations, thereby forming respective drift region portions 91, 92 that are doped to different concentrations. Each compensation region portion 93, 94. Can already be formed during the epitaxial process.

  In the procedure by the epitaxial method, in any compensation region portion, after a layer having a specific thickness is deposited by the epitaxial method, p-type dopant atoms are localized in the layer deposited by the epitaxial method. To be introduced. Finally, these introduced dopant atoms are diffused inwardly into the semiconductor substrate by a diffusion method, and thereafter form respective continuous compensation regions 93, 94.

  As described with reference to FIGS. 17 to 20, a capacitor 50 can be provided between the drift control region 3 and the source region 9, and the capacitor is driven in an off state. When the device is driven to be turned on, a storage channel is formed along the storage dielectric 4 in the drift control region 3. To work. One possibility to realize this capacitor 50 will be described below with reference to FIGS. 49A and 49B.

  In this case, FIG. 49A is a view showing a part of the semiconductor element in a side sectional view. FIG. 49B shows a cross-sectional view of the device, taken along the two cross-sections III-III and IV-IV shown in FIG. 49A. In FIG. 49B, the element structure of the cross section taken along the line III-III is indicated by a solid line, and the element structure of the cross section taken along the line IV-IV is indicated by a broken line. In this case, the numbers in parentheses indicate the reference numerals of the element structure in the section taken along line IV-IV.

  In the case of the described device, the capacitor 50 includes a dielectric layer 121 disposed between each of the two metal layers 122, 124. The first metal layer 122 among these metal layers is disposed below the capacitor dielectric layer 121 with respect to the semiconductor substrate 100, that is, between the capacitor dielectric layer 121 and the semiconductor substrate 100. Yes. In this case, the first metal layer 122 is formed directly on the drift control region 3 or, as shown in FIG. 49A, at least one region of the connection regions 33 and 34 described above. Connected through.

  In this case, the first metal layer 122 has a metal film portion, and the metal film portion partially extends to the surface 101 of the semiconductor substrate, and directly or indirectly to the drift control region 3. In contact with the surface 101. In this case, the portion of the first metal layer 122 extending in the direction of the surface 101 forms the connection contact 19 of the drift control region 3 described with reference to FIGS. The second metal layer 124 of each of the above metal layers is disposed above the capacitor dielectric 121 and is therefore dielectrically insulated from the first metal layer 122 by the capacitor dielectric 121.

  The capacitor dielectric 121 and the first metal layer 122 have respective cutouts 125, through which the metal layer 124 extends to the surface 101 of the semiconductor substrate, and the source region 9. And is connected to the substrate region 8 via a heavily doped connection region 17. Within the cutout 125, the second metal layer 124 is insulated from the first metal layer 122 by an insulating layer 127, for example, an oxide. In the case of this element, the second metal layer 124 simultaneously forms the source electrode 13 of the element.

  The transistors shown in FIGS. 49A and 49B are realized as trench transistors, and the gate electrode 15 of the trench transistor is arranged in one trench extending from the surface 101 into the semiconductor substrate. In the case of this element, the gate electrode 15 is disposed above the drift control region 3 in the vertical direction v. As shown in the left-hand part of FIGS. 49A and 49B, the drift control region 3 is It extends partially to the surface 101 where it is connected to the connection electrode 19. Between the gate electrode 15 and the first metal layer 122, a further insulating layer 123, for example an oxide layer, is arranged, which in the illustrated embodiment is the semiconductor substrate. It extends beyond the surface 101.

  Although not shown in detail, as a matter of course, the gate electrode 15 may be disposed apart from the drift control region 3 in the horizontal direction. In this case, the drift control region 3 may be directly adjacent to the surface 101 of the semiconductor substrate over the entire length or indirectly via the connection regions 33 and 34.

  The individual method steps for manufacturing the device shown in FIGS. 49A and 49B are briefly described below.

  In the semiconductor substrate 100, after the transistor structure is formed, that is, after the source region 9, the substrate region 8, and the heavily doped connection region 17 are formed, and the drift control region 3 and the gate. After forming the trench structure for realizing the electrode 15, a conductive layer (for example, doped polysilicon) is deposited on the insulating layer on the surface 101 of the semiconductor substrate. In this case, the insulating layer may be formed by the same insulating layer that forms the gate dielectric 16 and the storage dielectric 4 in the semiconductor substrate.

  The conductive layer filling the trench provided for the gate electrode 15 forms the gate electrode 15 of the device. Thereafter, an insulating layer 123 is deposited on the conductive layer. Subsequently, a contact hole is formed above the drift control region 3 in the insulating layer 123 and the conductive layer forming the gate electrode 15.

  An insulating layer 126 is formed on each side wall of the contact hole. Thereafter, the first metal layer 122 of the capacitor is deposited on the insulating layer 123 and in the contact hole. Thereafter, a capacitor dielectric 121 is deposited on the first metal layer 122, and a contact hole is formed on the source region 9. The contact hole extends through the capacitor dielectric 121, the insulating layer 123, the conductive layer forming the gate electrode 15, and the insulating layer deposited directly on the surface 101.

  Thereafter, on each side wall of the contact hole, an insulating layer 127 is formed at least on the exposed region of the first metal layer 122. Thereafter, a second metal layer 124 is deposited on the capacitor dielectric 121 and in the contact holes already formed. In this case, the capacitor dielectric 121 can be formed either before or after the contact hole is formed on the source region 9.

  However, when the capacitor dielectric 121 is deposited after the contact hole is formed, it is necessary to remove the capacitor dielectric again at least at the bottom of the contact hole before forming the second metal layer 124. is there.

  In the following, further possibilities for realizing the capacitor 50 between the source region 9 and the drift control region 3 will be described with reference to FIGS.

  FIG. 50A is a perspective view illustrating a portion of an exemplary embodiment of a semiconductor device according to the present invention. FIG. 50B is a plan view of the surface 101 of the semiconductor substrate 100 showing the capacitor structure of the device.

  The above element is realized as a trench MOSFET based on the element shown in FIG. 17A, and the storage capacitor 50 between the source region 9 and the drift control region 3 is different from the device shown in FIG. 17A in the drift control region 3. Is different in that it is incorporated in the semiconductor substrate above.

  In the case of the element of the present embodiment, the capacitor 50 has a first capacitor electrode 128, and this capacitor electrode 128 is in one trench above the drift control region 3 in the semiconductor substrate 100. Is arranged. In the exemplary embodiment described, the trench is formed in the horizontal direction, delimited by a dielectric layer 4 that forms the storage dielectric 4.

  The first capacitor electrode 128 is dielectrically insulated by the capacitor dielectric 129 from the drift control region 3 and possibly the connection regions 33 and 34 adjacent to the drift control region 3. In the case of this device, in particular, the connection region 34 doped with a high concentration of the base material in the region of the semiconductor surface 101 forms the second capacitor electrode. In order to achieve the maximum possible storage capacitance of the storage capacitor 50, the capacitor electrode 128 is implemented in a finger shape on the opposite side away from the storage dielectric layer 4.

  In the case of this element, the source electrode can be directly connected to the first capacitor electrode 128. Further, the source electrode and the gate electrode 15 may be connected to the drift control region 3 or the connection region 34 of the drift control region via a plurality of diodes by the method already described with reference to FIG. 17A. Good.

  FIG. 51 is a plan view showing a modification of the above-described capacitor structure incorporated in the semiconductor substrate 100. In the case of this capacitor structure, the first capacitor electrode 128 has a partially bent structure, and its contact surface, and therefore, between the first capacitor electrode 128 and the second capacitor electrode 34. The interface, that is, the region of the capacitor dielectric 129 in between is larger than the finger-shaped structure shown in FIG. The first capacitor electrode 128 may include, for example, heavily doped polysilicon.

  According to FIG. 52, the source region 9 can be directly connected to the first capacitor electrode 128 by the source electrode 13. In this case, the source electrode 13 extends from the source region 9 to the first capacitor electrode 128 through the connection region 17 of the highly doped substrate in the horizontal direction r of the semiconductor substrate 100.

  53A and 53B are cross-sectional views showing a further modified example for realizing the storage capacitor 50. FIG. In this case, FIG. 53A is a side cross-sectional view of a portion of an exemplary embodiment of a semiconductor device according to the present invention. 53B is a cross-sectional view of the semiconductor element in the region of the capacitor structure, taken along the line VI-VI shown in FIG. 53A.

  In the case of this element, the capacitor structure includes a large number of columnar electrode portions, and the electrode portions extend from the surface 101 in the semiconductor substrate in the vertical direction v. Are insulated from the region surrounding them by the capacitor dielectric. In the present embodiment, a part of each of the plurality of columnar electrode portions, which together form the first capacitor electrode 128, is adjacent to the storage dielectric layer 4, and the storage dielectric layer 4 partially Insulated from the semiconductor substrate 100.

  Each of the electrode portions is electrically connected to each other by a connection electrode 130, the connection electrode 130 is disposed above the semiconductor substrate 100, and is separated from a semiconductor region of the semiconductor substrate 100 by an insulating layer 131. Insulated. According to the exemplary embodiment described in connection with FIG. 52, the source region 9 is electrically connected to this capacitor structure by a source electrode 13 extending horizontally above the capacitor structure.

  FIG. 54 is a side cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention. In the device, in order to increase the capacitance of the capacitor structure, the doped semiconductor region 34 forming the second capacitor electrode is more than in the exemplary embodiment according to FIGS. Deeply extends into the semiconductor substrate. In the exemplary embodiment described, the heavily doped region 34 extends below the substrate region 8 in the vertical direction of the semiconductor substrate. In the case of this element, the first capacitor electrode 128 also extends to the lower side of the substrate region 8 in the vertical direction v of the semiconductor substrate.

  However, in order not to impair the dielectric strength of the device, the more heavily doped connection region 34 should not overly overlap the drift region 2 on the opposite side of the storage dielectric 4.

  The connection region 34 is adjacent to the drift control region 3 and forms a second capacitor electrode. Therefore, in order to further increase the capacitance of the capacitor structure, in the exemplary embodiment according to FIG. 55, the connection region 34, the substrate region 8 and the corresponding gate electrode 15 are formed on the surface 101. To extend deeper in the internal direction of the semiconductor substrate.

  The shape of the capacitor structure shown in FIGS. 54 and 55 corresponds to the shape of the capacitor structure described with reference to FIGS. 50B and 51. Optionally, the capacitor structure described in connection with FIG. 53B may be implemented.

  FIG. 56 is a cross-sectional view illustrating an exemplary embodiment of a power semiconductor device according to the present invention including an embedded capacitor structure. The embedded capacitor structure is realized above the drift region 2 in the semiconductor substrate, unlike the exemplary embodiment described with reference to FIGS. The shape of the capacitor structure shown in FIG. 56 is mirrored around the storage dielectric layer 4 of the capacitor structure described with reference to FIGS. Accordingly, the first capacitor electrode 128 can be realized in a finger shape, a bent shape, or a column shape having a plurality of columns.

  In this exemplary embodiment, the second capacitor electrode is formed by a heavily doped connection region 17. The connection region 17 functions to connect the source electrode 13 to the base material region 8 with a low resistance. The connection region 17 is directly adjacent to the capacitor dielectric 129 in the horizontal direction r. In the capacitor structure, a boundary is formed by the storage dielectric 4 on the side opposite to the connection region 17 side. The capacitor is connected to the drift control region 3 by the connection electrode 19 in the drift control region, and the connection electrode 19 passes over the storage dielectric 4 in the horizontal direction in the first direction in the capacitor structure. It extends to the upper side of the connection electrode 128.

  In particular, as described above with reference to FIGS. 16, 17A, 18, and 19, a diode is provided between the drain region 5 or the drain electrode 11 and the drift control region 3 of the semiconductor device according to the present invention. Can be provided. The diode prevents the charge carriers in the drift control region 3 from flowing out toward the drain region 5 or the drain electrode 11 when the device is in the on state. The charge carriers function to control the storage channel in the drift region along the storage dielectric 4.

  In FIG. 16, FIG. 17A and FIG. 19, this diode in the semiconductor substrate can be realized by two respective connection regions 31, 32 which are doped complementarily to each other. Each of the two connection regions is provided between the drift control region 3 and the drain region 5 or between the drift control region 3 and the drain electrode 11. Each of these connection regions forms a pn junction and thus provides a diode function.

  However, achieving the desired diode function by this method is complex. This is because the complementary doped semiconductor regions 31 and 32 are realized in the cell array, that is, in the region of the semiconductor substrate 100 where a plurality of individual transistor structures are formed along the transistor structure described. This is because suitable patterning is required. In the case of providing an external diode, the diode in the exemplary embodiment described so far is connected to the drift control region directly below the cell array.

  FIG. 57 is a perspective view showing an exemplary embodiment of a power semiconductor device according to the present invention, in which a diode between the drain region 5 and the drift control region 3 is spaced apart from the cell array in the horizontal direction. And connected to the semiconductor substrate 100. The diode is hereinafter referred to as a drain-drift control region diode. 57, a cell array having a MOSFET structure and a drift control region 3 adjacent to the drift region of the MOSFET structure includes a source region 9, a source electrode 13, and a source region 9 in the horizontal direction on the left side of the drawing. It is only shown schematically by a part of the surrounding substrate region 8.

  The source region 9 is connected by the source electrode 13, and the connection region 34 of the drift control region 3 is connected by the connection electrode 19 of the drift control region. In the cross section taken along the arrow VII-VII shown in FIG. 57, the MOSFET structure having the drift control region 3 can have any one of the above transistor structures. The MOS transistor can be realized in particular as a planar transistor or a trench transistor. For easy understanding, the gate electrode of the MOS transistor is omitted in FIG.

  In the present embodiment, the insulating layer 134 is disposed between the drift control region 3 and the drain region 5 realized as a semiconductor substrate in the present embodiment. The diode 43 is connected to the surface 101 of the semiconductor substrate, the cathode of the diode 43 is connected to the drift control region 3 via the drift control region connection contact 132, and the anode of the diode 43 is connected to the drain electrode 11. It is connected.

  Depending on the situation, the element is doped between the drift control region 3 and the insulating layer 134 at a higher concentration than the drift control region 3 and has a semiconductor region 131 having the same conductivity type as the drift control region 3. Including. This region 131 is intended to ensure that the reverse current generated in the drift control region 3 in the off state passes through the diode 43.

  This operation can be further improved by implementing a more heavily doped region 131 as follows. That is, by realizing a more highly doped region 131 so that the more highly doped region 131 extends to the diode 43 or connection region 132 in the end region of the device (not shown). It is possible to improve.

  FIG. 58 is a perspective view showing a modification of the semiconductor element shown in FIG. In the case of the device, the diode is incorporated in the semiconductor substrate and includes a p-type doped connection region 133 below the drift control region connection contact 132. This p-type region 133 forms a pn junction together with the drift control region 3, and the pn junction forms a diode 43.

  FIG. 59 is a perspective view showing a modification of the element shown in FIG. In the case of this element, the diode 43 is connected to the drain potential via the surface 101 of the semiconductor substrate. In this case, in the drift region 2, a connection region 135 having the same conductivity type as that of the drift region 2 is provided in the horizontal direction so as to be separated from the cell array, and the connection electrode 132 of the drift control region is connected to the region. Has been.

  Depending on the situation, the element includes a semiconductor region 136 at the height of the region 131 adjacent to the drift control region 3 below the drift region 2. The semiconductor region 136 is more heavily doped than the drift region 2 and has the same conductivity type as the drift region 2. In the off state, the semiconductor region 136 limits the expanding space charge region to the same depth as the region 131 below the drift control region 3 in the vertical direction. This avoids field strength spikes.

  In the case of the device according to FIG. 59, the connection electrode 132 in the drift control region and the highly doped region 135 are arranged in the end region of the semiconductor substrate 100. As a result, in the end region of the semiconductor substrate, the surface 101 of the semiconductor substrate is also at a drain potential. As a result, the drain potential passes through the connection region 135 that is highly doped in the drift region 2. The point that it can be pulled out is used.

  In the case of the element according to FIG. 59, the pn junction for realizing the diode 43 is formed extending directly to the end 103 of the semiconductor substrate. In the modification of the element shown in FIG. 60, n-type doped semiconductor regions 138 and 139 exist between the end portion 103 of the semiconductor substrate 100 and the pn junction, and the semiconductor region Similarly, the connection electrode 132 in the drift control region is in contact.

  By providing an n-type region that prevents the pn junction from extending to the end portion 103 of the semiconductor substrate, the leakage current in the region of the pn junction is reduced. A dielectric layer exists between the drift control region 3 and the semiconductor region 133, and the semiconductor region forms a pn junction together with the drift control region 3 and the n-type regions 138 and 139.

  The n-type regions 138, 139 may include two differently doped semiconductor regions, in which case the more heavily doped region is adjacent to the connection electrode 132 in the drift control region and is less concentrated The heavily doped semiconductor region 138 is located below the more heavily doped region.

  In FIG. 61, it is possible to improve the withstand voltage characteristics of the diode and the long-term stability of the element by a more highly doped region 137 of the same conductivity type as the drift control region 3. This more highly doped region 137 is disposed between the p-type region 133 and the drift control region 3 and prevents the formation of a parasitic p-type channel due to charges on the semiconductor surface.

  As already described, in the end region 103 of the semiconductor substrate 100, the surface 101 is also at the drain potential. However, the source region 9 and the base material region 8, and the connection region 34 of the drift control region 3, which are arranged in the horizontal direction so as to be separated from the end region 103, have a source potential during the operation of the element. It is possible that

  In order to allow the voltage difference between the drain potential and the source potential, in FIG. 63, in the region of the surface 101 of the semiconductor substrate between the cell array and the end 103 of the semiconductor substrate, So-called VLD regions (VLD = change in doping concentration in the horizontal direction) 141 and 142 may be provided. The VLD region is a semiconductor region doped in a complementary manner with respect to the drift region 2 and the drift control region 3, and the doping concentration of the VLD region decreases sequentially from the cell array toward the end portion 103. doing.

  In the case of the p-type doped drift region and the p-type doped drift control region (not shown in FIGS. 62 and 63), the p-type doping of the p-type drift region 2 and the p-type drift Since the p-type doping of the control region 3 assumes the function of the VLD region, these VLD regions are not required. However, after that, it is necessary to provide an n-type doped semiconductor region continuous in the vertical direction at the end of the element 103.

  A further variant for reducing the voltage difference between the end 103 and the cell array is to provide so-called field ring structures 143, 144. The field ring structure surrounds the cell array of the power semiconductor element in a ring shape. In the case of the element according to FIG. 62, three such field rings are provided. These are arranged in a state of being separated from each other in the horizontal direction of the semiconductor substrate 100, and all the field rings are doped in a complementary manner with respect to the drift region 2 and the drift control region 3.

  FIG. 64 is a cross-sectional view showing a portion of a device according to the present invention, implemented as a MOSFET, having a plurality of MOSFET cells 61, 62, 63. FIG. Each MOSFET cell 61, 62, 63 has a source region 9, a substrate region 8, a drift region 2, a bypass region 17, a gate electrode 15, a gate insulator 16, and a source electrode 13. In this case, the drain region 5 and the drain electrode 11 are shared by all MOSFET cells 61, 62, 63.

  A drift control region 3 is arranged between two adjacent MOSFET cells 61, 62, 63, and the drift control region has a first connection region 31 and a second connection region 32 on the drain side. Are connected to the drain region 5 through diodes 31 and 32 formed from

  In this case, the dielectric layer forming the storage dielectric extends at least until reaching the second connection region 32 as shown in the left-hand part of FIG. 64, or shown in the right-hand part of FIG. Thus, it is necessary to extend to the inside of the second connection region 32. Further, the dielectric may be formed so as to terminate only in the drain region 5 in the vertical direction (not shown).

  On the source side, each drift control region 3 is connected to a fourth electrode 19 via a fourth connection region 34 that is heavily p-type doped. In the present embodiment, most of the storage capacitance is formed by the external capacitance 50. Also in the present embodiment, the third connection region 33 may be formed between the fourth connection region 34 and the drift control region 3 as necessary.

  In order to connect each of the MOSFET cells 61, 62, 63 in parallel to each other, the source electrode 13, the gate electrode 15, and the fourth electrode 19 of each cell are interconnected. The electrical connection is preferably made by at least one metal layer (not shown in FIG. 64) which is arranged and patterned above the surface side or source side of the semiconductor substrate 1.

  The dielectric 4 is disposed at least partially between the adjacent drift region 2 and the drift control region 3. It is preferable that dielectric 4 is formed so as to cover and seal in all adjacent regions between drift region 2 and drift control region 3. On the drain side, the dielectric 4 preferably extends at least to the drain region 5. Furthermore, the dielectric 4 may extend to the drain side surface of the semiconductor substrate 1.

  The drift region 2 and the drift control region 3 may have the same doping concentration profile in a region extending in the vertical direction v. As a result, a similar potential distribution is achieved in the drift control region and the drift region when in the off state, resulting in a lower voltage load on the dielectric 4.

  In the case of the exemplary embodiment according to FIG. 64, the drain side blocking pn junctions 31 and 32 for connecting the drift control region 3 to the drain region 5 are formed in the vertical direction v in the drain region 5. Are arranged side by side.

  As another form, in the case of the MOSFET shown in FIG. 65, the first connection region 31 is disposed at the end in the vertical direction v in the region of the drift region 2, and the second connection region 32. Are arranged at the end in the vertical direction v within the drain region 5.

  Each individual cell may have a number of different shapes. 66, 67, 68, and 69 show horizontal cross sections of elements having different cell shapes, respectively.

  FIG. 66 is a cross-sectional view showing a state in which the MOSFET according to FIG. 65 is cut along a plane E-E ′ extending perpendicularly to the vertical direction v. The transistor cell of the MOSFET is formed as a strip cell. In the present embodiment, the individual regions of the MOSFET cells 61 and 62 are formed in a stripe shape in the first horizontal direction r of the cross section, and are arranged at a distance from each other in the second horizontal direction r ′. Yes. The drift control region 3 having the corresponding storage dielectric 4 is disposed between two adjacent MOSFET cells 61 and 62, respectively.

  FIG. 67 shows a cross section of a MOSFET having a rectangular cell structure. The drift control region 3 disposed between adjacent MOSFET cells 61, 62, 63 is continuously formed in this embodiment. However, in another embodiment, the individual drift control regions 3 arranged between two adjacent MOSFET cells may be formed discontinuously.

  FIG. 68 shows a cross section of a MOSFET having MOSFET cells formed in a circle instead of the rectangle shown in the embodiment of FIG.

  FIG. 69 is a variation of the strip-type layout according to FIG. Thus, when it has a meandering cell structure in a cross section, each area | region of a MOSFET cell is formed elongate, and has a meandering waveform at a predetermined distance.

  The semiconductor device according to the invention has been described above on the basis of typical embodiments relating to normally-off MOS transistors. These transistors are turned off when the gate electrode 15 does not have a sufficient driving potential for forming an inversion channel in the substrate region 8. These normally-off transistors are turned on only when the gate electrode 15 has an appropriate drive potential that leads to the formation of an inversion channel along the gate dielectric 16 in the substrate region 8. However, the formation of the drift control region 3 adjacent to the drift region and the formation of the storage dielectric between the drift region and the drift control region are not limited to the normally-off MOS transistor.

  In FIG. 70, the above concept is applied to a normally-on transistor (depletion transistor). Reference numeral 140 in FIG. 70 indicates a semiconductor region in the semiconductor substrate 100 in which transistor cells of normally-on transistors are integrated. Each of these transistor cells is formed as a trench transistor cell and has a gate electrode 144. These gate electrodes 144 extend from the surface 101 along the vertical direction v into the semiconductor substrate and are insulated from the semiconductor substrate by a gate dielectric 145.

  The depletion transistor shown in FIG. 70 is formed as an n-conducting transistor and has an n-type doped source region 142, a p-type doped substrate region 141, and a drift region 146. Yes. In the present embodiment, the base material region 141 is disposed between the source region 142 and the drift region 146.

  A thin channel region 148 having the same conductivity type as the source region 142 but a lower doping concentration than the source region 142 is formed in the substrate region 141 along the gate dielectric 145. The channel region 148 along the gate dielectric 145 provides a conductive connection between the source region 142 and the drift region 146 even when the gate electrode 144 is not driven.

  In order to drive the element in the off state, an appropriate driving potential for depleting charge carriers in the channel region 148 needs to be applied to the gate electrode 144. In the case of an n-conducting transistor, the potential is negative with respect to the potential of the source region 142.

  The drift control region 3 is formed adjacent to the drift region 146 along the horizontal direction r of the semiconductor substrate 100. The drift control region is dielectrically insulated from the drift region 146 by the storage dielectric 4. The drift control region 3 is formed according to each of the above descriptions, and can be connected to the drain region 5 using any one of the above connection methods. Although not shown in detail, the drift control region 3 can be further connected to the source electrode 147 of the depletion type transistor.

  In the case of the element shown in FIG. 70, the transistor cell of the normally-off transistor is formed in the same semiconductor substrate 100 as the depletion transistor. The transistor structure of the normally-off transistor may correspond to any one of the transistor structures of the normally-off transistor already described. The normally-off transistor shown in FIG. 70 is formed such that its gate electrode is disposed in the same trench as the drift control region 3 above the drift control region 3.

  The doping types of the drift region 2 of the normally-off transistor, the drift region 146 of the normally-on transistor, and the drift control region 3 can be used in any combination as desired. The drift region 2 of the normally-off transistor can be doped p-type or n-type irrespective of the doping type of the drift control region 3 and the drift region 146 of the normally-on transistor.

  The drift control region 3 can be p-type or n-type doped regardless of the doping of the drift regions 2 and 146. Drift region 146 can similarly be p-type or n-type doped to form an n-conducting depletion transistor. If the drift region 146 is p-type doped, in the illustrated embodiment, an n-doped semiconductor region 149 is formed between the drift region 146 and the substrate region 141.

  Due to the semiconductor region, charge carriers flow from the channel region 148 to the storage dielectric 4 along the horizontal direction. The low concentration p-type doped connection region 33 of the drift control region 3 shown in FIG. 70 can be omitted if the drift control region 3 is p-type doped.

  As described above, the semiconductor element according to the present invention can be formed in a cell shape having many element structures (for example, transistor structures) of the same type. In the modification shown in FIG. 71, the cell array of the elements may be connected to individual transistor cells (in this embodiment, the transistor cell 160) separately, that is, to be connected independently of other transistor cells. Good.

  In this embodiment, the source electrode 166 of the transistor cell 160 and, if necessary, the gate electrode 163 of the transistor cell 160 can be connected regardless of the gate electrode 15 and the source electrode 13 of other transistor cells. In the present embodiment, the drain electrode 11 is shared by all transistor cells.

  The transistor cell 160 that can be connected separately can be used by a known method, for example, for current measurement in an element. In the present embodiment, the cell, which will be referred to as a measurement cell below, is operated at the same operating point as other transistor cells during the operation of the element.

  Then, the current flowing through the measurement element is determined. In the present embodiment, needless to say, a plurality of measurement cells can be connected in parallel. The current flowing through the measurement cell or a plurality of measurement cells connected in parallel is proportional to the current flowing through another transistor cell (hereinafter referred to as a load cell). In the present embodiment, the proportional constant between the measurement current and the load current corresponds to the ratio of the number of measurement cells and load cells.

  The illustrated measurement cell is formed as a normally-off transistor cell, and has a source region 161, a drift region 167, and a substrate region 162. The base material region 162 is disposed between the source region 161 and the drift region 167 and is doped in a complementary manner with respect to the source region 161.

  The gate electrode 163 insulated from the semiconductor region of the device by the gate dielectric 164 has a function of controlling an inversion channel disposed in the base material region 162 between the source region 161 and the drift region 167. .

  The measurement cell further includes a drift control region 171 separated from the drift region 167 by the storage dielectric 172. The drift control region 171 can be connected to the drain region 5, the source region 161, and, where appropriate, the gate electrode 163 by the methods already described. The connection between the drift control region 171 of the transistor structure and other device regions is not shown in detail in FIG. 71 for the sake of brevity.

  In order to separate the measurement cell from the load cell, an intermediate region 173 can be formed between the drift control region 171 of the measurement cell and the drift control region 3 of the adjacent load cell. The intermediate region may specifically be a “dead” transistor cell, ie, a transistor cell that does not have a source region and a source metal layer, and possibly no gate. However, when the measurement cell is completely surrounded by the drift control region, there is no need for the intermediate region as described above.

  FIG. 72 shows a power semiconductor device according to the present invention in which a temperature sensor is integrally formed between two transistor cells (in the present embodiment, a normally-off transistor cell). The temperature sensor is formed as a diode having p-type emitters 181, 182, an n-type base 183, and an n-type emitter 184. These element regions are arranged adjacent to each other along the vertical direction v of the semiconductor substrate 100.

  In the illustrated embodiment, the p-type emitter has a heavily p-doped region to which the connection electrode 185 is connected. The p-type emitter further optionally includes a lightly doped p-type region 182 disposed adjacent to the heavily doped region along the direction of the n-type base 183. Yes.

  A voltage is supplied to the sensor through the drain electrode 11 on the back surface side to which the n-type emitter 184 is connected. At the connection electrode 185, the temperature signal can be extracted as a measurement current. This takes advantage of the fact that the reverse current flowing in the opposite direction in the diode is temperature dependent.

  FIG. 73 partially illustrates an exemplary embodiment of a power semiconductor device according to the present invention. The temperature sensor can be integrally formed in the horizontal direction in the semiconductor. In the present embodiment, the element regions 181 to 184 of the temperature sensor are arranged adjacent to each other along the horizontal direction r.

  Various edge structures for semiconductor devices that can be implemented in accordance with the present invention are described below with reference to FIGS. Each of these edge structures is basically provided in accordance with a known method in order to obtain a sufficient dielectric strength of a semiconductor element arranged in an edge region of a semiconductor chip or an edge region of a cell array.

  FIG. 74 shows an example of a power semiconductor element having an edge structure according to the first embodiment of the present invention. The element has a semiconductor substrate 5. The semiconductor substrate 5 forms a drain region of an element formed as a transistor in this embodiment. A semiconductor layer such as an epitaxial layer is formed on the semiconductor substrate. An active element structure, that is, a transistor structure and a drift control region 3 are formed in the semiconductor layer.

  The edge structure of the element is formed by etching back a semiconductor layer disposed on the substrate 5 from the surface 101 to the semiconductor substrate 5 located in the edge region of the semiconductor substrate or the edge region of the cell array. . An inactive protective layer 191 extending from the surface 101 to the semiconductor substrate 5 is formed on the edge that is not covered after the etching.

  In the present embodiment, the etching for forming the edge is performed in the region of the element structure corresponding to the drift control region 3 in the cell array. The element structure is indicated by reference numeral 192 in FIG. Between the semiconductor structure 192 and the first active drift control region (that is, the drift control region of the first active transistor cell) is an inactive transistor structure 190 (in this embodiment, a gate electrode and a source region) extending from the edge. There is a transistor structure that does not have.

  In the case of the illustrated element, the drift control region 3 has a plurality of semiconductor layers. Each of these semiconductor layers is continuously epitaxially deposited in the trench in contact with the storage dielectric 4 during the manufacturing process until the trench is filled. These layers can be p-type doped or n-type doped at low concentrations. In the case of doping as described above, the distribution profile of the electric field on the surface can be adjusted according to the target depending on the doping type.

  FIG. 75 shows a modification of the element shown in FIG. In the case of the element, the drift control region 3 has a multilayer structure, and the individual layers are arranged adjacent to each other only in the horizontal direction in the present embodiment. In such a structure, after a semiconductor layer is deposited in a trench in contact with the storage dielectric 4, the deposited semiconductor layer is formed by anisotropic etch back to the bottom of the trench.

  FIG. 76 shows another exemplary embodiment of a power semiconductor device having an edge structure according to the present invention. In the case of the element, the drift region 2 has a plurality of semiconductor layers doped at different concentrations along the horizontal direction r of the semiconductor substrate. Each of these semiconductor layers is adjacent to the storage dielectric 4 and is lightly doped semiconductor layer 301, and is adjacent to the lightly doped semiconductor layer 301 and is highly concentrated. It is a semiconductor layer 302 doped with.

  Similarly, the drift control region 3 is adjacent to the storage dielectric 4 and is lightly doped with the semiconductor layer 303, and is adjacent to the lightly doped semiconductor layer 303 and is highly concentrated. And a doped semiconductor layer 304. Each of these semiconductor layers 301 and 303, which are adjacent to the storage dielectric 4 and are doped to a lower concentration, prevent voltage breakdown in the storage dielectric 4 when the device is turned off.

  In the case of the semiconductor device shown in FIG. 76, the drift control region portion having the lightly doped semiconductor region 303 is arranged in the horizontal direction between the inactive transistor cell 190 and the protective layer 191. ing.

  FIG. 77 shows a modification of the element shown in FIG. In the element, the protective layer 191 is formed directly with respect to the inactive transistor cell 190. In this case, the dielectric layer 305 corresponding to the storage dielectric 4 in the cell array can be disposed between the inactive transistor cell and the transistor cell.

  FIG. 78 shows another exemplary embodiment of a semiconductor device having an edge structure according to the present invention. In the element in the present embodiment, the drift control region 3 is p-type doped. The p-type doped semiconductor portion is located between the inactive transistor cell 190 and the protective layer 191. The semiconductor portion is formed by partially etching the drift control region in the edge region.

  In the edge structure described with reference to FIGS. 74 to 78, the epitaxial layer needs to be etched back to the semiconductor substrate 5. However, in FIG. 79 such an etch back of the epitaxial layer is not necessary. In the element of the embodiment shown in FIG. 79, the edge termination is formed by a plurality of field rings 193 arranged at a distance from one another along the horizontal direction below the surface 101 of the semiconductor substrate. .

  Each of these field rings is complementarily doped with respect to the basic doping (in this embodiment, n-type doping) of the epitaxial layer. If necessary, each field electrode 195 can be connected to each field ring. Each field electrode or field plate 195 is insulated from the basic doped region of the epitaxial layer by an insulating layer.

  According to FIG. 80, it is also possible to form a VLD region 196 in place of the field ring in the edge region of the semiconductor substrate.

  According to FIG. 81, it is also possible to form in the edge region a semiconductor region 197 that is doped in a complementary manner to the basic doping of the epitaxial layer and is uniformly doped. Each field plate 199 is disposed above the semiconductor region 197. Each of these field plates is connected on the one hand to a basic doped region of the epitaxial layer and on the other hand to a semiconductor region 197 which is doped complementary to the basic doping.

  FIG. 82 shows an edge termination for an n-conducting semiconductor device having a p-type doped epitaxial layer, ie, a p-type doped drift region 2. In the element according to the present embodiment, the edge structure has an n-type doped semiconductor region 115 at the edge of the semiconductor substrate 100.

  In FIG. 83, the n-type doped semiconductor region 115 can be combined with the field plate structure 199 that is connected to the n-type region 115. The other of the field plates 199 is connected to the basic doped area of the epitaxial layer. The other field plate can be connected to the fundamentally doped area via a connection region 116 having the same conductivity type as the epitaxial layer.

  In FIG. 84, which shows another embodiment of the edge structure, two respective VLD regions 117, 118 are formed. One VLD region 117 extends from the cell array direction toward the edge direction, and the other VLD region 118 extends from the edge direction along the cell array direction. In the present embodiment, the “extending direction” indicates the direction in which the doping concentration of each VLD region decreases.

  According to FIG. 85 showing an embodiment in which the epitaxial layer is p-type doped, the n-type doped edge region 115 and the semiconductor substrate surface 101 located in the edge region of the p-type epitaxial layer are disposed below. N-type doped field ring 119 can be combined.

  The present invention is not limited to a MOSFET, but can be applied to any power semiconductor element, particularly a unipolar power semiconductor element. In the following drawings, an embodiment in which the principle of the present invention is applied to a Schottky diode is shown.

  FIG. 86 shows a Schottky diode having a metal anode 13. The metal anode 13 is connected to the drift region 2 that is lightly n-doped and forms a Schottky junction 60 with the drift region 2. The heavily doped n-type connection region 5 is disposed on the drift region 2 on the side away from the Schottky junction 60. The cathode electrode 11 is connected to the connection region.

  Adjacent to the drift region 2, a single crystal drift control region 3 doped with low concentration n-type is formed. The drift control region 3 is separated from the drift region via the dielectric layer 4. In the element in the embodiment of FIG. 86, the connection region 31 doped more heavily than the drift control region 3 is formed adjacent to the drift control region 3. The connection region 31 electrically connects the drift control region 3 to the second electrode 12 on the cathode side.

  According to a preferred embodiment, the drift region 2 and the drift control region 3 extend on the same region along the vertical direction v and have the same doping concentration profile (distribution) along the vertical direction v. It is preferable to have. Similarly, the connection region 5 and the first connection region 31 also extend on the same region along the vertical direction v, and preferably have the same doping concentration profile along the vertical direction v. .

  The cathode electrode 11 and the second electrode 12 are electrically insulated from each other.

The Schottky diode shown in FIG. 86 has a diode current I _D between the anode electrode 13 and the cathode electrode 11 during operation in the forward direction. The diode current _ID is significantly higher than the diode current _ID of the same element when the cathode electrode 11 and the second electrode 12 are short-circuited. In the latter case of the cathode electrode 11 short-circuited with the second electrode 12, apart from the storage dielectric 4, it corresponds to the cathode electrode of a conventional Schottky diode that does not have a drift control region.

  In order to operate the Schottky diode of FIG. 86 according to the present invention, it is necessary to connect the drift control region 3 to the cathode-side connection region 5 so as to preferably have a high resistance value. Such a connection can establish a potential profile in the drift control region that forms a storage channel along the storage dielectric in the drift region 2.

Figures 87 and 88, the diode current I _D corresponding to the diode voltage U _D, is a graph showing respectively a linear and logarithmic scale. A characteristic curve 51 in these graphs shows a current-voltage characteristic curve of the diode according to the embodiment of FIG. 86 of the present invention in which the second electrode 12 is connected to the cathode electrode 11 so as to have a high resistance value. Yes. The current-voltage characteristic curve 52 is a characteristic curve of the same diode when the cathode electrode 11 and the second electrode 12 are short-circuited, and is shown for comparison with the characteristic curve 51.

  The operating point 53 shows the state of a conventional Schottky diode that does not have a drift control region and dielectric. The drift region of the conventional Schottky diode extends in the horizontal direction on the dielectric 4 region of the Schottky diode and on the drift control region 3 of FIG. Therefore, the drift region of the conventional Schottky diode has a larger cross section than the drift region 2 of the Schottky diode in FIG. 86 (a steady-state current flows).

  The position of the operating point 53 is very close to the position of the characteristic curve 52 of the conventional Schottky diode. From this, it is clear that a Schottky diode having the same width as that of a conventional Schottky diode is caused by a short circuit between the cathode electrode 11 and the second electrode 12. If the dielectric 4 is additionally provided, the operating point 53 may deviate from the characteristic curve 52, but this can be ignored because the dimension of the dielectric 4 is fine.

  The reason why the characteristics of the characteristic curves 51 and 52 are so different is that the electron distribution in the drift region 2 of the Schottky diode according to the present invention is a highly non-uniform channel. Such an electron distribution is generated when the drift control region 3 and the connection region 5 are cathode-coupled with a high resistance value.

FIG. 89 shows the electron distribution as described above when the voltage level existing between the cathode electrode 11 and the anode electrode 13 is 5V. From the electron distribution, it can be clearly seen that a region having a high electron concentration of about 10 ¹⁷ electrons / cm ³ is formed on the drift region 2 facing the drift control region 3. This is because the drift control region 3 is connected to the connection region 5 with a high resistance value, so that an electric field is constructed in the storage dielectric 4.

  The high resistance value for linking the drift control region 3 to the connection region 5 is such that when the Schottky diode is in the OFF state, there is no significant voltage drop at the cathode electrode 11, and the connection region 5 on the cathode electrode side Must be low enough to dissipate the thermal leakage current from the area.

  However, on the other hand, this connection resistance value must be much higher than the volume resistance value of the region of the connection region 5 located near the electrode. This is to enable accumulation when a forward bias is applied to the Schottky diode.

If the reverse breakdown voltage of the Schottky diode is 600V, for convenience of the values of the cathode connection resistivity and the connection region 5 and the drift control region 3 is in the range of 1Ωcm ² ~10 ⁴ Ωcm ^2. Various embodiments for obtaining such connection resistance values are shown in FIGS. 90 to 96 below.

  In the Schottky diode shown in the embodiment of FIG. 90, a first connection region 31 that is p-type doped at a low concentration is formed for the above purpose. The connection region connects the drift control region 3 to the cathode-side drift region 2 via the cathode electrode 11 and to the connection region 5 that is highly doped n-type.

The Schottky diode shown in FIG. 91 has the same structure as the Schottky diode shown in FIG. 90, but the first connection region 31 is lightly p-type doped. rather, intrinsic (i.e. undoped) semiconductor regions or,, n in lower concentration than the drift control region 3 ^- differs in that it is formed as a doped semiconductor region.

  In FIG. 92, it is not necessary to couple the drift control region 3 to the drift region 2 with the cathode electrode 11 interposed. Alternatively, for example, the first connection region 31 can be coupled to the drift region 2 via the heavily doped connection region 5 to avoid the cathode electrode 11. In the present embodiment of the invention, the first connection region 31 is in direct contact with the heavily doped connection region 5. In order to make this possible, the dielectric 4 is arranged at least partially away from the cathode-side surface of the semiconductor substrate 1. However, the dielectric 4 needs to be formed so that the drift region 2 and the drift control region 3 are not directly connected.

  In the exemplary embodiment shown in FIG. 93, the drift control region 3 is directly connected to the heavily doped connection region 5. For this purpose, the dielectric 4 does not extend at least partially to the cathode-side surface of the semiconductor substrate 1. Within the region between the dielectric 4 and the cathode-side surface of the semiconductor substrate 1, the zone 56 of the drift control region 3 extends to the highly doped connection region 5 and is in direct contact therewith. . Specifically, the electrical coupling resistance value between the drift control region 3 and the drift region 2 is determined by, for example, the shape dimension of the extension of the area 56.

  However, instead of the area 56 of the drift control region 3, another electrical resistance material that electrically connects the drift control region 3 to the connection region 5 may be used.

  In the exemplary embodiment shown in FIG. 94, a layered resistor 55 is provided on the cathode side of the semiconductor substrate 1 in order to cathode connect the drift control region 3 to the connection region 5. In the present embodiment, the resistor 55 is in contact with both the first n-type doped connection region 31 and the heavily doped connection region 5.

  In the exemplary embodiment shown in FIG. 95, the dielectric 4 extends horizontally below the drift control region 3 between the cathode end of the drift control region 3 and the cathode electrode 11. Yes.

  The dielectric 4 has one or more cutouts 57 filled with a resistive material in the region between the drift control region 3 and the cathode electrode 11. The connection resistance value between the drift control region 3 and the connection region 5 can be determined according to the number and size of the cutouts 57 and the resistivity of the resistance material used in the cutouts 57. Specifically, n-type doped semiconductor materials, p-type doped semiconductor materials, or intrinsic semiconductor materials are also suitable as resistive materials.

  The exemplary embodiment shown in FIG. 96 has special features. In the present embodiment, the drift control region 3 is connected to the metal 13 of the Schottky junction 60 on the anode side via the third connection region 33 that is p-type doped at a low concentration. Since the drift control region 3 and the drift region 2 are cathode-connected with a high resistance value, bipolar charge carriers are not injected through the third connection region 33 that is p-doped at a low concentration.

  The lightly p-doped third connection region 33 has the function of protecting the field in the same manner as the p-type doped region of the corresponding merged pin Schottky diode. The electric field strength at the Schottky junction 60 is reduced. However, since no significant current flows in the drift control region 3, the undesirable injection operation in the case of a merged pin Schottky diode does not occur in the present invention. As a result, the turn-off loss does not increase unnecessarily due to the depletion of the injected charge carriers from the drift control region 3.

  In the exemplary embodiment shown in FIG. 96, the drift region 2 and the drift control region 3 are electrically connected to the cathode side via a symbolically shown resistor 55. This resistor can in principle be formed by any desired method. However, electrical coupling is specifically achieved according to the exemplary embodiments shown in FIGS. 89-95 and 97-100.

  FIG. 97 shows an embodiment in which the drift control region 3 and the connection region 5 are resistance-coupled by the cathode electrode 11 partially overlapping with the drift control region 3 in the section 11 ′. . In the present embodiment, the value of the contact resistance can be set by the width of the contact region 11 ′.

  The non-reactive resistance that can be realized by various methods between the drift control region 3 and the connection region 5 can be replaced by a tunnel dielectric, in particular a tunnel oxide. This will be described with reference to the following figures.

  In the embodiment of the Schottky diode shown in FIG. 98, the connection electrode 11 completely covers the drift control region 3 and the drift region 2. The drift control region 3 is connected to the connection electrode 11 via a connection region 31 and a tunnel dielectric 4 ′ that are heavily doped as required. The drift control region 3 is connected to the anode electrode 13 as necessary via the third connection region 33.

  The device shown in FIG. 99 is formed as a merged pin Schottky diode, and has a p-type doped implantation region 33 ′ partially adjacent to the anode electrode 13 in the drift region 2. ing. In the present embodiment, as shown in FIG. 99, the injection region 33 ′ can be disposed adjacent to the dielectric 4, or the side can be disposed away from the dielectric 4. An accumulation channel formed at the boundary between the Schottky junction 60 and the drift region 2 and the dielectric 4 by adopting an embodiment (not shown) in which the side of the implantation region 33 ′ is arranged away from the dielectric 4. And become easy to connect.

  In the element shown in FIG. 100, the point that the dielectric 4 does not extend until reaching the cathode electrode 11, and the connection region 5 extends below the tunnel dielectric 4 ′. It is different from the device shown in FIG. 98 in that it is connected to the connection region 5 via a connection region 31 and a tunnel dielectric 4 ′ that are heavily doped as required.

  FIG. 101 shows another exemplary embodiment of a power semiconductor device according to the present invention formed as a MOSFET. In the element in the present embodiment, the gate electrode 15 and the drift control region 3 are arranged adjacent to each other along the vertical direction of the semiconductor substrate 1, and the gate electrode 15 is directly adjacent to the drift control region 3. Matching.

  In the element according to the present embodiment, the gate electrode 15 is formed to have two portions and has a connection electrode 151. The connection electrode 151 is disposed above the surface of the semiconductor substrate 1 and is insulated from the source electrode 13 by the insulating layer 72. The p-type doped semiconductor area 152 is adjacent to the connection electrode 151 in the vertical direction.

  The semiconductor region of the p-doped semiconductor region 152 is adjacent to the substrate region 8 of the semiconductor substrate 1 in the horizontal direction and is separated from the substrate region 8 by the gate dielectric 16. The semiconductor region 152 performs the actual function of the gate electrode. The semiconductor region 152 also functions to form a conductive channel between the source region 9 and the drift region 2 along the gate dielectric 16 in the substrate region 8 when an appropriate drive potential is applied. have.

The semiconductor region 152 of the gate electrode 15 is p-type doped in the n-conducting MOSFET shown in FIG. The drift control region 3 directly adjacent to the semiconductor region 152 is n-type doped or p-type doped. The doping concentration of the drift control region is lower than the doping concentration of the semiconductor region 152. The doping of the drift control region is performed in a region of 1 × 10 ¹⁴ cm ⁻³ , for example, and may correspond to the doping concentration of the drift region 2. In the present embodiment, the doping concentration of the semiconductor region 152 may correspond to the doping concentration of the substrate region 8.

  In the n-MOSFET shown in FIG. 101, when a positive voltage exists between the drain region 5 and the source region 9, and the driving potential higher than the potentials of the source region 9 and the substrate region 8 is applied. When it exists in the gate electrode 15, it is turned on. An inversion channel is formed in the base material region 8 located between the source region 9 and the drift region 2 by the positive drive potential at the gate electrode 15.

  When the element is turned on, the drift control region 3 shows substantially the same potential as the gate electrode 15. As a result, a storage channel is formed along the storage dielectric 4 in the drift region 2. When the element is completely turned on, the potential of the drain region 5 is usually lower than the potential of the gate electrode 15. Thereby, a storage channel is formed in the vertical direction along the storage dielectric 4 between the substrate region 8 and the drain region 5.

  The diode 43 connected between the connection electrode 12 of the drift control region 3 and the drain region 5 or the drain electrode 11 exists in the drift control region 3 during the circuit state (causes an accumulation channel). ) The hole is prevented from flowing in the direction of the drain region 5 or the drain electrode 11.

  The diode 43 indicated only by the circuit reference in FIG. 101 can be formed as an external diode. In FIG. 102, a semiconductor that is complementarily doped with respect to the connection region 31 and the drain region 5 and that is provided between the connection region 31 and the drain electrode 11 that are highly doped in the drift control region 3. With the region 32, the diode 43 can also be integrally formed in the drift control region. As already described with reference to FIG. 16, the diode 43 has a function of preventing holes from flowing from the drift control region 3 to the drain region 5.

  In the device shown in the embodiment of FIGS. 101 and 102, the gate dielectric 16 and the storage dielectric 4 can be formed as a common dielectric layer that extends vertically within the semiconductor substrate 100. In the device shown in the embodiment of FIGS. 101 and 102, these dielectric layers extend vertically through the entire depth of the device. That is, these dielectric layers extend from the front surface side to the back surface side of the semiconductor substrate 1.

  FIG. 103 shows a modification of the element of FIG. In the element shown in FIG. 103, the storage dielectric 4 is located in front of the back surface 102 of the semiconductor substrate 1 so that the drain region 5 and the p-type doped connection region 32 are partially adjacent to each other in the horizontal direction. It is terminated. However, the N-type doped connection region 31 and drain region 5 are completely separated in the horizontal direction within the semiconductor substrate by the storage dielectric 4.

  FIG. 104 shows another variation of the element of FIG. In the present embodiment, the drift control region 3 has a connection region 34 that is doped at a higher concentration than the drift control region 3 in the direction of the gate electrode 15. This connection region is, for example, p-type doped. The connection region 34 is connected to the gate electrode 15 through a connection electrode 19 made of, for example, silicide or metal. In the element according to the present embodiment, the gate electrode 15 may be formed of a metal or highly doped polysilicon.

  When n-type doped polysilicon is used as the material of the gate electrode 15, the conductive connection electrode 19 is electrically and conductively connected to the p-type doped connection region of the drift control region 3. 34 is connected. When the connection electrode 19 is not formed, a pn junction is formed between the gate electrode 15 and the drift control region 3, and movement of charge carriers from the gate electrode 15 to the drift control region 3 is inhibited. When the gate electrode 15 is made of p-type doped polysilicon, the connection electrode 19 may not be formed.

  FIG. 105 shows a modified MOSFET for the MOSFET shown in FIG. In the element according to the present embodiment, the gate electrode 15 and the drift control region 3 are insulated from each other by another insulating layer 74 formed between the gate electrode 15 and the drift control region 3.

  In the element in the present embodiment, although not shown in detail, the connection electrode 19 adjacent to the insulating layer 74 in the drift control region 3 can be connected to a drive potential separated from the gate potential. The driving potential for forming the accumulation channel in the drift region 2 needs to be selected to be at least higher than the source potential (that is, the potential of the source electrode 13 or the source region 9 and the base material region 8).

  In the present embodiment, the driving potential can be selected to be higher than the drain potential (that is, the potential of the drain region 5). With this selection, the drift control region 3 exhibits a common potential by the diodes 31 and 32 to which a reverse bias is applied between the drift control region 3 and the drain region 5.

  When the drive potential of the connection electrode 19 is smaller than the potential of the drain region 5, in this embodiment, a voltage drop occurs in the vertical direction in the drift control region 3, and the length of the storage dielectric 4 in the drift region 2. A storage channel is not formed along the entire length. However, it is possible to partially form a storage channel in a region adjacent to the substrate region 8, thereby reducing the on-resistance.

  FIG. 106E shows a semiconductor device formed as a MOSFET of a variation of the device shown in FIG. In the element in the present embodiment, the semiconductor region 51 that is continuously and highly doped in the horizontal direction and is adjacent to the drain electrode 11 is located in the region of the back surface 102 of the semiconductor substrate 1. Yes.

  The connection regions 31 and 32 of the drift control region 3 are complementarily doped with each other and form a diode. Each connection region 31, 32 is also located between the semiconductor region 51 and the drift control region 3. Between the heavily doped semiconductor region 51 and the drift region 2, the drain region of the element is formed, and the n-type doped semiconductor has two semiconductor regions 52 and 53 arranged one above the other. The area is arranged.

  In the element according to the present embodiment, the area 52 of the drain region 5 is adjacent to the p-type doped connection region 32 of the drift control region 3 in the horizontal direction. In the element in the present embodiment, the semiconductor region 51 essentially functions as a substrate having an element structure on the upper part, and electrically connects the drain electrode 11 and the drain region 5 electrically and conductively with a low resistance.

  A method for manufacturing the device according to the embodiment of FIG. 106E will be described below with reference to FIGS. 106A to 106D.

  According to FIG. 106A, the method starts with the step of providing a semiconductor substrate 51. The semiconductor substrate 51 is, for example, a high concentration n-type semiconductor substrate. In this regard, it should be noted that the dimensions of the semiconductor substrate in the vertical direction described below and the dimensions of the element regions of the semiconductor elements are not shown as relative scales. The dimension of the substrate 51 in the vertical direction is usually much larger than that of another element region or semiconductor layer described below.

  In FIG. 106B, a semiconductor layer is formed on the semiconductor substrate 51. The semiconductor layer alternately includes n-type doped semiconductor regions 52 and p-type doped semiconductor regions 32 along the horizontal direction. In this embodiment, the p-doped region partially forms the later diode. The drift control region 4 is connected to the drain region or the drain electrode through the p-type doped region. The n-doped semiconductor region 52 partially forms the drain region after the device.

  The semiconductor layer formed on the semiconductor substrate 51 is formed as a uniformly doped one-conductivity type layer or an intrinsic doped semiconductor layer by, for example, epitaxy. The semiconductor regions 32 and 52 can later be doped differently by implantation methods in which dopant atoms are introduced into the semiconductor layer.

  In FIG. 106C, three separate semiconductor layers 53 ′, 2 ′, and 9 ′ are deposited on the semiconductor layer having the semiconductor regions 32 and 52 that are complementarily doped with each other. For example, the first layer 53 ′ is n-type doped, the second layer 2 ′ is n-type doped to a lower concentration than the first layer 53 ′, and the third layer 9 ′ is p-type. Doped.

  The third layer 9 'forms the surface 101 of the semiconductor substrate 1 after each of these semiconductor layers is deposited.

  In FIG. 106D, a trench is formed. These trenches extend from the surface 101 vertically into the semiconductor substrate and into the p-type doped semiconductor region 32 of the semiconductor layer. These trenches are then filled with a dielectric material such as a semiconductor oxide. This dielectric material forms the storage dielectric 4 in the region of the second layer 2 'and the gate dielectric 16 in the region of the third layer 9'.

  The trench having a dielectric disposed therein divides each of the three semiconductor layers 53 ', 2', 9 'into individual semiconductor areas. These semiconductor areas of the semiconductor layers 53 ′, 2 ′, 9 ′ are part of the drain region 5, the drift region 2, And the base material area | region 8 is formed. Each of these three semiconductor layers forms part 31 of the built-in diode, drift control region 3 and part 152 of the gate electrode 15 above the p-type doped semiconductor region 32 of the first layer. Yes.

  In FIG. 106E, the device is completed by forming the source region 9 in the substrate region. For this purpose, dopant atoms of conductivity type complementary to the doping of the substrate region are introduced into the region of the substrate region 8 located in the vicinity of the surface. Finally, the source electrode 13 and the connection electrode 151 of the gate electrode 15 are formed above the surface 101. These electrodes 13 and 151 can be formed by depositing a metal layer or a heavily doped polysilicon layer and patterning this layer. In the present embodiment, the pattern forming step includes a step of dividing the semiconductor layer into individual electrode sections and forming an insulating layer 72 between the individual electrode sections.

  In the device according to the embodiment of FIG. 106E, the drift control region 3 is defined by each p-type doped region 32 of the semiconductor layer deposited first, and by a region 31 of the n-type doped semiconductor layer deposited next. A built-in diode connected to the drain region 5 is formed. In the device according to this embodiment, the drain region 5 is formed by an n-type doped region 52 of the first deposited semiconductor layer and an area 53 of the next deposited n-type doped semiconductor layer.

  A modified example of the method of FIGS. 106A to 106E will be described below with reference to FIGS. 107A to 107D.

  This method differs from the method according to the embodiment of FIG. 106 in that it includes the step of forming the source region of the MOSFET. The method, which is a modification of the method according to FIG. 107, starts with the configuration shown in FIG. 106D. A highly n-type doped semiconductor layer 9 ″ is formed in the entire region on the third semiconductor layer 9 ′ extending from the surface 101. The heavily n-type doped semiconductor layer 9 ″ A later source region is partially formed. The semiconductor region 9 ″ is formed, for example, by ion implantation through the surface 101 of the semiconductor substrate.

  In FIG. 107B, an insulating region 72 is formed above the trench containing the dielectric material. These insulating regions are formed by first depositing an insulating layer and patterning the insulating layer. The insulating region 72 has a function of electrically insulating the source electrode and the gate electrode after the element from each other by the method described above. The dimensions of the insulating regions 72 located above these trenches are such that each of these insulating regions 72 is partially doped with the heavily doped semiconductor region 9 "on both sides of the trench adjacent horizontally in the semiconductor substrate. Selected to overlap.

  In FIG. 107C, the heavily n-type doped semiconductor layer 9 ″ is removed in the region not covered by the insulating area 72. This is because the semiconductor layer 9 is etched by anisotropic etching using an etchant. Can be performed by selectively etching the insulating region 72. After the etching is completed, the base material region 8 and the semiconductor region 152 that partially form the later gate electrode are partially exposed from the region of the surface 101 of the semiconductor base material.

  In the method according to the embodiment described with reference to FIG. 107, the areas 9 and 154 of the heavily doped semiconductor layer 9 ″ remain in the insulating area 72 on both sides of the trench containing dielectric material. In this embodiment, the n-type doped region 9 remaining above the substrate region 8 forms the source region of the later device. The remaining area 154 of the heavily doped layer 9 " It does not have a functional function, and is merely generated as a result of the manufacturing method in the present embodiment.

  In FIG. 107D, the source electrode 13 is formed above the base region 8 and the connection region 151 of the gate electrode 15 above the p-type doped semiconductor region of the gate electrode 15. If necessary, before forming the electrodes 13 and 151, the semiconductor regions 81 and 153 doped at a higher concentration than the base region 8 and the semiconductor region 152 are formed in the base region 8 and the semiconductor region 152. May be.

  These regions 81 and 153 that are more highly doped are formed in order to connect the electrodes 13 and 151 to the base material region 8 and the p-type semiconductor region 152 with low resistance. In the semiconductor device according to the embodiment of FIG. 107D, the source region 9 and the source electrode 13 are connected in a region where the source region 9 is adjacent to the source electrode 13 in the horizontal direction.

  Another method for forming the semiconductor device shown in FIG. 107D is described below with reference to FIGS. 108A-108F. In the method according to the present embodiment, first, a semiconductor substrate 1 having a highly doped semiconductor substrate 51 (for example, an n-type substrate) is provided. Then, a semiconductor layer 2 ′ doped at a lower concentration is formed on the semiconductor substrate. The semiconductor layer 2 'partially forms a drift region after the device. If necessary, a heavily doped semiconductor layer 53 ′ may be formed on the semiconductor substrate 51 before the lightly doped semiconductor layer 2 ′ is formed.

  Next, a trench 10 extending from the surface 101 of the semiconductor substrate is formed. These trenches extend in the vertical direction in the semiconductor substrate 51. These trenches are basically formed by forming a mask 200 above the surface 101 and selectively etching a semiconductor substrate in a region not covered by the mask 200 according to a known method.

  Next, in FIG. 108C, a dielectric is formed on the side wall of the trench 10 formed as described above. These dielectrics form the later gate dielectric 16 and storage dielectric 4. Formation of the dielectric on the side wall of the trench 10 is performed, for example, by first thermally oxidizing the semiconductor substrate and removing the obtained thermal oxide from the bottom of the trench 10. Removal of the oxide layer or dielectric layer from the bottom of the trench 10 can be performed by anisotropic etching.

  In FIG. 108D, a single crystal semiconductor material having a plurality of differently doped areas is introduced into the trench. This semiconductor material can be formed by an epitaxy method. A p-type doped semiconductor area 32 directly adjacent to the semiconductor substrate 51 is formed by this method. Above the p-doped region 32, a lightly n-doped semiconductor material is formed. The semiconductor material partially forms the later drift control region 3. If necessary, a semiconductor region 31 that is n-type doped at a higher concentration than the drift control region 3 can be formed between the p-type region 32 and the drift control region 3. The semiconductor region partially forms a later built-in diode.

  In FIG. 108E, p-type doped semiconductor regions 8 and 152 are formed in the region of the surface 101 of the obtained semiconductor substrate 1. Each of these semiconductor regions forms a base material region 8 in a region above the drift region 2 and partially forms a gate electrode of a later MOSFET above the drift control region 3. Each of these p-type regions 8 and 152 is formed, for example, by implanting p-type dopant atoms and then performing a corresponding annealing step.

  Subsequent to the formation of the p-type regions 8 and 152, the step of forming the source region 9 already described with reference to FIGS. 107A to 107D, the step of forming the source electrode 13, and the step of completing the gate electrode 15 Is done. FIG. 108F shows a cross-sectional view of the completed device.

  FIG. 109 shows a cross section of a variation of the MOSFET shown in FIG. 107D. In the element according to the present embodiment, the storage dielectric 4 is formed in the region between the drift control region 3 and the drift region 2, and the gate dielectric is formed in the region between the gate electrode 15 and the substrate region 8. Is formed as a multilayer structure. This element structure has, for example, two oxide layers 4A and 4C. These oxide layers 4A and 4C are directly adjacent to the drift region 2 on one side surface of the trench and directly adjacent to the drift control region 3 on the other side surface of the trench.

  Between the oxide layer 4A and the oxide layer 4C, a dielectric layer 4B preferably having a higher dielectric constant than the oxide layer 4A and the oxide layer 4C is disposed. The advantage of forming the dielectric layer as a stacked layer having a plurality of dielectric layers is that when a dielectric material having a high dielectric constant (for example, more than 15) is used, the drift control region 3 and the drift region 2 are used. The trench for forming the dielectric layer can be formed wider than in the case of using a single oxide layer without impairing the capacitive coupling between them.

  FIG. 110 shows a variation of the element shown in FIG. In the element according to this embodiment, a multilayer dielectric layer extends from the front surface 101 to the back surface 102 of the semiconductor substrate 100.

  When the voltage difference between drift control region 3 and drift region 2 is a certain value, the amount of charge carriers accumulated in drift region 2 is formed by drift region 2, drift control region 3 and storage dielectric 4. Depends on the stored capacitance. In this case, as the capacitance increases, the accumulated charge also increases. When the thickness of the storage dielectric 4 is a certain value, the dielectric constant of the storage dielectric increases as the capacitance increases. When the accumulated capacitance is a certain value, the required thickness of the accumulated dielectric is smaller as the dielectric constant is lower.

When silicon dioxide (SiO ₂ ) is used as the material for the storage dielectric, the thickness of the storage dielectric generally needs to be 200 nm or less in order to obtain a sufficient storage effect. However, dielectric layers that are so thin and extend deeper are difficult to form.

In this case, an embodiment of the present invention provides a storage dielectric, part or all of which is made of a material having an intermediate dielectric constant, so-called medium dielectric constant material. Such materials are distinguished by a relative dielectric constant or dielectric constant of about 7-25. By using such a material, it becomes possible to use a storage dielectric thicker than SiO ₂ , so that formation is facilitated.

As a material suitable for this, for example, silicon nitride (SiN) whose dielectric constant is 7.5 that is about twice that of SiO ₂ , or 9.7 that is about 2.5 times that of SiO ₂ is used. A silicon carbide (SiC) is mentioned. Unlike the so-called high dielectric constant material, the medium dielectric constant material can be formed by a standard process used in the manufacture of semiconductor elements.

In each of the elements described above, the storage dielectric 4 made of a medium dielectric constant material can be formed. For example, in each element according to FIGS. 11, 109, and 110, for example, the layer 4b in the middle of the plurality of dielectric layers may be formed of a medium dielectric constant material, and the outer layers 4a and 4c are It may be made of a material having a lower dielectric constant (for example, SiO ₂ ). In this case, the intermediate layer 4b may be a very thick layer, for example, 5 to 10 times thicker than the outer layers 4a and 4c.

  Further, the storage dielectric 4 positioned between the drift region 2 and the drift control region 3 is formed from a medium dielectric constant material, and the dielectric that separates the other regions of the element from the dielectric constant It is also possible to form from a low material. For example, in the element according to the embodiment of FIG. 19, the other region is the base material region 8 and the connection region 33 that can be separated by a dielectric having a lower dielectric constant. The connection region 31 and the drain region 5 are separable by a dielectric having a lower dielectric constant.

  As another embodiment, in the device according to FIG. 16, a dielectric layer located between the p-type doped semiconductor regions 33 and 34, the base region 8 and the short circuit region 17 is formed from a medium dielectric constant material. Thus, the internal storage capacitance of the element can be increased.

  In this case, the storage dielectric 4 located between the drift region 2 and the drift control region 3 is formed from a material having a lower dielectric constant. The storage dielectric 4 can also be formed from a medium dielectric constant material to increase the internal storage capacitance. In this case, the dielectric layer located between the p-type doped semiconductor regions 33 and 34 and the substrate region 8 and the short circuit region 17 is formed from a high dielectric constant material.

  The semiconductor device according to the present invention has been described based on a vertical power device, that is, a device in which a current flows in a vertical direction in a drift region. In this case, the drift region includes a first component region (corresponding to a source region in the case of a MOSFET and a Schottky metal in the case of a Schottky diode) and a second element region in the semiconductor substrate 100. (Corresponding to the drain region in the case of MOSFET and corresponding to the cathode region in the case of Schottky diode).

  As will be described below, the concept according to the present invention in which the storage dielectric and the drift control region are formed adjacent to the drift region of the semiconductor element can be applied to a lateral element.

  A typical embodiment of a lateral semiconductor device is described below. A cross-sectional view of a semiconductor substrate 100 having a first surface 101 referred to below as a front surface and a second surface 102 facing the first surface and referred to as a back surface below. This will be described below with reference to FIG. The vertical direction v of the semiconductor substrate is a direction extending perpendicularly to the front surface 101 and the back surface 102 between the front surface 101 and the back surface 102.

  The horizontal direction of the semiconductor substrate is a direction extending in parallel along the front surface 101 and the back surface 102, that is, a direction extending in a direction perpendicular to the vertical direction v. Hereinafter, the cross section refers to a cross section along the front surface 101 and the back surface 102, and the vertical cross section refers to a cross section perpendicular to the front surface 101 and the back surface 102.

  For an exemplary embodiment of a semiconductor device according to the present invention formed as a MOSFET, without limiting the general effectiveness of the present invention, an n-type doped drift region 211 and a p-type doped substrate. The description will be based on an n-channel MOSFET (n-MOSFET) having a region 212 and an n-type doped source region 213 and drain region 214. However, the drift region 211 of the n-channel MOSFET may be an undoped region, that is, an intrinsic doped region.

  However, it goes without saying that the present invention can also be applied to p-channel MOSFETs (p-MOSFETs). In the case of a p-MOSFET, the element region having the semiconductor substrate 103 already described in the form of an n-MOSFET must be complementarily doped.

  111A to 111D show an exemplary embodiment of a lateral power semiconductor device according to the present invention formed as a MOSFET, and various embodiments of a semiconductor substrate 100 in which a plurality of MOSFET device structures are integrally formed. The cross section is shown. FIG. 111A shows the semiconductor substrate 100 in the cross section ZZ. 111B and 111C show the semiconductor substrate 100 in two different vertical cross sections AA and BB, and a cross section of the semiconductor substrate 100 is shown in FIG. 111A. FIG. 111D is a partial perspective view showing a part of the semiconductor substrate 100.

  The power MOSFET shown in FIG. 111 has a source region 213 and a drain region 214 that are spaced apart from each other in the first horizontal direction x of the semiconductor substrate 100 and are n-type doped. ing. The drift region 211 is adjacent to the drain region 214.

  The drift region 211 has the same conductivity type as the drain region 214 in this embodiment, but may be doped at a lower concentration than the drain region 214 or may not be doped. . Between the source region 212 and the drift region 211, a base material region 212 that is complementarily doped with respect to the source region 213 and the drift region 211 is disposed.

  The base material region forms a pn junction with the drift region 211. When the element is turned off, a space charge region (depletion zone) spreads in the drift region 211 from the pn junction. Similarly, the base material region 212 is arranged at a distance from the drain region 214 in the first horizontal direction x.

  A gate electrode 221 is disposed to control the inversion channel 215 disposed in the base material region 212 between the source region 213 and the drift region 211. The gate electrode is disposed so as to be insulated from the semiconductor substrate 100 by the gate dielectric 222. The gate electrode 221 is disposed adjacent to the base material region 212 and extends from the source region 213 to the drift region 211. When an appropriate drive potential is applied to the gate electrode 221, an inversion channel is formed in the substrate region 212 along the gate dielectric 222 between the source region 213 and the drift region 211.

  In the illustrated embodiment, the surface 101 of the semiconductor substrate 100 is formed in the substrate region 212 so that the inversion channel 215 is formed in the first horizontal direction x along the surface 101 of the semiconductor substrate 100. A gate electrode 221 is disposed above the gate electrode 221. The gate electrode is not shown in the perspective view of FIG. 111D for clarity.

  The source region 213 is connected to the source electrode 231, and the drain region 214 is connected to the drain electrode 232. Each of these is arranged above the surface in the present embodiment, and their arrangement position with respect to each semiconductor region is indicated by a broken line in FIG. 111A. In the present embodiment, the source electrode 231 is also connected to the base material region 212 in order to short-circuit the source region 213 and the base material region 212.

  In the present embodiment, the source region 213, the base material region 212, and the drain region 214 are disposed in the semiconductor layer 104 that has been subjected to n-type basic doping. Referring also to FIG. 111A, the source region 213, the base material region 212, and the drain region 214 extend in a strip shape along a second horizontal direction y that is perpendicular to the first horizontal direction x. Similarly, the gate electrode 221, the source electrode 231, and the drain electrode 232 extend in a strip shape along the second horizontal direction y.

  The power MOSFET has a plurality of drift control regions 241 formed of a doped semiconductor material or an undoped semiconductor material. These drift control regions 241 are disposed adjacent to the drift region 221 in the semiconductor substrate 104, and are insulated from the drift region 211 by the first dielectric layer.

  The above-mentioned region of the dielectric layer disposed directly between the drift region 211 and the drift control region 241 is hereinafter referred to as a storage dielectric 251. Each of these drift control regions 241 is a region adjacent to the storage dielectric 251 in a direction orthogonal to the region of the storage dielectric 251. Accordingly, each of these drift control regions 241 is suitable for controlling a storage channel in the drift region 211 as described below.

  Drift control region 241 is coupled to drain region 214. In the illustrated embodiment, the drain region 214 is formed by a drift control region 241 connected to the drain electrode 232 via the connection region 242. The connection region 242 has the same conductivity type as the drift control region 241, but is doped at a higher concentration than the drift control region 241. In the present embodiment, the connection region 242 connects the drift control region 241 and the drain electrode 232 with low resistance.

  As will be described below, each drift control region 241 can also be connected to the drain electrode 232 via a diode. In the case of an n-channel MOSFET, a forward bias is applied to the diode in the direction from the drain electrode 232 to the drift control region 241.

  The diode may also be formed by a pn junction between the drift control region 241 and the connection region 243 doped complementary to the drift control region 241 in FIG. 111C. In this embodiment, the drain electrode 232 is connected to a connection region 243 that is complementarily doped.

  If desired, a complementary doped connection region 243 can be incorporated in the connection region 242 that has the same conductivity type as the drift control region, as shown in FIG. 111C. In this case, the pn junction is formed between the connection regions 242 and 243.

  In another embodiment, the drift control region 241 is the same conductivity type as the substrate region 212, but is doped at a lower concentration than the substrate region 212, or is not itself doped (intrinsic).

  In this embodiment, each drift control region 241 has a plate shape or a strip shape. The drift control regions 241 are arranged at a distance from each other in the second horizontal direction y, and are arranged adjacent to the areas of the drift region 211. In this embodiment, a layer structure or a plate structure in which the drift regions 211 and the drift control regions 241 are alternately arranged while being separated by the storage dielectric exists along the second horizontal direction.

  The drift control region 241 extends in the vertical direction v from the surface 101 of the semiconductor substrate 100 into the semiconductor substrate 100. In the illustrated embodiment, these drift control regions extend to the semiconductor substrate 103 and are insulated from the semiconductor substrate 103 by another insulating layer 252 (eg, an oxide layer).

  In this embodiment, the conductivity type of the substrate 103 is complementary to the drift region 211. These drift control regions extend from the drain region 214 in the first horizontal direction x and are electrically coupled to the drain region 214 in the direction of the substrate region 212. In this embodiment, these drift control regions 241 may terminate before the substrate region 212 in the first horizontal direction x, or may extend into the substrate region 212 (not shown). .

  As described in detail below, each drift control region 241 controls a storage channel disposed in the drift region 211 along the storage dielectric 251 when the element is turned on. The drift control region 241 is formed so as to extend as close as possible to the region where the inversion channel 215 (FIG. 111B) of the base material region 212 controlled by the gate electrode 221 transitions to the drift region 211. Is preferred.

  In the element according to the embodiment of FIG. 111, the inversion channel 215 is formed below the surface 101 of the semiconductor substrate 100. For this reason, the drift control region extends to the surface 101 in the vertical direction v, and substantially extends to the base material region 212 in the first horizontal direction x.

  The inversion channel 215 and the storage channel (shown by reference numeral 216 in FIG. 111A) formed along the storage dielectric 251 of the drift control region 241 in the drift region 211 rotate at an angle of 90 degrees with each other. It is extended in the state that was done. The inversion channel 215 extends along the surface 101 of the semiconductor substrate 100. On the other hand, the storage channel 216 is formed along the “side wall” extending in the vertical direction in the drift control region 241 in the storage dielectric in the drift region 211. In the element according to the present embodiment, the current direction corresponds to the first horizontal direction x of the semiconductor substrate.

  The drift control region 241 is a doped or undoped semiconductor material (preferably a single crystal) and has the same conductivity type as the doping of the drift region 211 or complementary to the doping of the drift region 211. It is made of a semiconductor material having a good conductivity type. Drift characteristics of drift control region 241 in the direction in which drift control region 241 and drift region 211 extend in parallel between drain region 214 and substrate region 212, that is, in the first horizontal direction x shown in FIG. Is preferably the same as the doping characteristics of the area of the drift region 211 extending in the same direction as the drift control region 241 in the same direction.

  These drift control regions 241 extend in a direction transverse to the current direction (that is, the second horizontal direction y in the present embodiment) and a semiconductor area that can be completely depleted by an electric field in the same direction. The drift control region 241 is doped so as to have at least one in the entire width.

  In particular, each drift control region 241 can be fully depleted. This is achieved when the index of net dopant charge in the drift control region 241 and storage dielectric 251 regions is less than the breakdown charge of the semiconductor material in the drift control region 241. In this case, the net dopant charge indicates the integral of the net dopant concentration of the drift control region 241 with respect to the volume of the drift control region 241.

  In this case, the index must be determined using only the region of the storage dielectric 251 located directly between the drift control region 241 and the drift region 211 in the embodiment shown in FIG. . In the case where the drift control region 241 is adjacent to the drift region 211 in the second horizontal direction y and separated from both sides by the storage dielectric 251, the index is located on both sides of the drift control region 241. It must be determined using the area of the storage dielectric 251.

  To further illustrate this, one of the plurality of drift control regions 241 is considered below. In FIG. 111, these drift control regions 241 include a dielectric layer 251 forming a storage dielectric on each of two surfaces, a surface in the second horizontal direction y and a surface in the direction of the base material region 212. Borders.

  In the following, special forms are assumed for explanation. In this special form, each drift control region 241 is uniformly doped with the same conductivity type as the drain region 214. In addition, the region 254 of the dielectric layer 251 that borders the drift control region 241 in the direction of the base material region 212 separates the drift control region 241 from the drift region 211 in the second horizontal direction y. It is smaller than “each horizontal region” of the dielectric layer 251.

In this particular form, the above-described doping specification is that the ionized dopant of the drift control region 241 in the direction r perpendicular to the dielectric layer 251 (corresponding to the second horizontal direction y in this embodiment). The integration of the concentration is equivalent to being less than twice the value of the dielectric breakdown charge of the semiconductor material forming the drift control region 241. When silicon is used as the semiconductor material, the breakdown charge is about 1.2 × 10 ¹² e / cm ² (e is the basic charge).

  When considering a uniformly doped drift control region (not shown in detail) that is adjacent to only one side of the drift region that is separated from the drift control region by a storage dielectric, for the dielectric layer It is necessary for this drift control region that the integration of the dopant concentration in the vertical direction be less than the value of the breakdown charge.

  By conforming to the above-described doping specifications for the drift control region 241, a semiconductor that forms the drift control region 241 in the direction of the dielectric layer 251 in the drift control region 241 regardless of the potential in the drift region 211. The effect is that an electric field that is always lower than the breakdown electric field strength of the material is constructed.

  These drift control regions 241 are preferably formed of the same material and the same doping concentration as the semiconductor material forming the drift region 211. The dimensions of the drift control region 241, particularly the dimension in the second horizontal direction y, are selected so as to satisfy the conditions described above in relation to the net dopant charge relative to the area of the dielectric layer 251.

  Regarding the above-described lateral power MOSFET, a function for turning on the element and a function for turning off the element will be described first.

  The MOSFET has an appropriate voltage (a positive voltage in the case of an n-channel MOSFET) applied between the drain region 214 and the source region 212 or the drain electrode 232 when an appropriate driving potential is applied to the gate electrode 221. When applied between the source electrode 231 and the source electrode 231, it is turned on. In the case of a p-channel MOSFET, the voltages or potentials need to be reversed with respect to each other.

  In the present embodiment, the potential of the drift control region 241 connected to the drain electrode 232 follows the potential of the drain region 214. In this case, when the drift control region 241 is connected to the drain region 214 via the pn junction, the potential of the drift control region 241 is equal to the forward voltage of the pn junction than the potential of the drain region 214. Can be lowered.

  When the element is turned on, the potential in the drift region 211 decreases in the direction of the base material region 212 due to the inevitable electrical resistance of the drift region 211. Therefore, as the potential of the drift control region 241 connected to the drain electrode 232 becomes higher than the potential of the drift region 211 and the distance from the drain region 214 in the direction of the base material region 212 is larger, the potential difference in the storage dielectric 251 is increased. Becomes larger. This potential difference provides an effect that a storage region or a storage channel in which charge carriers are stored is generated in the drift region 211 adjacent to the storage dielectric 251.

  As seen in this embodiment, these charge carriers are electrons when the potential in the drift control region 241 is higher than that of the drift region 211, and are holes in the opposite state. Unlike conventional devices that have a drift region doped according to the drift region 211 but do not have a drift control region, the storage channel reduces the on-resistance of the device.

  The accumulation effect obtained in the element includes not only the voltage difference between the drift control region 241 and the drift region 211 but also the thickness of the accumulation dielectric 251 in the second horizontal direction y (d in FIG. 111A) and the accumulation. It depends on the dielectric constant (dielectric constant) of the dielectric. In this case, the storage effect becomes stronger as the thickness d of the storage dielectric 251 decreases and as the dielectric constant increases. When the device is turned on, the minimum thickness of the dielectric is obtained from the maximum potential difference between the drift control region 241 and the drift region 211, and hence the maximum allowable permanent field strength load of the storage dielectric.

  As a material suitable for the storage dielectric 251, for example, a semiconductor oxide of a semiconductor material (for example, silicon) used for forming the drift region 211 or the drift control region 241 can be given. If the storage dielectric 251 is typically below a typical permanent voltage load of about 100V (eg, 5-20V), and if silicon oxide is used as the material of the storage dielectric 251, the thickness d of the dielectric 251 Is less than about 500 nm, preferably in the range of about 25 nm to about 150 nm.

  The above element has a drain-source voltage (a positive drain-source voltage in the case of an n-channel MOSFET) between the drain region 214 and the source region 213 when an appropriate driving potential does not exist in the gate electrode 221. ), That is, a voltage (a positive voltage in the case of an n-channel MOSFET) is present, the device is turned off. As a result, a reverse bias is applied to the pn junction between the drift region 211 and the base material region 212 so that a space charge region is formed in the direction of the drain region 214 from the pn junction in the drift region 211. Applied. In this case, the reverse voltage in the drift region 211 decreases. That is, the voltage in the drift region 211 substantially corresponds to the reverse voltage.

  In the off state, the space charge region expands in the drift region 211, so that the space charge region also expands in the drift control region 241 of the element. This space charge region is essentially caused by the low doping concentration of the drift control region by complying with the doping specifications described above in connection with the drift control region 241. In this case, the voltage drop in the storage dielectric 251 is limited to the maximum value obtained as follows.

The storage dielectric 251 _having a thickness d _accu forms a capacitance together with the drift control region 241 and the drift region 211. The capacitance C ′ related to the area is obtained as follows.
C ′ = ε ₀ ε _r / d _accu (4)
In this case, ε ₀ represents the permittivity of free space, and ε _r represents the relative permittivity of the dielectric used. The relative dielectric constant is about 4 in the case of silicon oxide (SiO ₂ ).

The voltage in the dielectric 251 depends on the electric charge accumulated by a known method as shown in the following equation.
U = Q '/ C' (5)
Q ′ represents the accumulated charge with respect to the area of the dielectric 251.

The charge that can be accumulated by the capacitance is limited by the net dopant charge in the drift control region 241. Assuming that the net dopant charge in the drift control region 241 with respect to the area of the dielectric is less than the dielectric breakdown charge Q _Br , the following equation (6) is established for the voltage U present in the dielectric 251.

Therefore, the maximum voltage existing in the dielectric 251 increases linearly according to the thickness d _accu of the dielectric 251. That is, the maximum voltage is a first approximation that is approximately the same as the dielectric strength of the dielectric 251. When SiO ₂ having an ε _{r of} approximately 4 and a thickness of 100 nm is used, the maximum voltage load U is 6.8V. This value is far below about 20 V, which is a value that allows continuous loading when such an oxide is used. In this case, the dielectric breakdown charge of silicon is about 1.2 × 10 ¹² / cm ² .

  Accordingly, a space charge region is formed in the drift control region 241 in the off state. This space charge region may have a potential profile that differs from the potential profile of the drift region 211 by a voltage that is present in the dielectric 251 and limited by the low doping of the drift control region. In this case, the voltage at the storage dielectric 251 is always lower than its withstand voltage.

  The dielectric strength of the device is determined by the doping concentration of the drift region 211 and the dimension of the drift region 211 in the direction in which the space charge region expands (that is, the first horizontal direction x in the device according to the embodiment of FIG. 111). It is decided. This dimension is referred to below as the “length” of the drift region 211. In this case, when a sufficiently low concentration of doping is applied, the dielectric strength increases as the length increases, and depends almost linearly on the length. When silicon is used as the semiconductor material, a length of about 10 μm is required to obtain a dielectric strength of 100V. The dielectric strength decreases as the doping concentration of the drift region 211 increases.

  The on-resistance of the device according to the present invention depends on the formation of the accumulation channel and also slightly depends on the doping concentration of the drift region 211. In the element according to the present invention, the drift region 211 can be doped at a low concentration in order to obtain a high dielectric strength, and a low on-resistance can be obtained by controlling the accumulation channel by the drift control region 241.

In this case, the maximum dopant concentration N of the drift region 211 is the critical electric field intensity E _crit at which breakdown occurs in the semiconductor material due to the avalanche phenomenon (avalanche breakdown) when in the off state and the voltage U _max to be cut off. And depends on. The critical electric field strength E _crit is about 200 kV / cm when silicon is used. When the pn junction is a single-sided step junction, the relationship of the following formula (7) is established between doping and the reverse voltage.

Therefore, in the case of a silicon device having a withstand voltage characteristic of 600 V, the donor or acceptor doping N of the drift region 211 needs to be less than about 2 · 10 ¹⁴ / cm ³ .

  For the reasons described above, the voltage load on the storage dielectric 251 is always lower than the maximum voltage that can be loaded on the storage dielectric 251 when the typical dimension setting as described above is performed. For this reason, the storage dielectric 251 does not limit the dielectric strength of the element, unlike the known field plate, when the typical dimension setting as described above is performed.

  In the case of the element described with reference to FIGS. 111A to 111D, the drift control region 241 is connected only to the drain region 214. When the element is turned off, holes are accumulated in the drift control region 241 (in this embodiment, n-type doped) by the heat generated by the electron-hole pairs, and these accumulated holes flow out. There is nothing. The amount of stored charge increases over time until the maximum field strength of the storage dielectric 251 is reached and the dielectric 251 is destroyed.

  FIG. 112 referred to shows a modification of the element based on FIG. When the electric field strength of the tunnel dielectric 253 reaches the dielectric breakdown value due to the characteristics of the storage dielectric 251 partially provided as the tunnel dielectric 253, the above-described modification example has the electric field strength of the remaining storage dielectric 251. Even before reaching the dielectric breakdown value, each accumulated charge carrier immediately flows out into the drift region 211. An exemplary embodiment is illustrated in FIG. 112, where the tunnel dielectric 253 is disposed in the region of the end of each drift control region 241 on the side facing the substrate region 212.

As the tunnel dielectric, for example, each layer of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), or another multilayer structure made of silicon oxide and silicon nitride is suitable. A mixed dielectric composed of silicon, oxygen, and nitrogen is also applicable as a tunnel dielectric. Generally, the electric field strength of the dielectric breakdown due to the tunnel effect is in the range of 1 V / nm to 2 V / nm. In the tunnel oxide 253 having a thickness of 13 nm, the above range results in a maximum voltage of 13V-26V. The maximum voltage is higher than the voltage present at the storage dielectric 251 during the normal off state. Further, for example, the storage dielectric 251 made of silicon oxide having a thickness of 100 nm can withstand the maximum voltage without any problem.

  FIG. 113 is a perspective view showing an essential part of another modified example of the element based on FIG. The drain and source electrodes in contact with the drain and source regions 214 and 213 illustrated in FIG. 111D are not shown in the device shown in FIG. 113 for reasons of brevity.

  In the element, the semiconductor substrate 100 is embodied as a so-called SOI substrate, and includes a continuous insulating layer 105 between the semiconductor substrate 103 and the semiconductor layer 104. In the semiconductor layer 104, a drift region 211, a drift control region 241, and drain and source regions 213 and 214 are also integrated and integrated. In the above case, the insulating layer is made of a semiconductor oxide and, for example, insulates both the drift region 211 and the drift control region 241 from the substrate 103. The semiconductor substrate 103 may have the same conductivity type as that of the semiconductor layer 104 or may have a conductivity type opposite to that of the semiconductor layer 104.

  During operation in the off state, each cutout portion 106 is provided below the source region 213 and / or in order to prevent undesired accumulation of charge carriers in the substrate 103 at the interface with the insulating layer 105. The insulating layer 105 may be provided below the drain region 214. Each cutout 106 is filled with a doped or undoped semiconductor material that forms a connection region 226 between the drift region 211 and the substrate 103.

  When each of the cutout portions 106 is provided, the drain region 214, that is, the connection region 226 below the drain electrode is used to dissipate the electrons accumulated in the substrate 103 at the interface portion with the insulating layer 105 to the drain region 214. Is preferred. When holes are accumulated in the substrate 103 at the interface with the insulating layer 105, the connection region 226 below the source region 213 is suitable for dissipating the holes into the source region 213.

  In the case of the element according to FIG. 113, the gate electrode 221 is arranged above the surface 101 of the semiconductor substrate 100 of the element of FIG. The gate electrode 221 and the gate dielectric located under the gate electrode 221 are formed in a strip shape, and extend along the second horizontal direction y in accordance with the width b of each section of the drift region, for example. It is formed as follows. The width b of the drift region 211 is set by the distance between two drift control regions 241 adjacent to each other.

  As not shown in detail, the gate electrode 221 may extend over the entire region of the semiconductor substrate 100 along the second horizontal direction y, and each drift control region 241 and You may extend over each part of the semiconductor substrate 100 in which each area of the drift region 211 is disposed.

  In the above connection, the horizontal overlap of the gate electrode 221 on the drift control region 241 is allowed, and the drift control region 241 has a length in the second horizontal direction y as in the formation of the gate electrode 221. Note that is less than the length of the drift region 211 in the second horizontal direction y.

  114A to 114D show still another modification of the power MOSFET according to the present invention shown in FIG. Based on FIGS. 111A to 111D, FIG. 114A shows the element in a horizontal section close to the surface 101, and FIGS. 114B and 114C show the CC line and DD line shown in FIG. 111A. FIG. 114D shows a perspective view of a partial cross-section of the element, each showing two different vertical sections of the element as seen from the arrows.

  Each drift control region 241 in the case of the element based on FIG. 111 has only one connection region 242 for connection to the drain region 214, that is, the drain electrode 232, while each drift control region 241 based on FIG. 114. Each have a second connection region 244 arranged away from the first connection region 242 along the first horizontal direction x.

  As described above, each second connection region 244 may have the same doping conductivity type as the drift control region 241, but each second connection region 244 is complementary to the drift control region 241. It is good also as a doping conductivity type. In the illustrated embodiment, each external dimension of each second connection region 244 matches each external dimension of each base material region 212 arranged adjacent to each other in the second horizontal direction y.

  Therefore, each second connection region 244 is formed along the first horizontal direction x from the surface position of each substrate region 212, and in the vertical direction v to the same depth as each substrate region 212. Along the inside of the semiconductor substrate 100. The formation of each second connection region 244 can be achieved by manufacturing each substrate region 212 and each second connection region 244 by the same method steps, ie, the same ion implantation and / or diffusion method steps. .

  However, it should be pointed out that the horizontal and vertical dimensions of the semiconductor substrate 100 in each second connection region 244 need not necessarily match the respective substrate regions 212. The drift control region 241 and the substrate region 212 may overlap each other in the first horizontal direction x of the semiconductor substrate 100 as illustrated in FIG. 115 corresponding to the cross section of FIG. 114A. .

  In order to avoid the effect of the drift control region 241 on the switching characteristics of the element of the present embodiment, each semiconductor region 216 that is highly doped with the same conductivity type as the base region 212 is formed in the base region 212. Is provided adjacent to the drift control region 241.

  Each boundary between each second connection region 244 and each heavily doped semiconductor region 216 may also be offset from each other in the first horizontal direction x, that is, different from each other, unlike FIG. .

  In the case of the element in FIG. 114A, the source region 213 and the base material region 212 are connected and connected by the source electrode 231. On the other hand, the drain region 214, that is, the plurality of drain region portions are connected by the drain electrode, that is, each drain electrode portion 232.

  In the present embodiment, each first connection region 242 of each drift control region 241 is connected to the first connection electrode s 233, and internal connection by each drain electrode 232 will be described below. Each second connection region of each drift control region 241 is connected to each second connection electrode of each drift control region 241. The other similar internal connections will be described below.

  In the case of the power MOSFET shown in FIGS. 114A to 114D, the gate electrode 221 has a plurality of gate electrode portions. Each of the plurality of gate electrode portions extends along the second horizontal direction y only on the individual width of each drift region 211.

  According to FIG. 114D, the gate dielectric 222 may be formed as a continuous strip-type dielectric layer in this embodiment. 114B and 114C indicate an insulating layer or a protective layer. The insulating layer or the protective layer insulates the gate electrode 221 from the source electrode 231 and covers each drift region 211 and each drift control region 241 on the surface 101 of the semiconductor substrate.

  Although not shown in detail, each dimension of each gate electrode 221 and / or gate dielectric 222 along the second horizontal direction y is equal to each dimension of each drift region 211 along the second horizontal direction y. And may be different. Therefore, the common gate electrode 221 may be specifically provided as a continuous electrode layer in alignment with the gate dielectric 222 shown in FIG. 114D.

  Referring to FIG. 116 showing an element of a modified example of the element based on FIG. 114, the gate electrode 221 may be realized as a strip-type electrode 221 continuous along the second horizontal direction y. Therefore, the strip-type electrode 221 is formed on each base material region 212, on each drift control region 241 or on each second connection region (not shown in FIG. 116) of each drift control region 241. 2 extends in the horizontal direction y.

  FIG. 117 shows another modification of the power MOSFET shown in FIG. In the element of the other modification described above, the semiconductor substrate is realized as an SOI substrate based on the element shown in FIG. 113, and also includes the semiconductor substrate 103, the insulating layer 105 disposed on the semiconductor substrate 103, and the semiconductor layer 104. ing. The semiconductor layer 104 is disposed on the insulating layer. In the semiconductor layer 104, each drift region 211, each drift control region 241, each source region 213, each substrate region 212, each drain region 214, and each connection region s 242, 244 of each drift control region 241. Also arranged.

  In the element shown in FIG. 117, the gate electrode 221 is formed to extend only within the range of the width of the drift region 211, but may be formed to have a different size from the width of the drift region 211. The gate electrode 221 may be realized as a continuous strip-type gate electrode (not shown) like the element shown in FIG.

  Various connection methods of the drift control region 241 or the drift control region 241 with the first and second connection electrodes will be described below.

  118A and 118B, the drift control region 241 is connected to the drain region 214, that is, the drain electrode 232 via the first diode 261 located at the drain side end, and A configuration for connecting to the source region, that is, the source electrode 231 via the second diode 262 located at the source side end is provided. In the present embodiment, each of these two diodes 261 and 262 is incorporated in the semiconductor substrate 100.

  The first diode 261 is formed by the connection regions 242 and 243 described in relation to the element of FIG. The connection region 242 has the same conductivity type as the drift control region 241, and the connection region 243 is doped complementarily to the drift control region 241. In the element of the present embodiment, the drain electrode 232 and the first connection electrode 233 are realized as a common electrode formed in a strip shape, and are complementary to each drift region 241 and each first connection region 242. Is connected to each connection region 243 doped with.

  The first diode 261 may be realized as an external diode (not shown) between the drain electrode 232 and the first connection electrode 234.

  In the present embodiment, the second diode 262 depends on the physical properties of the second connection region 244 in each drift control region 241 that is realized as each semiconductor region that is doped complementarily to each drift control region 241. It has been realized. In the present embodiment, the source electrode 231 and the second connection electrode 234 are electrically connected to each other, and based on the drain electrode 232 illustrated in FIG. 118B, a common strip-type electrode (not illustrated). ).

  In order to reduce the connection resistance between the second connection electrode 234 and the second connection region 244, a more highly doped semiconductor region 245 may be provided in the second connection region 244, if necessary. It may be formed and connected to the second connection region 244 by the second connection electrode 234.

  Each function of the element illustrated in FIGS. 118A and 118B will be described below.

  The illustrated n-channel MOSFET is switched to an ON state when an appropriate driving potential is applied to the gate electrode 221 and a positive potential is applied between the drain and source. As a result, an inversion channel is formed in the base material region 212 between the source region 213 and the drift region 211. During the operating state, the first diode 261 is forward biased. On the other hand, the second diode 262 is biased in the reverse direction. In this case, the standard of the second diode 262 is set so that the dielectric strength is higher than the potential existing between the drain and the source when the element is driven in the ON state.

  The potential of the drift control region 241 corresponds to a potential obtained by subtracting the forward potential of the first diode 261 from the drain potential due to the first diode 261 biased in the forward direction during the on-operation state. The potential of the drift control region 241 due to the load current flowing in the drift region 211 and hence the bulk voltage drop generated in the drift region 211 in the direction across each wider region of the drift region 211 is The potential in the drift region 211 becomes larger. Thereby, the voltage drop that occurs across the storage dielectric 251 results in the formation of a storage channel in a region along the storage dielectric 251 in the drift region 211.

  When the device is driven off, ie, there is a high positive drain-source potential but no inversion channel is formed, a space charge region is formed in the drift control region 241. As described above, the upper limit of the voltage across the storage dielectric 251 is set by the low-concentration dopant in each drift control region 241 in the second horizontal direction y.

  The second diode 262 is reverse-biased during the driving in the off state as described above. In this case, the space charge region formed in the drift control region 241 in the off-state element and controlled by the drift region 211 protects the second diode 262 against dielectric breakdown due to voltage application.

  Preferably, the second diode 262 withstand voltage characteristic with respect to the drift control region 241 and the withstand voltage characteristic of the base material region 212 with respect to the drift region 211 are particularly created in the same method step in the second diode 262 and the base material region 212. If so, it has the same high breakdown voltage characteristic.

  In the case of the element shown in FIGS. 118A and 118B, in the OFF operation state, the second diode 262 connected to the source region, that is, the source electrode 231 through the drift control region 241 has a thermal property. Charge carriers can flow out of the drift control region 241. Therefore, it is possible to prevent the dielectric breakdown due to the voltage of the storage dielectric 251 due to the accumulation of each thermal charge carrier.

  In the present embodiment, the second function (the so-called function for trapping electric charge shown below) does not occur because each generated hole flows out through the p-type region. If the p-type region is directly connected to the source as in the case shown, no charge accumulation occurs. However, when the p-type region is connected to the source through an external diode or capacitor and through another diode, suitable for limiting the voltage within the capacitor, the charge is stored. The above-described effect occurs.

  “Capturing” charge within the drift control region 241 functions as described when an internal connection according to FIG. 120 or 121 is present. In this case, the diode 261 and / or the diode 266 may be incorporated inside or attached outside. The lower or right hand portion of the drift control region 241 simply needs to include the n + doped region 242.

  When the element is driven in the ON state, the first diode 261 in this embodiment prevents each hole from flowing from the drift control region 241 to the drain electrode 232.

  As shown in FIG. 119, the first diode 261 may be omitted. However, the omission results in increased loss in the on state. This is because no accumulation of holes in the drift control region 241 occurs, but rather only a correspondingly increased drain voltage is available for the bulk voltage drop and channel formation in the drift region. is there.

  If necessary, another diode 265 for connecting the source electrode 231 and the connection electrode 234 may be provided as shown by a broken line in FIG. Other diodes 265 may be implemented as internal or external elements, such as diode 261. The other diode 265 is connected to each p-type charge carrier, that is, each hole, in the second connection region 244 that is doped complementarily to the drift control region 241 when the device is driven in the off state. Can be stored in each region of the storage dielectric 251 adjacent to the substrate region 212 (the location of which is illustrated in broken lines).

  When the device is driven substantially on, each hole is required in the drift control region 241 to control the storage channel in the drift region 211 along the storage dielectric 251. Is done. In the switch-on state as described above, each of the holes is extracted from the drift control region near the base material region 212, and the direction of the drain region 214 or the first connection region 242 of the drift control region. Shifted in the direction.

  When the device is driven substantially on, the charge in the holes of the second diode 262 functions as a storage capacitance when the device is driven off, and the drift region 211, The storage dielectric 251 and the drift control region 241 shift to the “storage capacitance”.

  Referring to FIG. 120, the above-described charge accumulation effect may be achieved by a capacitance 263 that connects between the source electrode 231 and the second connection electrode 233. The capacitance is illustrated as a capacitor 263 in FIG. 120, and may be realized in any desired form within the semiconductor substrate or outside the semiconductor substrate.

  In order to limit the voltage generated in the capacitor 263 charged by the leakage current in the off state, a diode 266 may be provided in parallel to the capacitor 263 as shown in FIG. The standard of the dielectric breakdown voltage of the diode is set to be adapted to the dielectric strength of the capacitor 263, that is, slightly smaller than the dielectric strength of the capacitor 263.

  In the case of both the element of FIG. 120 and the element of FIG. 121, the drain of the drift control region 241 is connected to the end portion and the drain as required by the first diode 261 as indicated by a broken line in each drawing. It may be provided between the region 214, that is, the drain electrode 232.

  Specifically, the diode 261 may be connected like a diode 266 formed by an internal connection to each of the connection electrodes 233 and 234, and preferably a diode structure in a single crystal semiconductor material, or The so-called “polysilicon diode” on the single crystal semiconductor substrate 100 may be provided.

  In a further exemplary embodiment illustrated in FIG. 122, an external storage capacitance 263 is provided connected to the gate electrode 221 via another diode 264. In this embodiment, the anode of the other diode 264 is connected to the gate electrode 221, and the cathode is connected to the second connection electrode 233 or the connection portion of the electrostatic capacitance 263 facing the second connection electrode 233. Yes.

  The other diode 264 has an effect that the p-type charge carriers are sequentially supplied from the gate drive circuit. Even when the first diode 261 prevents each hole from the drift control region 241 from flowing to the drain electrode 232, each p-type charge carrier is transmitted through charge recombination or by each leakage current. Since it is inevitably lost, it needs to be supplied sequentially.

  The other diode 264, specifically, when the MOSFET is initially driven to the on state, the capacitance 263 has already been charged previously by the reverse current generated by the heat in the drift control region 241. If not, it is charged from the gate drive circuit. In this case, the diode 265 for limiting the voltage may be connected in parallel to the capacitor 263 as necessary.

  Various possibilities for incorporating an “external” capacitance 263 into the semiconductor substrate 100 are described below with reference to FIGS.

  FIG. 123 is a fragmentary cross-sectional perspective view showing a part of a semiconductor substrate having a transistor structure of a lateral MOSFET incorporated in the semiconductor substrate. For the sake of simplicity, in this embodiment, the drift region 211 formed to extend in the horizontal direction, the drift control region 241 formed to extend in the horizontal direction, and the drift region 211 and the drift control region 241 Only the storage dielectric 251 disposed therebetween is shown.

  In the present embodiment, the capacitance 263 is formed by the dielectric layer 271 formed on the back surface 102 of the semiconductor substrate 100 or the semiconductor substrate 103, the semiconductor substrate 103, and the electrode layer 272 formed on the dielectric layer 271. ing. In the present embodiment, the electrode layer 272 is connected to the source electrode of the MOSFET, although not shown in detail. Therefore, the potential at the connection site of the capacitance 263 is the source potential.

  In the present embodiment, the semiconductor substrate 103 may be directly adjacent to the drift control region 241, and the drift control region 241 and the semiconductor substrate 103 may have the same conductivity type. The second connection portion of the capacitance is formed by the substrate 103 and is directly connected to the drift control region 241.

  As a modification, the dielectric layer 252 may be disposed between the semiconductor substrate 103 and the drift control region 241. In this modification, the second connection portion of the capacitance needs to be connected to the drift control region 241 via a connection line (not shown in detail).

  The semiconductor layer 273 doped more heavily than the substrate 103 may be provided on one surface side of the substrate 103 as necessary. The semiconductor layer is directly adjacent to the storage dielectric 271 and prevents the space charge region from expanding from the dielectric 271 into the substrate 103, thus ensuring a stable and large storage capacitance.

  In the present embodiment, the doping concentration of the substrate 103 may correspond to the doping concentration of the drift control region 241. In any case, the doping concentration of the substrate 103 needs to be sufficiently low so that almost the entire reverse voltage generated in the element is generated under the drain region of the transistor.

  As a modification, the doping of the semiconductor substrate 103 may be somewhat higher than the drift control region 241 (within the above-described conditions). In addition, the intermediate region 273 doped at a higher concentration than the above can be omitted. In addition, the drift control region 241 may be doped complementary to the semiconductor substrate.

  In order to increase the capacity of the storage capacitance, as shown in FIGS. 124 and 125, the shape of the storage dielectric 271 is not flat but is non-planar, for example, uneven, with respect to the horizontal direction. May be. In this case, the more highly doped region 273 may be provided along the shape of the dielectric 271 as needed (FIG. 125), or the interface with the semiconductor substrate 103 is substantially It may be realized to be flat.

  As shown in FIG. 126, the external capacitance 263 may be realized by a wafer bonding method. In this case, the semiconductor substrate on which the dielectric layer 271 is formed is bonded onto the back surface side of the semiconductor substrate by, for example, a bonding method including heat treatment. In this case, the substrate can be more heavily doped in the region on the back side to obtain a more highly doped intermediate region 273. The electrode layer 272 on the bonding surface away from the substrate 103 in the bonded semiconductor substrate ensures a good electrical connection of storage capacitance.

  In each of the above-described elements in which the gate electrode 221 is disposed above the surface 101 of the semiconductor substrate, the inversion channel is a substrate region below the gate dielectric 222 in the region of the surface 101 of the semiconductor substrate 100. It is formed to extend into 212. In this case, the effective channel width is substantially determined by the total width of the drift region 211, that is, the sum of the respective widths b (FIG. 111A) of the respective drift region sections located between the two drift control regions 241. Is done.

  When the device is driven to the on state, the current in the drift region 211 is concentrated in each storage channel formed in the drift region 211 along the storage dielectric 251. Each dimension of the region of the storage channel is extremely small in the direction orthogonal to the storage dielectric 251, that is, in the second horizontal direction y of each element according to the present invention described above. The distance between the regions 214, that is, the width b of each portion of each drift region 211 is selected to be extremely small without significant influence on the resistance value of the element, that is, each dimension value of the storage channel. Can be reduced to almost twice as much.

  Along with an increase in the distance reduction amount between the two drift control regions 241, that is, with an increase in the width b reduction amount in the portion of the drift region 211, in the case of each element described above, A reduction also occurs in the channel width of the inversion channel of the substrate region 212 that is effective in the portion. This reduction increases the on-resistance. The dimension of the storage channel in the second horizontal direction is, for example, in the range of less than 50 nm.

  Each element capable of avoiding the problem of increasing the on-resistance will be described below with reference to FIGS. 127 to 129. The gate electrode 221 is formed so as to extend along the vertical direction from the surface 101 of the semiconductor substrate into the semiconductor substrate 100. 127A, 128A, and 129A show plan views of the surface of the semiconductor substrate 100 in which each gate electrode 221 is incorporated, while FIGS. 127B, 128B, and 129B show the respective elements described above. FIG. 127C, FIG. 128C, and FIG. 129C each show a second vertical cross-sectional view of each element.

  In the case of the element based on FIG. 127, the source region 213 is disposed in the base region 212, and the gate electrode 221 passes through the source region 213 and the base region 212 and passes through the inside of the drift region 211 along the vertical direction. It extends to the position where it enters. In this case, the gate electrode 221 is disposed in the extension portion of the drift region 211 along the first horizontal direction x and at a position away from the storage dielectric 251 along the second horizontal direction y. .

  When the device is encased in the on state, the inversion channel is formed to extend vertically along the gate dielectric 221 from the source region 213 through the substrate region 212 to the drift region 211. The In this embodiment, the channel length of the inversion channel is determined by the dimension of the base material region 212 in the vertical direction v between the source region 213 and the drift region 211. The channel length is indicated by “l” in FIGS. 127B and 127C.

  In the present embodiment, FIG. 127B shows a vertical cross-sectional view of the semiconductor substrate 100 within the region of the gate electrode 221, while FIG. 127C shows the region between the gate electrode 221 and the storage dielectric 251. Sectional drawing inside the semiconductor base material 100 is shown.

  The sectional view of the drift control region and the illustration of the connection regions 242 and 244 of the drift control region are omitted in FIG. The cross-sectional view corresponds to the cross-sectional view described above with reference to FIG. 114C. The drift control region 241 of the present embodiment is not shown in detail, but is connected to the source electrode and the drain electrode according to the descriptions related to FIGS. 118 to 122, or the drain region according to the description related to FIG. It may be connected to only 214.

  Although not shown in detail, the semiconductor substrate 100 of the element shown in FIG. 127 may be realized along the semiconductor substrate shown in FIG. In this case, the semiconductor layer 104 is formed directly with respect to the semiconductor substrate 103, while the drift control region 241 is insulated from the semiconductor substrate 103 by the further insulating layer 252. Further, as another modification of the element shown in FIG. 127, a continuous insulating layer 105 is provided between the semiconductor substrate 103 and the semiconductor layer 104 in the SOI substrate, similarly to the element shown in FIG. Also good.

  128 is realized as a power MOSFET and shows a modification of the semiconductor device shown in FIG. In the element shown in FIG. 128, the inversion channel length is determined by the distance between the source region 213 and the drift region 211 in the first horizontal direction x. In the case of the above element, the gate electrode 221 is formed to extend along the vertical direction v from the source region 213 through the substrate region 212 to the position where the gate electrode 221 enters the drift region 211, and , Insulated by the gate dielectric 222 and extending along the first horizontal direction x. An inversion channel having a length “l” is formed to extend along the gate dielectric 222 in the first horizontal direction x when the device is in the on state.

  As shown in FIGS. 128B and 128C, the source region 213 is disposed within the substrate region 212, and is therefore in both the first horizontal direction x and the vertical direction v by the drift region 211 to the substrate region 213. Are separated. 128B and 128C, the source region 213 and the base material region 212 are disposed below the semiconductor layer 104 along the vertical direction v from the surface 101 of the semiconductor base material 100, respectively. Alternatively, the insulating layer 105 may be extended to the semiconductor substrate 103 or when an SOI substrate is used.

  As another variant similar to the device according to FIG. 127, the gate electrode 221 may be formed extending deeper along the vertical direction v than the substrate region 212. As a result, when switched to the on state, inversion channels can be formed in both the first horizontal direction x and the vertical direction v.

  FIG. 129 shows a modification of the element shown in FIG. In the case of the above element, the gate electrode 221 is disposed adjacent to the base material region 212 and the second horizontal direction y along the first horizontal direction x in the extension portion of the drift control region 241. ing. In the case of the above element, the storage dielectric 251 and the gate dielectric 222 are formed by a common dielectric layer. The common dielectric layer separates the drift region 211 from the drift control region 241 and the base material region 212 in the second horizontal direction y, and each portion of the source region 213 and the drift region 211 are also gate electrodes. 221. In the first horizontal direction x, the gate electrode 221 is separated from the drift control region 241 by another dielectric layer, that is, an insulating layer 224.

  As shown in FIGS. 129B and 129C, the semiconductor substrate 100 of the element is realized as an SOI substrate having a semiconductor substrate 103, an insulating layer 105, and a semiconductor layer 104. As shown in FIG. 129B, the base material and the source regions 212 and 213 are formed to extend to the insulating layer 105 along the vertical direction v of the semiconductor base material 100. Similarly, the gate electrode 221 is formed so as to extend to the insulating layer 105 along the vertical direction v. In the case of the device, the inversion channel is formed along the first horizontal direction x along the gate dielectric 222 in the substrate region 212 between the source region 213 and the drift region 211.

  Although not shown in detail, the lower end of the base material region 213 may be set above the insulating layer 105, and the source region 213 may be disposed only inside the base material region 212. . Therefore, a power MOSFET can be obtained in which the inversion channel extends in the vertical direction v based on the device according to FIG.

  The drift control region 241 of the element according to FIG. 129 can be connected in accordance with each description related to FIGS. 118 to 122. In this case, the second connection region 244 of the drift control region 241 may be disposed in the drift control region 241 adjacent to the further insulating layer 224 of the gate electrode 221 in the first horizontal direction x.

  Although not shown in detail, the second connection region 244 may extend along the vertical direction v over the entire depth of the substrate region 212 and / or the vertical to the insulating layer 105. It may extend along the direction.

  Of course, the drift control region may be connected to the drain potential only through the first connection electrode 233 based on the descriptions of FIGS. 111 to 113. In this connection, a diode may or may not be inserted between them.

  FIG. 130 and FIG. 131 show still other typical embodiments regarding a lateral power MOSFET using an SOI substrate. In the present embodiment, the semiconductor substrate 100 in which each MOSFET is incorporated also has a semiconductor substrate 103, an insulating layer 105 disposed on the semiconductor substrate 103, and a semiconductor layer 104 disposed above the insulating layer 105. ing. Each active element region of the MOSFET is incorporated in the semiconductor layer 104.

  In the case of each element according to FIGS. 130 and 131, the insulating layer 105 has a cut-out portion 106. The cutout portion 106 is formed so as to pass through the connection region 217 adjacent to the base material region 212, extend through the insulating layer 105, and extend straight into the semiconductor substrate 103. The connection region has the same conductivity type as the base material region 212. The semiconductor substrate 103 is doped complementary to the connection region 217.

  In the case of the device according to FIG. 130, each field region 218A, 218B, 218C, 218D, which is doped complementary to the substrate, is arranged in the semiconductor substrate 103. Each field region is arranged along the first horizontal direction x so as to be separated from each other, and is directly adjacent to the insulating layer 105.

  In the second horizontal direction y, the field regions 218A to 218D are formed in a strip shape, although not shown in detail. In the present embodiment, the field region 218 </ b> A is disposed at a position closest to the connection region 217 and is directly connected to the connection region 217. The horizontal spacing between the two adjacent field regions 218A to 218D is preferably increased as the distance from the connection region 217 increases.

  Each field region 218 </ b> A to 218 </ b> D satisfies the function of each known field ring from each edge end of the power semiconductor elements, and controls the electric field distribution in the drift region 211 through the dielectric insulating layer 105. The object is to reduce the voltage load on the insulating layer 105 in the case of the semiconductor substrate 103 to which a predetermined potential is applied. The potential may be a ground potential or a reference potential, or may correspond to a drain potential.

  In the case of the device according to FIG. 131, the same purpose as described above is achieved by a field region 219 which is complementarily doped with respect to the semiconductor substrate 103. The field region is formed such that the dopant concentration in the vertical direction v decreases as the distance from the connection region 217 increases. Such a field region is also referred to as a VLD region (VLD = change in horizontal doping).

  As shown in FIG. 131, the cutout portion 106 may be provided in the insulating layer 105 below the drain region 214, and from the drain region 214 through the cutout portion (notch portion) of the connection region 228. It may be formed to extend.

  In the cutout region, the semiconductor region 227 may be formed to extend below the insulating layer 105 along the first horizontal direction and be connected to the connection region 228 as necessary. Each field ring 229A, 229B may be provided in the substrate in a region below the drain region 214, if necessary.

  The function of each field ring described above corresponds to the function of each field ring shown in FIG. Connection region 228, semiconductor region 227 in substrate 103, and each field ring are preferably of the same conductivity type as drain region 214. Each of these regions is preferably doped at a higher concentration than the drift region 211.

  In the case of each element shown in FIGS. 130 and 131, the gate electrode 221 is arranged as a plate-type electrode above the surface 101 of the semiconductor substrate. Needless to say, the gate electrode may be realized as a trench electrode according to the exemplary embodiments shown in FIGS. 127 to 129, although not shown in detail.

  Moreover, in the case of each device according to FIGS. 130 and 131, the drift control region 241 is between the first connection region 242 and the semiconductor region 243 that is complementarily doped with respect to the first connection region 242. The drain electrode 232 is connected through a diode formed by a pn junction.

  Further, it is connected to the drift control region 241 through the second connection electrode 234. The drift control region 241 may be connected by any of the methods described above with reference to FIGS. In addition, the drift control region 241 may be connected only to the drain potential as described above in the exemplary embodiments shown in FIGS.

  In each of the above-described elements not based on the SOI substrate, the drift region 211 is located below the drift region 211 and directly adjacent to the semiconductor substrate 103 that is complementarily doped with respect to the drift region 211. For example, an insulating layer 252 (see, eg, FIG. 111D) that insulates the drift control region 241 from the semiconductor substrate 103 may be required by the method described above.

  Each of these elements is based on a basic structure having a semiconductor substrate 103, each drift region 211 disposed on the semiconductor substrate 103, and each drift control region 241 adjacent to each drift region 211 in the horizontal direction. Yes. Each drift control region is insulated from each drift region 211 by a storage dielectric 251 and from the semiconductor substrate 103 by a further insulator, that is, a dielectric layer 252.

  With reference to FIG. 132, a possible manufacturing method in the element having the above basic structure will be described below. As shown in FIG. 132A, the starting method step of the manufacturing method is formed by providing a semiconductor substrate 103.

  As shown in FIG. 132B, the insulating layer 252 ′ is formed on one surface of both surfaces of the semiconductor substrate 103. The insulating layer 252 'is an oxide layer, and may be formed by, for example, thermal oxidation, or may be formed by depositing an oxide such as TEOS (tetraethylorthosilicate).

  Patterning of the insulating layer 252 'followed by individual portions of the insulating layer 252' results in each strip-type insulating layer 252 resulting in illustration in FIGS. 132C and 132D. In this case, FIG. 132C shows a cross-sectional view of a configuration having a semiconductor substrate 103 and a patterned insulating layer, while FIG. 132D shows a plan view of the configuration.

  In the case of the above configuration, each of the strip-type insulating layers 252 is spaced apart from each other in the horizontal direction corresponding to the second horizontal direction y in the aforementioned element. The width of each remaining insulating layer 252 in the second horizontal direction y defines the width of each of the aforementioned drift control regions, while the distance between each of the two insulating layers 252 is the distance of each of the aforementioned drift regions 211. Define the width.

  Next, as shown in FIG. 132E, the semiconductor layer 104 is deposited and formed on the substrate 103 having the patterned insulating layer 252 by an epitaxy method. At this time, the semiconductor layer 104 is deposited on each insulating layer 252 epitaxically in each insulating layer 252.

  As the semiconductor layer 104 is formed thicker, the on-resistance of the obtained transistor becomes lower. The thickness is limited by the technical possibilities of the next etching and filling method steps and their costs. Typical thickness is in the range of 2 μm to 40 μm.

  As shown in FIG. 132F, etching is performed from the surface 101 of the semiconductor substrate 100 formed from the semiconductor substrate 103 and the semiconductor layer 104 using the etching mask 200, and each trench is etched into the semiconductor substrate 100. It is formed by. The trenches are arranged so as to be separated from each other in the second horizontal direction y, and to be located in the region of the end portion in the horizontal direction of each insulating layer 252.

  The etching is performed by, for example, an enchant that selectively etches the semiconductor layer 104 without etching the material of the insulating layer 252. At this time, each of the insulating layers 252 functions as an etching stop layer during etching.

  The width of each trench 107 is set by the maximum load voltage between the drift region 211 and the drift control region 241 described above, and also by the method for forming the dielectric layer. If the dielectric layer is formed by thermal oxidation of the semiconductor material, the reduction of the semiconductor material due to the trench width should be considered. Typical trench widths are in the range of about 20 nm to about 100 nm for each dielectric layer in thermal oxidation, and about 30 nm to about 200 nm for the dielectric filling of each trench. Within the range.

  Subsequently, a dielectric layer is formed in each of the trenches 107. The dielectric layer is, for example, an oxide layer. The formation of the oxide layer may be performed by thermal oxidation of each exposed region of the semiconductor substrate 100 before or after the removal of the etching mask 200, or for example, deposition of an insulator layer by a CVD process. Alternatively, a combination of the above methods may be used. When using the thermal oxidation after removal of the etching mask 200, an oxide layer is also formed on the surface 101 of the semiconductor substrate 100, after which the oxide layer is again formed by, for example, an anisotropic etching method. Need to be removed.

  FIG. 132G shows the semiconductor substrate 100 after the above method steps have been performed. In the basic structure illustrated in FIG. 132G, each of the semiconductor elements described above includes the base material, source, and drain regions 212, 213, and 214, and the connection regions 233 in the drift control regions 241 in the MOSFET structure. 234 may also be realized by known methods including, for example, conventional doping methods and ion implantation and / or ion diffusion methods.

  The use of the lightly doped drift control region 241 to control the storage channel in the drift region 211 of the power semiconductor device is not limited to power MOSFETs, but any power semiconductor device having a drift region It is also applicable to classes. The use of the drift control region as described above is specifically applicable to IGBTs.

  The IGBTs as described above are different from the power MOSFETs described above with reference to each of the above-described figures, due to the characteristic that the drain region 214 doped in a complementary manner to the drift region is referred to as an emitter region in the IGBT.

  Even in the case of unipolar power semiconductors, the use of a lightly doped drift control region 241 to control the storage channel in the drift region 211 provides specific advantages.

  Yet another application for a lightly doped drift control region located adjacent to a drift region is power Schottky diodes. Schottky diodes of the above type are different from the power MOSFETs described above due to the characteristic that the Schottky metal region is present instead of the base material region 212 and that the gate electrode is not present.

  FIG. 133 shows a power Schottky diode as described above as a variant of the embodiment according to FIG. In this case, reference numeral 271 indicates a Schottky metal region adjacent to the drift region 211. The Schottky metal region 271 forms an element coupling portion 272 together with the drift region 211, and promotes formation of a space charge region that propagates in the drift region 211 when the element is in an off state.

  In the case of the above element, the Schottky metal region 271 forms an anode region, while a highly doped semiconductor region 214 is disposed in the drift region 211. The semiconductor region forms a drain region in the MOSFET and a cathode region in the Schottky diode. The Schottky diode is switched to an off state when a positive voltage is present between the cathode region 214 and the anode region 261.

  In the power elements according to the present invention described above, the drift region 211 and the drift control region 241 are adjacent to each other along the second horizontal direction y of the semiconductor substrate 100 and separated from each other by the storage dielectric 251. It is arranged so that. In this case, when the element is driven to the on state, the region of the storage dielectric 251 along the storage channel propagating in the drift region 211 is formed to extend in a direction perpendicular to the surface 101 of the semiconductor substrate. Has been.

  134A through 134D show another exemplary embodiment of a lateral power semiconductor device according to the present invention. In the case of the above element, each drift control region 241 is disposed adjacent to the drift region 211 or adjacent to each individual portion of the drift region 211 along the vertical direction v in the semiconductor substrate 100. It is arranged to fit.

  FIG. 134A shows a plan view of the semiconductor element at the surface 101 of the semiconductor substrate 100, and FIG. 134B shows a vertical cross-sectional view of the element taken along line JJ of FIG. 134A. 134C shows a vertical cross-sectional view of the element as viewed in the direction of arrows KK in FIG. 134A, and FIG. 134D shows the surface of the element in the direction of arrows LL in FIGS. 134B and 134C. 1 shows a horizontal cross-sectional view extending parallel to 101. FIG.

  Each drift control region 241 is insulated from the drift region 211 by the storage dielectric 251 and is electrically connected to the drain region 214, that is, the drain electrode 232. 134B and 134C, the connection between each of the drift control regions 241 and the drain electrode 232 is illustrated by a solid connection line.

  A first connection electrode 233 is provided for connection to each drift control region 241. The first connection electrode 233 is formed to extend from the surface 101 along the vertical direction in the semiconductor substrate and is connected to each of the drift control regions 241. However, the first connection electrode 233 is insulated from the drift region 211. FIG. 134E shows a fragmentary cross-sectional view of the element in the region of the first connection electrode 233. In this case, the first connection electrode 233 is located at the end of each drift control region 241 on the side facing the drain region 214. The drain region 214 may be disposed at any desired position along the second horizontal direction y. FIG. 134A shows an example of a possible position of the first connection electrode 233 whose horizontal cross section is square, for example.

  The first connection electrode 233 is connected to the drain electrode 232 by an upper connection link portion 235 on the surface 101 of the semiconductor substrate, and is insulated from at least the drift region 211 by the insulating layer 256 on the surface. ing. Reference numeral 255 shown in FIG. 134E indicates a vertical insulating layer that insulates the drift region 211 in the semiconductor substrate 100 from the connection electrode 233 formed to extend in the semiconductor substrate 100.

  In order to allow connection with each end of each drift control region 241 on the side facing the base material region 212 or the source region 213, the second connection electrode 234 is connected to the first connection electrode 233 described above. Correspondingly, the semiconductor substrate 100 is connected to each drift control region 241 at a position on the substrate or source side of each drift control region 241 along the vertical direction. Insulated from region 211.

  An example of a possible position of the second connection electrode 234 provided as necessary is shown by a broken line in FIG. 134A. In the present embodiment, each second connection region 244 is provided in each drift control region. Each said 2nd connection area | region is doped complementarily with respect to each drift control area | region 241, and the 2nd connection electrode is connected with each 2nd connection area | region.

  Each drift control region 241 may be connected to the drain electrode 232 and the source electrode 231 by any desired connection method described above with reference to FIGS. 118 to 122. In order to connect each drift control region 241 to the drain electrode 232 via a diode, for example, each connection region 243 may be provided in each drift control region 241 in the region of the connection link portion 235.

  Each connection region is doped in a complementary manner with respect to the remaining regions of the drift control region 241. Each connection region as described above is illustrated in FIG. 134E. Specifically, the heavily doped region may be introduced between the connection region 243 and the drift control region 241. The heavily doped region is complementarily doped with respect to the connection region 243.

  When withstand voltage is present at the drain, the heavily doped region prevents the storage holes from flowing out of the drift control region to the connection electrode 233. Each connection region 244 that is doped complementarily to the drift control region 241 is connected to each drift control region in the region of the other connection part 237 for the purpose of connection between each drift control region 241 and the source electrode 231. 241 may be provided correspondingly.

  In the case of the device illustrated in FIG. 134, the substrate region 212 is doped complementary to the drift region 211 and extends along a first horizontal direction x in the direction to the drain region 214. Has each part.

  Due to the characteristics of the configuration of each base material region 218, the pn junctions of the drift regions 211 and the drift control regions 241 are alternately stacked along the first vertical direction x. Therefore, the electric field strength and the profile (distribution) of each space charge region are practically the same as the profiles generated in the two semiconductor regions. This can reduce the static load voltage in the direction across the storage dielectric 251 during off-state operation.

  The gate electrode 221 of the MOSFET shown in FIG. 134 is arranged as a flat electrode above the surface 101 of the semiconductor substrate. The source region 213 is completely surrounded by the substrate region 212 and the inversion channel. The inversion channel is formed along the first horizontal direction x between the source region 213 and the drift region 211 below the surface 101 of the semiconductor substrate 100 when the element is driven to an on state. The

  In the illustrated embodiment, each region of the storage dielectric 251 between each drift control region 241 and the drift region 211 is formed to extend parallel to the surface 101, so that the element is turned on. When driven, each storage channel in each drift region 211 is similarly formed parallel to the surface 101 of the semiconductor substrate.

  135A to 135C show a modification of the element shown in FIG. In the case of the above element, the gate electrode 221 is realized as a trench electrode. The trench electrode extends from the surface 101 into the semiconductor substrate 100 along the vertical direction.

  FIG. 135A shows a plan view of the surface 101 of the semiconductor substrate, and the illustration of the source, drain, and each gate electrode is omitted for the sake of brevity. FIG. 135B shows a vertical cross-sectional view of the device across the gate electrode 221, and FIG. 135C shows the vertical direction of the device in a plane along the second horizontal direction y at a position away from the gate electrode 221. FIG. A cross-sectional view is shown.

  The gate electrode 221 of the element is covered with a gate dielectric 222 and formed to extend from the source region 213 through the base material region 212 into the drift region 211 along the first horizontal direction x. Yes. When the device is driven to the on state, in this embodiment, the inversion channel is formed in the base material region 212 along each horizontal region in the gate electrode 221 along the first horizontal direction. The

  Although not shown in detail, each drift control region 241 based on the element shown in FIG. 134 may be connected to the drain electrode 232 via the first connection electrode 233 (FIG. 135A), Further, it may be connected to the source electrode 231 through a second connection electrode 234 provided as necessary (FIG. 135A).

  The gate structure may be implemented based on the descriptions of the formation of each gate with respect to FIG. In the above implementation, each modification specified in each description related to FIG. 128 is also included.

  136A through 136D show a further exemplary embodiment of a lateral power MOSFET. In the above embodiment, each drift control region 241 is arranged adjacent to each part of the drift region 211 along the vertical direction v of the semiconductor substrate 100. In this case, FIG. 136A shows a plan view of the surface 101 of the semiconductor substrate, and FIGS. 136B and 136C show two O− at each position separated from each other along the second horizontal direction y shown in FIG. 136A. FIG. 136D is a vertical sectional view of the semiconductor substrate as viewed in the direction of arrows O and PP, and FIG. 136D is a view in the direction of arrows Q-Q illustrated in FIGS. 136B and 136C. The horizontal direction sectional view which passes along the said semiconductor base material is shown.

  In the case of the above element, the gate electrode 221 has a plurality of electrode areas. Each of the plurality of electrode sections is disposed away from each other along the vertical direction v of the semiconductor substrate 100. In the case of the above element, each of the electrode areas of the gate electrode 221 is adjacent to each of the drift control regions 241 along the first horizontal direction x, and is insulated from each drift control region 241. Insulated by layer 224.

  The substrate region 212 has a plurality of substrate region areas. Each of the plurality of substrate region areas is arranged adjacent to a part of the drift region 211 along the first horizontal direction x, and in the vertical direction v with respect to at least one electrode area of the gate electrode 221. They are next to each other along the line.

  In the case of the above element, the gate dielectric 222 and the storage dielectric 251 are formed by a common dielectric layer. The gate dielectric 222 is disposed between the electrode area of the gate electrode 221 and the area of the substrate region 212. The storage dielectric 251 is formed between the drift control region 241 adjacent to the area of the gate electrode 221 and the drift region 211 arranged adjacent to the area of the base material region 212.

  Each region of the source region 213 is adjacent to each region of the base material region 212 at a position along the first horizontal direction x, and between the adjacent regions is from the surface 101. The semiconductor substrate 100 is connected by a source electrode 231 formed so as to extend in the vertical direction.

  In the case of the above element, each of the areas of the gate electrode 221, each of the areas of the substrate region 212, and each of the areas of the source region 213 are also each drift control region along the second horizontal direction y. 241 and each drift region 211 are formed in a strip shape.

  Similarly to the source region 213, the drain region 214 similarly has a plurality of sections in the element. Each area of the drain region 214 is adjacent to each area of the drift region 211. Each area of the drain region 214 is connected to each other by a drain electrode 232 formed so as to extend from the surface 101 into the semiconductor substrate 100 along the vertical direction. Each of the areas of the drain region 214 is formed in a strip shape, and is thus formed to extend along the second vertical direction y in accordance with each area of the source region 213.

  In the case of the above element, each drift control region 241 is separated from the drain electrode 232, that is, from the semiconductor region 245 disposed between the insulating layer 257 and the drain electrode 232, in the vertical direction to the first horizontal direction x. Insulated by layer 257.

  Although not shown in detail, each drift control region 241 is connected to the drain electrode 232 via the first connection electrode 233 in accordance with each drift control region 241 of the element shown in FIG. 135A), and may be connected to the source electrode 231 through a second connection electrode 234 provided as necessary (FIG. 135A). An example of each possible arrangement of the first and second connection electrodes 233, 234 is illustrated in FIG. 136A. As shown in FIG. 136A, each connection region 244 that is complementarily doped with respect to the drift control region 241 is provided inside each drift control region 241, and each of the connection regions is connected to each other by a connection electrode 234. It may be. In the above structure, a diode for connecting the drift control region 241 to the source electrode 231, that is, the source region 213 may be provided.

  Needless to say, the arrangement of each drift control region 241 arranged adjacent to each section of the drift region 211 along the vertical direction of the semiconductor substrate is the power MOSFET illustrated in FIGS. 134 to 136. The drift control region 241 as described above may be provided in any power element having a drift region, specifically, a Schottky diode. Schottky diodes differ from MOSFETs in that no gate electrodes are provided and a Schottky metal region is provided adjacent to the drift region instead of the base material and source regions. doing.

  In the case of each horizontal power device described above with reference to FIGS. 134 to 136, a stack-like device structure is continuously formed along the vertical direction v of the semiconductor substrate 100 to form a semiconductor layer as the drift region 211. , A dielectric layer as the storage dielectric 251, a further semiconductor layer as the drift control region 241, and another dielectric layer as another storage dielectric 251 is provided on the drift control region. .

  The above structure may be repeated a plurality of times along the vertical direction in order to alternately provide the plurality of drift regions 211 and the plurality of drift control regions 241 along the vertical direction of the semiconductor substrate. In order to separate the plurality of drift regions 211 and the plurality of drift control regions 241 from each other, a storage dielectric 251 is provided between the two.

  In the above case, each of the semiconductor regions forming each drift region 211, that is, each section of the drift region, and each drift control region 241 may have the same dimension along the vertical direction. , Each may have the same respective doping concentration.

  Each layer configuration in which the semiconductor layers and the dielectric layers are alternately formed may be formed by various methods.

  One method of creating a stack as described above includes method steps for forming respective insulating layers embedded in semiconductor layers at different depths. For the above production, oxygen ions are implanted into the semiconductor layer from the surface. In the heating step following this oxygen implantation, a semiconductor oxide is formed that forms an insulating layer in each region where oxygen is implanted. The implantation energy of oxygen ions implanted into the semiconductor substrate determines the penetration depth of oxygen ions, and thus determines the formation position of the insulating layer along the vertical direction of the semiconductor layer. By applying different implantation energies, it is possible to form a plurality of insulating layers at different distances from the surface along the ion implantation direction.

  Each insulating layer extending in a direction orthogonal to the surface of the semiconductor layer can also be created by the above method. For the above production, oxygen ions are implanted in a masked state using a mask. The mask determines the position and size of the insulating layer along the horizontal direction of the semiconductor layer. The applied implantation energy determines the position and size of the insulating layer along the vertical direction of the semiconductor layer.

  Another method of creating a stack having alternating semiconductor layers and dielectric layers initially includes method steps for forming a semiconductor layer having alternating silicon and silicon-germanium layers. The stack of the semiconductor layers as described above can be formed by a known epitaxial turn-off method. In the above lamination, the size (thickness) of the silicon-germanium layer along the vertical direction of the obtained lamination, which is perpendicular to each individual layer, is smaller than the size of each silicon layer.

  Subsequently, each trench is formed so as to enter the inside from the surface into each of the above stacks. Each trench region of the silicon-germanium layer is selectively removed from each trench by an etchant sequentially. As a result, cavities (spaces) along the vertical direction are formed between adjacent silicon layers.

  A semiconductor oxide is then formed in each cavity by introducing an oxidizing gas into each cavity of the stack through each previously created trench at a suitable oxidation temperature.

  Yet another method for creating a stack having alternating each semiconductor layer and each insulating layer is that each insulating layer is made of a semiconductor layer as described in the method described above with reference to FIGS. 132A to 132E. The epitaxial growth is performed repeatedly, and the above growth is repeated a plurality of times. That is, a patterned insulating layer is newly grown on the grown epitaxial layer, and the epitaxial layer is newly formed on the insulating layer. Grow.

  Furthermore, a stack having alternately each semiconductor layer and each insulating layer can be created by applying a so-called smart cut method. In principle, the smart cut method involves a method step for “ejecting” a thin semiconductor layer from a semiconductor layer by implanting hydrogen ions to a desired depth, followed by a heating step. And method steps for performing.

  In the smart cut method, a semiconductor layer having an insulating layer is oxidized in another semiconductor layer by oxidizing the surface of the semiconductor layer by a wafer bonding method so that an insulating layer is disposed between two semiconductor layers. Can be used to create a semiconductor-insulator layer.

  Thereafter, the semiconductor layer bonded thereon is ejected by the smart cut method so that the insulating layer and a thin layer of the semiconductor layer bonded thereon remain on the carrier.

  Subsequently, the thin layer of the semiconductor layer is oxidized, and then the semiconductor layer provided with the insulating layer is newly bonded thereon, and the layer bonded above is newly formed by the smart cut method. Will be ejected. Each of the above method steps can be repeated multiple times to create a semiconductor-insulator stack.

  Still another method for creating each buried oxide layer includes a method step of etching each trench in the semiconductor layer, followed by a method step of heating the semiconductor layer in a hydrogen atmosphere. Including. The heating method step creates each cavity in the semiconductor layer at a location proximate to each trench. Thereafter, each of the cavities is oxidized.

  The respective positioning of each cavity from the surface of the semiconductor layer is a selection of an etching method step that, in the above method, determines the depth of each etched trench into the semiconductor layer and the size of the trench sidewalls. Is defined in advance.

  Therefore, for example, in the so-called “Bosch process”, during the etching of the trench, the anisotropic and isotropic phases of surface treatment of the sidewalls are performed alternately. Alternating execution of the phases forms a regular structure having a scalloped pattern (wave pattern) on the walls of the trench.

  The formation of each chamber having the above-mentioned regular structure is a suitable choice of the ratio of the width of each isotropically etched region having a scallop to the width of each narrower region by anisotropic etching. To proceed. Oxidation of the semiconductor material in each cavity to create an insulating layer in the cavity requires the creation of another trench to open the cavity.

  One problem to be solved in the fabrication of each element described above with reference to FIGS. 134 to 136 is that each drift control region 241 and each drift region 211 are arranged so as to overlap each other along the vertical direction. The connection electrode is formed in the element.

  Examples of the connection electrode include the connection electrodes 233 and 234 described above in the drift control region 241 or the drain electrode 232 of the element according to FIG. The drain electrode 232 extends from the surface 101 to the inside of the semiconductor substrate, and only with all of the stacked second semiconductor layers, that is, only with each of the drift regions 211, or with each of the drift control regions 241. Only connected with.

  A method for creating the drain electrode 232 connected only to each drift region 211 that solves the above problem will be described below with reference to FIGS. 137A to 137F. In the present embodiment, the above method can be applied to the production of the first and second connection electrodes 233 and 234 of the element described in FIGS. 134 to 136, respectively.

  FIG. 137A shows the first stage of the method, in which each drift region 211 and each drift control region 241 are arranged so as to overlap each other along the vertical direction v, and the storage dielectric 251 lies between them. The semiconductor substrate 100 is shown separately.

  In FIG. 137A, reference numeral 111 is given to each first semiconductor layer that later forms each drift region 211 in the above-described element, and reference is made to each second semiconductor layer that later forms each drift control region 241. Reference numeral 141 is given.

  In each of the first semiconductor layers 111, every other insulating layer 257 in the vertical direction is arranged along the vertical direction v of the semiconductor substrate 100. Each of the insulating layers is formed to extend along the vertical direction between the two dielectric layers 251.

  As shown in FIG. 137B, a trench 117 is then formed to extend from the surface 101 inside the above configuration. In the present embodiment, a trench is similarly formed for the insulating layer. The trench is formed so as to extend from the surface 101 toward the inside of the semiconductor substrate along the vertical direction v, and above or below the lowermost dielectric layer 251 ′ in the stack along the vertical direction from the surface. The formation of the trench is stopped at a position above the body layer 251 ′. The trench is formed at an outer position in the region of each first semiconductor layer that is separated from each insulating region 257 along the first horizontal direction x and later forms each drift region 211.

  The trench may be created by an etching method using an etching mask that defines the horizontal position and size of the trench.

  As shown in FIG. 137C, each of the semiconductor layers 111 and 141 between the two dielectric layers 251 is then formed in a first horizontal direction by an isotropic etching method that proceeds from each side wall of the trench 117, respectively. Partially removed in the direction along. In the case of each part of each semiconductor layer that will later form each drift region 211, each insulating region 257 in the vertical direction functions as an etch stop, so that in the region of each semiconductor layer, the semiconductor material is Up to each insulating region 257 proceeds from the trench 117 and is removed by etching.

  In this case, in the etching method, the semiconductor material exceeds the insulating regions 257 disposed in the first semiconductor layers 111 in the regions of the second semiconductor layers 141 that will form the drift control regions 241 later. Up to the position is carried out so as to be removed along the first horizontal direction x. In the region relating to the side wall 117 ′ of the trench 117 opposite to each insulating region 257, each semiconductor layer is equally removed during the execution of the isotropic etching method.

  As a result of the isotropic etching method, each semiconductor layer that later forms each drift region 211 later forms each drift control region 241 in the first horizontal direction x on the first side wall of the trench 117. It further protrudes from each semiconductor layer in the direction of the cutout portion. Since the advancing portion from the cut-out portion 118 is formed by the above isotropic etching method, each drift control region 241 has retreated with respect to each drift region 211 along the first horizontal direction x. Set to position.

  The result of executing each other method step is illustrated in FIG. 137D. The insulating layers 258 and 259 are formed on the exposed regions of the semiconductor layers in the cutout portion 118 formed by the isotropic etching method. Only one second semiconductor layer 141 serving as each drift control region 241 exists on one side surface of the trench. Each of the newly created insulating layers is indicated by reference numeral 258 in the region. On the side surface on the opposite side of the cut-out portion and on the side walls (not shown) spaced apart from each other in the second horizontal direction y, the vertical insulating layers are formed in the first and second directions. Created on each exposed region of each semiconductor layer 111, 141 and is indicated by reference numeral 259 in FIG. 137D.

  FIG. 137E shows the configuration after each further method step has been performed, including the formation of other cutouts 119 by etching proceeding from the surface 101 into the stack. The cut-out portion includes the first vertical insulating regions 257 that have existed in the first semiconductor layers 111 and the first vertical insulating layers on the exposed side surfaces of the second semiconductor layers 141. Between the second vertical insulating regions 258 formed after the region 257, one horizontal direction region along the first horizontal direction is positioned.

  Since each first vertical insulating region 257 is removed by the above process, each first semiconductor layer 111 is exposed in the other cutout portion 119, while each second semiconductor layer is cut. In the out part 119, it covers with each 2nd insulation area | region.

  On the side of the newly created cut-out portion 119 that faces the first first insulating region 257, the side wall of the cut-out portion is in each second insulating region 258. As a result, in the region, Only the protruding portion (web portion) of each dielectric layer 251 extending in the first horizontal direction x is removed, but the semiconductor material is not removed, and each vertical insulating layer 259 is also not removed. Each method step described above also works effectively on the opposite side (not shown) of the cutout portion 119 along the second horizontal direction y.

  As shown in FIG. 137F, the above method is completed by forming an electrode layer in the cutout portion 119 by deposition, so that a connection electrode 232 is generated. In the present embodiment, the electrode 232 forms the drain electrode 232 and is connected to each first semiconductor layer 111. Each first semiconductor layer 111 is exposed after removing each insulating region 257 on each side wall of the cutout portion, and forms each drift region 211 at that position. The electrode 232 is insulated from each second semiconductor layer 141 by each second insulating region 258, and forms each drift control region 241 in each region adjacent to each drift region 211.

  Although not shown in detail, each dopant atom is implanted into each exposed region of each drift region 211 prior to depositing an electrode layer for the creation of electrode 232 to provide each heavily doped connection. A method step of implantation that creates the region may be performed. In this case, the implantation is performed at an angle inclined with respect to a direction perpendicular to the surface.

  The method described above with reference to FIGS. 137A to 137F is for creating connection electrodes connected only to all of the second semiconductor layers, but each connection electrode connected to each drift control region 241. (236, 237 in FIGS. 134 to 136) and can also be used in corresponding methods for creating the source electrode 231.

  The drift control regions 241 of the power semiconductor elements described above are formed so as to extend long in the drift region 211 along the direction of current flow of the elements. In the case of a MOSFET, the current direction corresponding to the direction between the substrate region 212 and the drain region 214 corresponds to the first horizontal direction x of the semiconductor substrate 100 in each of the exemplary embodiments described above. Yes.

  In the direction crossing the current direction, each drift control region is formed to extend in a direction perpendicular to the surface 101 of the semiconductor substrate in the case of each element shown in FIGS. 111 to 131 and 133. In the case of each of the typical embodiments shown in FIGS. 134 to 136, they are formed so as to extend in a direction parallel to the surface 101 of the semiconductor substrate. In each element shown in FIGS. 134 to 136, each drift control region may extend to the end of the semiconductor substrate along the second horizontal direction y, or may extend to the edge end of the semiconductor substrate. May be.

  As described below with reference to FIGS. 138 to 145, the above-described dimensions and sizes related to each drift control region 241 may be combined. 138 to 145 are perspective views showing portions of the drift regions 211 and the drift control regions 241 of the power semiconductor element, respectively.

  As shown in FIGS. 138A and 138B, each drift control region 241 is formed in a strip shape and is disposed so as to be surrounded by the storage dielectric 251 in the drift region 211. In the case of the above element, each accumulation channel is positioned in the drift region 211 in the horizontal direction adjacent to each drift control region 241 and each position along the vertical direction both above and below each drift control region 241. It can be formed respectively at the position along.

  The semiconductor substrate 100 may include a semiconductor substrate 103 and a semiconductor layer 104 added to the semiconductor substrate by a known method. The semiconductor substrate 103 and the semiconductor layer 104 may have different conductivity types, or may have the same conductivity type. In this case, the basic doping of the semiconductor layer 104 corresponds to the doping of the drift region 211, and may be of the same conductivity type, for example.

  As shown in FIG. 139, the insulating layer 105 is disposed between the semiconductor substrate 103 and the semiconductor layer 104 as necessary, so that the drift region 100 can be insulated from the semiconductor substrate 103.

  In the case of each element based on FIGS. 138 and 139, the lowest drift control region 241 farthest from the surface 101 side is disposed at a position away from the semiconductor substrate 103. In the position modification of the exemplary embodiment based on FIG. 138, the lowermost drift control region 241 is formed so as to reach the semiconductor substrate 103 as shown in FIG. 140. In the case of this exemplary embodiment, an insulating layer exists between the lowest layer in each drift control region 241 and the semiconductor substrate 103, and the insulating layer defines the drift control region as a semiconductor substrate. Insulation from 103.

  FIG. 141 shows a modification of the configuration shown in FIG. In this case, each drift region 211 is formed in the drift control region 241 in a strip shape. The storage dielectric 251 is provided corresponding to each other between the drift control region 241 and each drift region 211. In this case, the insulating layer 252 is provided at least between the drift control region 241 and the semiconductor substrate 103, while one of the lowest portions in each drift region 211 is directly adjacent to the semiconductor substrate 103. Matching. In this case, the semiconductor substrate 103 may be of the same conductivity type as the lowermost drift region 211 or may be of a complementary conductivity type. In the above case, another insulating layer may be provided between the lowermost drift region 211 and the semiconductor substrate 103 as necessary (not shown).

  Regarding the above-described strip shape in each drift control region 241 or each drift region 211, the dimensions of the regions 241 and 211 are larger in the second horizontal direction y than in the vertical direction. Is provided large, so that a strip-shaped outer shape of each element region is generated. As another modification, the strip shape may be provided so that the dimensions of the regions 241 and 211 are larger in the vertical direction than in the second horizontal direction y.

  142A and 142B show a modification of the element shown in FIG. 139, and each drift control region 241 in this modification is realized in a “columnar shape”. In the columnar strip, the cross section formed by both the vertical direction v and the second horizontal direction y has at least a quadrangular shape. Each of these drift control regions is formed in a shape extending long along the first horizontal direction x.

  The insulating layer 105 illustrated in FIG. 142A is provided between the semiconductor substrate 103 and the semiconductor layer 104 or the drift region 211 as necessary. The semiconductor substrate 103 may be the same conductivity type as the drift region 211 or may be a conductivity type complementary to the drift region 211.

  FIG. 143A and FIG. 143B show a modification of the configuration based on FIG. 142. Each drift region 211 of the above modification is realized in a “columnar shape” and is surrounded by the drift control region 241. Also, the storage dielectric 251 is provided so as to be separated from both the vertical direction and the horizontal direction. In this case, the drift control region 241 is insulated from the semiconductor substrate 103 by another insulating layer 252. In the above variation, the semiconductor substrate may have the same conductivity type as that of the drift control region 241 or a complementary conductivity type.

  In the configuration based on FIG. 144, the drift control region 241 is formed so as to extend along the first horizontal direction x and has an outer shape that has a meandering shape along the vertical direction v. Yes. In this case, the drift control region 241 is completely surrounded by the drift region 211 and is separated by the storage dielectric 251. The drift region 211 and the drift control region 241 are disposed in the semiconductor layer 104. The semiconductor layer 104 is disposed on the semiconductor substrate 103 and is insulated from the semiconductor substrate 103 by an insulating layer 105 as necessary.

  FIG. 145 shows a modification of the configuration based on FIG. 145, and the drift region 211 is surrounded by the drift control region 241. The drift region 211 has an outer shape in which the storage dielectric 251 is disposed between the drift region 211 and the drift control region 241 having a serpentine outer shape along the vertical direction v.

  The meandering outer shape of the storage dielectric can realize a larger area area of the storage dielectric 251 in a semiconductor material having a predetermined capacity required for realizing the drift region 211 and the drift control region 241. When the device is driven to the on state, it has the advantage that a storage channel with a large width can be formed.

  In the present invention, an example based on a MOSFET and a Schottky diode is described. In the case of a MOSFET, specifically, a p-channel MOSFET can be provided instead of the n-channel MOSFET shown. In each exemplary embodiment of the n-channel MOSFET illustrated in this case, all of the n-type doped semiconductor regions need to be replaced with each p-type doped semiconductor region, on the contrary, p-type. All of the doped semiconductor regions need to be replaced with each n-doped semiconductor region. The specific first, second and third diodes can also be replaced in the same manner as described above, and in each replaced diode, it is necessary to be connected to each correspondingly doped region. There is.

  The technical idea of the present invention can be applied to any unipolar element having a drift region, specifically, JFETs.

  It is noted that for the realization of the drift control region, a single crystal semiconductor material is not necessarily required, and it is also possible to use a polycrystalline semiconductor material that satisfies the doping specifications that can be completely depleted as described above. I want. However, when a polycrystalline semiconductor material is used for the drift control region 3, higher leakage currents that lead to an increase in charge carriers generated at each grain boundary between the individual crystals of the polycrystalline material should be considered. is there.

  The semiconductor element according to the present invention has a drift region and a drift control region made of a semiconductor material in a semiconductor substrate. The drift control region is at least partially disposed adjacent to the drift region. A storage dielectric is disposed between the drift region and the drift control region. In the present semiconductor element, the drift control region functions to control a conductive channel in the drift region along the storage dielectric.

Another semiconductor element of the present invention is a semiconductor element having a semiconductor substrate (100), the first conductivity type drift region (2; 211) in the semiconductor substrate (100), and the above A drift control region (3; 241) made of a semiconductor material and disposed at least partially adjacent to the drift region (2) in the semiconductor substrate (100), and the drift region (2; 211). ) And the drift control region (3; 241), and the storage dielectric (4; 251). In the semiconductor element, the drift control region (3; 241) It may be provided with at least one semiconductor region that is doped so that it is completely depleted in a direction perpendicular to the storage dielectric (4; 251).

  In the semiconductor element, a plurality of element structures having the same conductivity type as that of the semiconductor substrate (100) are arranged in the semiconductor substrate (100), and the drift region (2; 211) and the drift control are arranged. You may provide for every area | region (3; 241).

  In the semiconductor element, the drift control region (3; 241) may have the same conductivity type as the drift region (2; 211).

  In the semiconductor element, the drift control region (3; 241) may be of a conductivity type complementary to the conductivity type of the drift region (2; 211).

  In the semiconductor element, at least one of the drift region (2; 211) and the drift control region (3; 241) may be an intrinsic semiconductor.

  In the semiconductor element, the first element region (8; 212) and the second element region (5) disposed away from the first element region (8) between the drift region (2; 211) are disposed. 214).

  In the semiconductor element, the first element region (8) may be arranged away from the second element region (9) in the vertical direction of the semiconductor substrate (100).

  In the semiconductor element, the first element region (212) may be arranged away from the second element region (214) in the horizontal direction of the semiconductor substrate (100).

  In the semiconductor element, the drift control region (3) and the drift region (2) may have the same dopant concentration.

  In the semiconductor element, the drift control region (3) and the drift region (2) may have dopant concentrations having the same profile in a direction parallel to the storage dielectric.

  In the semiconductor element, the drift control region (3; 241) may be connected to the second element region (5; 214).

  In the semiconductor element, the drift control region (3; 241) may be connected to the second element region (5; 214) via a rectifying element (43; 261). In the semiconductor element, the rectifying element (43; 261) may be a diode.

  In the semiconductor device, the diode is between the drift control region (3; 241) and a connection region (32; 243) doped complementarily to the drift control region (3; 241). a semiconductor region (31; 242) formed by a pn junction or adjacent to the drift control region (241) and doped at a higher concentration than the drift control region (241); and the drift control region A pn junction may be formed between the connection region (32; 243) doped in a complementary manner to (241).

  In the semiconductor element, the drift control region (3; 241) has the same conductivity type as the drift control region (3; 241) and is doped at a higher concentration than the drift control region (3). It may be connected to the second element region (5; 214) via the connection region (31; 242).

  The semiconductor element may include a tunnel dielectric (4 ') disposed between the drift control region (2) and the second element region (5).

  In the semiconductor element, the drift control region (3) may be connected to the first connection region (5) via a resistance element (55). In the semiconductor element, the resistance element may be an intrinsically doped semiconductor region.

  In the semiconductor element, a part of the drift region (2) may be disposed between the tunnel dielectric (4 ') and the second element region (5).

  In the semiconductor element, the drift control region (3; 241) may be electrically connected to the first element region (8; 212).

  In the semiconductor element, the drift control region may be connected to the first element region (8; 212) via a rectifying element (42; 262). In the semiconductor element, the rectifying element (42; 262) is a diode.

  In the semiconductor element, the drift control region (3) is connected to the first element region (8;) via connection regions (33, 34; 244) which are doped complementarily to the drift control region (3). 212).

In the semiconductor element, the connection region (33, 34) includes a connection electrode (19),
A rectifying element (41) connected between the connection electrode (19) and the first element region (8) may be included.

  The semiconductor element may include a capacitive element (50; 263) connected between the drift control region (3; 241) and the first element region (8; 212). In the semiconductor element, the capacitive element may be incorporated in the semiconductor substrate (100).

  In the semiconductor element, the drift control region (3; 241) may be connected to a plurality of portions of the drift region (2; 211) via a tunnel dielectric (4 ', 253).

  In the semiconductor element, the first element region (8; 212; 271) has a reverse voltage applied between the drift region (2; 211) and the first element region (8; 212; 271). An element junction where a space charge region propagating in the drift region (2; 211) travels may be formed together with the drift region (2; 211).

  The semiconductor element is embodied as a MOS transistor, wherein the first element region (8; 212) forms a substrate region, the second element region (5; 214) forms a drain region, and A source region (9; 212) separated from the substrate region (8; 212) by the drift region (2; 211) and insulated from the semiconductor substrate (100) by a gate dielectric (16; 222). And a gate electrode (15; 221) extending adjacent to the base material region (8; 212) from the source region (9; 213) to the drift region (2; 211). May be included.

  In the semiconductor element, the base material region (8) and the source region (9) are of the same conductivity type as the source electrode (13) and the base material region (8) that connect each other, Including the semiconductor region (17) having a higher doping concentration than the material region (8), and the capacitive element (50) may be connected to the source electrode (13).

  The semiconductor device may be embodied as a MOSFET, and the drain region (214) may have the same conductivity type as the drift region (211).

  The semiconductor device may be embodied as an IGBT, and the drain region (214) may be complementarily doped with respect to the drift region (211).

  The semiconductor element may be embodied as a MOSFET, and the drift region (2) may be complementarily doped with respect to the source region (9).

  In the semiconductor element, an intermediate region (22) having the same conductivity type as the source region (9; 213) is disposed between the drift region (2; 211) and the base material region (8; 212). May be.

  In the semiconductor element, the gate electrode (15; 221) may be disposed on the surface (101) of the semiconductor substrate (100).

  In the semiconductor element, the gate electrode (15; 221) may be disposed in a trench of the semiconductor substrate (100).

  In the semiconductor element, the gate electrode (15; 221) may be arranged away from the drift control region (3; 241) in the current direction in the semiconductor element.

  In the semiconductor element, the gate electrode (15; 221) may be disposed away from the drift control region (3; 241) in a direction transverse to the current direction in the semiconductor element.

  In the semiconductor element, the gate electrode (221) may extend from the source region (213) to the drift region (211) in the first horizontal direction of the semiconductor substrate (100).

  In the semiconductor element, the gate electrode (221) may be disposed adjacent to at least one of the drift control regions (241) in the first horizontal direction.

  In the semiconductor element, the gate electrode (221) may extend from the source region (213) to the drift region (211) in a direction perpendicular to the semiconductor substrate (100).

  In the semiconductor device, the drift region (2) may include at least one compensation region (7) doped in a complementary manner to the drift region (2).

  In the semiconductor element, the drift control region (3; 241) may be electrically connected to the gate electrode (15; 211).

  In the semiconductor element, the drift control region (3; 241) may be connected to the gate electrode (15; 221) via a rectifier element (42; 264).

  In the semiconductor element, a drain electrode (11) that is in contact with the drain region (5), a semiconductor region (27) that is complementarily doped with the drain region (5), and is partially disposed The drift region (2) may be disposed between the drain electrode (11) and the drift region (2).

  In the semiconductor element, the semiconductor substrate (100) includes a second horizontal direction y extending in a direction orthogonal to the first horizontal direction x, and at least one of the drift control regions (241) includes It may be arranged at least partially adjacent to the drift region (211) in the second horizontal direction y so as to be separated by the storage dielectric (251).

  In the semiconductor device, a plurality of drift regions (211) arranged apart from each other in the second horizontal direction y and a plurality of drift controls arranged apart from each other in the second horizontal direction. Region (241).

  In the semiconductor element, the semiconductor substrate (100) has a vertical direction v, and at least one of the drift control regions (241) is at least partially with respect to the drift region (211) in the vertical direction v. May be arranged next to each other.

  In the semiconductor element, a plurality of drift regions (211) arranged apart from each other in the vertical direction v and a plurality of drift control regions (241) arranged apart from each other in the vertical direction v. And may be provided.

  In the semiconductor element, the semiconductor substrate (100) includes a semiconductor substrate (103) and a semiconductor layer (104) disposed on the semiconductor substrate (103), and at least one of the drift regions (211). And at least one of the drift control region (241) may be disposed in the semiconductor layer (104).

  In the semiconductor element, the drift region (211) is adjacent to the semiconductor substrate (103), and an insulating layer (252) disposed between the drift control region (241) and the semiconductor substrate (103). May be included.

  The semiconductor element may include an insulating layer (105) disposed between the semiconductor substrate (103), the drift region (211), and the drift control region (241).

  In the semiconductor device, the semiconductor substrate (103) has one conductivity type basic doping, and the semiconductor substrate (103) is adjacent to the insulating layer (105) and has a conductivity type of the basic doping. It may have at least one complementary conductive semiconductor region (218A to 218D; 219).

  In the semiconductor device, the semiconductor substrate (103) has one conductivity type basic doping, and the semiconductor substrate (103) has a conductivity type semiconductor region (218A) complementary to the conductivity type of the basic doping. 218D; 219) at least one.

  In the semiconductor element, a semiconductor region (218A to 218D; 219) doped in a complementary manner to the conductivity type of the basic doping is connected to the first element region (212) through a connection region (217). May be.

  In the semiconductor device, a plurality of semiconductor regions (218A to 218D) doped in a complementary manner to the conductivity type of the basic doping of the semiconductor substrate and arranged apart from each other in the first horizontal direction. One of the plurality of semiconductor regions (218A to 218D) may be connected to the connection region (217).

  In the semiconductor device, the doping amount of the semiconductor region (219) doped in a complementary manner to the conductivity type of the basic doping of the semiconductor substrate may be decreased in the first horizontal direction x.

  The semiconductor element is embodied as a Schottky diode, wherein the first element region (8; 212) forms an anode region, and the second element region (5; 214) forms a cathode region. Also good.

  In the semiconductor element, the drift control region (3; 241) may include a connection electrode (19) for applying a driving potential.

  In the semiconductor element, the storage dielectric (4) may include at least two partial layers.

  In the semiconductor element, the storage dielectric (4) may include at least one partial layer having a relative dielectric constant of 7 or more.

The power transistor of the present invention is a power transistor provided with a semiconductor substrate,
Source region (9) and drain region (5) of the first conductivity type, drift region (2) adjacent to the drain region (5), source region (9) and drift region (2) A second conductivity type substrate region (8), a gate electrode (15), and a gate dielectric disposed between the gate electrode (15) and the substrate region (8) (16), coupled to the source region (9) and the drain region (5) and arranged at least partially adjacent to the drift region (2) in the semiconductor substrate, A drift control region (3; 241) made of a semiconductor material, and a storage dielectric (4; 251) disposed between the drift region (2; 211) and the drift control region (3; 241). As a feature That.

  In the power transistor, the drift control region (3) may be coupled to the drain region (5) and the source region (9) via respective rectifier elements (41, 43).

  In the power transistor, the drift control region (3) may be coupled to the drain region (5) via a tunnel dielectric (4 ′) and a part of the drift region (2). .

  The power transistor includes an intermediate region (27) that is in contact with the drain region (5) by a drain electrode (11) and is complementarily doped with respect to the drift region (2). (5) may be disposed between the drain electrode (11) and the drift region (2).

  In the power transistor, the drift region (2) may be of the same conductivity type as the base material region (8).

  In the power transistor, the drift region (2) may be of a conductivity type complementary to the base material region (8).

  Another power transistor of the present invention is a power transistor provided with a semiconductor substrate, and is adjacent to the first conductivity type source region (9) and drain region (5) and the drain region (5). A second conductivity type substrate disposed between the source region (9) and the drift region (2), the drift region (2) doped complementary to the drain region (5) A region (8), a gate electrode (15), a gate dielectric (16) disposed between the gate electrode (15) and the substrate region (8), and the drift region in the semiconductor substrate (2), the drift control region (3; 241) which is arranged at least partially adjacent to each other and is made of a semiconductor material, the drift region (2; 211), and the drift control region (3; 241) It is characterized in that it comprises a; (251 4) arranged storage dielectric in between.

  In the power transistor, the drift control region (3) may be coupled to the drain region (5).

  In the power transistor, the drift control region (3) may be coupled to the source region (9).

Claims (15)

A MOS transistor having a semiconductor substrate (100),
In the semiconductor substrate (100), a drift region (2) of the first conductivity type;
In the semiconductor substrate (100), the drift control region (3), which is disposed at least partially adjacent to the drift region (2) and is made of a semiconductor material;
A storage dielectric (4) disposed between the drift region (2) and the drift control region (3);
A base region (8) of a second conductivity type formed adjacent to the drift region (2) ;
A drain region (5) separated from the substrate region (8) and adjacent to the storage dielectric (4);
A source region (9) separated from the drift region (2) by the substrate region (8);
Adjacent to the substrate region (8; 212) until insulated from the semiconductor substrate (100) by the gate dielectric (16) and from the source region (9) to the drift region (2). An extending gate electrode (15);
A drain electrode (11) in contact with the drain region (5);
A semiconductor region (27) doped complementary to the drain region (5),
The semiconductor region (27) is disposed between the drain electrode (11) and the drift region (2), and is adjacent to the drain electrode (11) ,
The MOS transistor according to claim 1, wherein the drift control region (3) is connected to the drain region (5) via a rectifying element (43) . The part of the semiconductor region (27) doped complementary to the drain region (5) is arranged between the drain region (5) and the drift region (2). MOS transistor. A field stop region (28) doped between the drift region (2) and the semiconductor region (27), which has the same conductivity type as the drift region (2) and is doped more heavily than the drift region (2). )
The MOS transistor according to claim 2, wherein the field stop region (28) extends in the width direction of the drift region (2) between the two storage dielectrics (4).   The MOS transistor according to claim 1, wherein the drain region (5) and the semiconductor region (27) are adjacent to the drift region (2). A field stop region (28) doped between the drift region (2) and the semiconductor region (27), which has the same conductivity type as the drift region (2) and is doped more heavily than the drift region (2). )
The MOS transistor according to claim 4, wherein the field stop region (28) extends in the width direction of the drift region (2) between the two storage dielectrics (4). A field stop region (28) doped between the drift region (2) and the semiconductor region (27), which has the same conductivity type as the drift region (2) and is doped more heavily than the drift region (2). )
2. The MOS transistor according to claim 1, wherein the semiconductor region (27) extends in the direction of the width of the drift region (2) between the two storage dielectrics (4). A capacitive element (50) connected between the drift control region (3) and the substrate region (8);
A rectifying element for interposing and connecting the drift control region (3) to the base material region (8);
And / or a connection region (33, 34) for connecting the drift control region (3) to the base material region (8).
The connection region (33, 34) has the same conductivity type as the drift control region (3) or a conductivity type complementary to the drift control region (3). The MOS transistor according to item. Including the connection electrode (19) of the drift control region (3),
8. The MOS transistor according to claim 1, wherein the connection electrode (19) is for applying a driving potential. Including the connection electrode (19) of the drift control region (3),
The connection electrode (19) is for applying a drive potential,
The MOS transistor according to claim 7 , wherein the connection region (33, 34) is disposed between the drift control region (3) and the connection electrode (19).   The MOS transistor according to any one of claims 1 to 9, wherein the drift control region (3) has the same conductivity type as the drift region (2).   The MOS transistor according to any one of claims 1 to 9, wherein the drift control region (3) is of a conductivity type complementary to the conductivity type of the drift region (2). The drift control region (3) has the same conductivity type as the drift control region (3) and is connected to the rectifier element via a connection region doped at a higher concentration than the drift control region (3) (43) MOS transistor according to claim 1 connected to. A source electrode (13) connecting the substrate region (8) and the source region (9) to each other;
A semiconductor region (17) having the same conductivity type as the substrate region (8) and having a higher doping concentration than the substrate region (8) ,
The MOS transistor according to claim 7 , wherein the capacitive element (50) is connected to the source electrode (13) . The drift control region (3), MOS transistor according to any one of claims 1 to 13 including a rectifying element (42) for connecting interposed the gate electrode (15). The source region (9), the drift region (2), and the drain region (5) are of the same conductivity type and are of a conductivity type complementary to the base material region (8). 15. The MOS transistor according to any one of items 1 to 14 .

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