JP5577909B2 - Optical semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an optical semiconductor device and a method for manufacturing the same.

  Recently, phase shifters using silicon materials have been proposed (Non-Patent Documents 1 to 3).

  In the proposed technique, a P-type semiconductor layer is provided on one side of an I-type optical waveguide, and an N-type semiconductor layer is provided on the other side of the I-type optical waveguide, and a PIN structure is provided. (PIN diode) is formed.

  When a forward bias is applied to such a PIN structure, carriers are injected into the optical waveguide. When carriers are injected into the optical waveguide, a carrier plasma effect occurs in the optical waveguide, and the refractive index of light in the optical waveguide changes. When the refractive index of light in the optical waveguide changes, the wavelength of the light traveling through the optical waveguide changes, so that the phase of the light can be changed in the course of traveling through the optical waveguide.

William M. J. Green et al., “Ultra-compact, low RF power, 10 Gb / s silicon Mach-Zehnder modulator”, Optics Express, Vol. 15, No. 25, pp. 17106-17113 (2007) Tom Baehr-Jones et al., “Nonlinear polymer-clad silicon slot waveguide modulator with a half wave voltage of 0.25 V”, Applied Physics Letters, Vol. 92, 163303 (2008) F. Gan et al., “Compact, Low-Power, High-Speed Silicon Electro-Optic Modulator”, Conference on Laser and Electro-optics 2007, CTuQ6 (2007)

  However, in the proposed technology, since the capacitance of the PIN diode is relatively large, the CR time constant is large, and it is not always possible to obtain good high frequency characteristics.

  An object of the present invention is to provide an optical semiconductor device having good high-frequency characteristics and a method for manufacturing the same.

  According to one aspect of the embodiment, an intrinsic semiconductor layer formed on a substrate, an optical waveguide that is a part of the semiconductor layer, and formed on the semiconductor layer on one side of the optical waveguide, A first impurity region into which a first conductivity type impurity is introduced and a second conductivity type impurity that is formed in the semiconductor layer on the other side of the optical waveguide and into which a second conductivity type opposite to the first conductivity type is introduced. A capacitor having two impurity regions, a lower electrode that is a part of the second impurity region, an insulating film formed on at least the lower electrode, and an upper electrode formed on the insulating film; There is provided an optical semiconductor device having a third impurity region formed in the semiconductor layer in a part of the lower region of the upper electrode and introduced with the impurity of the first conductivity type.

  According to another aspect of the embodiment, an intrinsic semiconductor layer formed on a substrate, an optical waveguide that is a part of the semiconductor layer, and formed on the semiconductor layer on one side of the optical waveguide, A first impurity region introduced with a first conductivity type impurity and a second conductivity type impurity opposite to the first conductivity type formed in the semiconductor layer on the other side of the optical waveguide. A capacitor having a second impurity region, a lower electrode which is a part of the second impurity region, an insulating film formed on at least the lower electrode, and an upper electrode formed on the insulating film; And a third impurity region formed in the semiconductor layer on the other side of the lower electrode and doped with the second conductivity type impurity at a lower impurity concentration than the second impurity region. Optical semiconductor device There is provided.

  According to still another aspect of the embodiment, a step of forming an optical waveguide in a part of the semiconductor layer by etching an intrinsic semiconductor layer formed on the substrate, and one side of the optical waveguide A step of forming a first impurity region by introducing an impurity of a first conductivity type into the semiconductor layer in the semiconductor layer, and a region excluding a predetermined region in the semiconductor layer on the other side of the optical waveguide. Introducing an impurity of a second conductivity type opposite to the first conductivity type to form a second impurity region, and introducing the impurity of the first conductivity type into the semiconductor layer in the predetermined region Thus, a step of forming a third impurity region, and an upper electrode is formed on the second impurity region and the third impurity region with an insulating film interposed therebetween, whereby one of the second impurity regions is formed. In the department A lower electrode that, said insulating film, a method of manufacturing an optical semiconductor device characterized by a step of forming a capacitor having said upper electrode.

  According to still another aspect of the embodiment, a step of forming an optical waveguide in a part of the semiconductor layer by etching an intrinsic semiconductor layer formed on the substrate, and one side of the optical waveguide A step of forming a first impurity region by introducing an impurity of a first conductivity type into the semiconductor layer in the semiconductor layer, and a region excluding a predetermined region in the semiconductor layer on the other side of the optical waveguide. Introducing an impurity of a second conductivity type opposite to the first conductivity type to form a second impurity region and introducing an impurity of the second conductivity type into the semiconductor layer in the predetermined region A step of forming a third impurity region having an impurity concentration lower than that of the second impurity region, and an upper portion of the third impurity region on the one side of the third impurity region via an insulating film. Electrode And forming a capacitor having a lower electrode that is a part of the second impurity region, the insulating film, and the upper electrode, thereby forming an optical semiconductor device. Is provided.

  According to the disclosed optical semiconductor device and the manufacturing method thereof, the first impurity region of the first conductivity type is formed in the semiconductor layer on one side of the optical waveguide of the intrinsic semiconductor, and the semiconductor layer on the other side of the optical waveguide. A second impurity region of the second conductivity type is formed. A capacitor is formed by the lower electrode which is a part of the second impurity region, the insulating film formed on the lower electrode, and the upper electrode formed on the insulating film. A third impurity region of the first conductivity type is formed in the semiconductor layer in the lower region of the upper electrode of the capacitor. When a voltage is applied to the upper electrode of the capacitor, an inversion layer is formed in the third impurity region. The third impurity region is formed as a resistance layer. For this reason, a capacitor or a resistor can be directly connected to the PIN structure without performing wiring. Therefore, it is possible to provide an optical semiconductor device with good high frequency characteristics.

It is sectional drawing which shows the optical semiconductor device by 1st Embodiment. 1 is a plan view showing an optical semiconductor device according to a first embodiment. 1 is a perspective view showing an optical semiconductor device according to a first embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. FIG. 9 is a process cross-sectional view (part 2) illustrating the method for manufacturing the optical semiconductor device according to the first embodiment; It is process sectional drawing (the 3) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. FIG. 11 is a process cross-sectional view (part 4) illustrating the method for manufacturing the optical semiconductor device according to the first embodiment; It is process sectional drawing (the 5) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. It is process sectional drawing (the 6) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. It is sectional drawing which shows the optical semiconductor device by 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the optical semiconductor device by 2nd Embodiment. It is sectional drawing which shows the optical semiconductor device by the modification of 2nd Embodiment. It is sectional drawing which shows the optical semiconductor device by 3rd Embodiment. It is a top view which shows the optical semiconductor device by 3rd Embodiment. It is a perspective view which shows the optical semiconductor device by 3rd Embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the optical semiconductor device by 3rd Embodiment. It is process sectional drawing (the 2) which shows the manufacturing method of the optical semiconductor device by 3rd Embodiment. It is process sectional drawing (the 3) which shows the manufacturing method of the optical semiconductor device by 3rd Embodiment. It is process sectional drawing (the 4) which shows the manufacturing method of the optical semiconductor device by 3rd Embodiment. It is process sectional drawing (the 5) which shows the manufacturing method of the optical semiconductor device by 3rd Embodiment. It is process sectional drawing (the 6) which shows the manufacturing method of the optical semiconductor device by 3rd Embodiment. It is sectional drawing which shows the optical semiconductor device by 4th Embodiment. It is process sectional drawing which shows the manufacturing method of the optical semiconductor device by 4th Embodiment. It is sectional drawing which shows the optical semiconductor device by the modification of 4th Embodiment. It is a figure which shows an equivalent circuit.

  FIG. 25A shows an equivalent circuit of a phase shifter having a PIN structure.

  Since the capacitance of the PIN diode is relatively large, the CR time constant is relatively large, and good high frequency characteristics cannot always be obtained.

  In order to improve the high-frequency characteristics, it is conceivable to add a capacitor or a resistor as shown in FIG. 25B (see Non-Patent Document 3).

  However, when a capacitor or a resistor is simply added, the parasitic capacitance increases due to the wiring for connecting the capacitor and the resistor, and it is difficult to obtain good high-frequency characteristics.

[First Embodiment]
The optical semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

(Optical semiconductor device)
First, the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 1 is a sectional view of the optical semiconductor device according to the present embodiment. FIG. 2 is a plan view of the optical semiconductor device according to the present embodiment. FIG. 3 is a perspective view showing the optical semiconductor device according to the present embodiment.

  In the present embodiment, an optical phase shifter is described as an example of the optical semiconductor device, but the present invention is not limited to the phase shifter and can be applied to various optical semiconductor devices.

  A semiconductor layer 14 is formed on the semiconductor substrate 10 via an insulating film 12. Here, for example, an SOI substrate in which a silicon layer 14 is formed on a silicon substrate 10 via a buried oxide film 12 is used. The thickness of the insulating film 12 is, for example, about 2 to 3 μm. Since the thickness of the insulating film 12 is set to be sufficiently thick, the capacitance between the semiconductor substrate 10 and the semiconductor layer 14 is suppressed to be sufficiently small.

  The semiconductor layer 14 is processed into a rib shape. The portion of the semiconductor layer 14 where the thickness is thick (rib portion) is an optical waveguide 18. The height of the optical waveguide 18, that is, the vertical dimension of the optical waveguide 18 in FIG. 1 is, for example, about 250 nm. The width of the optical waveguide 18, that is, the dimension in the horizontal direction of the optical waveguide 18 in FIG. 1 is, for example, about 500 nm. The thickness of the thinned portion of the semiconductor layer 14 is, for example, about 50 nm. The optical waveguide 18 extends in the direction perpendicular to the paper surface in FIG. The optical signal introduced into the optical waveguide 18 travels in the direction perpendicular to the paper surface in FIG. The length of the optical waveguide 18, that is, the dimension of the optical waveguide 18 in the direction perpendicular to the plane of FIG. 1 is, for example, about 1 mm. No dopant impurities are introduced into the optical waveguide 18. The optical waveguide 18 is formed of an intrinsic semiconductor, that is, an I (Intrinsic) type semiconductor.

A P-type impurity region (P ⁺ impurity region) 20 is formed in the semiconductor layer 14 on one side of the optical waveguide 18, that is, on the left side in FIG. The impurity region 20 is formed in parallel with the optical waveguide 18.

N-type impurity regions (N ⁺ impurity regions) 22 and 24 are formed on the semiconductor layer 14 on the other side of the optical waveguide 18, that is, on the right side in FIG. The impurity regions 22 and 24 are formed in regions excluding a predetermined region where the P-type impurity region 26 is formed. The impurity region 22 and the impurity region 24 are formed at a predetermined interval. The distance between the impurity region 22 and the impurity region 24 is, for example, about 200 nm.

  The semiconductor layer 14 in a region between the P-type impurity region 20 and the N-type impurity regions 22 and 24 is an intrinsic semiconductor region 14a.

  A PIN structure (PIN diode) 16 is formed by the P-type impurity region 20, the I-type optical waveguide 18, and the N-type impurity regions 22 and 24.

  A P-type impurity region 26 is formed between the N-type impurity region 22 and the N-type impurity region 24. The impurity region 26 functions as a resistance layer by forming an inversion layer when a predetermined voltage is applied to the upper electrode 30 of the capacitor 32. The dimension of the impurity region 26 in the left-right direction on the paper surface is, for example, about 200 nm. The impurity region 26 is formed in parallel with the optical waveguide 18.

  The resistance value of the resistance layer 26 when a predetermined voltage is applied to the upper electrode 30 of the capacitor 32 is, for example, about 100 to 500Ω.

  Since the current flowing through the PIN structure 16 is about 10 μA per 1 μm of the optical waveguide length, there is no particular problem even with the electric resistance obtained by forming the inversion layer.

  Since the current flowing through the inversion layer has saturation characteristics with respect to the voltage, the differential resistance of the resistance layer is set to about 10 to 100 times the differential resistance of the PIN diode 16 by appropriately setting the channel length of the inversion layer. Is possible.

  The resistance value of the resistance layer 26 is not limited to 100 to 500Ω. The resistance value of the resistance layer 26 can be appropriately set so as to obtain a desired high frequency characteristic. The resistance value of the resistance layer 26 can be adjusted by appropriately setting the concentration of the P-type dopant impurity introduced into the impurity region 26, the voltage value applied to the upper electrode 30 of the capacitor 32, and the like.

  An upper electrode 30 is formed on the impurity regions 22 and 24 and the impurity region 26 via an insulating film (dielectric film) 28. The insulating film 28 is made of, for example, a silicon oxide film. The thickness of the insulating film 28 is, for example, about 3 to 10 nm. Here, the film thickness of the insulating film 28 is, for example, about 3 nm. The upper electrode 30 is formed of, for example, a polysilicon film into which an N-type dopant impurity is introduced. The upper electrode 30 is formed in parallel with the optical waveguide 18. The dimension of the upper electrode 30 in the left-right direction in FIG. 1 is about 800 nm, for example. The size of the region where the upper electrode 30 and the impurity region 22 overlap with each other in the left-right direction on the paper surface is, for example, about 500 nm.

  A capacitor (MOS capacitor) 32 is formed by the lower electrode which is a part of the impurity region 22, the insulating film 28, and the upper electrode 30. The capacitance of the capacitor 32 is preferably about 1/10 to 1/100 of the capacitance of the PIN diode 16. Here, the capacitance of the capacitor 32 is, for example, about 0.1 to 0.5 pF.

  Note that the capacitance of the capacitor 32 is not limited to 0.1 to 0.5 pF. What is necessary is just to set the electrostatic capacitance of the capacitor 32 suitably so that a desired high frequency characteristic may be acquired. The capacitance of the capacitor 32 can be adjusted by appropriately setting the facing area between the impurity region 22 and the upper electrode 30, the thickness of the capacitor dielectric film 28, the material, and the like.

  Here, the case where a part of the impurity region 24 and the upper electrode 30 overlap is described as an example, but a part of the impurity region 24 and the upper electrode 30 do not need to overlap.

  The capacitor 32 is for reducing the CR time constant of the PIN structure 16. In order to reduce the CR time constant of the PIN structure 16, it is preferable to connect the capacitor 32 directly to the impurity region 22 serving as the cathode. Therefore, in this embodiment, a part of the impurity region 22 also serves as the lower electrode of the capacitor 32, and a part of the impurity region 22 and a part of the upper electrode 30 of the capacitor 32 overlap each other.

  Since the conductivity type of the impurity region 26 is opposite to that of the impurity regions 22 and 24, the impurity region 26 is in a very high resistance state when no bias is applied to the upper electrode 30 of the capacitor 32. . In the present embodiment, an inversion layer is formed in the impurity region 26 by applying a predetermined bias voltage to the upper electrode 30 of the capacitor 32, and the resistance value of the impurity region 26 is set to a desired resistance value. It is preferable that the impurity region 26 be positioned in a lower region of the upper electrode 30 so that an inversion layer is formed in the impurity region 26 when a predetermined bias voltage is applied to the upper electrode 30 of the capacitor 32.

  In order to achieve miniaturization, it is preferable to set the size of the upper electrode 30 in the left-right direction in FIG. 1 to be relatively small. In order to ensure sufficient capacitance of the capacitor 32 while miniaturization, the position of the center line of the impurity region 26 is on the right side of the page in FIG. 1 with respect to the position of the center line of the upper electrode 30 of the capacitor 32. positioned.

  On the semiconductor layer 14 on which the capacitor 32 is formed, for example, an interlayer insulating film 34 of a silicon oxide film is formed. The film thickness of the interlayer insulating film 34 is, for example, about 1 μm.

  An opening 36 a reaching the upper electrode 30, an opening 36 b reaching the impurity region 20, and an opening 36 c reaching the impurity region 24 are formed in the interlayer insulating film 34.

  For example, a silicide film 38 of nickel silicide is formed on the bottom surfaces of the contact holes 36a to 36c.

  In the openings 36a to 36c in which the silicide film 38 is formed and on the interlayer insulating film 34, for example, an adhesion layer 40 formed of a laminated film of a Ti film and a TiN film is formed.

  For example, aluminum wiring layers (electrodes) 42 a to 42 c are formed in the openings 36 a to 36 c in which the adhesion layer 40 is formed and on the interlayer insulating film 34. The wiring layer 42 a is connected to the upper electrode 30 of the capacitor 32. The wiring layer 42 b is connected to the impurity region 20. The wiring layer 42 c is connected to the impurity region 24.

  Thus, the optical semiconductor device according to the present embodiment is formed.

  Next, the operation of the optical semiconductor device according to the present embodiment will be explained.

  Here, a case where the wiring layer 42a is a ground line, the wiring layer 42b is a signal line, and the wiring layer 42c is a DC bias line will be described as an example.

A DC bias voltage V _bias is applied between the ground line 42a and the DC bias line 42c.

Between the ground line 42a and the signal line 42b, the input signal voltage _{V in} is applied.

First, the bias voltage V _bias applied between the ground line 42a and the DC bias line 42c will be described.

The bias voltage V _bias is set so that an inversion layer is formed in the impurity region 26 located in the region below the upper electrode 30 of the capacitor 32, and the impurity region 26 becomes a resistance layer having a desired resistance value. The bias voltage V _bias is about 0.9V, for example. When the potential of the ground line 42a is set to 0V, the potential of the bias line 42c is set to −0.9V. When such a bias voltage V _bias is applied, an inversion layer is formed in the impurity region 26 located below the upper electrode 30 of the capacitor 32, and the impurity region 26 can function as a resistance layer having a desired resistance value.

  In the present embodiment, not only the capacitor 32 but also the resistance layer 26 is connected to the PIN structure 16 in order to ensure the balance of the circuit. That is, when the capacitor 32 is simply connected in series with the cathode of the PIN diode 16, the circuit balance is lost and desired electrical characteristics cannot be obtained. In order to ensure the balance of the circuit, it is preferable to connect not only the capacitor 32 but also an electric resistance. For this reason, in this embodiment, not only the capacitor 32 but also the resistance layer 26 is formed.

Note that the bias voltage V _bias is not limited to 0.9V. Upon application of a bias voltage V _bias, so that a desired resistance value in the impurity region 26 is obtained, it may be appropriately set a bias voltage V _bias.

Next, a description will be given input signal voltage _{V in} applied between the ground line 42a and the signal line 42b.

The input signal voltage _{V in,} for example, a logic signal of a high frequency (RF, Radio Frequency) are used.

When the data of the input signal is 1, i.e., the input signal voltage _{V in} at the time of the input signal is "H (High)" level is, e.g., about 0.5V. A bias voltage _{V bias} is, for example 0.9V, if the input signal voltage _{V in} is, for example, 0.5V, the potential of the impurity region 24 is for example 1.4V higher potential relative to the potential of the impurity region 20. When the voltage drop generated in the resistance layer 26 is about 0.4V, for example, a forward bias of about 1V is applied to the PIN structure 16. Since a sufficiently large forward bias is applied to the PIN structure 16, carriers (electrons and holes) are injected into the optical waveguide 18. When carriers are injected into the optical waveguide 18, the refractive index of light in the optical waveguide 18 decreases due to the carrier plasma effect, and the phase of the optical signal traveling through the optical waveguide 18 shifts. Therefore, when the input signal is at “H” level, the phase of the optical signal traveling through the optical waveguide 18 changes.

When the data input signal is 0, i.e., the input signal voltage _{V in} at the time of the input signal is "L (Low)" level is, e.g., about -0.5 V. A bias voltage _{V bias} is, for example 0.9V, if the input signal voltage _{V in} is, for example, -0.5 V, the potential of the impurity region 24 is for example 0.4V higher potential relative to the potential of the impurity region 20. When the voltage drop generated in the resistance layer 26 is about 0.2V, for example, a forward bias of about 0.2V is applied to the PIN structure 16. Since the forward bias applied to the PIN structure 16 is small, sufficient carriers are not injected into the optical waveguide 18 in this case, and the carrier plasma effect is suppressed. Accordingly, when the input signal is at the “L” level, the refractive index of the optical waveguide 18 increases, and the phase of the optical signal traveling through the optical waveguide 18 shifts in the opposite direction.

The input signal voltage _{V in} is not intended to be limited to ± 0.5V. As desired phase shift amount can be obtained, it may be appropriately set an input signal voltage V _in.

  In the optical semiconductor device according to the present embodiment, a capacitor 32 is formed by a part of the impurity region 22 forming the cathode of the PIN structure 16, the insulating film 28, and the upper electrode 30. In the optical semiconductor device according to the present embodiment, the resistance layer is formed by the impurity region 26 formed in the region below the upper electrode 30 of the capacitor 32. Therefore, in the present embodiment, the capacitor 32 and the resistance layer 26 can be connected to the PIN structure 16 without performing wiring. Therefore, according to the present embodiment, an optical semiconductor device with good high-frequency characteristics can be provided.

(Manufacturing method of optical semiconductor device)
Next, the method for fabricating the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. 4 to 9 are process cross-sectional views illustrating the method for manufacturing the optical semiconductor device according to the present embodiment.

  First, an SOI (Silicon On Insulator) 15 in which a semiconductor layer 14 is formed on a semiconductor substrate 10 via an insulating film (buried oxide film) 12 is prepared (see FIG. 4A). For example, a silicon substrate is used as the semiconductor substrate 10. As the insulating film 12, for example, a silicon oxide film having a thickness of about 2 to 3 μm is formed. As the semiconductor layer 14, an I (Intrinsic) type, ie, intrinsic semiconductor silicon layer 14 is formed. The thickness of the silicon layer 14 is, for example, about 250 nm.

  Next, a photoresist film 44 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 44 is patterned into a planar shape of the optical waveguide 18 by using a photolithography technique.

  Next, the semiconductor layer 14 is anisotropically etched using the photoresist film 44 as a mask. At this time, the semiconductor layer 14 is etched until the thickness of the portion of the semiconductor layer 14 not covered with the photoresist film 44 becomes, for example, about 50 nm.

  Thus, a rib-type optical waveguide 18 is formed (see FIG. 4B). The width of the optical waveguide 18, that is, the horizontal dimension of the optical waveguide 18 in FIG. The height of the optical waveguide 18, that is, the vertical dimension of the optical waveguide 18 in FIG. 4B is about 250 nm, for example. The optical waveguide 18 is formed so as to extend in the direction perpendicular to the paper surface in FIG. The thickness of the semiconductor layer 14 excluding the optical waveguide 18 is, for example, about 50 nm.

  Thereafter, the photoresist film 44 is removed by, for example, ashing.

  Next, a photoresist film 46 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 46 is patterned using a photolithography technique. As a result, an opening 48 for forming the P-type impurity region 20 is formed in the photoresist film 46.

Next, a P-type impurity region (P ⁺ -type impurity region) 20 is formed by introducing a P-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 46 as a mask. (See FIG. 5 (a)). The ion implantation conditions are as follows. For example, boron is used as the P-type dopant impurity. The impurity concentration is, for example, about 1 × 10 ¹⁹ cm ⁻³ . The impurity region 20 is formed in parallel with the optical waveguide 18.

  Thereafter, the photoresist film 46 is removed by, for example, ashing.

  Next, a photoresist film 50 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 50 is patterned using a photolithography technique. As a result, openings 52 a and 52 b for forming the impurity regions 22 and 24 are formed in the photoresist film 50.

Next, N-type impurity regions (N ⁺ -type impurity regions) 22 and 24 are formed by introducing an N-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 50 as a mask. (See FIG. 5 (b)). The ion implantation conditions are as follows. For example, phosphorus is used as the N-type dopant impurity. The impurity concentration is, for example, about 1 × 10 ¹⁹ cm ⁻³ . The impurity region 22 is formed in the semiconductor layer 14 on the other side of the optical waveguide 18 so as to be parallel to the optical waveguide 18. The impurity region 24 is formed to be parallel to the optical waveguide 18 at a predetermined interval from the impurity region 22. The dimension between the impurity region 22 and the impurity region 24 is, for example, about 200 nm.

  Thereafter, the photoresist film 50 is removed by, for example, ashing.

  Next, a photoresist film 54 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 54 is patterned using a photolithography technique. Thereby, an opening 56 for forming the impurity region 26 is formed in the photoresist film 54.

Next, a P-type impurity region (resistance layer) 26 is formed by introducing a P-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 54 as a mask (FIG. 6A). )reference). The ion implantation conditions are as follows. For example, boron is used as the dopant impurity. The impurity concentration is, for example, about 5 × 10 ¹⁷ cm ⁻³ . The impurity region 26 is formed between the impurity region 22 and the impurity region 24 so as to be parallel to the optical waveguide 18. The dimension of the impurity region 26 in the left-right direction in FIG. 6A is about 200 nm, for example.

  Thereafter, the photoresist film 54 is removed by, for example, ashing.

  Next, as shown in FIG. 6B, an insulating film 28 of a silicon oxide film is formed by, eg, thermal oxidation. The film forming temperature is about 900 ° C., for example. The thickness of the insulating film 28 is, for example, about 3 to 10 nm. Here, the film thickness of the insulating film 28 is, for example, about 3 nm.

Next, a polysilicon film into which an N-type dopant is introduced is formed by, for example, a CVD (Chemical Vapor Deposition) method (see FIG. 7A). For example, phosphorus is used as the dopant impurity. The thickness of the polysilicon film is, for example, about 150 nm. The impurity concentration in the polysilicon film is, for example, about 1 × 10 ²⁰ cm ⁻³ .

  Next, a photoresist film 57 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 57 is patterned into a planar shape of the upper electrode 30 of the capacitor 32 by using a photolithography technique.

  Next, the polysilicon film 30 is anisotropically etched using the photoresist film 57 as a mask (see FIG. 7B). Thereby, the upper electrode 30 of polysilicon is formed. The upper electrode 30 is formed in parallel with the optical waveguide 18.

  Thereafter, the photoresist film 57 is removed by, for example, ashing.

  Thus, the capacitor 33 having the lower electrode, which is a part of the impurity region 22, the insulating film 28, and the upper electrode 30 is formed. The dimension of the region where the upper electrode 30 of the capacitor 32 and the impurity region 22 overlap in the left-right direction of FIG.

  Next, as shown in FIG. 8A, a silicon oxide interlayer insulating film 34 having a thickness of about 1 μm is formed on the entire surface by, eg, CVD.

  Next, using an photolithography technique, an opening 36 a reaching the upper electrode 30 of the capacitor 32, an opening 36 b reaching the N-type impurity region 20, and an opening 36 c reaching the N-type impurity region 24 are formed into a photo It forms in the resist film 34 (refer FIG.8 (b)). The openings 36a, 36b, and 36c are formed so as to be parallel to the optical waveguide 18, respectively.

  Next, a nickel film (not shown) is formed on the entire surface by, eg, sputtering.

  Next, the nickel film and the semiconductor layer 14 are reacted by performing heat treatment. As a result, nickel in the nickel film and silicon in the semiconductor layer 14 react to form a silicide film 38 of nickel silicide.

  Next, the unreacted nickel film is removed by, for example, wet etching. Thus, silicide films 38 are respectively formed on the bottom surfaces of the openings 36a to 36c (see FIG. 9A).

  Next, a Ti film having a thickness of 2 nm is formed on the entire surface by, eg, sputtering.

  Next, a 2 nm-thick TiN film is formed on the entire surface by, eg, sputtering. Thus, the adhesion layer 40 formed by the laminated film of the Ti film and the TiN film is formed in the openings 36 a to 36 c and on the interlayer insulating film 34.

  Next, an aluminum film having a thickness of 200 nm is formed on the entire surface by, eg, sputtering.

  Next, the aluminum film and the adhesion layer 40 are patterned using a photolithography technique. Thus, for example, aluminum wiring layers (electrodes) 42a to 42c are formed in the openings 36a to 36c and on the interlayer insulating film 34 (see FIG. 9B).

  Thus, the optical semiconductor device according to the present embodiment is formed.

[Second Embodiment]
The optical semiconductor device and the manufacturing method thereof according to the second embodiment will be described with reference to FIGS. The same components as those of the optical semiconductor device according to the first embodiment shown in FIGS. 1 to 9 are denoted by the same reference numerals, and description thereof is omitted or simplified.

(Optical semiconductor device)
First, the optical semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 10 is a cross-sectional view of the optical semiconductor device according to the present embodiment.

  The optical semiconductor device according to the present embodiment is mainly characterized in that the resistance layer 26a is formed of an N-type impurity region.

As shown in FIG. 10, an N-type dopant impurity is introduced at a low concentration between the N-type impurity region (N ⁺ impurity region) 22 and the N-type impurity region (N ⁺ impurity region) 24. Impurity region (N ^- impurity region) 26a is formed. The concentration of the N-type dopant impurity in the impurity region 26 a is set lower than the concentration of the N-type dopant impurity in the impurity regions 22 and 24. Therefore, the carrier concentration in the impurity region 26 a is lower than the carrier concentration in the impurity regions 22 and 24.

  The resistance value in the impurity region 26a is, for example, about 100 to 500Ω.

As the N-type dopant impurity introduced into the impurity regions 22 and 24, for example, phosphorus is used. The concentration of the N-type dopant impurity in the impurity regions 22 and 24 is, for example, about 1 × 10 ¹⁹ cm ⁻³ .

For example, phosphorus is used as the N-type dopant impurity to be introduced into the impurity region 26a. The concentration of the N-type dopant impurity in the impurity region 26a is, for example, about 1 × 10 ¹⁷ cm ⁻³ .

  Note that the concentration of the dopant impurity in the impurity region 26a is not limited to the above. It can be set as appropriate so that a desired electric resistance can be obtained in the impurity region 26a.

  Further, the resistance value of the impurity region 26a is not limited to 100 to 500Ω. What is necessary is just to set the resistance value of the impurity region 26a suitably so that a desired high frequency characteristic may be acquired.

When an N-type impurity region is used as the resistance layer 26a, it is not necessary to apply a bias voltage for forming an inversion layer in the resistance layer 26a to the upper electrode 30 of the capacitor 32. For this reason, you may electrically short-circuit the wiring layer 42a and the wiring layer 42c. In this case, the input signal voltage _{V in} between a ground line 42a and the signal line 42b is applied.

  Thus, the resistance layer 26a may be formed of an N-type impurity region.

(Manufacturing method of optical semiconductor device)
Next, the method for fabricating the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 11 is a process cross-sectional view illustrating the method for manufacturing the optical semiconductor device according to the present embodiment.

  First, from the step of preparing the SOI substrate 16 to the step of forming the N-type impurity regions 22 and 24, the method of manufacturing the optical semiconductor device according to the first embodiment shown in FIGS. The description is omitted because it is similar.

  Next, a photoresist film 54 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 54 is patterned using a photolithography technique. Thereby, an opening 56 for forming the impurity region 26 a is formed in the photoresist film 54.

Next, an N-type impurity region (N ^- impurity region, resistance layer) 26a is formed by introducing an N-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 54 as a mask. (See FIG. 11 (a)). The ion implantation conditions are as follows. For example, phosphorus is used as the dopant impurity. The concentration of the N-type dopant impurity introduced into the N-type impurity region 26 a is, for example, 1 × 10 ¹⁷ cm ⁻³ and is set lower than the concentration of the N-type dopant impurity introduced into the N-type impurity regions 22, 24. The The carrier concentration of the N-type impurity region 26a is set lower than the carrier concentration of the N-type impurity regions 22 and 24. The impurity region 26 a is formed between the impurity region 22 and the impurity region 24 so as to be parallel to the optical waveguide 18. The dimension of the impurity region 26a in the left-right direction in FIG. 11A is about 200 nm, for example.

  Thereafter, the photoresist film 54 is removed by, for example, ashing.

  The subsequent manufacturing method of the optical semiconductor device is the same as the manufacturing method of the optical semiconductor device according to the first embodiment shown in FIG. 6B to FIG.

  Thus, the optical semiconductor device according to the present embodiment is manufactured (see FIG. 11B).

(Modification)
Next, a modification of the optical semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 12 is a cross-sectional view showing an optical semiconductor device according to this modification.

  The optical semiconductor device according to this modification is mainly characterized in that the resistance layer 26 a is located outside the region below the upper electrode 30 of the capacitor 32.

  As shown in FIG. 11, the resistance layer 26 a is located outside the region below the upper electrode 30 of the capacitor 32.

  When the resistance layer 26a is arranged between the capacitor 32 and the impurity region 22, good high frequency characteristics cannot be obtained. Therefore, when the impurity region 26 a is positioned outside the region below the upper electrode 30 of the capacitor 32, it is preferably positioned between the capacitor and the impurity region 24, not between the capacitor 32 and the impurity region 22. . Therefore, in the present embodiment, the resistance layer 26 a is formed on the right side of FIG. 11, that is, on the impurity region 24 side with respect to the upper electrode 30 of the capacitor 32.

  As described above, the impurity region 26 a may be disposed outside the region below the upper electrode 30 of the capacitor 32.

[Third Embodiment]
The optical semiconductor device and the manufacturing method thereof according to the third embodiment will be described with reference to FIGS. The same components as those of the optical semiconductor device and the manufacturing method thereof according to the first or second embodiment shown in FIGS. 1 to 12 are denoted by the same reference numerals, and description thereof is omitted or simplified.

(Optical semiconductor device)
First, the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 13 is a cross-sectional view of the optical semiconductor device according to the present embodiment. FIG. 14 is a plan view of the optical semiconductor device according to the present embodiment. FIG. 15 is a perspective view showing the optical semiconductor device according to the present embodiment.

  The optical semiconductor device according to the present embodiment is mainly characterized in that the optical waveguide 18a is formed by arranging a plurality of openings 58 in the semiconductor layer 14 on both sides of the region where the optical waveguide 18a is formed. .

  In the present embodiment, the semiconductor layer 14 is not formed into a rib shape. The thickness of the semiconductor layer 14 is uniform. In the present embodiment, as shown in FIG. 14, a plurality of openings 58 are formed in the semiconductor layer 14 on both sides of the region where the optical waveguide 18a is formed. The plurality of openings 58 define the optical waveguide 18a.

  The dimension of the opening 58 in the left-right direction in FIG. 14 is about 1 μm, for example. The dimension of the opening 58 in the vertical direction of the paper in FIG. 14 is, for example, about 250 nm. The pitch of the openings 58 is about 300 nm, for example.

  In a place where the opening 58 is formed, the progress of light is hindered. For this reason, the region 18a between the regions in which the plurality of openings 58 are arranged functions as an optical waveguide.

  Since the semiconductor layer 14 exists between the adjacent openings 58, it is possible to introduce carriers into the optical waveguide 18a.

  The dimension of the optical waveguide 18a in FIG. The width of the optical waveguide 18a, that is, the dimension of the optical waveguide 18a in FIG. The optical waveguide 18a extends in the direction perpendicular to the paper surface in FIG. The optical signal introduced into the optical waveguide 18a travels in the direction perpendicular to the paper surface in FIG. The length of the optical waveguide 18a, that is, the dimension of the optical waveguide 18a in the direction perpendicular to the plane of FIG. No dopant impurity is introduced into the optical waveguide 18a. The optical waveguide 18a is formed of an intrinsic semiconductor, that is, an I-type semiconductor.

A P-type impurity region (P ⁺ impurity region) 20 is formed on the semiconductor layer 14 on one side of the optical waveguide 18a, that is, on the left side in FIG. The impurity region 20 is formed in parallel with the optical waveguide 18a.

N-type impurity regions (N ⁺ impurity regions) 22 and 24 are formed in the semiconductor layer 14 on the other side of the optical waveguide 18, that is, on the right side in FIG. The impurity regions 22 and 24 are formed in regions other than the predetermined region where the impurity region 26 is formed. The impurity region 22 and the impurity region 24 are formed with a predetermined distance therebetween. The distance between the impurity region 22 and the impurity region 24 is, for example, about 200 nm.

  The semiconductor layer 14 in the region between the P-type impurity region 20 and the N-type impurity region 22 is an intrinsic semiconductor region 14b.

  The P-type impurity region 20, the I-type optical waveguide 18a, and the N-type impurity region 22 form a PIN structure (PIN diode) 16.

  A P-type impurity region 26 is formed between the N-type impurity region 22 and the N-type impurity region 24. The impurity region 26 functions as a resistance layer when a predetermined voltage is applied to the upper electrode 30 of the capacitor 32. The dimension of the impurity region 26 in the left-right direction on the paper surface is, for example, about 200 nm. The impurity region 26 is formed in parallel with the optical waveguide 18a. The resistance value of the resistance layer 26 when a predetermined voltage is applied to the upper electrode 30 of the capacitor 32 is, for example, about 100 to 500Ω.

  The resistance value of the resistance layer 26 is not limited to 100 to 500Ω. The resistance value of the resistance layer 26 can be appropriately set so as to obtain a desired high frequency characteristic. The resistance value of the resistance layer 26 can be adjusted by appropriately setting the concentration of the P-type dopant impurity introduced into the impurity region 26, the voltage value applied to the upper electrode 30 of the capacitor 32, and the like.

  An upper electrode 30 is formed on the impurity regions 22 and 24 and the impurity region 26 via an insulating film 28. The insulating film 28 is made of, for example, a silicon oxide film. The thickness of the insulating film 28 is, for example, about 3 to 10 nm. Here, the film thickness of the insulating film 28 is, for example, about 3 nm. The upper electrode 30 is formed of, for example, a polysilicon film into which an N-type dopant impurity is introduced. The upper electrode 30 is formed in parallel with the optical waveguide 18. The dimension of the upper electrode 30 in the left-right direction in FIG. 13 is about 800 nm, for example. The size of the region where the upper electrode 30 and the impurity region 22 overlap with each other in the left-right direction on the paper surface is, for example, about 500 nm.

  A capacitor 32 is formed by a part of the impurity region 22, the insulating film 28, and the upper electrode 30. The capacitance of the capacitor 32 is, for example, about 0.1 to 0.5 pF.

  Note that the capacitance of the capacitor 32 is not limited to 0.1 to 0.5 pF. What is necessary is just to set the electrostatic capacitance of the capacitor 32 suitably so that a desired high frequency characteristic may be acquired. The capacitance of the capacitor 32 can be adjusted by appropriately setting the facing area between the impurity region 22 and the upper electrode 30, the thickness of the capacitor dielectric film 28, the material, and the like.

  Here, the case where a part of the impurity region 24 and the upper electrode 30 overlap is described as an example, but a part of the impurity region 24 and the upper electrode 30 do not need to overlap.

  The capacitor 32 is for reducing the CR time constant of the PIN structure 16. In order to reduce the time constant of the PIN structure 16, it is preferable to connect the capacitor 32 directly to the impurity region 22 serving as the cathode. Therefore, in this embodiment, a part of the impurity region 22 also serves as one electrode of the capacitor 32, and a part of the impurity region 22 and a part of the upper electrode 30 of the capacitor 32 are overlapped.

  Since the conductivity type of the impurity region 26 is opposite to that of the impurity regions 22 and 24, the impurity region 26 is in a very high resistance state when no bias is applied to the upper electrode 30 of the capacitor 32. . In the present embodiment, an inversion layer is formed in the impurity region 26 by applying a predetermined bias voltage to the upper electrode 30 of the capacitor 32, and the resistance value of the impurity region 26 is set to a desired resistance value. It is preferable that the impurity region 26 be positioned in a lower region of the upper electrode 30 so that an inversion layer is formed in the impurity region 26 when a predetermined bias voltage is applied to the upper electrode 30 of the capacitor 32.

  Thus, the optical semiconductor device according to the present embodiment is formed.

The operation of the optical semiconductor device according to the present embodiment is the same as that of the optical semiconductor device according to the first embodiment described above, and a description thereof will be omitted. For example, as in the optical semiconductor device according to the first embodiment, the bias voltage V _bias is applied between the ground line 42a and the DC bias line 42c, and the input signal voltage V _in is between the ground line 42a and the signal line 42c. Can be operated in the same manner as the optical semiconductor device according to the first embodiment.

(Manufacturing method of optical semiconductor device)
Next, the method for fabricating the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. 16 to 21 are process cross-sectional views illustrating the method for manufacturing the optical semiconductor device according to the present embodiment.

  First, in the same manner as in the optical semiconductor device manufacturing method according to the first embodiment shown in FIG. 4A, an SOI substrate 15 in which a semiconductor layer 14 is formed on an insulating film 12 on a semiconductor substrate 10 is prepared ( FIG. 16 (a)).

  Next, a photoresist film 60 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 60 is patterned using a photolithography technique. Thereby, an opening 62 for forming the opening 58 is formed in the photoresist film 60.

  Next, the semiconductor layer 14 is etched using the photoresist film 60 as a mask and the insulating film 12 as an etching stopper, thereby forming a plurality of openings 58 in the semiconductor layer 14. As shown in FIGS. 14 and 15, the openings 58 are arranged on both sides of the region where the waveguide layer 18a is formed. The dimension of the opening 58 in the left-right direction in FIG. 16 is about 1 μm, for example. The dimension of the opening 58 in the direction perpendicular to the paper surface of FIG. 16 is, for example, about 250 nm. The pitch of the openings 58 in the direction perpendicular to the paper surface of FIG. 16 is about 300 nm, for example.

  In this way, the optical waveguide 18 a defined by the plurality of openings 58 is formed in the semiconductor layer 14. The width of the optical waveguide 18a, that is, the dimension in the horizontal direction of the optical waveguide 18a in FIG. The height of the optical waveguide 18a, that is, the vertical dimension of the optical waveguide 18a in FIG. 16B is about 250 nm, for example. The optical waveguide 18a is formed so as to extend in the direction perpendicular to the paper surface in FIG.

  Thereafter, the photoresist film 60 is removed by, for example, ashing.

  Next, a photoresist film 46 is formed on the entire surface by, eg, spin coating, in the same manner as in the method of manufacturing the optical semiconductor device according to the first embodiment.

  Next, the photoresist film 46 is patterned using a photolithography technique. As a result, an opening 48 for forming the P-type impurity region 20 is formed in the photoresist film 46.

Next, a P-type impurity region (P ⁺ -type impurity region) 20 is formed by introducing a P-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 46 as a mask. (See FIG. 17 (a)). The ion implantation conditions are as follows. For example, boron is used as the P-type dopant impurity. The impurity concentration is, for example, about 1 × 10 ¹⁹ cm ⁻³ . The impurity region 20 is formed in parallel with the optical waveguide 18.

  Thereafter, the photoresist film 46 is removed by, for example, ashing.

  Next, a photoresist film 50 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 50 is patterned using a photolithography technique. As a result, openings 52 a and 52 b for forming the impurity regions 22 and 24 are formed in the photoresist film 50.

Next, N-type impurity regions (N ⁺ -type impurity regions) 22 and 24 are formed by introducing an N-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 50 as a mask. (See FIG. 17B). The ion implantation conditions are as follows. For example, phosphorus is used as the N-type dopant impurity. The impurity concentration is, for example, about 1 × 10 ¹⁹ cm ⁻³ . The impurity region 22 is formed in the semiconductor layer 14 on the other side of the optical waveguide 18 so as to be parallel to the optical waveguide 18. The impurity region 24 is formed to be parallel to the optical waveguide 18 at a predetermined interval from the impurity region 22. The dimension between the impurity region 22 and the impurity region 24 is, for example, about 200 nm.

  Thereafter, the photoresist film 50 is removed by, for example, ashing.

  Next, a photoresist film 54 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 54 is patterned using a photolithography technique. Thereby, an opening 56 for forming the impurity region 26 is formed in the photoresist film 54.

Next, a P-type impurity region (resistance layer) 26 is formed by introducing a P-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 54 as a mask (FIG. 18A). )reference). The ion implantation conditions are as follows. For example, boron is used as the dopant impurity. The impurity concentration is, for example, about 5 × 10 ¹⁷ cm ⁻³ . The impurity region 26 is formed between the impurity region 22 and the impurity region 24 so as to be parallel to the optical waveguide 18. The dimension of the impurity region 26 in the left-right direction in FIG. 18A is about 200 nm, for example.

  The subsequent manufacturing method of the optical semiconductor device is the same as the manufacturing method of the semiconductor device according to the first embodiment described above with reference to FIGS. 6B to 9B, and thus the description thereof is omitted (FIG. 18). (See (b) to FIG. 21 (b)).

  Thus, the optical semiconductor device according to the present embodiment is formed.

[Fourth Embodiment]
The optical semiconductor device and the manufacturing method thereof according to the fourth embodiment will be described with reference to FIGS. The same components as those of the optical semiconductor device and the manufacturing method thereof according to the first to third embodiments shown in FIGS. 1 to 21 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

(Optical semiconductor device)
First, the optical semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 22 is a cross-sectional view of the optical semiconductor device according to the present embodiment.

  The optical semiconductor device according to the present embodiment is mainly characterized in that the resistance layer 26a is formed of an N-type impurity region.

As shown in FIG. 22, an N-type dopant impurity is introduced at a low concentration between the N-type impurity region (N ⁺ impurity region) 22 and the N-type impurity region (N ⁺ impurity region) 24. Impurity region (N ^- impurity region) 26a is formed. The concentration of the N-type dopant impurity in the impurity region 26 a is set lower than the concentration of the N-type dopant impurity in the impurity regions 22 and 24. Therefore, the carrier concentration in the impurity region 26 a is lower than the carrier concentration in the impurity regions 22 and 24.

  The resistance value in the impurity region 26a is, for example, about 100 to 500Ω.

As the N-type dopant impurity introduced into the impurity regions 22 and 24, for example, phosphorus is used. The concentration of the N-type dopant impurity in the impurity regions 22 and 24 is, for example, about 1 × 10 ¹⁹ cm ⁻³ .

For example, phosphorus is used as the N-type dopant impurity to be introduced into the impurity region 26a. The concentration of the N-type dopant impurity in the impurity region 26a is, for example, about 1 × 10 ¹⁷ cm ⁻³ .

  Note that the concentration of the dopant impurity in the impurity region 26a is not limited to the above. It can be set as appropriate so that a desired electric resistance can be obtained in the impurity region 26a.

  Further, the resistance value of the impurity region 26a is not limited to 100 to 500Ω. What is necessary is just to set the resistance value of the impurity region 26a suitably so that a desired high frequency characteristic may be acquired.

When an N-type impurity region is used as the resistance layer 26a, it is not necessary to apply a bias voltage for forming an inversion layer in the resistance layer 26a to the upper electrode 30 of the capacitor 32. For this reason, you may electrically short-circuit the wiring layer 42a and the wiring layer 42c. In this case, the input signal voltage _{V in} between a ground line 42a and the signal line 42b is applied.

  Thus, the resistance layer 26a may be formed of an N-type impurity region.

(Manufacturing method of optical semiconductor device)
Next, the method for fabricating the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 23 is a process sectional view showing the method for manufacturing the optical semiconductor device according to the present embodiment.

  First, from the step of preparing the SOI substrate 16 to the step of forming the N-type impurity regions 22 and 24, the method of manufacturing the optical semiconductor device according to the third embodiment shown in FIGS. Since it is the same, description is abbreviate | omitted.

  Next, a photoresist film 54 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 54 is patterned using a photolithography technique. Thereby, an opening 56 for forming the impurity region 26 a is formed in the photoresist film 54.

Next, an N-type impurity region (N ^- impurity region, resistance layer) 26a is formed by introducing an N-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 54 as a mask. (See FIG. 23 (a)). The ion implantation conditions are as follows. For example, phosphorus is used as the dopant impurity. The impurity concentration is, for example, about 1 × 10 ¹⁷ cm ⁻³ . The concentration of the N-type dopant impurity introduced into the N-type impurity region 26 a is set lower than the concentration of the N-type dopant impurity introduced into the N-type impurity regions 22 and 24. The carrier concentration of the N-type impurity region 26a is set lower than the carrier concentration of the N-type impurity regions 22 and 24. The impurity region 26 a is formed between the impurity region 22 and the impurity region 24 so as to be parallel to the optical waveguide 18. The dimension of the impurity region 26a in the left-right direction in FIG. 23A is, for example, about 200 nm.

  Thereafter, the photoresist film 54 is removed by, for example, ashing.

  The subsequent manufacturing method of the optical semiconductor device is the same as the manufacturing method of the optical semiconductor device according to the third embodiment shown in FIG. 18B to FIG.

  Thus, the optical semiconductor device according to the present embodiment is manufactured (see FIG. 23B).

(Modification)
Next, a modification of the optical semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 24 is a cross-sectional view showing an optical semiconductor device according to this modification.

  The optical semiconductor device according to this modification is mainly characterized in that the resistance layer 26 a is located outside the region below the upper electrode 30 of the capacitor 32.

  As shown in FIG. 24, the resistance layer 26 a is located outside the region below the upper electrode 30 of the capacitor 32.

  When the resistance layer 26a is arranged between the capacitor 32 and the impurity region 22, good high frequency characteristics cannot be obtained. Therefore, when the impurity region 26 a is positioned outside the region below the upper electrode 30 of the capacitor 32, it is preferably positioned between the capacitor and the impurity region 24, not between the capacitor 32 and the impurity region 22. . Therefore, in the present embodiment, the resistance layer 26a is formed on the right side of FIG. 24, that is, on the impurity region 24 side with respect to the upper electrode 30 of the capacitor 32.

  As described above, the impurity region 26 a may be disposed outside the region below the upper electrode 30 of the capacitor 32.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above embodiment, the case where a silicon layer is used as the material of the semiconductor layer 14 has been described as an example, but the semiconductor layer 14 is not limited to the silicon layer. For example, an indirect transition type semiconductor layer such as a germanium layer may be used as the semiconductor layer 14.

  In the above embodiment, a silicon oxide film is used as the insulating film 28. However, the insulating film 28 is not limited to a silicon oxide film. For example, an Hf oxide film or the like may be used as the insulating film 28. Further, as the insulating film 28, a silicon nitride film or the like may be used.

  In the above embodiment, the case where the capacitor 32 and the resistance layers 26 and 26a are provided on the cathode side of the PIN structure 16 has been described as an example. However, the present invention is not limited to this. For example, the capacitor 32 and the resistance layers 26 and 26a may be provided on the anode side of the PIN structure 16. In this case, the conductivity type of the upper electrode 30 and the resistance layers 26 and 26a may be set to a conductivity type opposite to the conductivity type of the above embodiment.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, silicon substrate 12 ... Insulating film, buried insulating film 14 ... Semiconductor layer, silicon layers 14a, 14b ... I type semiconductor 15 ... SOI substrate 16 ... PIN structure, PIN diodes 18, 18a ... Optical waveguide 20 ... P type Impurity region 22 ... N-type impurity region 24 ... N-type impurity region 26 ... P-type impurity region 26a ... N-type impurity region 28 ... Insulating film 30 ... Upper electrode 32 ... Capacitor 34 ... Interlayer insulating films 36a to 36c ... Opening 38 ... Silicide film 40 ... adhesion layer 42a ... wiring layer, electrode, ground line 42b ... wiring layer, electrode, signal line 42c ... wiring layer, electrode, DC bias line 44 ... photoresist film 46 ... photoresist film 48 ... opening 50 ... Photoresist films 52a, 52b ... opening 54 ... photoresist film 56 ... opening 57 ... photoresist film 58 ... opening 60 ... photo Resist film 62 ... opening

Claims (8)

An intrinsic semiconductor layer formed on a substrate;
An optical waveguide that is part of the semiconductor layer;
A first impurity region formed in the semiconductor layer on one side of the optical waveguide and doped with an impurity of a first conductivity type;
A second impurity region formed in the semiconductor layer on the other side of the optical waveguide and introduced with an impurity of a second conductivity type opposite to the first conductivity type;
A capacitor having a lower electrode which is a part of the second impurity region, an insulating film formed on at least the lower electrode, and an upper electrode formed on the insulating film;
A third impurity region formed in the semiconductor layer in a part of the lower region of the upper electrode and introduced with the impurity of the first conductivity type ;
A first electrode connected to the first impurity region;
An optical semiconductor device comprising: a second electrode connected to the second impurity region on the other side of the third impurity region . An intrinsic semiconductor layer formed on a substrate;
An optical waveguide that is part of the semiconductor layer;
A first impurity region formed in the semiconductor layer on one side of the optical waveguide and doped with an impurity of a first conductivity type;
A second impurity region formed in the semiconductor layer on the other side of the optical waveguide and introduced with an impurity of a second conductivity type opposite to the first conductivity type;
A capacitor having a lower electrode which is a part of the second impurity region, an insulating film formed on at least the lower electrode, and an upper electrode formed on the insulating film;
A third impurity region formed in the semiconductor layer on the other side of the lower electrode and into which the impurity of the second conductivity type is introduced at an impurity concentration lower than that of the second impurity region ;
A first electrode connected to the first impurity region;
An optical semiconductor device comprising: a second electrode connected to the second impurity region on the other side of the third impurity region . The optical semiconductor device according to claim 1 or 2,
The optical semiconductor device, wherein the upper electrode and the third impurity region of the capacitor are formed in parallel with the optical waveguide. The optical semiconductor device according to any one of claims 1 to 3,
The optical semiconductor device, wherein the semiconductor layer is a silicon layer or a germanium layer. Etching an intrinsic semiconductor layer formed on the substrate to form an optical waveguide in a part of the semiconductor layer;
Forming a first impurity region by introducing a first conductivity type impurity into the semiconductor layer on one side of the optical waveguide; and
A second impurity region is formed by introducing an impurity of a second conductivity type opposite to the first conductivity type into a region excluding a predetermined region in the semiconductor layer on the other side of the optical waveguide. Process,
Forming a third impurity region by introducing an impurity of the first conductivity type into the semiconductor layer in the predetermined region;
By forming an upper electrode on the second impurity region and the third impurity region via an insulating film, a lower electrode that is part of the second impurity region, the insulating film, and the upper electrode Forming a capacitor having an electrode ;
Forming a first electrode connected to the first impurity region;
Forming a second electrode connected to the second impurity region on the other side of the third impurity region. 8. A method of manufacturing an optical semiconductor device, comprising: Etching an intrinsic semiconductor layer formed on the substrate to form an optical waveguide in a part of the semiconductor layer;
Forming a first impurity region by introducing a first conductivity type impurity into the semiconductor layer on one side of the optical waveguide; and
A second impurity region is formed by introducing an impurity of a second conductivity type opposite to the first conductivity type into a region excluding a predetermined region in the semiconductor layer on the other side of the optical waveguide. Process,
Forming a third impurity region having an impurity concentration lower than that of the second impurity region by introducing a second conductivity type impurity into the semiconductor layer in the predetermined region;
An upper electrode is formed on the second impurity region on the one side of the third impurity region via an insulating film, whereby a lower electrode that is a part of the second impurity region, and the insulation Forming a capacitor having a film and the upper electrode ;
Forming a first electrode connected to the first impurity region;
Forming a second electrode connected to the second impurity region on the other side of the third impurity region. 8. A method of manufacturing an optical semiconductor device, comprising: In the manufacturing method of the optical semiconductor device according to claim 5 or 6,
In the step of forming the third impurity region, the third impurity region is formed in parallel with the optical waveguide,
In the step of forming the capacitor, the upper electrode of the capacitor is formed so as to be parallel to the optical waveguide. In the manufacturing method of the optical semiconductor device according to any one of claims 5 to 7,
The method for manufacturing an optical semiconductor device, wherein the semiconductor layer is a silicon layer or a germanium layer.

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