JP5567405B2 - Comb-shaped MOS semiconductor device for electrostatic protection - Google Patents

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a MOS type semiconductor device for electrostatic protection.

  An ESD (Electrostatic Discharge) element is indispensable for reliability although it is not related to the function of the IC. This is an electrostatic discharge element that discharges static electricity so that the IC is not destroyed by static electricity.

  Therefore, it is an essential condition that the ESD element itself is not thermally destroyed by static electricity, and that the internal circuit can be protected by quickly extracting charges before static electricity enters the internal circuit. In recent years, an ESD element provided in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit is often a MOS type using a parasitic bipolar operation, which is an element using a snapback phenomenon. In order to satisfy the protection performance against static electricity required for the ESD element, the channel width of the MOS type ESD element is often about several hundred μm.

  However, when installing an ESD element in a normal CMOS integrated circuit, a small MOS type ESD having a unit width of about 10 to 50 μm is required in order to efficiently install an element constituting the integrated circuit such as a pad or an internal circuit element. A method of efficiently installing an element (unit ESD element) by using a comb-shaped ESD element in which a plurality of comb-shaped elements are connected in parallel is used.

  FIG. 10 is a plan view of an embodiment of a conventional comb-type ESD element, and FIG. 11 is a cross-sectional view taken along a broken line CC ′ shown in FIG. As shown in FIGS. 10 and 11, the comb-type ESD element 20 is composed of a plurality of unit ESD elements 30, and is unidirectionally arranged on a P-type well region 2 formed on the surface of the semiconductor substrate 1 with a gate insulating film 12 interposed therebetween. A plurality of gate electrodes 3 extending in parallel to each other are provided in parallel with each other, and a region immediately below the gate electrode 3 on the surface of the P-type well region 2 is a channel region 9. A region between the channel regions 9 is an N + source region 5 or an N + drain region 4, and the N + source region 5 and the N + drain region 4 are alternately arranged. Further, a P + well tap region 6 is provided on the outer periphery of the comb-shaped ESD element 20 so as to surround the unit ESD element 30.

  In this comb-type ESD element, the unit ESD element does not simultaneously enter the parasitic bipolar operation, the current concentrates on the unit ESD element that operates first, and the unit that operates first before other adjacent unit ESD elements operate There is a problem that the ESD element is destroyed. This can be explained by the difference in substrate resistance.

  The distance from the ground potential installed around the comb ESD element to the channel region of each unit ESD element, that is, the base of the parasitic bipolar element is different. That is, since the base resistance varies depending on each comb, the rate of increase in substrate resistance after avalanche breakdown differs. When a parasitic bipolar having a high base resistance first reaches a base potential necessary for operation and reaches a bipolar operation, current concentrates on the unit ESD element. Therefore, the drain current flowing through the adjacent unit ESD elements is reduced, and the substrate current generated by impact ionization is reduced. As a result, the increase in the base potential of the parasitic bipolar of the adjacent unit ESD element becomes dull and it becomes difficult to operate. Before the adjacent unit ESD element operates, the unit ESD element that operates first will be destroyed. In order to increase the ESD tolerance of the comb-type ESD element, it is important to operate the unit ESD element continuously before the specific unit ESD element breaks down.

  Patent Document 1 is an invention for continuously operating unit ESD elements constituting a comb-type ESD element. A circuit diagram of the invention of Patent Document 1 is shown in FIG. The gate electrode of the unit ESD element is connected to the source of the adjacent unit ESD element. When the ESD surge enters the comb-type ESD element, the source potential of the unit ESD element that has first performed the bipolar operation rises, and the gate potential of the adjacent unit ESD element that is connected to the source increases, thereby increasing the terminal ESD element. Bipolar operation is performed by amplifying the substrate current and raising the base potential. By repeating this, the present invention continuously expands the bipolar operation.

JP 2005-64462 A

  However, since the invention disclosed in Patent Document 1 is not an invention for reducing the difference in substrate resistance of each unit ESD element itself, there is a large difference in easiness of increasing the base potential. It may not work. In order to improve the ESD resistance by continuously performing bipolar operation on the unit ESD elements constituting the comb-type ESD element, it is possible to reduce the difference in the rate of increase in the substrate potential of each unit ESD element, that is, adjacent unit ESD elements. It is important to reduce the substrate resistance between the channel regions.

  Therefore, in order to solve the above problems, the following means were used.

  First, a semiconductor substrate, a first conductivity type well region having an impurity concentration higher than that of the semiconductor substrate provided on the surface of the semiconductor substrate, and a second conductivity type source region having an impurity concentration higher than that of the first conductivity type well region And a second conductivity type drain region are alternately arranged, a channel region located between the second conductivity type source region and the second conductivity type drain region, and a gate insulating film on the channel region. A static electricity protection MOS type semiconductor device having a gate electrode, wherein a first conductivity type impurity region is provided between adjacent channel regions in parallel.

  The first conductivity type impurity region is provided in a part of the second conductivity type drain region between the channel regions adjacent in parallel, and the channel regions sandwiching the second conductivity type drain region are connected to the first conductivity type. A MOS type semiconductor device for electrostatic protection, characterized by being connected in an impurity region.

  The first conductivity type impurity region is provided in a part of a second conductivity type source region between adjacent channel regions in parallel, and channel regions sandwiching the second conductivity type source region are connected to the first conductivity type. A MOS type semiconductor device for electrostatic protection, characterized by being connected in an impurity region.

  In addition, the MOS type semiconductor device for electrostatic protection is characterized in that a gate electrode connection region is formed on the first conductivity type impurity region.

  Further, the MOS type semiconductor device for electrostatic protection is characterized in that the impurity concentration of the first conductivity type impurity region is equal to the impurity concentration of the channel region.

  An electrostatic protection MOS semiconductor device, wherein the impurity concentration of the first conductivity type impurity region is higher than the impurity concentration of the channel region.

  Further, the impurity concentration of the first conductivity type impurity region is provided at a position deeper than the second conductivity type drain region and is higher than the impurity concentration of the first conductivity type well region. It was set as the MOS type semiconductor device for electrostatic protection.

  Further, the impurity concentration of the first conductivity type impurity region is provided at a position deeper than the second conductivity type source region, and is higher than the impurity concentration of the first conductivity type well region. It was set as the MOS type semiconductor device for electrostatic protection.

  The impurity concentration of the first conductivity type impurity region is provided in the entire ESD element region at a position deeper than the second conductivity type drain region and the second conductivity type source region, and the first conductivity type well. The MOS type semiconductor device for electrostatic protection is characterized in that the impurity concentration is higher than the impurity concentration of the region.

  By using the above-mentioned means, the difference in the substrate resistance between the channel regions of the adjacent unit ESD elements is reduced, so that the difference in the rate of increase of the base potential is reduced. It will operate | move and ESD tolerance will improve.

It is a top view which shows Example 1 of this invention. It is sectional drawing which shows Example 1 of this invention. It is a top view which shows Example 2 of this invention. It is a top view which shows Example 3 of this invention. It is sectional drawing which shows Example 3 of this invention. It is a top view which shows Example 4 of this invention. It is sectional drawing which shows Example 5 of this invention. It is sectional drawing which shows Example 6 of this invention. It is sectional drawing which shows Example 7 of this invention. It is a top view which shows the Example of the conventional comb-shaped ESD element. It is sectional drawing which shows the Example of the conventional comb-shaped ESD element. It is a circuit diagram which shows invention of patent document 1. FIG.

  Each example will be described below with reference to the drawings.

  FIG. 1 is a plan view of Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view taken along a broken line AA ′ in FIG. As shown in FIGS. 1 and 2, the ESD element 21 includes a plurality of gate electrodes 3 extending in one direction on a P-type well region 2 formed on the surface of a semiconductor substrate 1 with a gate insulating film 12 interposed therebetween. The channel region 9 is a region immediately below the gate electrode 3 on the surface of the P-type well region 2. A region between the channel regions 9 is an N + source region 5 or an N + drain region 4, and the N + source region 5 and the N + drain region 4 are alternately arranged. Further, a P + well tap region 6 is provided on the outer periphery of the ESD element 21. Here, the P + well tap region 6, the N + source region 5, and the gate electrode 3 are electrically connected and are at a ground potential. Then, the N + drain region 4 positioned between the adjacent gate electrodes 3 in parallel is divided, and the gate electrode junction region 10 is provided so as to connect the adjacent gate electrodes 3. The gate electrode junction region 10 is made of the same material as the gate electrode 3, and a region 11 having the same impurity concentration as the channel region 9 is provided immediately below the gate electrode junction region 10.

  In this way, by connecting the gate electrodes that are adjacent to and separated from each other with the drain region 4 interposed therebetween, the channel regions that are adjacent to and separated from each other are connected in the region immediately below the gate electrode junction region 10. Since the substrate current from the unit ESD element that has reached the bipolar operation flows to the base of the other unit ESD element with low resistance, the other base potential can be easily raised.

  As a result, the adjacent unit ESD element can be brought into the bipolar operation before the current is concentrated on the unit ESD element that has first reached the bipolar operation and the breakdown occurs. As a result, the ESD tolerance can be improved as compared with the conventional comb-type ESD element.

  FIG. 3 is a plan view of Embodiment 2 of the present invention. In the first embodiment, the gate electrode connection region is provided so as to divide the N + drain region 4, but here, instead of the N + drain region 4, the N + source region 5 is divided and the gate electrode 3 adjacent in parallel is divided. A gate electrode junction region 10 is provided so as to connect the two. The gate electrode junction region 10 is made of the same material as the gate electrode 3, and a region having the same impurity concentration as that of the channel region 9 is provided immediately below the gate electrode junction region 10.

  In this way, by connecting the gate electrodes that are adjacent to and separated from each other with the source region 5 interposed therebetween, the channel regions that are adjacent to each other and separated are connected in the region immediately below the gate electrode junction region 10. Since the substrate current from the unit ESD element that has reached the bipolar operation flows to the base of the other unit ESD element with low resistance, the other base potential can be easily raised.

  As a result, the adjacent unit ESD element can be brought into the bipolar operation before the current is concentrated on the unit ESD element that has first reached the bipolar operation and the breakdown occurs. As a result, like the first embodiment, the ESD tolerance can be improved as compared with the comb-type ESD element of the prior art.

  FIG. 4 is a plan view of the third embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the broken line BB ′ of FIG. As shown in FIGS. 1 and 2, the ESD element 21 includes a plurality of gate electrodes 3 extending in one direction on a P-type well region 2 formed on the surface of the semiconductor substrate 1 with a gate insulating film 12 interposed therebetween. A channel region 9 is provided in parallel, and a region immediately below the gate electrode 3 on the surface of the P-type well region 2 is a channel region 9. A region between the channel regions 9 is an N + source region 5 or an N + drain region 4, and the N + source region 5 and the N + drain region 4 are alternately arranged. Further, a P + well tap region 6 is provided on the outer periphery of the ESD element 21.

  Here, the P + well tap region 6, the N + source region 5, and the gate electrode 3 are electrically connected and are at a ground potential. Then, a shorting P + region 8 is formed so as to connect the adjacent channel regions 9 to a part of the N + drain region 4 located between the adjacent channel regions 9 in parallel.

  As a result, the substrate current from the unit ESD element that has first reached the bipolar operation flows to the base of the other unit ESD element with a low resistance via the P + region 8 for short circuit, so that the other base potential easily rises. It becomes possible to make it. The adjacent unit ESD element can be brought into the bipolar operation before the current concentrates on the unit ESD element that has first reached the bipolar operation and causes the breakdown. As a result, the ESD tolerance can be improved as compared with the conventional comb-type ESD element.

  FIG. 6 is a plan view of Embodiment 4 of the present invention. This is a modification of the above-described third embodiment, and instead of the N + drain region 4, a short-circuiting P + region 8 is formed so as to connect adjacent channel regions 9 to a part of the N + source region 5. is there.

  As a result, the substrate current from the unit ESD element that first reaches the bipolar operation flows to the base of the other unit ESD element with a low resistance, so that the other base potential can be easily raised. The adjacent unit ESD element can be brought into the bipolar operation before the current concentrates on the unit ESD element that has first reached the bipolar operation and causes the breakdown. As a result, like the third embodiment, the ESD tolerance can be improved as compared with the comb-type ESD element of the prior art.

  FIG. 7 is a cross-sectional view of Embodiment 5 of the present invention. 10 and 11 is different from the conventional example shown in FIGS. 10 and 11 in that the impurity concentration is higher than that of the P-type well region 2 and higher than that of the P + well tap region 6 at a position deeper than the substrate surface below the N + drain region 4. A low P ± region 7 is provided. The P ± region 7 is arranged so as to be contained in the P-type well region 2.

  As a result, the channel regions adjacent to and separated from each other are connected via the low resistance P ± region, and the substrate current from the unit ESD element that has first reached the bipolar operation is applied to the base of the other unit ESD element with a low resistance. It is possible to easily increase the other base potential. The adjacent unit ESD element can be brought into the bipolar operation before the current concentrates on the unit ESD element that has first reached the bipolar operation and causes the breakdown. As a result, the ESD tolerance can be improved as compared with the conventional comb-type ESD element.

  FIG. 8 is a cross-sectional view of Embodiment 6 of the present invention. 10 and 11 is different from the conventional example shown in FIGS. 10 and 11 in that the impurity concentration is higher than that of the P-type well region 2 and higher than that of the P + well tap region 6 at a position deeper than the substrate surface below the N + source region 5. A low P ± region 7 is provided.

  As a result, the channel regions adjacent to and separated from each other are connected via the low resistance P ± region, and the substrate current from the unit ESD element that has first reached the bipolar operation is applied to the base of the other unit ESD element with a low resistance. It is possible to easily increase the other base potential. The adjacent unit ESD element can be brought into the bipolar operation before the current concentrates on the unit ESD element that has first reached the bipolar operation and causes the breakdown. As a result, the ESD tolerance can be improved as compared with the conventional comb-type ESD element.

  FIG. 9 is a cross-sectional view of Embodiment 7 of the present invention. 10 and 11 is different from the conventional example shown in FIGS. 10 and 11 in that the impurity concentration is higher than that of the P-type well region 2 and deeper than the N + drain region 4 and the N + source region 5 in the P + well tap region 6. Further, a P ± region 7 having a lower impurity concentration is provided in the entire ESD element region.

  As a result, the channel regions adjacent to and separated from each other are connected via the low resistance P ± region, and the substrate current from the unit ESD element that has first reached the bipolar operation is applied to the base of the other unit ESD element with a low resistance. It is possible to easily increase the other base potential. The adjacent unit ESD element can be brought into the bipolar operation before the current concentrates on the unit ESD element that has first reached the bipolar operation and causes the breakdown. As a result, the ESD tolerance can be improved as compared with the conventional comb-type ESD element.

  In addition, this invention is not limited to said embodiment, This invention can be deform | transformed and implemented in the range which does not deviate from the summary.

1 Semiconductor substrate 2 P-type well region 3 Gate electrode 4 N + drain region 5 N + source region 6 P + well tap region 7 P ± region 8 P + region for short circuit 9 Channel region 10 Gate electrode junction region 11 Impurity concentration same as channel region Region 12 Gate Insulating Film 20 Comb ESD Element 21 ESD Element 30 Unit ESD Element

Claims (6)

A semiconductor substrate;
A first conductivity type well region having a higher impurity concentration than the semiconductor substrate provided from the surface to the inside of the semiconductor substrate;
A second conductivity type source region and a second conductivity type drain region having an impurity concentration higher than that of the first conductivity type well region, alternately disposed in the first conductivity type well region;
A plurality of channel regions positioned between the alternately disposed second conductivity type source regions and the second conductivity type drain regions;
A first conductivity type impurity region that is disposed between and in contact with part of the surface of the semiconductor substrate between adjacent channel regions of the plurality of channel regions, and electrically connects the adjacent channel regions;
Comb-shaped MOS type semiconductor device for electrostatic protection. The comb-shaped electrostatic region according to claim 1, wherein the first conductivity type impurity region is provided in a part of the second conductivity type drain region existing between the adjacent channel regions in the second conductivity type drain region. MOS type semiconductor device for protection. The comb-shaped electrostatic region according to claim 1, wherein the first conductivity type impurity region is provided in a part of the second conductivity type source region existing between the adjacent channel regions in the second conductivity type source region. MOS type semiconductor device for protection. 4. The comb-shaped MOS semiconductor device for electrostatic protection according to claim 1, wherein a gate electrode connection region is formed on the first conductivity type impurity region. 5. 5. The comb-shaped electrostatic protection MOS semiconductor device according to claim 1, wherein an impurity concentration of the first conductivity type impurity region is equal to an impurity concentration of the channel region. 6. . 5. The comb- type MOS semiconductor device for electrostatic protection according to claim 1, wherein an impurity concentration of the first conductivity type impurity region is higher than an impurity concentration of the channel region. 6.

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