JP5562502B1 - Control and monitoring signal transmission system - Google Patents

Abstract

An object of the present invention is to use a predetermined controlled device, an input unit, or an input unit without using a high-speed transmission clock while transmitting data by a transmission synchronization method using a wire as a common data signal line and using one type of start signal It is possible to speed up the transmission response of the output unit and to use a slave station having the same specification for high-speed data transmission and low-speed data transmission.
A data signal area is defined as a predetermined period in the second half or the first half in which a predetermined power supply voltage level is not reached for each cycle of the transmission clock, and the first area and the second Time-divided into areas. The slave station including the first cycle counter superimposes the first monitoring signal on the first area. A slave station including a second cycle counter whose maximum count value is a number smaller than the count value of the first cycle counter superimposes a second monitoring signal on the second area.
[Selection] Figure 1

Description

  The present invention reduces the number of signal lines between a master station connected to a control unit and a plurality of output units and input units, or a plurality of slave stations corresponding to a plurality of controlled devices, and connects them with a common data signal line. The present invention also relates to a control / monitor signal transmission system that transmits data by a transmission synchronization method such as synchronization by a transmission clock.

  In a control system including a control unit, a plurality of output units and input units, or a plurality of controlled devices, so-called wiring saving, which reduces the number of wirings, is widely implemented. As a general technique for reducing the wiring, a parallel signal and a serial signal are used instead of a parallel connection that directly connects a plurality of output units and input units or signal lines extending from a controlled device to the control unit. The master station and the plurality of slave stations having the conversion function are connected to the control unit, the plurality of output units and the input unit, or the plurality of controlled devices, respectively, and common data between the master station and the plurality of slave stations. A method of exchanging data with a serial signal via a signal line is widely adopted.

  As the common data signal line in the above wiring saving, a general two-wire electric wire used for connection to a power source is convenient and suitable. However, when a general-purpose electric wire (hereinafter referred to as an electric wire) is used as a common data signal line, it is difficult to reliably perform transmission unless the transmission clock is set to a low speed of 100 kHz or less. There was a problem that became slow.

  Accordingly, proposals have been made to increase the speed of signal transmission in a control / monitor signal transmission system based on the premise that an electric wire is used as a common data signal line. For example, in the control / monitor signal transmission system (first prior art) disclosed in Japanese Patent Application Laid-Open No. 2002-152864, a transient current generated at the rise of the power supply voltage level in the latter half of every clock cycle is used as a monitor signal. By detecting, it is possible to superimpose a monitoring signal from the input unit to the control unit in addition to the control signal from the control unit to the controlled device on the clock signal including the power supply, and the signal transmission speed can be increased to 2 It is possible to increase the speed more than twice.

  In addition, in the control / monitor signal transmission system (second prior art) disclosed in Japanese Patent Application Laid-Open No. 2002-271878, a control signal from a control unit to a controlled device is expressed as a binary value of a predetermined duty ratio (the power supply voltage). Level and other levels) signal, and the monitoring signal from the input unit to the control unit is detected at the rise of the power supply voltage level as the presence or absence of a current signal, thereby controlling the clock signal including the power supply In addition to the control signal from the unit to the controlled device, it is possible to superimpose the monitoring signal from the input unit to the control unit. That is, it is not necessary to separately provide a period for transmitting the control signal or the monitoring signal in the transmission signal of the common data signal line, and bidirectional signal transmission between the control unit and the controlled device or the input unit is performed simultaneously. It is possible to increase the speed (rate) of signal transmission to twice that of the prior art.

  Furthermore, in the control / monitor signal transmission system (third prior art) disclosed in Japanese Patent Application Laid-Open No. 2003-152748, the first and second control signals and the first and second monitor signals are added to the clock signal. One of the superposed and duplicated control signal and monitoring signal is transmitted at high speed data (first control and monitoring data signal) to be transmitted in a short cycle, and the other is transmitted at a low speed sufficient for transmission at a long cycle (first control and monitoring data signal). By using the second control and monitoring data signal), low-speed data is not inserted during high-speed data transmission, and the cycle time of high-speed data transmission is prevented from becoming long, and high-speed data is satisfied. It is possible to transmit at a transmission rate.

JP 2002-152864 A JP 2002-271878 A JP 2003-152748 A

  The first conventional technique and the second conventional technique include a control signal transmitted from the control unit side to the controlled device, and a monitoring signal transmitted from the input unit provided on the controlled device side to the control unit. Is basically superimposed on the same period of the transmission clock. That is, the transmission amount per cycle of the transmission clock is doubled as compared with the previous system in which only one of the control signal and the monitoring signal is superimposed on one cycle of the transmission clock.

  However, in the first prior art and the second prior art, the amount of data that can be transmitted in one frame cycle from the start signal of the transmission signal to the next start signal increases, but the transmission response speed is still one frame cycle of the transmission signal. It becomes. That is, in the transmission synchronization method in which the input unit of a predetermined controlled device is assigned to a predetermined position of one frame of a transmission signal, the input unit of the predetermined controlled device can transmit data in one frame cycle. Since the transmission response speed is limited to one frame cycle of the transmission signal, the device that requires a response faster than one frame cycle cannot be applied unless the transmission clock is increased. It was.

  In contrast, in the third prior art, a short start signal and a long start signal are formed, and a high-speed data transmission period (high-speed data refresh time) and a low-speed data transmission period (low-speed data refresh time) are distinguished. It is possible to increase the transmission response speed by adjusting the length of one frame of the high-speed data transmission signal. However, since it is necessary to use two types of start signals, there is a problem that the method cannot be applied to a system in which only one type of start signal is used. Furthermore, since the types of transmission signals (voltage and current, frequency and pulse width, etc.) differ between high-speed data and low-speed data, transmission is performed between the slave station used for high-speed data transmission and the slave station used for low-speed data transmission. The signal specifications were different, and it was necessary to prepare a dedicated slave station for each application, which caused problems such as high cost and low versatility.

  Therefore, the present invention uses a wire as a common data signal line and transmits data by a transmission synchronization method using one type of start signal, and does not increase the transmission clock, and allows a predetermined controlled device or input. It is possible to provide a control / monitoring signal transmission system that can speed up the transmission response of the transmission unit or the output unit and that can use a slave station of the same specification for high-speed data transmission and low-speed data transmission. And

  In the control / monitor signal transmission system according to the present invention, a master station and a plurality of slave stations are connected by a common data signal line, and a transmission signal transmitted to the common data signal line is a timing generation means of the master station. Under the control of the generated timing signal, for each cycle of the transmission clock, the first half or the second half is set to a predetermined power supply voltage level, and a predetermined value is set in the second half or the first half that is not at the power supply voltage level. A predetermined period is a data signal area. The data signal area is time-divided into a first area where a control signal or a first monitoring signal is superimposed and a second area where a second monitoring signal is superimposed. Then, the slave station including a first cycle counter that starts counting from the end of the start signal of the transmission signal as a starting point and the counter value corresponds to the number of the transmission clocks in one frame cycle of the transmission signal, The first monitoring signal is superimposed on the first area. Further, the slave station including a second cycle counter that starts counting from the end of the start signal of the transmission signal as a starting point and that has a maximum count value that is smaller than the count value of the first cycle counter, The second monitoring signal is superimposed on the second area.

  In the present invention, when the count started from the end of the start signal of the transmission signal reaches the maximum value, the second cycle counter does not stop counting until the start of the next start signal. Will be repeated.

  In the control / monitor signal transmission system according to the present invention, a first cycle counter (hereinafter referred to as a low speed cycle counter) whose counter value corresponds to the number of transmission clocks of one frame cycle of the transmission signal, and a first cycle counter A second cycle counter (hereinafter referred to as a high-speed cycle counter) having a maximum count value that is smaller than this count value is used. Then, the second monitoring signal superimposed on the transmission signal by the slave station equipped with the high-speed cycle counter is shorter than one frame cycle of the transmission signal, and is superposed by the slave station equipped with the low-speed cycle counter. Is superposed at a timing (second area) different from the monitoring signal. Therefore, the second monitoring signal can be obtained as a signal that can be distinguished from the first monitoring signal in a shorter cycle than the first monitoring signal. Therefore, the predetermined high-speed input slave station can scan the predetermined input signal at a high speed in a time shorter than one frame cycle of the transmission signal by using the second monitoring signal, and the high-speed input slave station is faster than the input slave station. Transmission response is possible. In other words, it is possible to increase the transmission response of a predetermined controlled device, input unit or output unit without increasing the transmission clock while transmitting data by a transmission synchronization method using one type of start signal. Become. In addition, since the first monitoring signal and the second monitoring signal are superimposed at different timings, they can be distinguished even if the signal types are the same. Therefore, by selecting the timings of the first area and the second area, the slave station having the same transmission signal specification corresponding to the same type of signal can be transmitted to the low-speed data using the first monitoring signal, and the second It is possible to use both for high-speed data transmission using the monitoring signal.

1 is a system configuration diagram showing a schematic configuration of a control / monitor signal transmission system according to the present invention. It is a system configuration | structure figure of a master station. It is a block diagram of a slave station input part. It is a block diagram of a high-speed slave station input unit. It is a block diagram of a slave station output unit. It is a schematic diagram of a transmission signal that shows data extracted from a transmission signal exchanged between a master station and a slave station separately for low speed data and high speed data.

An embodiment of a control / monitor signal transmission system according to the present invention will be described with reference to FIGS.
As shown in FIG. 1, the control / monitor signal transmission system includes a single master station 2 connected to a control unit 1 and common data signal lines DP and DN (hereinafter also referred to as transmission lines), It comprises a plurality of input / output slave stations 4, output slave stations 6, input slave stations 7 and high-speed input slave stations 10 connected to the common data signal lines DP and DN. In FIG. 1, for convenience of illustration, each slave station is shown one by one, but there is no limitation on the type and number of slave stations connected to the common data signal lines DP and DN.

    The input / output slave station 4, the output slave station 6, the input slave station 7, and the high-speed input slave station 10 are provided with signal output processing for the output unit 8 that operates according to the output instruction of the control unit 1 and input information to the control unit 1. One or both of the input signal processing from the input unit 9 that takes in The output unit 8 is, for example, an actuator, a (stepping) motor, a solenoid, a solenoid valve, a relay, a thyristor, or a lamp. The input unit 9 is, for example, a reed switch, a micro switch, a push button switch, or a photoelectric switch. And various sensors. The input / output slave station 4 is connected to a controlled device 5 including an output unit 8 and an input unit 9, the output slave station 6 is connected only to the output unit 8, and the input slave station 7 and the high-speed input slave station 10 are It is connected only to the input unit 9. The output slave station 6 may include an output unit 8 (output unit integrated slave station 80), and the input slave station 7 and the high-speed input slave station 10 include an input unit 9 (input unit). The integrated slave station 90 and the input unit integrated high-speed slave station 110) may be used.

  The control unit 1 is, for example, a programmable controller, a computer, and the like, and is obtained based on the output unit 11 that sends the control parallel data 13 and the monitoring data extracted from the monitoring signals from the input / output slave station 4 and the input slave station 7. And an input unit 12 that receives the monitoring parallel data 15 and a high-speed input unit 14 that receives the high-speed monitoring parallel data 16 obtained based on the monitoring data extracted from the monitoring signal from the high-speed input slave station 10. These output unit 11, input unit 12, and high-speed input unit 14 are connected to the master station 2.

  As illustrated in FIG. 2, the master station 6 includes an output data unit 21, a timing generation unit 23, a master station output unit 24, a master station input unit 25, an input data unit 26, and a high-speed input data unit 28. A control signal (hereinafter referred to as a transmission clock signal) that is connected to the common data signal lines DP and DN and is a series of pulse signals corresponding to the transmission signal of the present invention is connected to the common data signal lines DP and DN. In addition to the transmission, the input / output slave station 4, the output slave station 6, the input slave station 7, or the high-speed input slave station 10 (hereinafter referred to as “slave stations 4, 6, 7, 10” when a plurality of these are collectively shown) The monitoring parallel data 15 and the high-speed monitoring parallel data 16 extracted from the monitoring signal sent from the above are sent to the input unit 12 and the high-speed input unit 14 of the control unit 1.

  The output data unit 21 delivers the control parallel data 13 from the output unit 11 of the control unit 1 to the master station output unit 24 as serial data.

  The timing generation unit 23 includes an oscillation circuit (OSC) 31 and a timing generation unit 32. Based on the OSC 31, the timing generation unit 32 generates a timing clock of this system and supplies it to the master station output unit 24 and the master station input unit 25. hand over.

  The master station output unit 24 includes control data generating means 33 and a line driver 34. Based on the data received from the output data section 21 and the timing clock received from the timing generation section 23, the control data generation means 33 transmits a series of pulse signals to the common data signal lines DP and DN via the line driver 34. Send a clock signal.

  As shown in FIG. 6, the transmission clock signal has a control / monitoring data area following the start signal ST. The control / monitoring data area includes control signal data (hereinafter referred to as transmission control data) transmitted from the master station 2 and monitoring signal data (hereinafter referred to as transmission monitoring data) transmitted from the slave stations 4, 7, and 10. It consists of. As shown in FIG. 6, the pulse of the transmission clock signal (corresponding to the transmission clock of the present invention) has the power supply voltage level (+ 24V in this embodiment) in the second half of one cycle, and becomes the power supply voltage level. The first half of the low potential level pulse is the data signal area. In the data signal area, the pulse width interval represents the data of the control signal, and the presence / absence of a current superimposed thereon represents the data of the monitoring signal. Also, a first area (the second half area b of the data signal area shown in FIG. 6 and hereinafter referred to as the second half area b) on which the first monitoring signal from the input / output slave station 4 or the input slave station 7 is superimposed. The second monitoring signal from the high-speed input slave station 10 is time-divided into a second area (the first half area a of the data signal area shown in FIG. 6 and hereinafter referred to as the first half area a). . In this embodiment, when one cycle of the transmission clock signal is t0, the pulse width interval of the data signal area is expanded from (1/2) t0 to (3/4) t0. As long as it corresponds to the value of each data of the input control parallel data 13, the width is not limited and may be determined appropriately. Furthermore, the first half of one cycle of the transmission clock signal may be the power supply voltage level, and the second half may be the low potential level.

  The start signal ST has the same potential level as the high potential level of the transmission clock signal and is a signal longer than one cycle of the transmission clock signal.

  The master station input unit 25 includes a monitoring signal detection unit 35 and a first monitoring data extraction unit 36. The monitoring signal detection means 35 detects the monitoring signal transmitted from the input / output slave station 4, the input slave station 7 and the high-speed input slave station 10 via the common data signal lines DP and DN. As described above, the data value of the monitoring signal is represented by the presence or absence of the current superimposed on the low potential level. After the start signal ST is transmitted, the input / output slave station 4, the input slave station 7, and the high-speed input A monitoring signal is received from each of the slave stations 10. Then, the monitoring signal detected by the monitoring signal detection unit 35 is delivered to the first monitoring data extraction unit 36. The first monitoring data extraction unit 36 extracts monitoring signal data superimposed on the second half area b in synchronization with the timing of the second half area b from the timing generation unit 32. Then, the data of the first monitoring signal is sent to the input data unit 26 as serial input data.

  The master station input unit 25 also includes second monitoring data extraction means 37. The second monitoring data extraction unit 37 extracts monitoring signal data superimposed on the first half area a in synchronization with the timing of the first half area a from the timing generation unit 32. Then, the data of the second monitoring signal is sent to the high-speed input data unit 28 as serial input data.

  The input data unit 26 converts the serial input data received from the master station input unit 25 into parallel (parallel) data, and sends the parallel data to the input unit 12 of the control unit 1. The high-speed input data unit 28 converts the serial input data received from the second monitoring data extraction unit 37 into parallel (parallel) data, and sends it to the high-speed input unit 14 of the control unit 1 as the high-speed monitoring parallel data 16. .

  As shown in FIG. 3, the input slave station 7 includes a transmission reception means 41, an address extraction means 43, a first monitoring data transmission means 45, a low speed address data storage means 51, a low speed cycle counter maximum value storage means 52, an input A slave station input unit 70 having means 71 is provided. The input slave station 7 of this embodiment includes an MCU that is a microcomputer control unit as an internal circuit, and this MCU functions as the slave station input unit 70. Calculations and storages necessary for the processing are executed using the CPU, RAM, and ROM included in the MCU, and the CPU, RAM, and ROM in the processing of each of the above-described means constituting the slave station input unit 70 The relationship is omitted for convenience of explanation.

  The transmission receiving means 41 receives the transmission clock signal transmitted to the common data signal lines DP and DN, and delivers it to the address extracting means 43.

    The address extraction means 43 counts pulses starting from the end of the start signal ST indicating the start of the transmission clock signal, and the count value of the own station based on the head address data set in the low-speed address data storage means 51. The first monitoring data transmission means 45 is validated at the timing of the second half area b that coincides with the address data.

  The first monitoring data transmission means 45 is enabled by the above-mentioned coincidence timing delivered from the address extraction means 43, and the base current of the transistor TR is set to “on” or “off” based on the data delivered from the input means 71. ". When the base current is “on”, the transistor TR is turned “on”, and a current signal as a monitoring signal is output to the common data signal lines DP and DN.

  The low speed cycle counter maximum value storage means 52 functions as a low speed cycle counter together with the address extraction means 43, and sets the maximum value of the pulse count in the address extraction means 43. In this embodiment, since the number of pulses (transmission clock) in one frame cycle of the transmission signal is 256 as shown in FIG. 6, 255 is stored as the maximum value because 0 is the start address.

  The input unit 71 delivers the monitoring data to the first monitoring data transmission unit 45 based on the input data from the input unit 9.

  Similarly to the input slave station 7, the high-speed input slave station 10 includes an MCU that is a microcomputer control unit as an internal circuit, and this MCU functions as the high-speed slave station input unit 100. Similar to the MCU of the slave station input unit 70, calculations and storages necessary for processing of the high-speed input slave station 10 are executed using the CPU, RAM, and ROM included in this MCU. .

  As shown in FIG. 4, the functional configuration of the high-speed slave station input unit 100 includes the first monitoring data transmission unit 45, the low-speed address data storage unit 51, and the low-speed cycle counter maximum value of the slave station input unit 70 shown in FIG. The storage means 52 is replaced with the second monitoring data transmission means 46, the high-speed address data storage means 53, and the high-speed cycle counter maximum value storage means 54, respectively, and the rest is the same as the input slave station section 70. Therefore, in FIG. 4, parts that are substantially the same as those of the slave station input unit 70 are denoted by the same reference numerals, and description thereof is simplified or omitted.

  The high-speed address data storage means 53 has the same function as the low-speed address data storage means 51, but the set address data is different. The low-speed address data is data that is arbitrarily set within a range below the maximum value of the number of pulses of one frame cycle of the transmission signal, but the high-speed address data is the maximum value of the low-speed address data ( A number smaller than the number of one frame cycle of the transmission signal is set as a maximum value and is set in a smaller range. In this embodiment, the low-speed address data is set in the range of 255 or less, and the high-speed address data is set in the range of 3 or less (because 0 is the start address).

  The high speed cycle counter maximum value storage means 54 sets the maximum value of the pulse count in the address extraction means 43 in the same manner as the low speed cycle counter maximum value storage means 52. Then, it functions as a high-speed cycle counter together with the address extracting means 43. However, the maximum count value set by the low-speed cycle counter maximum value storage means 52 is the number of pulses of one frame cycle of the transmission signal, whereas it is set by the high-speed cycle counter maximum value storage means 54. The maximum count value is smaller than the count value stored in the low speed cycle counter maximum value storage means 52. The smaller the maximum count value set in the high-speed cycle counter maximum value storage means 54, the faster the transmission response. In this embodiment, since 0 is the start address, 3 is stored as the maximum value.

  The second monitoring data transmission means 46 is enabled by the timing of the first half area a that matches the address data of the own station set by the high-speed address data setting means 53 delivered from the address extraction means 43 and delivered from the input means 71. Based on the data, the base current of the transistor TR is set to “on” or “off”. When the base current is “on”, the transistor TR is turned “on”, and a current signal as a monitoring signal is output to the common data signal lines DP and DN.

  Similarly to the input slave station 7, the output slave station 6 and the input / output slave station 4 include MCUs as microcomputer control units as internal circuits, and these MCUs are slave station output units 60 or slave station input / output units. It functions as 40. Similar to the MCU of the slave station input unit 70, calculations and storages necessary for processing of the output slave station 6 or the input / output slave station 4 are executed using the CPU, RAM, and ROM included in this MCU. It has become a thing.

  As shown in FIG. 5, the functional configuration of the slave station output unit 60 is such that the first monitoring data transmission unit 45 of the slave station input unit 70 shown in FIG. 3 is the first control data extraction unit 44, and the input unit 71 is the output unit. The others are the same as those of the input slave unit 70. Therefore, in FIG. 5, parts that are substantially the same as those of the slave station input unit 70 are denoted by the same reference numerals, and description thereof is simplified or omitted.

    The first control data extraction means 43 obtains the data value from the transmission clock signal delivered when the address extraction means 43 matches the address data of its own station based on the head address data set in the low-speed address data storage means 51. The extracted slave station control data is delivered to the output means 61. Note that the address extraction means 43 of the slave station output unit 60 is also set within a range of 256 or less (first address counter setting means 52) and 256 or less, similarly to the address extraction means 43 of the slave station input unit 70. Data is extracted based on the address data (first address data).

  The output unit 61 outputs output information based on the slave station control data delivered from the first control data extraction unit 43 to the output unit 8 to operate or stop the output unit.

  The functional configuration of the slave station input / output unit 40 is a configuration having both functions of the slave station output unit 60 and the slave station input unit 70 combined, and each component is a slave station output unit 60 and a slave station input unit. The description is omitted because it is the same as 70.

  In this control / monitor signal transmission system, the first monitor signal transmitted from the input slave station 7 in which the low-speed address is set is superimposed on the second half area b, and based on this first monitor signal, FIG. As shown in the upper part of FIG. As described, the low-speed address data for setting the low-speed address in the input slave station 7 is data that is arbitrarily set within the range below the maximum number of pulses of one frame cycle of the transmission signal. . Therefore, the first monitoring signal is output only once per frame cycle from each input slave station 7, and the transmission response speed Tc of the low-speed data is equal to one frame cycle of the transmission clock signal.

  On the other hand, the second monitoring signal transmitted from the high-speed input slave station 10 to which the high-speed address is set is superimposed on the first half area a, and based on this second monitoring signal, as shown in the lower part of FIG. The master station 2 extracts the data as high-speed data. As described above, the high-speed address data for setting the high-speed address in the high-speed input slave station 10 is set to a value smaller than the maximum value of the low-speed address data (the number of one frame cycle of the transmission signal). Data set in a small range. In this embodiment, the starting address is 0 and the maximum value is 3. Accordingly, the second monitoring signal is output from each high-speed input slave station 10 every four transmission clocks, and the transmission response cycle Thc for high-speed data is 1/64 (4 ÷ 4) of the transmission response cycle Tc for low-speed data. 256). That is, the transmission response speed is 64 times. The number of inputs of the high-speed input slave station 10 is at most four in this embodiment.

1 Control Unit 2 Master Station 4 I / O Slave Station 5 Controlled Device 6 Output Slave Station 7 Input Slave Station 8 Output Unit 9 Input Unit 11 Output Unit 12 Input Unit 13 High-Speed Input Unit 14 Control Parallel Data 15 Monitoring Parallel Data 16 High-Speed Monitoring parallel data 21 Output data section 23 Timing generation section 24 Master station output section 25 Master station input section 26 Input data section 28 High-speed input data section 31 OSC (oscillation circuit)
32 timing generating means 33 control data generating means 34 line driver 35 monitoring signal detecting means 36 first monitoring data extracting means 37 second monitoring data extracting means 40 slave station input / output unit 41 transmission receiving means 43 address extracting means 44 control data extracting means 45 First monitoring data transmission means 46 Second monitoring data transmission means 51 Low speed address data storage means 52 Low speed cycle counter maximum value storage means 53 High speed address data storage means 54 High speed cycle counter maximum value means 61 Output means 71 Input Means 80 Output unit integrated slave station 90 Input unit integrated slave station 100 High speed slave station input unit 110 Input unit integrated high speed slave station TR Transistor

Claims (1)

The master station and multiple slave stations are connected by a common data signal line.
The transmission signal transmitted to the common data signal line has a predetermined power supply voltage in the first half or the second half for each cycle of the transmission clock under the control of the timing signal generated by the timing generating means of the master station. The data signal area is a predetermined period in the second half or the first half that is not at the level of the power supply voltage.
The data signal area is time-divided into a first area where a first monitoring signal is superimposed and a second area where a second monitoring signal is superimposed,
The slave station including a first cycle counter that starts counting from the end of the start signal of the transmission signal and has a counter value corresponding to the number of transmission clocks in one frame cycle of the transmission signal is the first station The first monitoring signal is superimposed on the area of
The slave station comprising a second cycle counter that starts counting from the end of the start signal of the transmission signal and that has a maximum count value that is smaller than the count value of the first cycle counter is the second station A control / monitoring signal transmission system, wherein the second monitoring signal is superimposed on an area.

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