JP5550681B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that supplies a charging current to an element to be charged.

  Semiconductor devices that drive power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) have been developed. In such a semiconductor device, for example, a floating circuit is used as a circuit for driving a power semiconductor element having a large potential fluctuation. As a method of supplying a voltage to the floating circuit, for example, a bootstrap method using a capacitor connected to a power supply voltage via a diode as a power supply is adopted (for example, Patent Documents 1 to 3 and Non-Patent Document 1). reference).

JP-A-6-188372 JP 2006-5182 A JP 2004-47937 A

Proceedings of The 13th International Symposium on Power Semiconductor Devices & ICs

  However, in the configurations described in Patent Documents 1 to 3, the n-type diffusion region, which is the path of the charging current from the power source to the capacitor, becomes narrow due to the spread of the depletion layer, so that the charging current becomes small.

  Further, in Non-Patent Document 1, in the p-type diffusion region and the n-type diffusion region constituting the diode, holes injected from the p-type diffusion region to the n-type diffusion region flow to the p− type substrate instead of the capacitor. There is no suggestion to prevent power loss.

  Therefore, an object of the present invention is to provide a semiconductor device capable of efficiently supplying a charging current to an element to be charged.

  In order to solve the above-described problem, a semiconductor device according to an aspect of the present invention is a semiconductor device that supplies a charging current to an element to be charged, and includes a first conductive type semiconductor layer and a first electrode of the element to be charged. And a second node coupled to a power supply potential node to which a power supply voltage is supplied, and a second conductivity type first semiconductor region formed on the main surface of the semiconductor layer A second semiconductor region of the first conductivity type having a third node coupled to the power supply potential node and spaced from the semiconductor layer on the surface of the first semiconductor region, and from the third node A charge carrier movement restriction unit for restricting movement of charge carriers to the semiconductor layer.

  A semiconductor device according to still another aspect of the present invention is a semiconductor device for supplying a charging current to an element to be charged, the first conductivity type semiconductor layer being coupled to the first electrode of the element to be charged. A first semiconductor region of the second conductivity type formed on the main surface of the semiconductor layer, and a third node and a fourth node coupled to a power supply potential node to which a power supply voltage is supplied. The second semiconductor region of the first conductivity type formed at a distance from the semiconductor layer on the surface of the first semiconductor region and the movement of charge carriers from the third node and the fourth node to the semiconductor layer are limited. A charge carrier movement limiting unit.

  A semiconductor device according to still another aspect of the present invention is a semiconductor device that supplies a charging current to an element to be charged, a first terminal coupled to a power supply potential node to which a power supply voltage is supplied, A first transistor having one conduction electrode coupled to the second end of the resistor, a second conduction electrode coupled to a ground potential node to which a ground voltage is supplied, and a control electrode coupled to the first electrode of the charging target element; And a second transistor having a first conduction electrode coupled to the power supply potential node, a second conduction electrode coupled to the first electrode of the charge target element, and a control electrode coupled to the second end of the resistor.

  According to the present invention, it is possible to efficiently supply a charging current to an element to be charged.

1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 7th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 8th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 8th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 9th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 10th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 10th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 11th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 12th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device based on the 13th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device based on the 14th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device based on the 14th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device which concerns on the 15th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device based on 15th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device based on the 16th Embodiment of this invention. It is a circuit diagram which shows the structure of the semiconductor device based on the 17th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device based on the 18th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device based on the 19th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device based on 20th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
[Configuration and basic operation]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 1, a semiconductor device 101 includes a PNP transistor TR1, a junction field-effect transistor (JFET) TR2, a diode D1, and a resistor (charge carrier movement limiting unit) R. .

  The drive device 201 includes a high voltage side drive circuit 51 and a low voltage side drive circuit 52. High-voltage side drive circuit 51 includes a P-channel MOS transistor TR51, an N-channel MOS transistor TR52, a capacitor (charge target element) C, a power supply voltage terminal T1, and a reference voltage terminal T2. Low voltage side drive circuit 52 includes a P channel MOS transistor TR53 and an N channel MOS transistor TR54.

  Power conversion device 202 includes a high-voltage power semiconductor element TR101 and a low-voltage power semiconductor element TR102.

  The driving device 201 may include a bipolar transistor instead of the MOS transistor. Further, the semiconductor device 101 may be configured to further include a capacitor C, may be configured to further include the high-voltage side driving circuit 51, or may be configured to further include the driving device 201, Moreover, the structure further provided with the drive device 201 and the power converter device 202 may be sufficient.

  Power supply voltage Vcc is supplied to power supply potential nodes NL1 and NL2. For example, a high voltage HV of several hundred volts is supplied to the high voltage node HV. Ground voltage Vsub is supplied to ground potential nodes NG1 to NG3.

  A first end of resistor R is connected to power supply potential node NL1. The anode of diode D1 is connected to power supply potential node NL1. PNP transistor TR1 has an emitter (conducting electrode) connected to the second end of resistor R, a collector (conducting electrode) connected to ground potential node NG1, and a base (control electrode) connected to the first electrode of capacitor C. The The junction field effect transistor TR2 has a drain (conductive electrode) connected to the cathode of the diode D1, a source (conductive electrode) connected to the first electrode of the capacitor C, and a gate (control electrode) connected to the second end of the resistor R. Connected to.

  The capacitor C has a first electrode connected to the power supply voltage terminal T1 of the high-voltage side drive circuit 51 and a second electrode connected to the reference voltage terminal T2 of the high-voltage side drive circuit 51. More specifically, the source of P channel MOS transistor TR51 is connected to the first electrode of capacitor C, and the drain is connected to the drain of N channel MOS transistor TR52 and the gate of high voltage side power semiconductor element TR101. The source of N channel MOS transistor TR52 is connected to the second electrode of capacitor C.

  The reference voltage terminal T2 of the high voltage side drive circuit 51 is connected to a connection point between the high voltage side power semiconductor element TR101 and the low voltage side power semiconductor element TR102 connected in series.

  In low voltage side drive circuit 52, the source of P channel MOS transistor TR53 is connected to power supply potential node NL2, and the drain is connected to the drain of N channel MOS transistor TR54 and the gate of low voltage side power semiconductor element TR102. The source of P-channel MOS transistor TR54 is connected to ground potential node NG3.

  The drain of the high voltage side power semiconductor element TR101 is connected to the high voltage node NH. The source of low voltage side power semiconductor element TR102 is connected to ground potential node NG2.

  High-voltage side drive circuit 51 supplies a voltage to the gate of high-voltage side power semiconductor element TR101 based on the control voltage supplied to the gates of P-channel MOS transistor TR51 and N-channel MOS transistor TR52. Low-voltage side drive circuit 52 supplies a voltage to the gate of low-voltage side power semiconductor element TR102 based on a control voltage supplied to each gate of P-channel MOS transistor TR53 and N-channel MOS transistor TR54.

FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention.
Referring to FIG. 2, semiconductor device 101 includes p − type substrate (semiconductor layer) 1, n type diffusion region (first semiconductor region) 2, p type diffusion region (second semiconductor region) 3, and , N + type diffusion regions 4 and 5, p type diffusion region 6, n + type diffusion regions 7 and 8, resistor R, diode D1, contacts CT1 to CT7, p + type diffusion regions 21 to 23, gates Electrodes G1 and G2, gate insulating films GF1 and GF2, and an oxide film F are provided.

  The dotted line in FIG. 2 indicates the boundary of the depletion layer extending from the junction surface between the p − type substrate 1 and the n type diffusion region 2.

  P − type substrate 1 is connected to ground potential node NG1 through contact CT7. N type diffusion region 2 is formed on the main surface of p − type substrate 1.

  P type diffusion region 3 is formed on the surface of n type diffusion region 2 with a distance from the main surface of p − type substrate 1. P type diffusion region 3 has a node N3 coupled to power supply potential node NL1.

  N + type diffusion region 4 is formed on the surface of n type diffusion region 2 with a distance from the main surface of p − type substrate 1 and p type diffusion region 3. N + type diffusion region 4 has a node N2 coupled to power supply potential node NL1. That is, n + type diffusion region 4 is connected to power supply potential node NL1 through contact CT2 and diode D1.

  N + type diffusion region 5 is formed on the surface of n type diffusion region 2 with a distance from the main surface of p − type substrate 1, p type diffusion region 3 and n + type diffusion region 4. N + type diffusion region 5 has a node N 1 coupled to the first electrode of capacitor C. That is, the n + type diffusion region 5 is connected to the first electrode of the capacitor C through the contact CT3.

  The semiconductor device 101 may be configured without the n + -type diffusion regions 4 and 5. In this case, n type diffusion region 2 has a node N1 coupled to the first electrode of capacitor C and a node N2 coupled to power supply potential node NL1.

  Resistor R has a first end connected to power supply potential node NL1 and a second end connected to p-type diffusion region 3 via contact CT1. The resistor R limits the movement of holes (charge carriers) from the node N3 to the p − type substrate 1.

  PNP transistor TR 1 has a collector formed by p − type substrate 1, a base formed by n type diffusion region 2, and an emitter formed by p type diffusion region 3. The PNP transistor TR 1 supplies a charging current to the capacitor C through the n-type diffusion region 2.

  Junction field effect transistor TR2 has a gate formed by n-type diffusion region 2 and p-type diffusion region 3, a drain formed by n-type diffusion region 2 and coupled to power supply potential node NL1 through node N2. , Having a source formed by n-type diffusion region 2 and coupled to the first electrode of capacitor C via node N1. The junction field effect transistor TR2 supplies a charging current to the capacitor C through the n-type diffusion region 2.

  The diode D1 includes a cathode (n-type electrode) connected to the drain of the junction field effect transistor TR2 via the contact CT2, and an anode (p-type electrode) connected to the power supply potential node NL1 and the first end of the resistor R. And have.

  P + type diffusion region 21 is formed on the surface of n type diffusion region 2 with a distance from the main surface of p − type substrate 1, p type diffusion region 3 and n + type diffusion region 4. The p + type diffusion region 21 is connected to the first electrode of the capacitor C through the contact CT3.

  The p + type diffusion region 22 is formed on the surface of the n type diffusion region 2 with a space from the main surface of the p − type substrate 1, the p type diffusion region 3, the n + type diffusion regions 4 and 5, and the p + type diffusion region 21. Is done. P + type diffusion region 22 is connected to n + type diffusion region 7 through contacts CT5 and CT6.

  P-channel MOS transistor TR51 is formed by a gate electrode G1 formed on the surface of n-type diffusion region 2 via gate insulating film GF1, a source formed by p + -type diffusion region 21, and p + -type diffusion region 22. Drain. The gate electrode G1 is provided to face the channel region in the n-type diffusion region 2 sandwiched between the p + -type diffusion regions 21 and 22 via the gate insulating film GF1.

  The p type diffusion region 6 is formed on the main surface of the p − type substrate 1, the p type diffusion region 3, the n + type diffusion regions 4 and 5, the p + type diffusion region 21 and the p + type diffusion region 22 on the surface of the n type diffusion region 2. And spaced apart.

  N + type diffusion region 7 is formed on the surface of p type diffusion region 6 with a distance from the main surface of p − type substrate 1 and n type diffusion region 2. N + type diffusion region 7 is connected to p + type diffusion region 22 through contacts CT5 and CT6.

  N + type diffusion region 8 is formed on the surface of p type diffusion region 6 with a distance from the main surface of p − type substrate 1, n type diffusion region 2 and n + type diffusion region 7. N + type diffusion region 8 is connected to the second electrode of capacitor C through contact CT4.

  N-channel MOS transistor TR52 is formed by a gate electrode G2 formed on the surface of p-type diffusion region 6 via gate insulating film GF2, a drain formed by n + -type diffusion region 7, and n + -type diffusion region 8. And have a source. The gate electrode G2 is provided to face the channel region in the p-type diffusion region 6 sandwiched between the n + -type diffusion regions 7 and 8 with the gate insulating film GF2 interposed therebetween.

  The p + type diffusion region 23 is formed on the surface of the p type diffusion region 6 with a space from the main surface of the p − type substrate 1 and the n + type diffusion region 7. The p + type diffusion region 23 is connected to the second electrode of the capacitor C through the contact CT4.

  P type diffusion regions 3 and 6 have a higher impurity concentration than p − type substrate 1. The p + type diffusion regions 21 to 23 have a higher impurity concentration than the p type diffusion regions 3 and 6. The n + type diffusion regions 4, 5, 7, and 8 have a higher impurity concentration than the n type diffusion region 2.

Semiconductor device 101 is designed to correspond to a power conversion circuit that requires a withstand voltage of 600 V, for example. In this case, the impurity concentration of the p − type substrate 1 is 5 × 10 ¹³ / cm ^{3 to} 5 × 10 ¹⁴ / cm ³ , and the power supply voltage Vcc is, for example, 15V to 30V.

  Strictly speaking, the gate electrode of junction field effect transistor TR2 is formed by both p − type substrate 1 coupled to ground potential node NG1 and p type diffusion region 3 coupled to power supply potential node NL1. . However, since the impurity concentration of the p-type diffusion region 3 is higher than that of the p-type substrate 1, the influence of the depletion layer extending from the p-type diffusion region 3 is greater than the influence of the depletion layer extending from the p-type substrate 1. Therefore, in order to simplify the description, it is assumed that the gate electrode of the junction field effect transistor TR2 is formed by the p-type diffusion region 3 and the n-type diffusion region 2.

[Operation]
Next, the operation when the semiconductor device according to the first embodiment of the present invention charges the capacitor C will be described.

  The power supply voltage Vcc is, for example, 15V, and the high voltage HV is, for example, 300V. The potential Vs of the reference voltage terminal T2 of the high-voltage side drive circuit 51 changes in the range of 0V to 300V, for example.

  Further, the potential Vb of the power supply voltage terminal T1 of the high-voltage side drive circuit 51 is higher than the potential Vs by the voltage held by the capacitor C.

  Here, since the potential Vs repeats up and down in accordance with the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102, the potential Vb also repeats up and down corresponding to the potential Vs. That is, the potential Vb alternately repeats the state of Vb <Vcc and the state of Vb> Vcc.

  Here, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, the PNP transistor TR1 is turned on, that is, a forward bias voltage is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2. The Then, holes are injected from p-type diffusion region 3 to n-type diffusion region 2, that is, resistance R, p-type diffusion region 3, n-type diffusion region 2 and n + -type diffusion region 5 are supplied from power supply potential node NL1 to capacitor C. Current is supplied through the capacitor C, and the capacitor C is charged.

  Further, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, the junction field effect transistor TR2 supplies a current to the capacitor C. That is, current is supplied to capacitor C from power supply potential node NL1 through diode D1, n + type diffusion region 4, n type diffusion region 2, and n + type diffusion region 5, and capacitor C is charged.

  On the other hand, when the potential Vb rises and becomes higher than the power supply voltage Vcc, a reverse bias voltage is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2, so 5. Backflow current to power supply potential node NL1 through n-type diffusion region 2, p-type diffusion region 3 and resistor R is blocked.

  Further, when the potential Vb rises and becomes higher than the power supply voltage Vcc, a reverse bias voltage is applied to the diode D1, so that the n + type diffusion region 5, the n type diffusion region 2, the n + type diffusion region 4 and the diode from the capacitor C are applied. Backflow current to power supply potential node NL1 via D1 is blocked. The junction field effect transistor TR2 is pinched off before the potential Vb further rises and reaches the breakdown voltage of the diode D1. That is, the depletion layer spreads in the n-type diffusion region 2 and the current path is closed, so that the voltage applied to the diode D1 can be prevented from reaching the breakdown voltage.

  In this way, since the capacitor C is charged every time the potential Vb becomes equal to or lower than the power supply voltage Vcc, the capacitor C can be used as a power source for the high-voltage side drive circuit 51 that is a floating circuit. Further, it is possible to prevent a backflow current from capacitor C to power supply potential node NL1.

  Here, in the PNP transistor TR 1 formed by the p − type substrate 1, the n type diffusion region 2 and the p type diffusion region 3, the current from the p type diffusion region 3 to the p − type substrate 1 which is a collector current is greater. It becomes larger by the hFE (current amplification factor) of the PNP transistor TR1 than the current from the p-type diffusion region 3 which is the base current to the capacitor C. That is, when the capacitor C is charged, holes injected from the p-type diffusion region 3 to the n-type diffusion region 2 almost flow into the p − type substrate 1. For this reason, when it is assumed that the semiconductor device 101 does not include the resistor R, when the capacitor C is charged, even if a large amount of current flows from the power supply potential node NL1 to the contact CT1, the current reaching the capacitor C decreases. For this reason, the power loss of the power supply for supplying the power supply voltage Vcc becomes considerably large.

  However, the semiconductor device according to the first embodiment of the present invention includes a resistor R connected between the power supply potential node NL1 and the p-type diffusion region 3. With such a configuration, the potential of the contact CT1 becomes smaller than the power supply voltage Vcc by the voltage drop in the resistor R. Therefore, in the semiconductor device according to the first embodiment of the present invention, the amount of holes injected from the p-type diffusion region 3 to the n-type diffusion region 2 can be limited, and the power loss of the power supply can be reduced. Can do.

  Further, in a configuration that simply includes a resistor R connected between power supply potential node NL 1 and p type diffusion region 3, a hole that flows from power supply potential node NL 1 to n type diffusion region 2 through p type diffusion region 3. Is reduced by the resistor R, the charging current from the power supply potential node NL1 to the capacitor C is reduced.

  However, in the semiconductor device according to the first embodiment of the present invention, n + -type diffusion region 4 has node N2 coupled to power supply potential node NL1. With such a configuration, a charging current can be supplied from the junction field effect transistor TR2 formed by the n-type diffusion region 2 and the p-type diffusion region 3 to the capacitor C via the n-type diffusion region 2. It can be prevented that the charging current from the potential node NL1 to the capacitor C becomes small.

  Further, as in the configurations described in Patent Documents 1 to 3, assuming that the semiconductor device 101 does not include the resistor R and the potential of the p-type diffusion region 3 is the ground potential, the potential Vb decreases and the power supply voltage Vcc is exceeded. Even when it becomes smaller, a reverse bias voltage is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2, so that a depletion layer from the p-type diffusion region 3 spreads in the n-type diffusion region 2. End up. For this reason, the conduction resistance of the junction field effect transistor TR2, that is, the resistance between the contacts CT1 and CT3 increases, and the charging current from the junction field effect transistor TR2 to the capacitor C decreases.

  However, in the semiconductor device according to the first embodiment of the present invention, p type diffusion region 3 is coupled to power supply potential node NL1. With such a configuration, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, a forward bias voltage is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2, and thus the n-type diffusion region 2, the depletion layer from the p-type diffusion region 3 can be prevented from spreading.

  In the semiconductor device according to the first embodiment of the present invention, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, the forward bias is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2. Since a voltage is applied, holes are injected from the p-type diffusion region 3 to the n-type diffusion region 2. The conductivity modulation occurs in the n-type diffusion region 2 due to the injected holes, that is, the electrons gather in the n-type diffusion region 2 to increase the conductivity of the n-type diffusion region 2. Therefore, in the semiconductor device according to the first embodiment of the present invention, it is possible to prevent the conduction resistance of the junction field effect transistor TR2 from being reduced, and to prevent the charging current to the capacitor C from being reduced. it can.

  In the semiconductor device according to the first embodiment of the present invention, the amount of holes injected from the p-type diffusion region 3 to the n-type diffusion region 2 by adjusting the resistance value of the resistor R and the junction field effect. The conduction resistance of the transistor TR2 can be set appropriately.

  As described above, in the semiconductor device according to the first embodiment of the present invention, the charging current can be efficiently supplied to the charging target element.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the first embodiment. The contents other than those described below are the same as those of the semiconductor device according to the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor device according to the second embodiment of the present invention.
Referring to FIG. 3, the semiconductor device 102 further includes a diode D2 as compared with the semiconductor device 101 according to the first embodiment of the present invention.

  Diode D2 has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a sudden rise in the potential Vb, and the potential of the contact CT1 becomes significantly larger than the power supply voltage Vcc, thereby inducing an avalanche between the n + type diffusion region 4 and the p diffusion region 3. There is a case.

  However, in the semiconductor device according to the second embodiment of the present invention, since the diode D2 is in a forward bias state when the potential Vb is rapidly increased, the potential of the contact CT1 is higher than the power supply voltage Vcc. Can be prevented.

  Since other configurations and operations are the same as those of the semiconductor device according to the first embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the second embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the first embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Third Embodiment>
The present embodiment relates to a semiconductor device in which a transistor is added compared to the semiconductor device according to the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor device according to the third embodiment of the present invention.
Referring to FIG. 4, the semiconductor device 103 further includes an NPN transistor TR11 as compared with the semiconductor device 101 according to the first embodiment of the present invention. NPN transistor TR11 has a collector connected to power supply potential node NL1, an emitter connected to the first electrode of capacitor C, and a base connected to the second end of resistor R.

FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention.
Referring to FIG. 5, the semiconductor device 103 further includes an n + type diffusion region 11 and a contact CT11 as compared with the semiconductor device 101 according to the first embodiment of the present invention.

  N + type diffusion region 11 is formed on the surface of p type diffusion region 3 with a distance from the main surface of p − type substrate 1 and n type diffusion region 2. N + type diffusion region 11 has a node N4 connected to power supply potential node NL1 through contact CT11.

  NPN transistor TR11 has a collector formed by n + -type diffusion region 11, a base formed by p-type diffusion region 3, and an emitter formed by n-type diffusion region 2. The NPN transistor TR11 supplies a charging current to the capacitor C through the n-type diffusion region 2.

  With such a configuration, the charging current supplied to the capacitor C is such that the charging current from the contact CT1 to the capacitor C due to the holes injected from the p-type diffusion region 3 to the n-type diffusion region 2, and the junction field effect transistor TR2 Is the sum of the charging current from the contact CT2 to the capacitor C and the charging current from the contact CT11 to the capacitor C by the NPN transistor TR11.

  Since other configurations and operations are the same as those of the semiconductor device according to the first embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the third embodiment of the present invention, as compared with the semiconductor device 101 according to the first embodiment of the present invention, the resistance of the current path from the power supply potential node NL1 to the capacitor C is further increased. A value can be made small and a charging current can be efficiently supplied to a charge object element.

  Although the semiconductor device according to the third embodiment of the present invention is configured to include the n + -type diffusion region 11, as in the semiconductor device according to the eighteenth embodiment of the present invention described later, A configuration without the n + -type diffusion region 11 is possible. In this case, p type diffusion region 3 has a node N4 connected to power supply potential node NL1 through contact CT11.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fourth embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the third embodiment. The contents other than those described below are the same as those of the semiconductor device according to the third embodiment.

FIG. 6 is a circuit diagram showing a configuration of a semiconductor device according to the fourth embodiment of the present invention.
Referring to FIG. 6, the semiconductor device 104 further includes a diode D11 as compared with the semiconductor device 103 according to the third embodiment of the present invention.

  Diode D11 is a Schottky diode, and has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1. Diode D11 has a forward voltage smaller than the forward voltage of the pn junction formed by p type diffusion region 3 and n + type diffusion region 11.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a sudden rise in the potential Vb, and the potential of the contact CT1 becomes significantly higher than the power supply voltage Vcc, and a pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11 Since a forward bias voltage is applied to the capacitor C, a reverse current may flow from the capacitor C to the power supply potential node NL1.

  However, the semiconductor device according to the fourth embodiment of the present invention includes the diode D11 whose forward voltage is smaller than the forward voltage of the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11. With such a configuration, it is possible to prevent a forward bias voltage from being applied to the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11, so that a backflow current flows from the capacitor C to the power supply potential node NL 1. It can be prevented from flowing.

  Since other configurations and operations are the same as those of the semiconductor device according to the third embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the fourth embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the third embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fifth embodiment>
The present embodiment relates to a semiconductor device in which a transistor is added as compared with the semiconductor device according to the third embodiment. The contents other than those described below are the same as those of the semiconductor device according to the third embodiment.

FIG. 7 is a circuit diagram showing a configuration of a semiconductor device according to the fifth embodiment of the present invention.
Referring to FIG. 7, semiconductor device 105 further includes an N-channel MOS transistor TR21, as compared with semiconductor device 103 according to the third embodiment of the present invention.

  N-channel MOS transistor TR21 has a drain connected to power supply potential node NL1, a source connected to the first electrode of capacitor C, and a gate connected to power supply potential node NL1.

FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to the fifth embodiment of the present invention.
Referring to FIG. 8, the semiconductor device 105 further includes a gate electrode G21 and a gate insulating film GF21 as compared with the semiconductor device 103 according to the third embodiment of the present invention.

  N-channel MOS transistor TR 21 is formed by a gate electrode G 21 formed on the surface of p-type diffusion region 3 via gate insulating film GF 21, a source formed by n-type diffusion region 2, and n + -type diffusion region 11. Drain. The gate electrode G21 is provided to face the channel region in the p-type diffusion region 3 sandwiched between the n-type diffusion region 2 and the n + -type diffusion region 11 with the gate insulating film GF21 interposed therebetween. N-channel MOS transistor TR 21 supplies a charging current to capacitor C through n-type diffusion region 2.

  When the potential Vb decreases and becomes smaller than the power supply voltage Vcc, a positive bias voltage is applied to the gate electrode G21 by a voltage drop due to the current flowing through the resistor R. When this positive bias voltage becomes larger than the threshold voltage of N channel MOS transistor TR 21, N channel MOS transistor TR 21 is turned on, and N channel MOS transistor TR 21 supplies a charging current to capacitor C through n-type diffusion region 2.

  With such a configuration, the charging current supplied to the capacitor C is such that the charging current from the contact CT1 to the capacitor C due to the holes injected from the p-type diffusion region 3 to the n-type diffusion region 2, and the junction field effect transistor TR2 Is the sum of the charging current from the contact CT2 to the capacitor C, the charging current from the contact CT11 to the capacitor C by the NPN transistor TR11, and the charging current from the contact CT11 to the capacitor C by the N-channel MOS transistor TR21.

  Since other configurations and operations are the same as those of the semiconductor device according to the third embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the fifth embodiment of the present invention, compared with the semiconductor device 103 according to the third embodiment of the present invention, the resistance of the current path from the power supply potential node NL1 to the capacitor C is further increased. A value can be made small and a charging current can be efficiently supplied to a charge object element.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Sixth Embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the fifth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the fifth embodiment.

FIG. 9 is a circuit diagram showing a configuration of a semiconductor device according to the sixth embodiment of the present invention.
Referring to FIG. 9, the semiconductor device 106 further includes a diode D21 as compared with the semiconductor device 105 according to the fifth embodiment of the present invention.

  Diode D21 is a Zener diode, and has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1. The diode D21 clamps the applied reverse voltage to a predetermined voltage value.

  With such a configuration, it is possible to prevent a transient overvoltage from being applied to the gate electrode G21 of the N channel MOS transistor TR21 and to prevent the gate of the N channel MOS transistor TR21 from being destroyed.

  Since other configurations and operations are the same as those of the semiconductor device according to the fifth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the sixth embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the fifth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Seventh embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the fifth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the fifth embodiment.

FIG. 10 is a circuit diagram showing a configuration of a semiconductor device according to the seventh embodiment of the present invention.
Referring to FIG. 10, the semiconductor device 107 further includes a diode D22 as compared with the semiconductor device 105 according to the fifth embodiment of the present invention.

  Diode D22 is a Schottky diode, and has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1. Diode D22 has a forward voltage smaller than the forward voltage of the pn junction formed by p type diffusion region 3 and n + type diffusion region 11.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a sudden rise in the potential Vb, and the potential of the contact CT1 becomes significantly higher than the power supply voltage Vcc, and a pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11 Since a forward bias voltage is applied to the capacitor C, a reverse current may flow from the capacitor C to the power supply potential node NL1.

  However, the semiconductor device according to the seventh embodiment of the present invention includes the diode D22 whose forward voltage is smaller than the forward voltage of the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11. With such a configuration, it is possible to prevent a forward bias voltage from being applied to the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11, so that a backflow current flows from the capacitor C to the power supply potential node NL 1. It can be prevented from flowing.

  Since other configurations and operations are the same as those of the semiconductor device according to the fifth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the seventh embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the fifth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Eighth Embodiment>
The present embodiment relates to a semiconductor device provided with a bipolar transistor instead of a junction field effect transistor as compared with the semiconductor device according to the first embodiment. The contents other than those described below are the same as those of the semiconductor device according to the first embodiment.

[Configuration and basic operation]
FIG. 11 is a circuit diagram showing a configuration of a semiconductor device according to the eighth embodiment of the present invention.

  Referring to FIG. 11, the semiconductor device 108 includes a PNP transistor TR1, an NPN transistor TR31, and a resistor (charge carrier movement limiting unit) R.

  A first end of resistor R is connected to power supply potential node NL1. PNP transistor TR1 has an emitter (conducting electrode) connected to the second end of resistor R, a collector (conducting electrode) connected to ground potential node NG1, and a base (control electrode) connected to the first electrode of capacitor C. The NPN transistor TR31 has a collector connected to power supply potential node NL1, an emitter connected to the first electrode of capacitor C, and a base connected to the second end of resistor R.

FIG. 12 is a cross-sectional view showing a configuration of a semiconductor device according to the eighth embodiment of the present invention.
Referring to FIG. 12, semiconductor device 108 includes a p − type substrate (semiconductor layer) 1, an n type diffusion region (first semiconductor region) 2, a p type diffusion region (second semiconductor region) 3, and , N + type diffusion region 5, p type diffusion region 6, n + type diffusion regions 7 and 8, resistor R, contacts CT1, CT3 to CT7, CT11, and n + type diffusion region (charge carrier movement limiting portion) P + type diffusion regions 21 to 23, gate electrodes G1 and G2, gate insulating films GF1 and GF2, and oxide film F.

  The dotted line in FIG. 12 indicates the boundary of the depletion layer extending from the junction surface between the p − type substrate 1 and the n type diffusion region 2.

  P − type substrate 1 is connected to ground potential node NG1 through contact CT7. N type diffusion region 2 is formed on the main surface of p − type substrate 1.

  P type diffusion region 3 is formed on the surface of n type diffusion region 2 with a distance from the main surface of p − type substrate 1. P type diffusion region 3 has a node N3 coupled to power supply potential node NL1.

  N + type diffusion region 11 is formed on the surface of p type diffusion region 3 with a distance from the main surface of p − type substrate 1 and n type diffusion region 2. N + type diffusion region 11 has a node N4 connected to power supply potential node NL1 through contact CT11. The n + type diffusion region 11 restricts the movement of holes (charge carriers) from the node N 4 to the p − type substrate 1.

  N + type diffusion region 5 is formed on the surface of n type diffusion region 2 with a distance from the main surface of p − type substrate 1 and p type diffusion region 3. N + type diffusion region 5 has a node N 1 coupled to the first electrode of capacitor C. That is, the n + type diffusion region 5 is connected to the first electrode of the capacitor C through the contact CT3.

  The semiconductor device 101 may be configured without the n + type diffusion region 5. In this case, n-type diffusion region 2 has a node N1 coupled to the first electrode of capacitor C.

  Resistor R has a first end connected to power supply potential node NL1 and a second end connected to p-type diffusion region 3 via contact CT1. The resistor R limits the movement of holes (charge carriers) from the node N3 to the p − type substrate 1.

  PNP transistor TR 1 has a collector formed by p − type substrate 1, a base formed by n type diffusion region 2, and an emitter formed by p type diffusion region 3. The PNP transistor TR 1 supplies a charging current to the capacitor C through the n-type diffusion region 2.

  NPN transistor TR31 has a collector formed by n + type diffusion region 11, a base formed by p type diffusion region 3, and an emitter formed by n type diffusion region 2. The NPN transistor TR31 supplies a charging current to the capacitor C through the n-type diffusion region 2.

  The p + type diffusion region 21 is formed on the surface of the n type diffusion region 2 at a distance from the main surface of the p − type substrate 1 and the p type diffusion region 3. The p + type diffusion region 21 is connected to the first electrode of the capacitor C through the contact CT3.

  The p + -type diffusion region 22 is formed on the surface of the n-type diffusion region 2 at a distance from the main surface of the p − -type substrate 1, the p-type diffusion region 3 and the p + -type diffusion region 21. P + type diffusion region 22 is connected to n + type diffusion region 7 through contacts CT5 and CT6.

  P-channel MOS transistor TR51 is formed by a gate electrode G1 formed on the surface of n-type diffusion region 2 via gate insulating film GF1, a source formed by p + -type diffusion region 21, and p + -type diffusion region 22. Drain. The gate electrode G1 is provided to face the channel region in the n-type diffusion region 2 sandwiched between the p + -type diffusion regions 21 and 22 via the gate insulating film GF1.

  The p type diffusion region 6 is spaced from the main surface of the p − type substrate 1, the p type diffusion region 3, the n + type diffusion region 5, the p + type diffusion region 21 and the p + type diffusion region 22 on the surface of the n type diffusion region 2. It is formed with a gap.

  N + type diffusion region 7 is formed on the surface of p type diffusion region 6 with a distance from the main surface of p − type substrate 1 and n type diffusion region 2. N + type diffusion region 7 is connected to p + type diffusion region 22 through contacts CT5 and CT6.

  N + type diffusion region 8 is formed on the surface of p type diffusion region 6 with a distance from the main surface of p − type substrate 1, n type diffusion region 2 and n + type diffusion region 7. N + type diffusion region 8 is connected to the second electrode of capacitor C through contact CT4.

  N-channel MOS transistor TR52 is formed by a gate electrode G2 formed on the surface of p-type diffusion region 6 via gate insulating film GF2, a drain formed by n + -type diffusion region 7, and n + -type diffusion region 8. And have a source. The gate electrode G2 is provided to face the channel region in the p-type diffusion region 6 sandwiched between the n + -type diffusion regions 7 and 8 with the gate insulating film GF2 interposed therebetween.

  The p + type diffusion region 23 is formed on the surface of the p type diffusion region 6 with a space from the main surface of the p − type substrate 1 and the n + type diffusion region 7. The p + type diffusion region 23 is connected to the second electrode of the capacitor C through the contact CT4.

  P type diffusion regions 3 and 6 have a higher impurity concentration than p − type substrate 1. The p + type diffusion regions 21 to 23 have a higher impurity concentration than the p type diffusion regions 3 and 6. The n + type diffusion regions 5, 7, 8, and 11 have a higher impurity concentration than the n type diffusion region 2.

Semiconductor device 101 is designed to correspond to a power conversion circuit that requires a withstand voltage of 600 V, for example. In this case, the impurity concentration of the p − type substrate 1 is 5 × 10 ¹³ / cm ^{3 to} 5 × 10 ¹⁴ / cm ³ , and the power supply voltage Vcc is, for example, 15V to 30V.

[Operation]
Next, an operation when the semiconductor device according to the eighth embodiment of the present invention charges the capacitor C will be described.

  The power supply voltage Vcc is, for example, 15V, and the high voltage HV is, for example, 300V. The potential Vs of the reference voltage terminal T2 of the high-voltage side drive circuit 51 changes in the range of 0V to 300V, for example.

  Further, the potential Vb of the power supply voltage terminal T1 of the high-voltage side drive circuit 51 is higher than the potential Vs by the voltage held by the capacitor C.

  Here, since the potential Vs repeats up and down in accordance with the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102, the potential Vb also repeats up and down corresponding to the potential Vs. That is, the potential Vb alternately repeats the state of Vb <Vcc and the state of Vb> Vcc.

  Here, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, the PNP transistor TR1 is turned on, that is, a forward bias voltage is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2. The Then, holes are injected from p-type diffusion region 3 to n-type diffusion region 2, that is, resistance R, p-type diffusion region 3, n-type diffusion region 2 and n + -type diffusion region 5 are supplied from power supply potential node NL1 to capacitor C. Current is supplied through the capacitor C, and the capacitor C is charged.

  Further, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, the NPN transistor TR31 supplies a current to the capacitor C. That is, current is supplied from the power supply potential node NL1 to the capacitor C through the n + -type diffusion region 11, the p-type diffusion region 3, the n-type diffusion region 2, and the n + -type diffusion region 5, and the capacitor C is charged.

  On the other hand, when the potential Vb rises and becomes higher than the power supply voltage Vcc, a reverse bias voltage is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2, so 5. Backflow current to power supply potential node NL1 through n-type diffusion region 2, p-type diffusion region 3 and resistor R is blocked. Similarly, backflow current from the capacitor C to the power supply potential node NL1 through the n + -type diffusion region 5, the n-type diffusion region 2, the p-type diffusion region 3 and the n + -type diffusion region 11 is also prevented.

  In this way, since the capacitor C is charged every time the potential Vb becomes equal to or lower than the power supply voltage Vcc, the capacitor C can be used as a power source for the high-voltage side drive circuit 51 that is a floating circuit. Further, it is possible to prevent a backflow current from capacitor C to power supply potential node NL1.

  Here, in the PNP transistor TR 1 formed by the p − type substrate 1, the n type diffusion region 2 and the p type diffusion region 3, the current from the p type diffusion region 3 to the p − type substrate 1 which is a collector current is greater. It becomes larger by the hFE (current amplification factor) of the PNP transistor TR1 than the current from the p-type diffusion region 3 which is the base current to the capacitor C. That is, when the capacitor C is charged, holes injected from the p-type diffusion region 3 to the n-type diffusion region 2 almost flow into the p − type substrate 1. Therefore, assuming that the semiconductor device 108 does not include the resistor R, when the capacitor C is charged, the current reaching the capacitor C is reduced even if the current flowing from the power supply potential node NL1 to the contact CT1 is large. For this reason, the power loss of the power supply for supplying the power supply voltage Vcc becomes considerably large.

  However, the semiconductor device according to the eighth embodiment of the present invention includes a resistor R connected between the power supply potential node NL1 and the p-type diffusion region 3. With such a configuration, the potential of the contact CT1 becomes smaller than the power supply voltage Vcc by the voltage drop in the resistor R. Therefore, in the semiconductor device according to the eighth embodiment of the present invention, the amount of holes injected from the p-type diffusion region 3 to the n-type diffusion region 2 can be limited, and the power loss of the power supply can be reduced. Can do.

  Further, in a configuration that simply includes a resistor R connected between power supply potential node NL 1 and p type diffusion region 3, a hole that flows from power supply potential node NL 1 to n type diffusion region 2 through p type diffusion region 3. Is reduced by the resistor R, the charging current from the power supply potential node NL1 to the capacitor C is reduced.

  However, the semiconductor device according to the eighth embodiment of the present invention is formed on the surface of the p-type diffusion region 3 at a distance from the main surface of the p − -type substrate 1 and the n-type diffusion region 2. N + type diffusion region 11 coupled to node NL1 is provided. With such a configuration, a charging current can be supplied to the capacitor C through the n-type diffusion region 2 from the NPN transistor TR31 formed by the n + -type diffusion region 11, the p-type diffusion region 3, and the n-type diffusion region 2. Therefore, the charging current from power supply potential node NL1 to capacitor C can be prevented from becoming small.

  Further, in the configuration including the junction field effect transistor that supplies the charging current to the capacitor C as in the configuration described in Non-Patent Document 1, even when the potential Vb is decreased and becomes smaller than the power supply voltage Vcc, the n-type diffusion region is used. 2, the depletion layer from the p-type diffusion region 3 spreads. For this reason, the resistance of the n-type diffusion region 2 increases, and the charging current to the capacitor C decreases.

  However, unlike the semiconductor device 101 according to the first embodiment of the present invention, the semiconductor device according to the eighth embodiment of the present invention includes the n + type diffusion region 4 coupled to the power supply potential node NL1. Therefore, a junction field effect transistor is not formed. That is, since the depletion layer from the p-type diffusion region 3 can be prevented from spreading in the n-type diffusion region 2, the conduction resistance of the n-type diffusion region 2 can be reduced, and the power supply potential node NL1 to the capacitor C can be reduced. Can be prevented from being reduced.

  In the semiconductor device according to the eighth embodiment of the present invention, p type diffusion region 3 is coupled to power supply potential node NL1. With such a configuration, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, a forward bias voltage is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2, and thus the n-type diffusion region 2, the depletion layer from the p-type diffusion region 3 can be prevented from spreading.

  In the semiconductor device according to the eighth embodiment of the present invention, when the potential Vb decreases and becomes lower than the power supply voltage Vcc, a forward bias is applied to the pn junction formed by the p-type diffusion region 3 and the n-type diffusion region 2. Since a voltage is applied, holes are injected from the p-type diffusion region 3 to the n-type diffusion region 2. The conductivity modulation occurs in the n-type diffusion region 2 due to the injected holes, that is, the electrons gather in the n-type diffusion region 2 to increase the conductivity of the n-type diffusion region 2. Therefore, in the semiconductor device according to the first embodiment of the present invention, it is possible to prevent the conduction resistance of the junction field effect transistor TR2 from being reduced, and to prevent the charging current to the capacitor C from being reduced. it can.

  In the semiconductor device according to the eighth embodiment of the present invention, the amount of holes injected from the p-type diffusion region 3 to the n-type diffusion region 2 and the junction field effect by adjusting the resistance value of the resistor R. The conduction resistance of the transistor TR2 can be set appropriately.

  As described above, in the semiconductor device according to the eighth embodiment of the present invention, the charging current can be efficiently supplied to the charging target element.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Ninth embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the eighth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the eighth embodiment.

FIG. 13 is a circuit diagram showing a configuration of a semiconductor device according to the ninth embodiment of the present invention.
Referring to FIG. 13, the semiconductor device 109 further includes a diode D31 as compared with the semiconductor device 103 according to the eighth embodiment of the present invention.

  Diode D31 is a Schottky diode, and has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1. Diode D31 has a forward voltage smaller than the forward voltage of the pn junction formed by p type diffusion region 3 and n + type diffusion region 11.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a sudden rise in the potential Vb, and the potential of the contact CT1 becomes significantly higher than the power supply voltage Vcc, and a pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11 Since a forward bias voltage is applied to the capacitor C, a reverse current may flow from the capacitor C to the power supply potential node NL1.

  However, the semiconductor device according to the ninth embodiment of the present invention includes the diode D31 whose forward voltage is smaller than the forward voltage of the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11. With such a configuration, it is possible to prevent a forward bias voltage from being applied to the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11, so that a backflow current flows from the capacitor C to the power supply potential node NL 1. It can be prevented from flowing.

  Since other configurations and operations are the same as those of the semiconductor device according to the eighth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the ninth embodiment of the present invention, the charging current can be efficiently supplied to the charging target element, similarly to the semiconductor device according to the eighth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Tenth Embodiment>
The present embodiment relates to a semiconductor device in which a transistor is added as compared with the semiconductor device according to the eighth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the eighth embodiment.

FIG. 14 is a circuit diagram showing a configuration of a semiconductor device according to the tenth embodiment of the present invention.
Referring to FIG. 14, the semiconductor device 110 further includes an N-channel MOS transistor TR41 and a junction field effect transistor TR42, as compared with the semiconductor device 108 according to the eighth embodiment of the present invention.

  N-channel MOS transistor TR41 has a drain connected to power supply potential node NL1, and a source connected to the second end of resistor R.

  Junction field effect transistor TR42 has a drain connected to the gate of N-channel MOS transistor TR41, a gate connected to the second end of resistor R, and a source connected to the first electrode of capacitor C.

FIG. 15 is a cross-sectional view showing the configuration of the semiconductor device according to the tenth embodiment of the present invention.
Referring to FIG. 15, semiconductor device 110 further includes gate electrode G41, gate insulating film GF41, and n + type diffusion regions 4 and 12 as compared with semiconductor device 108 according to the eighth embodiment of the present invention. And a contact CT2.

  N + type diffusion region 4 is formed on the surface of n type diffusion region 2 with a distance from the main surface of p − type substrate 1 and p type diffusion region 3. N + type diffusion region 4 has a node N2 coupled to gate electrode G41. That is, the n + -type diffusion region 4 is connected to the gate electrode G41 through the contact CT2.

  The semiconductor device 110 may be configured not to include the n + type diffusion region 4. In this case, n type diffusion region 2 has a node N2 coupled to power supply potential node NL1.

  N + type diffusion region 12 is formed on the surface of p type diffusion region 3 with a distance from the main surface of p− type substrate 1, n type diffusion region 2 and n + type diffusion region 11. N + type diffusion region 12 has a node N3 connected to power supply potential node NL1 through contact CT1 and resistor R.

  N-channel MOS transistor TR41 is formed by a gate electrode G41 formed on the surface of p-type diffusion region 3 via gate insulating film GF41, a drain formed by n + -type diffusion region 11, and n + -type diffusion region 12. And have a source. The gate electrode G41 is provided to face the channel region in the p-type diffusion region 3 sandwiched between the n + -type diffusion region 11 and the n + -type diffusion region 12 with the gate insulating film GF41 interposed therebetween. N-channel MOS transistor TR41 supplies a charging current to capacitor C through n-type diffusion region 2.

  Junction field effect transistor TR42 has a gate formed by n-type diffusion region 2 and p-type diffusion region 3, a drain formed by n-type diffusion region 2 and coupled to gate electrode G41 via node N2, A source formed by n-type diffusion region 2 and coupled to the first electrode of capacitor C via node N1.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a sudden rise in the potential Vb, and the potential of the contact CT1 becomes significantly higher than the power supply voltage Vcc, and a pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11 Since a forward bias voltage is applied to the capacitor C, a reverse current may flow from the capacitor C to the power supply potential node NL1.

  However, in the semiconductor device according to the tenth embodiment of the present invention, when the potential Vb increases and becomes higher than the power supply voltage Vcc, the potential of the contact CT2 increases until the junction field effect transistor TR42 is pinched off. When the potential of contact CT2, that is, the potential of gate electrode G41 becomes larger than the threshold voltage of N channel MOS transistor TR41, N channel MOS transistor TR41 is turned on, and n + type diffusion region 11 and p type diffusion region 3 become n + type diffusion region 12. And a short circuit via the contact CT1. With such a configuration, it is possible to prevent a forward bias voltage from being applied to the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11, so that a backflow current flows from the capacitor C to the power supply potential node NL 1. It can be prevented from flowing.

  Since other configurations and operations are the same as those of the semiconductor device according to the eighth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the tenth embodiment of the present invention, as compared with the semiconductor device 108 according to the eighth embodiment of the present invention, the resistance of the current path from the power supply potential node NL1 to the capacitor C is further increased. A value can be made small and a charging current can be efficiently supplied to a charge object element.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Eleventh embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the tenth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the tenth embodiment.

FIG. 16 is a circuit diagram showing a configuration of a semiconductor device according to the eleventh embodiment of the present invention.
Referring to FIG. 16, the semiconductor device 111 further includes a diode D41 as compared with the semiconductor device 110 according to the tenth embodiment of the present invention.

  Diode D41 is a Zener diode and has an anode connected to power supply potential node NL1 and a cathode connected to gate electrode G41. The diode D41 clamps the applied reverse voltage to a predetermined voltage value.

  With such a configuration, it is possible to prevent a transient overvoltage from being applied to the gate electrode G41 of the N channel MOS transistor TR41, and to prevent the gate breakdown of the N channel MOS transistor TR41.

  Since other configurations and operations are the same as those of the semiconductor device according to the tenth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the eleventh embodiment of the present invention, the charging current can be efficiently supplied to the charging target element, similarly to the semiconductor device according to the tenth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Twelfth embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the tenth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the tenth embodiment.

FIG. 17 is a circuit diagram showing a configuration of a semiconductor device according to the twelfth embodiment of the present invention.
Referring to FIG. 17, the semiconductor device 112 further includes a diode D42 as compared with the semiconductor device 110 according to the tenth embodiment of the present invention.

  The diode D42 is a Zener diode, and has an anode connected to the second end of the resistor R, that is, the p-type diffusion region 3, that is, the second end of the resistor R, and a cathode connected to the gate electrode G41. The diode D41 clamps the applied reverse voltage to a predetermined voltage value.

  With such a configuration, it is possible to prevent a transient overvoltage from being applied to the gate electrode G41 of the N channel MOS transistor TR41, and to prevent the gate breakdown of the N channel MOS transistor TR41.

  Since other configurations and operations are the same as those of the semiconductor device according to the tenth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the twelfth embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the tenth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Thirteenth embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the tenth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the tenth embodiment.

FIG. 18 is a circuit diagram showing a configuration of a semiconductor device according to the thirteenth embodiment of the present invention.
Referring to FIG. 18, the semiconductor device 113 further includes a diode D43 as compared with the semiconductor device 110 according to the tenth embodiment of the present invention.

  Diode D43 is a Schottky diode, and has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1. Diode D43 has a forward voltage smaller than the forward voltage of the pn junction formed by p-type diffusion region 3 and n + -type diffusion region 11.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a sudden rise in the potential Vb, and the potential of the contact CT1 becomes significantly higher than the power supply voltage Vcc, and a pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11 Since a forward bias voltage is applied to the capacitor C, a reverse current may flow from the capacitor C to the power supply potential node NL1.

  However, the semiconductor device according to the thirteenth embodiment of the present invention includes the diode D43 whose forward voltage is smaller than the forward voltage of the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11. With such a configuration, it is possible to prevent a forward bias voltage from being applied to the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11, so that a backflow current flows from the capacitor C to the power supply potential node NL 1. It can be prevented from flowing.

  Since other configurations and operations are the same as those of the semiconductor device according to the tenth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the thirteenth embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the tenth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fourteenth embodiment>
The present embodiment relates to a semiconductor device in which a current path from a power supply potential node NL1 to a capacitor C is added as compared with the semiconductor device according to the tenth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the tenth embodiment.

  FIG. 19 is a circuit diagram showing a configuration of a semiconductor device according to the fourteenth embodiment of the present invention. FIG. 20 is a sectional view showing a configuration of a semiconductor device according to the fourteenth embodiment of the present invention.

  19 and 20, semiconductor device 114 further includes a diode D51 as compared with semiconductor device 110 according to the tenth embodiment of the present invention.

  Diode D51 has an anode connected to power supply potential node NL1, and a cathode connected to contact CT2 and gate electrode G41.

  Junction field effect transistor TR42 has a drain connected to power supply potential node NL1 via diode D51, and thus supplies a charging current to capacitor C via n-type diffusion region 2.

  With such a configuration, the charging current supplied to the capacitor C is such that the charging current from the contact CT1 to the capacitor C by the hole injected from the p-type diffusion region 3 to the n-type diffusion region 2 and the contact CT11 by the NPN transistor TR31. To the capacitor C and the charging current from the contact CT2 to the capacitor C by the junction field effect transistor TR42.

  Since other configurations and operations are the same as those of the semiconductor device according to the tenth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the fourteenth embodiment of the present invention, as compared with the semiconductor device 110 according to the tenth embodiment of the present invention, the resistance of the current path from the power supply potential node NL1 to the capacitor C is further increased. A value can be made small and a charging current can be efficiently supplied to a charge object element.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fifteenth embodiment>
The present embodiment relates to a semiconductor device in which a transistor is added as compared with the semiconductor device according to the eighth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the eighth embodiment.

FIG. 21 is a circuit diagram showing a configuration of a semiconductor device according to the fifteenth embodiment of the present invention.
Referring to FIG. 21, the semiconductor device 115 further includes an N-channel MOS transistor TR61 as compared with the semiconductor device 108 according to the eighth embodiment of the present invention.

  N-channel MOS transistor TR61 has a drain connected to power supply potential node NL1, a source connected to the first electrode of capacitor C, and a gate connected to power supply potential node NL1.

FIG. 22 is a cross-sectional view showing the configuration of the semiconductor device according to the fifteenth embodiment of the present invention.
Referring to FIG. 22, the semiconductor device 115 further includes a gate electrode G61 and a gate insulating film GF61 as compared with the semiconductor device 108 according to the eighth embodiment of the present invention.

  N-channel MOS transistor TR61 is formed by a gate electrode G61 formed on the surface of p-type diffusion region 3 via gate insulating film GF61, a source formed by n-type diffusion region 2, and n + -type diffusion region 11. Drain. The gate electrode G61 is provided to face the channel region in the p-type diffusion region 3 sandwiched between the n-type diffusion region 2 and the n + -type diffusion region 11 with the gate insulating film GF61 interposed therebetween. N-channel MOS transistor TR 61 supplies a charging current to capacitor C through n-type diffusion region 2.

  When the potential Vb decreases and becomes lower than the power supply voltage Vcc, a positive bias voltage is applied to the gate electrode G61 by a voltage drop due to the current flowing through the resistor R. When this positive bias voltage becomes larger than the threshold voltage of N channel MOS transistor TR61, N channel MOS transistor TR61 is turned on, and N channel MOS transistor TR61 supplies a charging current to capacitor C through n-type diffusion region 2.

  With such a configuration, the charging current supplied to the capacitor C is such that the charging current from the contact CT1 to the capacitor C by the hole injected from the p-type diffusion region 3 to the n-type diffusion region 2 and the contact CT11 by the NPN transistor TR31. To the capacitor C and the charging current from the contact CT11 to the capacitor C by the N-channel MOS transistor TR61.

  Since other configurations and operations are the same as those of the semiconductor device according to the eighth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the fifteenth embodiment of the present invention, compared to the semiconductor device 108 according to the eighth embodiment of the present invention, the resistance of the current path from the power supply potential node NL1 to the capacitor C is further increased. A value can be made small and a charging current can be efficiently supplied to a charge object element.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Sixteenth Embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the fifteenth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the fifteenth embodiment.

FIG. 23 is a circuit diagram showing a configuration of a semiconductor device according to the sixteenth embodiment of the present invention.
Referring to FIG. 23, the semiconductor device 116 further includes a diode D61 as compared with the semiconductor device 115 according to the fifteenth embodiment of the present invention.

  Diode D61 is a Zener diode, and has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1. The diode D61 clamps the applied reverse voltage to a predetermined voltage value.

  With such a configuration, it is possible to prevent a transient overvoltage from being applied to the gate electrode G61 of the N channel MOS transistor TR61, and to prevent the gate breakdown of the N channel MOS transistor TR61.

  Since other configurations and operations are the same as those of the semiconductor device according to the fifteenth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the sixteenth embodiment of the present invention, a charging current can be efficiently supplied to the charging target element, similarly to the semiconductor device according to the fifteenth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Seventeenth embodiment>
The present embodiment relates to a semiconductor device in which a protection circuit is added as compared with the semiconductor device according to the sixteenth embodiment. Except for the contents described below, the semiconductor device is the same as that of the sixteenth embodiment.

FIG. 24 is a circuit diagram showing a configuration of the semiconductor device according to the seventeenth embodiment of the present invention.
Referring to FIG. 24, semiconductor device 117 further includes a diode D62 as compared with semiconductor device 116 according to the sixteenth embodiment of the present invention.

  Diode D62 is a Schottky diode, and has an anode connected to p-type diffusion region 3, that is, the second end of resistor R, and a cathode connected to power supply potential node NL1. Diode D62 has a forward voltage smaller than the forward voltage of the pn junction formed by p type diffusion region 3 and n + type diffusion region 11.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a sudden rise in the potential Vb, and the potential of the contact CT1 becomes significantly higher than the power supply voltage Vcc, and a pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11 Since a forward bias voltage is applied to the capacitor C, a reverse current may flow from the capacitor C to the power supply potential node NL1.

  However, the semiconductor device according to the seventeenth embodiment of the present invention includes the diode D62 whose forward voltage is smaller than the forward voltage of the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11. With such a configuration, it is possible to prevent a forward bias voltage from being applied to the pn junction formed by the p-type diffusion region 3 and the n + -type diffusion region 11, so that a backflow current flows from the capacitor C to the power supply potential node NL 1. It can be prevented from flowing.

  Since other configurations and operations are the same as those of the semiconductor device according to the sixteenth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the seventeenth embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the sixteenth embodiment of the present invention.

  In the semiconductor device according to the seventeenth embodiment of the present invention, by providing diodes D61 and D62 connected in parallel, gate breakdown of N channel MOS transistor TR61 can be prevented and power supply potential node NL1 is connected from capacitor C. It is possible to prevent a reverse current from flowing. The same applies to the semiconductor devices according to the sixth, seventh, twelfth and thirteenth embodiments of the present invention.

Although the semiconductor device according to the first to seventeenth embodiments of the present invention is configured to include the resistor R, the present invention is not limited to this. When the impurity concentration of the p-type diffusion region 3 is reduced to, for example, 1 × 10 ¹⁷ / cm ³ , electrons flowing from the n-type diffusion region 2 to the p-type diffusion region 3 can reach the contact CT1. Can relatively reduce the amount of holes injected from the p-type diffusion region 3 to the n-type diffusion region 2. Therefore, the semiconductor device can be configured without the resistor R. Further, when the resistor R can be dispensed with, for example, the diode D2 in the semiconductor device 102 according to the second embodiment of the present invention is dispensed with. That is, even if the semiconductor device does not include the diode D2, the potential of the contact CT1 can be prevented from becoming higher than the power supply voltage Vcc, and the avalanche between the n + type diffusion region 4 and the p diffusion region 3 can be prevented. Can be prevented from being triggered.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Eighteenth embodiment>
The present embodiment relates to a semiconductor device configured not to include the n + -type diffusion region 11 as compared with the semiconductor device according to the eighth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the eighth embodiment.

FIG. 25 is a cross-sectional view showing the configuration of the semiconductor device according to the eighteenth embodiment of the present invention.
Referring to FIG. 25, semiconductor device 118 does not include n + -type diffusion region 11 as compared with semiconductor device 108 according to the eighth embodiment of the present invention, and p + -type diffusion region (charge carrier movement limiting unit). 24 and a p-type diffusion region (charge carrier movement restricting portion) 25 instead of the p-type diffusion region 3.

P-type diffusion region 25 has an impurity concentration equal to or lower than a predetermined value at which charge carriers can move from n-type diffusion region 2 to node N4. For example, the impurity concentration of the p-type diffusion region 25 is as low as 1 × 10 ¹⁷ / cm ³ . With such a configuration, electrons flowing from the n-type diffusion region 2 to the p-type diffusion region 25 can reach the contact CT11. Therefore, the NPN transistor TR31 can be formed by the p-type diffusion region 25 and the n-type diffusion region 2. More specifically, the NPN transistor TR31 has a base and a collector formed by the p-type diffusion region 25, and an emitter formed by the n-type diffusion region 2. The NPN transistor TR31 supplies a charging current to the capacitor C through the n-type diffusion region 2.

  In this case, electrons flowing from the n-type diffusion region 2 to the p-type diffusion region 25 reach the contact CT11, so that the n-type diffusion region 2 is supplied from the power supply potential node NL1 via the contact CT11 and the p-type diffusion region 25. The amount of holes injected into the can can be relatively reduced. That is, the semiconductor device 118 limits the amount of holes injected from the power supply potential node NL1 into the n-type diffusion region 2 through the contact CT11 and the p-type diffusion region 25 even if the n + type diffusion region 11 is not provided. Can do.

  The p + -type diffusion region 24 is formed on the surface of the p-type diffusion region 25 with a space from the main surface of the p − -type substrate 1 and the n-type diffusion region 2. The p-type diffusion region 25 is connected to the contact CT1 through the p + type diffusion region 24. As described above, by providing the p + -type diffusion region 24 having an impurity concentration higher than that of the p-type diffusion region 25 between the p-type diffusion region 25 and the contact CT1, the n-type diffusion region 2 flows into the p-type diffusion region 25. Can be prevented from reaching the contact CT1.

  Further, by providing a p + type diffusion region 24 having an impurity concentration higher than that of the p type diffusion region 25 between the p type diffusion region 25 and the contact CT1, the contact CT1 and the p type diffusion region 25 are connected from the power supply potential node NL1. Thus, the amount of holes injected into the n-type diffusion region 2 can be limited. Therefore, the semiconductor device 118 may be configured not to include the resistor R.

  Further, even if the semiconductor device 118 does not include the p + -type diffusion region 24, the contact CT11, that is, the node N4 is connected to the contact CT3, that is, the node N1, as compared with the contact CT1, that is, the node N3 in the cross-sectional view of FIG. When the distance between the contacts CT1 and CT11 is set to a predetermined value or more, the electrons flowing from the n-type diffusion region 2 into the p-type diffusion region 25 reach the contact CT1 by setting the distance between the contacts CT1 and CT11. It can be prevented by internal resistance.

  Here, the drain of the high-voltage power semiconductor element TR101 is connected to a voltage of several hundred volts, for example. In this case, the potential Vs rapidly rises to several hundred V in 1 microsecond, for example, according to the switching operation of the high-voltage power semiconductor element TR101 and the low-voltage power semiconductor element TR102.

  For this reason, a displacement current flows through the resistor R due to a rapid rise in the potential Vb, and the potential of the contact CT1 becomes significantly higher than the power supply voltage Vcc.

  However, the semiconductor device according to the eighteenth embodiment of the present invention does not include the n + -type diffusion region 11. With such a configuration, it is not necessary to provide a Schottky diode as in the semiconductor device according to the ninth embodiment of the present invention. That is, in the semiconductor device according to the eighteenth embodiment of the present invention, since the pn junction is not formed between the p-type diffusion region 25 and the contact CT11, the potential of the contact CT1 is significantly higher than the power supply voltage Vcc. Even in this case, it is possible to prevent a reverse current from flowing from the capacitor C to the power supply potential node NL1.

  When semiconductor device 118 does not include n + type diffusion region 11, p type diffusion region 25 has node N4 coupled to power supply potential node NL1.

  Since other configurations and operations are the same as those of the semiconductor device according to the eighth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the eighteenth embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the eighth embodiment of the present invention.

  Although the semiconductor devices according to the first to eighteenth embodiments of the present invention are configured to include the resistor R, the present invention is not limited to this. When the electric resistance of the p-type diffusion region 3 can limit the amount of holes injected from the p-type diffusion region 3 to the n-type diffusion region 2, the semiconductor device does not include the resistor R. be able to. For example, in the cross-sectional view shown in FIG. 2, the p-type diffusion region 3 is formed to have a large length in the vertical direction on the paper surface, or the p-type diffusion region 3 is formed to have a small width in the vertical direction on the paper surface. It is possible to increase the electrical resistance of the current path from the region 3 to the p − type substrate 1. More specifically, for example, in the cross-sectional view shown in FIG. 2, the length of the p-type diffusion region 3 in the stacking direction of the n-type diffusion region 2 and the p-type diffusion region 3 is set to a predetermined value or more. The width of the p-type diffusion region 3 in the stacking direction of the 2 and p-type diffusion regions 3 is set to a predetermined value or less, thereby increasing the electric resistance of the current path from the p-type diffusion region 3 to the p-type substrate 1. Is possible.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Nineteenth embodiment>
The present embodiment relates to a semiconductor device having a configuration that does not include a resistor R as compared with the semiconductor device according to the tenth embodiment.

FIG. 26 is a cross-sectional view showing the configuration of the semiconductor device according to the nineteenth embodiment of the present invention.
Referring to FIG. 26, semiconductor device 119 does not include resistor R as compared with semiconductor device 110 according to the tenth embodiment of the present invention, and includes p-type diffusion region 26 instead of p-type diffusion region 3. A contact CT12.

  The p-type diffusion region 26 has an electric resistance that can limit the amount of holes injected from the p-type diffusion region 26 to the n-type diffusion region 2. For example, as described above, in the cross-sectional view shown in FIG. 26, the length of the p-type diffusion region 26 in the stacking direction of the n-type diffusion region 2 and the p-type diffusion region 26 is set to a predetermined value or more. By forming the width of the p-type diffusion region 26 in the stacking direction of the region 2 and the p-type diffusion region 26 to be equal to or less than a predetermined value, the electric resistance of the current path from the p-type diffusion region 26 to the p − type substrate 1 is reduced. It can be enlarged. With such a configuration, it is possible to reduce the power loss of the power supply that supplies the power supply voltage Vcc.

  Further, by providing the n + -type diffusion region 11 and the n + -type diffusion region 12 with a predetermined length or more therebetween, the internal resistance of the p-type diffusion region 26 can be reduced by the resistance R between the drain and source of the N-channel MOS transistor TR 41 in the semiconductor device 110. Instead of

  The contact CT12 is connected to the p-type diffusion region 26 and provided at a position close to the n + -type diffusion region 11. The contact CT12 is provided opposite to the contact CT1 connected to the n + type diffusion region 12 with the contact CT11 connected to the n + type diffusion region 11 interposed therebetween. With such a configuration, the internal resistance of p-type diffusion region 26 can be short-circuited when N-channel MOS transistor TR41 is on.

  Since other configurations and operations are the same as those of the semiconductor device according to the tenth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the nineteenth embodiment of the present invention, a charging current can be efficiently supplied to the charging target element, similarly to the semiconductor device according to the tenth embodiment of the present invention.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<20th Embodiment>
The present embodiment relates to a semiconductor device having a configuration that does not include a resistor R as compared with the semiconductor device according to the first embodiment.

FIG. 27 is a cross-sectional view showing the configuration of the semiconductor device according to the twentieth embodiment of the present invention.
Referring to FIG. 27, semiconductor device 120 does not include resistor R and further includes p + -type diffusion region (charge carrier movement limiting unit) 27 as compared with semiconductor device 101 according to the first embodiment of the present invention. Prepare.

  The p + type diffusion region 27 is formed on the surface of the p type diffusion region 3 at a distance from the main surface of the p − type substrate 1 and the n type diffusion region 2. The p-type diffusion region 3 is connected to the contact CT1 through the p + -type diffusion region 27. Thus, by arranging p + type diffusion region 27 having an impurity concentration higher than that of p type diffusion region 25 between p type diffusion region 3 and contact CT1, contact CT1 and p type diffusion region are provided from power supply potential node NL1. The amount of holes injected into the n-type diffusion region 2 through 3 can be limited.

  Since other configurations and operations are the same as those of the semiconductor device according to the first embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the twentieth embodiment of the present invention, a charging current can be efficiently supplied to the charge target element, similarly to the semiconductor device according to the first embodiment of the present invention.

Although the semiconductor device 120 according to the twentieth embodiment of the present invention is configured to include the p + -type diffusion region 27, the present invention is not limited to this. Even if the semiconductor device 120 does not include the p + -type diffusion region 27, the configuration including the p-type diffusion region having a low impurity concentration of, for example, 1 × 10 ¹⁷ / cm ³ instead of the p-type diffusion region 3, allows the n-type Electrons flowing from the diffusion region 2 into the p-type diffusion region can reach the contact CT1. Therefore, the amount of holes injected from power supply potential node NL1 into n-type diffusion region 2 via contact CT1 and p-type diffusion region can be relatively reduced.

  Moreover, although the semiconductor devices according to the first to twentieth embodiments of the present invention have the cross-sectional structures shown in the corresponding cross-sectional views, the present invention is not limited to this. The relationship of the conductivity type between the semiconductor layer and each semiconductor region, that is, the relationship between p-type and n-type may be reversed. In this case, for example, in the semiconductor device according to the first embodiment of the present invention, power supply voltage Vcc is a negative voltage, the cathode of diode D1 is connected to power supply potential node NL1, and the anode is connected to contact CT2.

  Moreover, although the semiconductor devices according to the first to twentieth embodiments of the present invention have the cross-sectional structures shown in the corresponding cross-sectional views, the present invention is not limited to this. Each diffusion region may be stacked in a horizontal direction, or the semiconductor device may be formed of discrete components.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 p− type substrate (semiconductor layer), 2 n type diffusion region (first semiconductor region), 3, 6 p type diffusion region (second semiconductor region), 4, 5, 7, 8, 12 n + type diffusion Region, 11 n + type diffusion region (charge carrier movement restriction unit), 21-23 p + type diffusion region, 24, 27 p + type diffusion region (charge carrier movement restriction unit), 25 p type diffusion region (charge carrier movement restriction unit) , 51 High-voltage side drive circuit, 52 Low-voltage side drive circuit, 101-120 semiconductor device, 201 drive device, 202 power converter, T1 power supply voltage terminal, T2 reference voltage terminal, TR1 PNP transistor, TR2, TR42 junction type field effect transistor , TR11, TR31 NPN transistor, TR51, TR53 P-channel MOS transistor, TR21, TR41, TR52, TR54, R61 N channel MOS transistor, TR101 high voltage side power semiconductor element, TR102 low voltage side power semiconductor element, C capacitor (element to be charged), D1, D2, D11, D21, D22, D31, D41 to D43, D51, D61, D62 diode , R resistance (charge carrier movement limiting part), CT1 to CT7, CT11, CT12 contact, G1, G2, G21, G41, G61 gate electrode, GF1, GF2, GF21, GF41, GF61 gate insulating film, F oxide film, N1 ~ N4 node, NL1, NL2 power supply potential node, NG1-NG3 ground potential node, HV high voltage node.

Claims (22)

A semiconductor device for supplying a charging current to an element to be charged,
A first conductivity type semiconductor layer;
A first semiconductor region having a first node coupled to a first electrode of the device to be charged and formed on a main surface of the semiconductor layer;
A first conductivity type first node having a second node and a third node coupled to a power supply potential node to which a power supply voltage is supplied and formed at a surface of the first semiconductor region and spaced from the semiconductor layer. Two semiconductor regions;
A semiconductor device comprising: a charge carrier movement limiting unit that limits movement of charge carriers from the second node and the third node to the semiconductor layer.   The semiconductor device according to claim 1, wherein the charge carrier movement limiting unit includes a resistor connected between the power supply potential node and the second node.   The charge carrier movement limiting portion is formed on the surface of the second semiconductor region at a distance from the first semiconductor region, has the second node, and has an impurity concentration higher than that of the second semiconductor region. The semiconductor device according to claim 1, comprising a first conductivity type semiconductor region. The charge carrier movement restriction unit includes the second semiconductor region,
The semiconductor device according to claim 1, wherein the second semiconductor region has an impurity concentration equal to or lower than a predetermined value at which charge carriers can move from the first semiconductor region to the third node. The charge carrier movement restriction unit includes the second semiconductor region,
The length of the second semiconductor region in the stacking direction of the first semiconductor region and the second semiconductor region is a predetermined value or more, or the length of the first semiconductor region and the second semiconductor region is The semiconductor device according to claim 1, wherein a width in the stacking direction is a predetermined value or less.   The charge carrier movement restricting portion is formed on the surface of the second semiconductor region at a distance from the first semiconductor region, and includes a fourth semiconductor region of a second conductivity type having the third node. Item 14. A semiconductor device according to Item 1. The semiconductor device includes:
A first transistor having a first conduction electrode formed by the semiconductor layer, a control electrode formed by the first semiconductor region, and a second conduction electrode formed by the second semiconductor region;
2. The semiconductor device according to claim 1, comprising: a first conduction electrode formed by the first semiconductor region; and a second transistor having a control electrode and a second conduction electrode formed by the second semiconductor region. . The semiconductor device further includes:
A first conductivity type electrode coupled to the second semiconductor region; and a second conductivity type electrode coupled to the power supply potential node, wherein a forward voltage is applied to the second semiconductor region and the fourth semiconductor region. The semiconductor device according to claim 6, further comprising a diode smaller than a forward voltage between the semiconductor regions. The first semiconductor region further includes a fourth node;
The semiconductor device further includes:
A third semiconductor region of a second conductivity type having the second node and formed on the surface of the second semiconductor region and spaced from the first semiconductor region;
A fourth semiconductor region of the second conductivity type having the third node and formed on the surface of the second semiconductor region and spaced apart from the first semiconductor region and the third semiconductor region; ,
A control electrode formed on the surface of the second semiconductor region via an insulating film and coupled to the fourth node, a first conduction electrode formed by the third semiconductor region, and the fourth A third transistor having a second conduction electrode formed by the semiconductor region;
And a fourth transistor having a control electrode formed by the first semiconductor region and the second semiconductor region, and a first conduction electrode and a second conduction electrode formed by the first semiconductor region. The semiconductor device according to claim 7.   The semiconductor device according to claim 9, wherein the charge carrier movement restriction unit includes a resistor connected between the power supply potential node and the second semiconductor region and the third semiconductor region. The semiconductor device further includes:
A first conductivity type electrode coupled to the power supply potential node; and a second conductivity type electrode coupled to the control electrode of the third transistor, wherein the applied reverse voltage is clamped to a predetermined voltage value. The semiconductor device according to claim 9, further comprising a diode. The semiconductor device further includes:
A first conductivity type electrode coupled to the second semiconductor region; and a second conductivity type electrode coupled to a control electrode of the third transistor, wherein an applied reverse voltage is set to a predetermined voltage value. The semiconductor device according to claim 9, further comprising a diode for clamping. The semiconductor device further includes:
A first conductivity type electrode coupled to the second semiconductor region; and a second conductivity type electrode coupled to the power supply potential node, wherein a forward voltage is applied to the second semiconductor region and the fourth semiconductor region. The semiconductor device according to claim 9, further comprising a diode smaller than a forward voltage between the semiconductor regions. The semiconductor device further includes:
The semiconductor device according to claim 9, further comprising a diode having a first conductivity type electrode coupled to the power supply potential node and a second conductivity type electrode coupled to a control electrode of the third transistor. The semiconductor device further includes:
A control electrode formed on the surface of the second semiconductor region via an insulating film and coupled to the power supply potential node, a first conduction electrode formed by the first semiconductor region, and the fourth The semiconductor device according to claim 7 , further comprising a fifth transistor having a second conduction electrode formed by the semiconductor region. The semiconductor device further includes:
A first conductivity type electrode coupled to the second semiconductor region; and a second conductivity type electrode coupled to a control electrode of the second transistor, wherein the applied reverse voltage is set to a predetermined voltage value. The semiconductor device according to claim 15, further comprising a diode for clamping. The semiconductor device further includes:
A fourth semiconductor region of a second conductivity type having the third node and formed on the surface of the second semiconductor region and spaced apart from the first semiconductor region;
A first conductivity type electrode coupled to the second semiconductor region; and a second conductivity type electrode coupled to a control electrode of the second transistor, wherein a forward voltage is applied to the second semiconductor region and The semiconductor device according to claim 15, further comprising a diode having a smaller forward voltage between the fourth semiconductor regions. The first electrode of the element to be charged is a power supply voltage of a drive circuit that supplies a voltage to a control electrode of the high-voltage power semiconductor element among the high-voltage power semiconductor element and the low-voltage power semiconductor element connected in series. Connected to the terminal,
A second electrode of the charge target element is connected to a reference voltage terminal of the drive circuit;
The semiconductor device according to claim 1, wherein a reference voltage terminal of the drive circuit is connected to a connection point of the high-voltage power semiconductor element and the low-voltage power semiconductor element. A semiconductor device for supplying a charging current to an element to be charged,
A resistor having a first end coupled to a power supply potential node to which a power supply voltage is supplied;
A first conduction electrode is coupled to the second end of the resistor, a second conduction electrode is coupled to a ground potential node to which a ground voltage is supplied, and a control electrode is coupled to the first electrode of the charging target element. Transistors
A second transistor having a first conduction electrode coupled to the power supply potential node, a second conduction electrode coupled to the first electrode of the charge target element, and a control electrode coupled to a second end of the resistor. Semiconductor device. The semiconductor device further includes:
A fourth transistor having a first conduction electrode coupled to the power supply potential node and a second conduction electrode coupled to a second end of the resistor;
A first conduction electrode is coupled to the control electrode of the fourth transistor, a second conduction electrode is coupled to the first electrode of the charging target element, and a control electrode is coupled to the second end of the resistor. 20. The semiconductor device according to claim 19 , further comprising a transistor. The semiconductor device further includes:
The semiconductor device according to claim 19, further comprising: a sixth transistor in which a first conduction electrode and a control electrode are coupled to the power supply potential node, and a second conduction electrode is coupled to the first electrode of the charging target element. The first electrode of the element to be charged is a power supply voltage of a drive circuit that supplies a voltage to a control electrode of the high-voltage power semiconductor element among the high-voltage power semiconductor element and the low-voltage power semiconductor element connected in series. Connected to the terminal,
A second electrode of the charge target element is connected to a reference voltage terminal of the drive circuit;
The semiconductor device according to claim 19 , wherein a reference voltage terminal of the drive circuit is connected to a connection point of the high-voltage power semiconductor element and the low-voltage power semiconductor element.

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