JP5545067B2 - Information processing apparatus and self-diagnosis method of information processing apparatus - Google Patents

Description

  The present invention relates to an information processing apparatus having a plurality of arithmetic processing means such as a CPU (Central Processing Unit) and the like and capable of executing the same arithmetic processing redundantly by the plurality of arithmetic processing means, and a self-diagnosis method thereof.

  In recent years, information processing apparatuses (computers) having a plurality of arithmetic processing means such as CPUs have been widely used. In this type of information processing apparatus, it is possible to execute different contents of processing in parallel by a plurality of arithmetic processing means, but the same processing is redundantly executed by a plurality of arithmetic processing means, and the arithmetic processing By comparing the results, it can be detected that any of the arithmetic processing means has fallen into a failure state, and the reliability of the arithmetic processing results can be improved.

  In particular, when used as a control device for controlling a moving body such as a facility such as a plant or a vehicle, a ship, or an aircraft, there is a high demand for the reliability of the arithmetic processing result. It is expensive. In addition, such a requirement for reliability of the calculation processing result is similarly generated in a general personal computer for home use in recent years when the use of computers is expanding.

  The following are disclosed as techniques for comparing the results of arithmetic processing by a plurality of arithmetic processing means.

  Patent Document 1 describes a failure detection device that detects a failure in operation mismatch by causing a plurality of microprocessors to operate synchronously, code-compressing the bus output of each microprocessor, and comparing the compressed data.

  In Patent Document 2, a plurality of CPUs perform the same processing, a check code is added to the output data of each CPU, the result is output to a memory, and the check code is the same among the plurality of output data output to the memory And a collation system that detects an error in CPU output by comparing and collating the entire extracted output data.

  The techniques described in these documents are aimed at reducing the amount of comparison / collation data or the transfer amount.

JP-A-5-324391 JP 2010-9327 A

  However, in the device described in the above-mentioned conventional patent document 1, there is a possibility that comparison / collation is erroneous by comparing compressed data.

  The possibility of erroneous comparison and collation in the encoded data has been pointed out, for example, in the “Free Encyclopedia“ Wikipedia: Hash Function ”” on the Internet. The hash function is one of methods for encoding data, but the Internet site points out the possibility that it is difficult to obtain two input values that give the same hash value.

  Such a phenomenon is likely to occur when the number of encoded data bits (number of encoded bits) is small. Similarly, as the compressed data is compressed, the difference in the original data is buried and the possibility of overlooking the failure increases. In the above-mentioned patent document 1, although such a problem exists, no consideration is given to how far the compression is performed.

  Further, in the system described in Patent Document 2, the amount of data output from the CPU to the memory itself is not reduced, and the transmission load and transmission time from the CPU to the memory cannot be reduced. Furthermore, since the comparison of the entire output data is performed after extracting the check code that matches, the amount of comparison verification data cannot be reduced.

  The present invention is for solving such problems, and provides an information processing apparatus and a self-diagnosis method for reducing the amount of data transmission and data comparison for self-diagnosis and maintaining reliability. The main purpose is to provide it.

In order to achieve the above object, the first aspect of the present invention provides:
An information processing apparatus comprising a plurality of arithmetic processing means connected in communication, wherein the plurality of arithmetic processing means can execute the same arithmetic processing synchronously,
An encoding method selecting means for selecting one encoding method having an error probability less than a set value from a plurality of encoding methods;
When the plurality of arithmetic processing means synchronously execute the same arithmetic processing, the information including the arithmetic processing result by the plurality of arithmetic processing means is encoded by the encoding technique selected by the encoding technique selecting means. Encoding means for
A determination unit that compares information encoded by the plurality of encoding units and determines whether the plurality of arithmetic processing units are operating normally;
Is an information processing apparatus.

  According to the first aspect of the present invention, the encoding method selecting unit that selects one encoding method having an error probability less than the set value from a plurality of encoding methods is provided, and the plurality of arithmetic processing units are the same. When performing the above-mentioned arithmetic processing synchronously, information including the results of arithmetic processing by a plurality of arithmetic processing means is encoded by the encoding method selected by the encoding method selection means, so that data transmission for self-diagnosis The amount of data and the amount of data comparison can be reduced and the reliability can be maintained.

In the first aspect of the present invention,
The encoding method selection means may be a means for selecting an encoding method having the smallest number of encoding bits from among the encoding methods having the error probability less than a set value.

  In this way, the data transmission amount and data comparison amount for self-diagnosis can be kept to a minimum within a range in which reliability is maintained.

In the first aspect of the present invention,
The set value is calculated, for example, as a value obtained by multiplying the CPU required safety level set as a parameter by a sign error ratio and further dividing the number of comparisons per time by the determination means.

In the first aspect of the present invention,
The encoding method selection means calculates the minimum number of encoded bits based on the logarithmic value of the set value, and selects an encoding method in which the number of encoded bits exceeds the calculated minimum number of encoded bits, It may be a means for selecting an encoding method having an error probability less than a set value.

The second aspect of the present invention is:
A self-diagnosis method for an information processing apparatus comprising a plurality of arithmetic processing means connected in communication, wherein the plurality of arithmetic processing means can execute the same arithmetic processing synchronously,
An encoding method selection step of selecting one encoding method having an error probability less than a set value from a plurality of encoding methods;
When the plurality of arithmetic processing means synchronously execute the same arithmetic processing, the information including the arithmetic processing result by the plurality of arithmetic processing means is encoded by the encoding technique selected by the encoding technique selecting means. An encoding step to
A determination step of comparing the information encoded in the encoding step to determine whether or not the plurality of arithmetic processing means are operating normally;
It is a self-diagnosis method of information processing apparatus provided with.

  According to the second aspect of the present invention, there is provided an encoding method selection step of selecting one encoding method having an error probability less than a set value from a plurality of encoding methods, and the plurality of arithmetic processing means are the same. Data transmission for self-diagnosis to encode information including the results of arithmetic processing by a plurality of arithmetic processing means by the encoding method selected in the encoding method selection step when the arithmetic processing is executed synchronously. The amount of data and the amount of data comparison can be reduced and the reliability can be maintained.

In a second aspect of the invention,
In the encoding method selection step, an encoding method having the smallest number of encoded bits may be selected from among the encoding methods having the error probability less than a set value.

  In this way, the data transmission amount and data comparison amount for self-diagnosis can be kept to a minimum within a range in which reliability is maintained.

In the second aspect of the present invention,
There may be further provided a setting value calculating step of calculating the setting value as a value obtained by multiplying the CPU required safety level set as a parameter by a sign error ratio and dividing the number of comparisons per time in the determination step .

In the second aspect of the present invention,
In the encoding method selection step, a minimum number of encoded bits is calculated based on a logarithmic value of the set value, and an encoding method having a larger number of encoded bits than the calculated minimum number of encoded bits is selected. The encoding method having an error probability less than a set value may be selected.

  According to the present invention, it is possible to provide an information processing apparatus and a self-diagnosis method thereof that can simultaneously reduce the amount of data transmission and data comparison for self-diagnosis and maintain reliability.

1 is a system configuration example of an information processing apparatus 1 according to an embodiment of the present invention. It is a figure which shows code error probability table 20 # A, 20 # B. It is a figure which shows management table 30 # A, 30 # B. It is a time chart which shows the order of the process etc. which are repeatedly performed by each functional block. It is a flowchart which shows the flow of the encoding method selection process performed by encoding method selection part 25 # A and 25 # B. It is a flowchart which shows the flow of the CPU calculation data collection process performed by CPU calculation data collection process part 35 # A, 35 # B. It is a figure which shows typically the data read from calculation data storage part 15 # A and 15 # B by CPU calculation data collection process part 35 # A, 35 # B, and managed as continuous data. It is a flowchart which shows the flow of the encoding process performed by encoding process part 40 # A and 40 # B. It is a flowchart which shows the flow of the transmission process performed by transmission process part 45 # A, 45 # B. It is a flowchart which shows the flow of the comparison / determination process performed by comparison / determination process part 55 # A, 55 # B.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

  Hereinafter, an information processing apparatus and a self-diagnosis method thereof according to an embodiment of the present invention will be described with reference to the drawings. The information processing apparatus of the present invention has a basic configuration of a computer including a plurality of arithmetic processing means such as a multi-processor device and a multi-core processor.

  The plurality of arithmetic processing means can execute the same arithmetic processing synchronously. In the information processing apparatus of the present invention, it is possible to detect a failure in the arithmetic processing means by encoding and transmitting data including the calculation result and comparing the encoded data. Hereinafter, such failure detection is referred to as “self-diagnosis”.

[Basic configuration]
FIG. 1 is a system configuration example of an information processing apparatus 1 according to an embodiment of the present invention. The information processing apparatus 1 includes a CPU #A and a CPU #B. The same clock signal is supplied to CPU #A and CPU #B, and the same arithmetic processing can be executed synchronously. The clock signal generator may belong to any of the CPUs. Although CPU #A and CPU #B are connected for communication, there is no particular limitation on communication modes such as wired / wireless, serial communication / multiplex bus, frequency band, modulation method, and the like.

  The CPU #A includes an arithmetic processing unit 10 # A, an arithmetic data storage unit 15 # A, a code error probability table 20 # A, an encoding technique selection unit 25 # A, a management table 30 # A, and a CPU calculation A data collection processing unit 35 # A, an encoding processing unit 40 # A, a transmission processing unit 45 # A, an encoded data storage unit 50 # A, and a comparison / determination processing unit 55 # A are provided.

  Similarly, the CPU #B includes an arithmetic processing unit 10 # B, an arithmetic data storage unit 15 # B, a code error probability table 20 # B, an encoding technique selection unit 25 # B, and a management table 30 # B. CPU calculation data collection processing unit 35 # B, encoding processing unit 40 # B, transmission processing unit 45 # B, encoded data storage unit 50 # B, and comparison / determination processing unit 55 # B. Prepare.

  It should be noted that functional blocks to which the same numerals are attached have basically the same functions regardless of whether “#A” or “#B” indicating which CPU belongs to.

  Among the functional blocks of the CPUs #A and #B, the operation data storage units 15 # A and 15 # B, the encoding error tables 20 # A and 20 # B, the management tables 30 # A and 30 # B, and the encoding The data storage units 50 # A and 50 # B are storage areas constructed in a RAM (Random Access Memory), a flash memory, a register, etc. (not shown).

  The arithmetic processing units 10 # A and 10 # B include, for example, an ALU (Arithmetic Logic Unit), an FPGA (Field Programmable Gate Array), and the like. Arithmetic processing units 10 # A and 10 # B execute various arithmetic processes according to instructions fetched from the program memory under the control of an OS (Operating System) (not shown). This command is a command for a task that should be executed by the information processing apparatus 1, and is different from a command related to self-diagnosis. As described above, the arithmetic processing units 10 # A and 10 # B synchronously execute the same arithmetic processing.

  Here, the same arithmetic processing includes diversity (diversification) and includes the same input / output relationship, but includes arithmetic processing with different algorithms, programming languages, compilers, compiler parameters, and the like.

  The calculation target values, calculation parameters, and calculation results (hereinafter referred to as input state, status data, and output state as necessary) of the calculation processing units 10 # A and 10 # B are stored in the calculation data storage unit 15 # A, 15 # B.

[Parameters for selecting the encoding method]
The code error probability tables 20 # A and 20 # B include a request code error probability table and a coding operation function error probability table. FIG. 2 is a diagram illustrating the code error probability tables 20 # A and 20 # B.

  The request code error probability table stores the CPU request safety level, the code error ratio, and the number of comparisons per second. These parameters are a group of parameters for calculating a required code error probability (required value of the probability that the same data is obtained by encoding and the failure is overlooked even though the original data does not match). The request code error probability corresponds to a “set value” in the claims.

  Each parameter is read from, for example, an EEPROM (Electrically Erasable and Programmable Read Only Memory) or a ROM (Read Only Memory) when the information processing apparatus 1 is activated, and stored in the request code error probability table. The code error probability tables 20 # A and 20 # B themselves may be storage areas on the EEPROM or the ROM.

  The parameters stored in the request code error probability table may be changeable by the user.

  In the example of FIG. 2, the CPU required safety level is exemplified as 10 to the eighth power, but the numerical value corresponds to “SIL (Safety Integrity Level) 3” in the safety level of the CPU system. This numerical value is an example in which the required safety level is relatively high. If the required safety level is low, a larger value (for example, 10 to the sixth power) may be set. The case where the required safety level is high is, for example, a case where it is used as a control device for a facility such as a plant or a moving body, and the case where the required safety level is low is, for example, a personal computer for home use. This is a case where it is used as a game machine. Further, when used as a control device for controlling a nuclear power plant or the like, the required safety level may be further increased (the CPU required safety level is a smaller value). As described above, the information processing apparatus 1 according to the present embodiment can set the safety level required for the value according to the application, and therefore selects an optimal encoding method at the time of encoding processing to be described later. be able to.

  The safety level of the CPU system is described in, for example, “IEC61508 FUNCTIONAL SAFETY OF ELECTRICAL / ELECTRONIC / PROGRAMMABLE ELECTRONIC SAFETY-RELATED SYSTEMS”.

  The code error ratio is a ratio shown in the CPU required safety degree of the probability that a verification error occurs due to encoding. The number of comparisons per second is the number of times per second for comparing encoded data.

  On the other hand, the encoding operation function error probability table includes an encoding operation function that can be selected by the information processing apparatus 1 according to the present embodiment, the number of bits after encoding (hereinafter referred to as “the number of encoding bits”), Specifies the expected error probability. As shown in FIG. 2, the error probability assumed when each encoding operation function is selected is a power of 2 (the number of minus encoded bits). This is described in, for example, “Val Henson, Richard Henderson,“ Guidelines for Using Compare-by-hash ”, Originally Appeared in HotOS 2003 (2003)”.

  In the present embodiment, HMAC (Keyed-Hashing for Message Authentication code), MD4, and SHA1 (Secure Hash Algorithm 1) can be selected as the encoding operation function. These are all arithmetic functions using a hash function. Thus, the encoding operation function registered in the encoding operation function error probability table is selected in consideration of the number of encoding bits, the operation speed, the amount of memory used, and the like.

  Note that selecting any one of the encoding operation functions corresponds to “selecting an encoding method” in the claims.

[Selection of encoding method]
The encoding method selection units 25 # A and 25 # B obtain the optimum encoding operation function from the encoding operation function error probability table based on the parameters stored in the code error probability tables 20 # A and 20 # B, respectively. The selected encoding operation function is stored in the encoding operation function tables of the management tables 30 # A and 30 # B. The selection method will be described below.

  The encoding method selection units 25 # A and 25 # B calculate the minimum number of encoded bits based on the following equation (1). Then, an encoding operation function having the smallest number of encoded bits is selected from among the encoding operation functions having the number of encoded bits exceeding the minimum number of encoded bits. In the following formula (1), “Log” is, for example, a common logarithm.

(Minimum encoding bit number) = − Log (Request code error probability) ÷ Log 2
= −Log {(CPU required safety level) × (sign error ratio)} ÷ {(number of comparisons per second) × 3600} ÷ Log2 (1)

  As a result, an encoding operation function having the smallest number of encoded bits is selected from among the encoding operation functions whose expected error probability is less than the required code error probability (FIG. 2 and the following equation (2) ) And (3)). Expression (3) is a modification of the above expression (1). As can be seen from FIG. 2 and equations (2) and (3), when the number of encoded bits exceeds the minimum number of encoded bits, the assumed error probability is smaller than the required code error probability.

(Probable error probability) = 2 ^ {-(number of encoded bits)} (2)
(Requested code error probability) = 2 ^ {-(the minimum number of encoded bits)} (3)

  Thus, the reliability of the arithmetic processing is ensured by selecting an encoding arithmetic function that satisfies the required error probability (the assumed error probability is smaller than the required encoding error probability). Further, by selecting a coding operation function that satisfies the required error probability and having the smallest number of coding bits, it is possible to minimize the amount of data transmission and data comparison between CPUs to be described later. it can.

  When the value of FIG. 2 is applied to the above equation (1), the minimum number of encoded bits is calculated as the following equation (4).

(Minimum number of encoded bits) = − Log {(10 ^ −8) × (10 ^ −3) ÷ (10 × 3600)} ÷ Log2
≒ 16 ÷ 0.3
≒ 54 (4)

  In this case, if an encoding operation function having an encoding bit number exceeding 54 bits is selected, the assumed error probability becomes smaller than the required encoding error probability. In the example of FIG. 2, since the number of encoded bits is greater than 54 for any of the encoding operation functions, the HMAC having the minimum number of encoded bits is selected.

[Calculation data collection-encoding-comparison / judgment processing]
The CPU calculation data collection processing units 35 # A and 35 # B are operated by the calculation processing units 10 # A and 10 # stored in the calculation data storage units 15 # A and 15 # B according to the management tables 30 # A and 30 # B. The input state, status data, and output state of B are collected and output to the encoding processing units 40 # A and 40 # B (a storage unit for transfer may be sandwiched therebetween).

  FIG. 3 is a diagram showing the management tables 30 # A and 30 # B. As shown in the figure, in the management tables 30 # A and 30 # B, calculation data storage units 15 # A and 15 # in which the input states, status data, and output states of the calculation processing units 10 # A and 10 # B are stored. A CPU calculation data collection table in which the address of B and the number of data bytes are defined, and an encoding calculation in which an encoding calculation function (or an identifier thereof) selected by the encoding method selection units 25 # A and 25 # B is stored Function table.

  The encoding processing units 40 # A and 40 # B use the arithmetic operation units 10 # A and 10 # B by using the encoding arithmetic function stored in the encoding arithmetic function table of the management tables 30 # A and 30 # B. The input state, status data, and output state are encoded. The encoded data (hereinafter referred to as encoded data) is stored in the encoded data storage units 50 # A and 50 # B and is output to the transmission processing units 45 # A and 45 # B. Since details of the encoding process using the encoding function are known, various descriptions are omitted.

The transmission processing units 45 # A and 45 # B are, for example, safety communication standards such as IEC61784-3 and IEC622.
According to the requirement such as 80, the encoded data is transmitted to the other CPU. The transmission processing units 45 # A and 45 # B store the encoded data received from the other CPU in the encoded data storage units 50 # A and 50 # B. Considering the error rate of communication data, a safety code such as CRC is added as necessary.

  The comparison / determination processing units 55 # A and 55 # B compare the encoded data by the own CPU stored in the encoded data storage units 50 # A and 50 # B with the encoded data received from the other CPU. Whether any CPU or its peripheral device is in a failure state is determined. In this embodiment, since processing is performed by two CPUs, it is difficult to specify a failed CPU. When a failure is detected, both CPUs are reset or stopped, but three or more CPUs are provided. In some cases, it is possible to identify the failed CPU by performing a process such as majority vote.

[Time chart]
FIG. 4 is a time chart showing the order of processes repeatedly executed by each functional block described above. In this figure, time is plotted on the horizontal axis. As shown in the figure, first, the CPUs #A and #B execute input, calculation, and output processing synchronously by the calculation processing units 10 #A and 10 #B. Such processing is executed by the information processing apparatus 1 as an original task (when used as a control apparatus, a control calculation or the like).

  Next, CPU calculation data collection processing units 35 # A and 35 # B perform CPU calculation data collection processing ((a) in the figure), and encoding processing units 40 # A and 40 # B perform encoding processing. ((B) in the figure), the transmission processing units 45 # A and 45 # B perform transmission processing ((c) in the figure), and finally the comparison / determination processing units 55 # A and 55 # B perform comparison. A determination process is performed ((d) in the figure).

  When these are completed, the input, calculation, and output processes by the calculation processing units 10 # A and 10 # B are started again, and repeated with a certain processing cycle (for example, about 100 [ms]), and the input, calculation, and output processes are started. Comparison / determination processing is executed. This processing cycle is controlled, for example, by the count register 70 counting the rising edge of the clock signal.

[Processing flow for self-diagnosis]
Hereinafter, the flow of processing executed by each functional block will be described.

  FIG. 5 is a flowchart showing the flow of the encoding method selection process executed by the encoding method selection units 25 # A and 25 # B. This flow is started when the information processing apparatus 1 is activated or when the parameters stored in the request code error probability tables of the code error probability tables 20 # A and 20 # B are changed. Note that the change of the parameter stored in the request code error probability table may be designed to be notified by a software interrupt when the change is made, or the coding method selection unit 25 # A. 25 # B may be detected by polling at an appropriate period.

  First, the encoding method selection units 25 # A and 25 # B read parameters stored in the request code error probability table (S100).

  Next, the minimum number of encoded bits is calculated as described above (S102), and the encoding operation function having the smallest number of encoded bits is selected from among the encoding operation functions in which the number of encoded bits exceeds the minimum number of encoded bits. Select (S104).

  Then, the selected encoding operation function is stored in the encoding operation function tables of the management tables 30 # A and 30 # B (S106).

  FIG. 6 is a flowchart showing the flow of CPU calculation data collection processing executed by the CPU calculation data collection processing units 35 # A and 35 # B. This flow is started at the timing when the input, calculation, and output processes by the calculation processing units 10 # A and 10 # B are completed, as described in the above time chart.

  First, the CPU calculation data collection processing units 35 # A and 35 # B receive the addresses and data bytes of the calculation data storage units 15 # A and 15 # B from the CPU calculation data collection table of the management tables 30 # A and 30 # B. The number is read (S200).

  Then, the input state, status data, and output state of the arithmetic processing units 10 # A and 10 # B stored in the arithmetic data storage units 15 # A and 15 # B are read and managed as continuous data (S202). The managed data is output to the encoding processing units 40 # A and 40 # B as described above.

  FIG. 7 is a diagram schematically illustrating data read from the calculation data storage units 15 # A and 15 # B by the CPU calculation data collection processing units 35 # A and 35 # B and managed as continuous data. By performing the encoding process on such continuous data, the time required for the encoding process can be shortened.

  FIG. 8 is a flowchart showing the flow of encoding processing executed by the encoding processing units 40 # A and 40 # B. This flow is started at the timing when the CPU calculation data collection processing by the CPU calculation data collection processing units 35 # A and 35 # B is completed.

  First, the encoding processing units 40 # A and 40 # B read encoding operation functions from the encoding operation function tables of the management tables 30 # A and 30 # B (S300).

  Next, continuous data input from the CPU calculation data collection processing units 35 # A and 35 # B is encoded using the read encoding calculation function (S302).

  Then, the transmission processing units 45 # A and 45 # B are instructed to transmit the encoded data to other CPUs (S304), and are stored in the encoded data storage units 50 # A and 50 # B (S306).

  FIG. 9 is a flowchart showing a flow of transmission processing executed by the transmission processing units 45 # A and 45 # B. This flow is started at the timing when the encoding processing by the encoding processing units 40 # A and 40 # B is completed.

  First, the transmission processing units 45 # A and 45 # B create a message that matches the transmission specification from the encoded data encoded by its own CPU, and transmits it to another CPU (S400).

  Next, the encoded data is received from the other CPU (S402). Then, the received encoded data is stored in the encoded data storage units 50 # A and 50 # B (S404). At this time, if an abnormality is detected in the message or transmission, the abnormal data is stored in the encoded data storage units 50 # A and 50 # B.

  In the flow of FIG. 9, the order of transmission → reception is uniform, but in actuality, one CPU performs processing in the order of transmission → reception, and the other CPU performs processing in the order of reception → transmission. .

  FIG. 10 is a flowchart showing the flow of comparison / determination processing executed by the comparison / determination processing units 55 # A and 55 # B. This flow is started at the timing when the transmission processing by the transmission processing units 45 # A and 45 # B is completed.

  First, the comparison / determination processing units 55 # A and 55 # B are the encoded data stored in the encoded data storage units 50 # A and 50 # B and the encoded data received from the other CPU. Is read (S500).

  Next, the read encoded data is compared to determine whether or not they match (S502). If the encoded data matches, this flow ends without performing any processing.

  On the other hand, if the encoded data does not match, it is determined whether or not it has been determined that there is a mismatch from the previous time (S504).

  If it is not determined that there is a mismatch from the previous time, CPU minor failure processing is performed, and a flag or the like indicating the occurrence of a mismatch is written in the encoded data storage units 50 # A, 50 # B, etc. (S506). Here, the CPU minor failure processing includes re-downloading of each parameter such as CPU reset. Such processing is for transient failures such as soft errors. That is, when it is determined that the encoded data does not coincide with each other, the error processing on the software is stopped and the task performed by the information processing apparatus 1 is continued.

  If it is determined that there is a mismatch from the previous time, CPU serious failure processing is performed, and the flag indicating the occurrence of the mismatch written in the encoded data storage units 50 # A, 50 # B, etc. is deleted (S508). Here, the CPU serious failure processing includes shutting down the information processing apparatus and subsequent access prohibition other than administrator authority. Such processing is for failures that are difficult to repair, such as transmission line disconnection, IC failure, ROM data corruption, CPU failure, and the like. That is, when it is determined that the encoded data does not match continuously, the task performed by the information processing apparatus 1 is stopped in consideration of safety. By performing such stepwise error processing, it is possible to perform appropriate processing according to the degree of failure.

  According to the information processing apparatus 1 of the present embodiment described above, the reliability of the arithmetic processing is ensured by selecting an encoding arithmetic function whose expected error probability is smaller than the required encoding error probability. By selecting a coding operation function that satisfies the error probability and having the smallest number of coding bits, the data transmission amount and data comparison amount between CPUs can be minimized.

  As a result, it is possible to achieve both reduction in the amount of data transmission and data comparison for self-diagnosis and maintenance of reliability.

  Reducing the amount of data transmitted for self-diagnosis prevents system performance degradation that becomes a bottleneck in communication time when low-speed and low-speed communication paths such as RS232C serial communication are used for communication between CPUs. be able to.

  Further, according to the information processing apparatus 1 of the present embodiment, it is possible to perform appropriate processing according to the degree of failure by performing stepwise error processing.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  For example, in the embodiment, the information processing apparatus 1 includes two CPUs, but may include three or more CPUs. In this case, the failed CPU can be specified by majority vote.

  Further, a CPU dedicated to monitoring (when the information processing apparatus 1 includes three or more CPUs), a logic circuit, or the like may be provided.

  The present invention can be used in the manufacturing industry of computers and peripheral devices.

1 Information processing apparatus 10 # A, 10 # B arithmetic processing unit 15 # A, 15 # B arithmetic data storage unit 20 # A, 20 # B Code error probability table 25 # A, 25 # B Coding method selection unit 30 # A, 30 # B management table 35 # A, 35 # B CPU calculation data collection processing unit 40 # A, 40 # B encoding processing unit 45 # A, 45 # B transmission processing unit 50 # A, 50 # B encoding Data storage unit 55 # A, 55 # B Comparison / determination processing unit 70 Count register #A, #B CPU

Claims (8)

An information processing apparatus comprising a plurality of arithmetic processing means connected in communication, wherein the plurality of arithmetic processing means can execute the same arithmetic processing synchronously,
An encoding method selecting means for selecting one encoding method having an error probability less than a set value from a plurality of encoding methods;
When the plurality of arithmetic processing means synchronously execute the same arithmetic processing, the information including the arithmetic processing result by the plurality of arithmetic processing means is encoded by the encoding technique selected by the encoding technique selecting means. Encoding means for
A determination unit that compares information encoded by the plurality of encoding units and determines whether the plurality of arithmetic processing units are operating normally;
An information processing apparatus comprising: The information processing apparatus according to claim 1,
The encoding method selection means is means for selecting an encoding method having the smallest number of encoding bits among encoding methods in which the error probability is less than a set value.
Information processing device. The information processing apparatus according to claim 1 or 2,
The set value is calculated as a value obtained by multiplying the CPU required safety level set as a parameter by a sign error ratio and further dividing the number of comparisons per time by the determination means.
Information processing device. The information processing apparatus according to any one of claims 1 to 3,
The encoding method selection means calculates the minimum number of encoded bits based on the logarithmic value of the set value, and selects an encoding method in which the number of encoded bits exceeds the calculated minimum number of encoded bits, A means for selecting an encoding method with an error probability less than a set value.
Information processing device. A self-diagnosis method for an information processing apparatus comprising a plurality of arithmetic processing means connected in communication, wherein the plurality of arithmetic processing means can execute the same arithmetic processing synchronously,
An encoding method selection step of selecting one encoding method having an error probability less than a set value from a plurality of encoding methods;
When the plurality of arithmetic processing means synchronously execute the same arithmetic processing, the information including the arithmetic processing result by the plurality of arithmetic processing means is encoded by the encoding technique selected in the encoding technique selecting step. An encoding step to
A determination step of comparing the information encoded in the encoding step to determine whether or not the plurality of arithmetic processing means are operating normally;
A self-diagnosis method for an information processing apparatus comprising: A self-diagnosis method for an information processing apparatus according to claim 5,
In the encoding method selection step, among the encoding methods whose error probability is less than a set value, an encoding method having the smallest number of encoding bits is selected,
A self-diagnosis method for an information processing apparatus. A self-diagnosis method for an information processing device according to claim 5 or 6,
A setting value calculating step of calculating the setting value as a value obtained by multiplying the CPU required safety degree set as a parameter by a sign error ratio and dividing the number of comparisons per time by the determination step ;
A self-diagnosis method for an information processing apparatus. A self-diagnosis method for an information processing apparatus according to any one of claims 5 to 7,
In the encoding method selection step, a minimum number of encoded bits is calculated based on a logarithmic value of the set value, and an encoding method having a larger number of encoded bits than the calculated minimum number of encoded bits is selected. , Characterized by selecting an encoding method with an error probability less than a set value,
A self-diagnosis method for an information processing apparatus.

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