JP5534912B2 - Data storage device - Google Patents

Description

  The present invention relates to a technique for saving and reading data to and from a storage device, and more particularly to a technique for saving and reading data to and from a storage device based on a memory management algorithm such as an LRU (Least Recently Used) algorithm.

  Conventionally, a memory management algorithm for giving priority to data stored in a storage device or its storage area as means for controlling storage and reading of data to and from a storage device such as a hard disk drive (HDD), cache memory, or virtual memory Is widely used. By using the memory management algorithm, the data with the lowest priority is selected from the data stored in the storage device, and the data is limited (deleted) from the storage device as necessary. An area for storing as much significant data as possible can be secured in the storage area. As this type of memory management algorithm, for example, an LRU algorithm based on a temporal locality principle or a LFU (Least Frequently Used) algorithm is widely known. The LRU algorithm is an algorithm that selects data that has not been referenced for the longest time as the least likely reference in the near future, and the LFU algorithm can refer to data that is least frequently referenced in the near future. This algorithm is selected as the one with the lowest probability.

  Prior art documents relating to the LRU algorithm include, for example, Japanese Patent Laid-Open No. 9-288617 (Patent Document 1) and Japanese Patent No. 4369524 (Patent Document 2). The LRU control method disclosed in Patent Document 1 includes means for searching for search target data from a table, and when the search target data exists in the table, the search target data is arranged so as to be positioned at the head of the table. And means for replacing. On the other hand, the LRU control device disclosed in Patent Document 2 stores LRU information including a plurality of pieces of identification information for identifying a plurality of entries (for example, IDs uniquely assigned to the entries). And means for taking out the identification information of the used entry from the LRU information and moving it to the tail and updating the LRU information when any one of the plurality of entries is used. ing. A plurality of pieces of identification information constituting the LRU information are written in order from the oldest when the entry is last used.

JP-A-9-288617 Japanese Patent No. 4369524

  One memory management algorithm is called a rearrangement method. The rearrangement method is a method in which entry data is rearranged in the data storage area in accordance with priority every time an entry is registered, deleted or updated. The LRU control method disclosed in Patent Document 1 is a kind of rearrangement method. However, the rearrangement method has a problem that a period during which the data storage area for storing the entry data cannot be accessed is generated while the entry data is rearranged, which causes a reduction in processing speed.

  The LRU control device disclosed in Patent Document 2 constructs LRU information in a storage area different from the data storage area for storing entry data, and a plurality of entries in the LRU information are registered for each entry registration, deletion, or update. The LRU information is updated by rearranging and storing the identification information in the order of last use. Therefore, even when the identification information is being rearranged by the LRU control, the entry data can be read by accessing the data storage area. However, since it is necessary to secure another storage area for LRU control, the amount of memory consumption increases. In addition, when the number of entries subject to LRU control increases, there is a problem that the number of bits necessary to realize LRU control increases.

  In view of the above, an object of the present invention is to provide a data storage device that operates with a small amount of memory consumption and can suppress a decrease in processing speed even when rearranging entry data based on a memory management algorithm. It is.

The data storage device according to the present invention has a plurality of data storage areas to which access orders are respectively assigned, an entry holding circuit for holding entry data in each data storage area in the order of access from the external device, and the external device An entry control circuit for writing the entry data to the plurality of data storage areas in response to the access request, and each data storage area stores the entry data held in the data storage area. A valid flag area for storing a valid flag having one of a valid value to be valid and an invalid value for invalidating entry data held in each data storage area, and actual data of the entry data And the entry control circuit executes the writing of the entry data. The memory control for determining whether the valid flag has the invalid value from the data storage area with the lowest access order to the data storage area with the lowest access order in the lower order. And when the result of the determination does not have the invalid value, the memory control unit is one more than the access order of the data storage area determined not to have the invalid value. Proceeding to the determination of the upper data storage area, and if the determination result has the invalid value, the memory control unit accesses the data storage area determined to have the invalid value. The entry data held in the data storage area having the access order higher than the rank is shifted to the data storage area one level lower and the access The effective flag having the invalid value is stored in the valid flag area of the uppermost data storage area, and one rank higher than the access rank of the data storage area determined to have the invalid value. The process proceeds to the determination of the data storage area.

  According to the present invention, entry data including a valid flag and entity data is held in the data storage area. While the entry data is not written to the data storage area, the entry data can be rearranged efficiently by the shift operation using the valid flag.

It is a functional block diagram which shows schematic structure of the data processing system of Embodiment 1 which concerns on this invention. 3 is a diagram showing a configuration of a data storage area in an entry holding circuit of the data storage device according to the first embodiment. FIG. FIG. 3 is a functional block diagram illustrating an example of a configuration of an entry control circuit of the data storage device according to the first embodiment. FIG. 3 is a diagram illustrating a preferred configuration of an entry holding circuit according to the first embodiment. 6 is a flowchart schematically showing a procedure of entry rearrangement processing according to the first embodiment. It is a figure which shows the mode of the state transition of a data storage area when the entry rearrangement process of FIG. 5 is performed. 4 is a flowchart schematically showing a procedure of entry deletion processing according to the first embodiment. 4 is a flowchart schematically showing an example of a procedure of entry registration processing according to the first embodiment. 12 is a flowchart schematically showing another example of the procedure of entry registration processing according to the first embodiment. It is a figure which shows the structure of the data storage area of Embodiment 2 which concerns on this invention. 12 is a flowchart schematically showing a procedure of entry deletion processing according to the second embodiment. 10 is a flowchart schematically showing a procedure of entry registration processing according to the second embodiment. 13 is a flowchart showing a procedure of entry search processing (step S326) in FIG. It is a figure which shows the structure of the data storage area of Embodiment 3 which concerns on this invention. 12 is a flowchart schematically showing an example of a control process according to the third embodiment. It is a flowchart which shows roughly the procedure of the entry update process which concerns on Embodiment 4 which concerns on this invention. FIG. 20 is a diagram showing a state transition of a data storage area when an entry update process according to Embodiment 4 is executed. It is a figure which shows the structure of the data storage area of the modification of Embodiment 1-4.

  Hereinafter, various embodiments according to the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a functional block diagram showing a schematic configuration of a data processing system 1 according to the first embodiment of the present invention. The data processing system 1 includes an input / output device 14 that executes data processing and a data storage device 11 that temporarily stores entry data including entity data that is referred to during the data processing. Examples of the input / output device 14 include, but are not limited to, a communication device (such as a relay device or a line concentrator) that processes communication data in a communication network. As long as the device requires a memory for data processing, the data storage device 11 can be applied to any device.

  The data storage device 11 controls the entry holding circuit 12 having a plurality of data storage areas for storing a plurality of entry data, and writing and reading of entry data to and from the entry holding circuit 12 based on a memory management algorithm such as an LRU algorithm. And an entry control circuit 13. The entry control circuit 13 selects the entry data having the lowest priority among the plurality of entry data based on the memory management algorithm, and secures a free area in the entry holding circuit 12 by invalidating the selected entry data. It has the function to do.

2A, 2B, and 2C show n data storage areas M ₀ , M ₁ , M ₂ ,..., M _n−3 , M _n−2 , M _n in the entry holding circuit 12. It is a figure which shows _-1 (n is a positive integer) typically. Here, n is an integer value indicating the maximum number of entries that can be secured in the entry holding circuit 12. Although FIG. 2A shows six or more data storage areas M _{0 to} M _n−1 , it is sufficient that at least two data storage areas are secured. Each of the data storage areas M _{0 to} M _n−1 has a storage capacity for holding entry data. In addition, the data storage areas M ₀ , M ₁ ,..., M _n−1 are assigned ranks (hereinafter referred to as access ranks) corresponding to the priority levels of the entry data. In the entry control circuit 13, the data storage area _{M 0,} M 1, _..., identifier # corresponding to each of the access order with respect to _{M n-1 (0),} # (1), ..., # (n-3 ), # (N-2) and # (n-1) are set. The entry control circuit 13 can access the entry data held in the data storage areas M _{0 to} M _n−1 based on these identifiers # (0) to # (n−1).

As shown in FIG. 2A, the access order of the data storage area M _n−1 having the identifier # (n−1) is the highest order, and the priority order is assigned to the highest data storage area M _n−1. The highest entry data is stored. When the LRU algorithm is adopted, the priority of entry data becomes higher as the elapsed time from the last reference is shorter. The access order of the data storage area M ₀ having an identifier # a (0) is the lowest, the lowest entry data priority in the data storage area M ₀ of the lowest is stored. As will be described later, when entry data is registered in the entry holding circuit 12, this entry data is first stored in the uppermost data storage area M _n−1 . Thereafter, each time entry data is registered, updated, or deleted, the entry data is one lower data storage area M from the higher data storage area M _i (i is an integer from 1 to n−1). shifted to _i-1 .

2 (B) is a schematic diagram showing an example of the configuration of the data storage area M _i identifier # (i). As shown in FIG. 2B, each data storage area M _i is held in a data area 21 for storing entity data (entry data body) referred to in data processing, and in the data storage area M _i. And a flag area 22 for storing a validity flag which is a kind of control flag indicating the validity of the entry data. The valid flag has one of a valid value for validating entry data (for example, a value of “1”) and an invalid value for invalidating entry data (for example, a value of “0”). Hereinafter, a valid flag having an invalid value is referred to as an “invalid flag”. Also, the entry control circuit 13 determines that the missing free space entry data storage area M _i for holding the invalid flag in the flag area 22. Entry control circuit 13 can make free space by invalidating entries in the data storage area M _i by writing invalid flag in the flag area 22 of the data storage area M _i.

  In the present embodiment, single entity data is stored in the data area 21, but the present invention is not limited to this. Depending on the system to be constructed, the data area 21 may be functionally divided into areas 21A, 21B,... For storing a plurality of entity data related to each other as shown in FIG. . As a result, the entry holding circuit 12 can be used as a search table. For example, when the input / output device 14 is a line concentrator connected to a LAN (Local Area Network), the substance data of the address search table can be stored in the two areas 21A and 21B in the data area 21. More specifically, if two substance data such as a data transmission source MAC (Media Access Control) address and a communication port number are stored in the two areas 21A and 21B in the data area 21, the entry holding circuit 12 is connected to the MAC. It can be used as an address search circuit that holds an address table. In response to the inquiry request from the input / output device 14, the entry control circuit 13 can acquire the communication port number corresponding to the MAC address from the entry holding circuit 12 and return it as a search result.

  In the present embodiment, a single control flag (valid flag) is stored in the flag area 22, but the present invention is not limited to this. As shown in FIG. 2C, the flag area 22 may have areas 22A, 22B,... For storing a plurality of control flags. As will be described later, in the second and third embodiments, two types of control flags are stored in the flag area 22.

FIG. 3 is a functional block diagram showing an example of the configuration of the entry control circuit 13, and FIG. 4 is a diagram showing a preferred configuration of the entry holding circuit 12. As shown in FIG. 3, the entry control circuit 13 includes a transmission / reception unit 131 that transmits and receives data to and from the input / output device 14, and all data storage areas M _{0 to} M _n−1 in the entry holding circuit 12. The entry data receiving unit 132 that receives the entry data group 31 output in parallel from and the entry update control unit 133 is included. The entry data reception unit 132 supplies the entry data group 31 received from the entry holding circuit 12 to the transmission / reception unit 131 and the entry update control unit 133. The entry update control unit 133 can grasp the state of the entry holding circuit 12 based on the entry data group 31 supplied from the entry data receiving unit 132 and control the operation state of the entry holding circuit 12 for each processing cycle. it can. Here, one processing cycle consists of one clock cycle or a predetermined number of clock cycles. The entry update control unit 133 includes a data search unit 133A, an area detection unit 133B, and a memory control unit 133C.

  The entry update control unit 133 supplies the control data group 32 to the entry holding circuit 12. The entry holding circuit 12 operates according to the control data group 32 supplied from the entry update control unit 133 for each processing cycle.

The transmission / reception unit 131 has a function of receiving and analyzing the access request RQ from the input / output device 14. The transmission / reception unit 131 outputs the analysis result of the access request RQ to the entry update control unit 133. The entry update control unit 133 executes processing according to the analysis result, and returns the processing result RS to the input / output device 14 via the transmission / reception unit 131. Examples of the access request RQ include an entry registration instruction, an entry deletion instruction, a valid entry number notification instruction, a data search request, and a data read instruction. Among these access requests RQ, the data search request, the data read instruction, and the valid entry count notification instruction are those that do not involve entry changes in the data storage areas M _{0 to} M _n−1 .

  When receiving the access request RQ including the data read instruction, the transmission / reception unit 131 extracts all the entity data from the entry data group 31 supplied from the entry data reception unit 132 and transmits these entity data to the input / output device 14. It has the function to do.

  When the transmission / reception unit 131 receives an access request RQ including a data search request with search key data, the data search unit 133A selects the entry data group 31 supplied from the entry data reception unit 132 in response to the data search request. Of the entry data including a valid flag having a valid value, entity data matching the search key data is retrieved, and the retrieval result is returned to the input / output device 14 via the transmission / reception unit 131. For example, when the entry holding circuit 12 holds the MAC address table, the data search unit 133A can use the MAC address as search key data and return the corresponding communication port number as a search result.

  When an access request RQ including a notification instruction for the number of valid entries is received, the data search unit 133A determines that a valid value having a valid value from the entry data group 31 supplied from the entry data reception unit 132 in response to the notification instruction. The entry data including the flag is counted, and the counting result, that is, the number of valid entries in the entry holding circuit 12 is notified to the input / output device 14 via the transmission / reception unit 131.

  When the transmission / reception unit 131 receives an access request RQ including an entry change instruction (hereinafter referred to as an entry operation instruction) such as an entry registration instruction or an entry deletion instruction, the memory control unit 133C sets the entry operation instruction. It has an entry operation function for executing the corresponding processing.

When the access request RQ including the entry registration instruction is received, the memory control unit 133C determines whether or not the invalid flag is held in the uppermost data storage area M _n−1 according to the entry registration instruction. . Based on the entry data group 31 supplied from the entry data reception unit 132, the region detection unit 133B has a free region M _e (e is 1 to n) having an invalid flag among the data storage regions M _{0 to} M _n−1. -1), and the detection result is given to the memory control unit 133C. The memory control unit 133C can determine whether or not the invalid flag is held in the uppermost data storage area M _n−1 from the detection result by the area detection unit 133B.

When it is determined that the data storage area M _n−1 is an empty area holding the invalid flag, the memory control unit 133C sets the entry data including the valid flag having a valid value and the entity data to be registered as the empty area M _n. Write to _-1 . This completes entry registration. On the other hand, if the invalid flag in the data storage area M _n-1 is not held, in other words, if the data storage area M _n-1 holds the entry data including the valid flag with valid values, the memory controller 133C , first, it writes the invalid flag in the lowest of the data storage area M _0. Thereafter, the entry data in the data storage areas M _{1 to} M _n−1 are shifted to the data storage areas M _{0 to} M _n−2 which are lower by one by executing a shift operation described later. Then, the memory control unit 133C writes entry data including a valid flag having a valid value and entity data to be registered in the uppermost data storage area M _n−1 . This completes entry registration.

When the access request RQ including the entry deletion instruction is received, the data search unit 133A has a valid flag having a valid value in the entry data group 31 supplied from the entry data reception unit 132 in response to the entry deletion instruction. The entity data to be deleted that matches the specific data is searched from the entry data including “”. When the data search unit 133A cannot find the actual data, the data search unit 133A notifies the input / output device 14 of the search result via the transmission / reception unit 131. On the other hand, when the entity data is found, the memory control unit 133C writes the invalid flag to the data storage area M _d (d is an integer from 0 to n−1) that holds the corresponding entity data, and the data invalidating an entry in the storage area M _d. Then, the memory control unit 133C notifies the input / output device 14 of the result via the transmission / reception unit 131. Entry data held in the data storage area M _{d + 1} that is one level higher is shifted to the empty area M _d by a shift operation described later.

When an access request RQ including an instruction to delete all entries (simultaneous deletion instruction) is received, the memory control unit 133C includes an invalid flag in all of the data storage areas M _{0 to} M _n−1 within one processing cycle. To invalidate all entries, and notify the input / output device 14 via the transmission / reception unit 131 that simultaneous deletion has been completed.

Further, the memory control unit 133C rearranges (rearranges) the entry data including the valid flag having a valid value in the data storage areas M _{0 to} M _n−1 and arranges the valid entries continuously. It has an entry rearrangement function (entry rearrangement function). Specifically, within the processing cycle period in which entry data is not written to the data storage areas M _{0 to} M _n−1 , the memory control unit 133C determines that the data storage area is higher than the rank of the free area M _d. A shift operation for shifting the entry data held in M _{d + 1 to} M _n−1 to the data storage area M _{d to} M _n−2 that is one level lower is executed, and the highest data storage area M _n−1 is executed. Write invalid flag. The shift operation is executed in one processing cycle. For example, if the data storage area _{M 1} Identifier # (1) is a free area, the memory controller 133C, the entry data stored in the upper data storage area _M 2 _{~M n-1} than the free space _{M 1} Are _respectively shifted to the data storage areas M _{1 to} M _n−2 one level lower. Alternatively, when the data storage area M _{n−2 of} the identifier # (n−2) is an empty area, the memory control unit 133C holds the data storage area M _n−1 higher than the empty area M _n−2. The entered data is shifted to the data storage area M _n−2 which is one level lower.

By such an entry rearranging function, entry data including a valid flag having a valid value can be continuously arranged (reordered) in the data storage areas M _{0 to} M _n−1 . It is possible to eliminate the presence of an empty area between the data storage areas that hold the data (fragmentation of the empty area). Further, the upper data storage area group including the uppermost data storage area M _n−1 can be made as free as possible. When a new entry is registered in the highest data storage area M _n−1 in response to the entry registration instruction, if the highest data storage area M _n−1 is an empty area, the data storage area M is changed by a shift operation. _The entity data can be written to the data storage area M _n−1 without waiting for _n−1 to become a free area.

  In addition, the entry sorting function allows entry data including valid flags with valid values to be placed continuously, so that the search range is limited when there is a data search instruction or a specific entry deletion instruction. Can do. Therefore, it is possible to realize high speed data search processing and entry deletion processing.

Next, a preferred configuration of the entry holding circuit 12 will be described with reference to FIG. The entry holding circuit 12 is a shift register circuit having _n- stage register circuits 40 ₀ ,..., 40 _n−3 , 40 _n−2 , and 40 _n−1 . Each register circuit 40 _j (j is an arbitrary integer from 0 to n−1) includes, for example, a register 50 _j such as a flip-flop that operates in synchronization with a clock signal and an entry as shown in FIG. It has a selector 60 _j and its own entry data control circuit 70 _j . Registers 50 ₀ ,..., 50 _n−1 are storage elements constituting the data storage areas M ₀ ,..., M _n−2 , M _n−1 of FIG.

The entry control circuit 13 supplies the control data group 32 to the entry holding circuit 12. The control data group 32 includes selection control signals SEL ₀ ,..., SEL _n−2 , SEL _n−1 supplied to the entry selectors 60 ₀ ,..., 60 _n−2 , 60 _n−1 , and own entry data control. circuit _{70 0, ..., 70 n-} 2, 70 n-1 to the control signal _C 0 is _{supplied, ...,} consisting of _{C n-2, C n-} 1 Tokyo. Each entry selector 60 _j has a function of selecting data input to any one of the three input terminals according to the value of the selection control signal SEL _j and outputting this data to the input terminal of the register 50 _j. .

In the uppermost register circuit 40 _n−1 , the registration data (substance data) OD _n supplied from the entry control circuit 13 and the own entry data control circuit 70 are connected to the three input terminals of the entry selector 60 _n−1. the output data _{AD n-1} to _n-1, the register ₅₀ and the feedback output _{OD n-1} to _n-1 are inputted. When an entry selector _{60 n-1} selects the feedback output _{OD n-1} of the register _{50 n-1,} a feedback loop is formed between the input terminal and the output terminal of the register _{50 n-1,} the register _{50 n-1} Continues to hold the same bit value (entry data). When the entry selector 60 _n-1 selects the output data AD _n-1 of its own entry data control circuit 70 _n-1 , the register 50 _n-1 selects its own entry data control circuit according to the pulse edge of the clock signal. 70 _n−1 output data AD _n−1 is latched (held). When the entry selector 60 _n-1 selects the data OD _n supplied from the entry control circuit 13, the register 50 _n-1 latches the data OD _n according to the pulse edge of the clock signal.

The own entry data control circuit 70 _n−1 receives replacement data AD _n−1 for changing part or all of the entry data held in the register 50 _n−1 in accordance with the control signal C _n−1. It has a function to generate. The output data OD _n-1 of the register 50 _n-1 is fed back and input to the own entry data control circuit 70 _n-1 . The own entry data control circuit 70 _n−1 is included in _one of the valid flag and invalid flag having a valid value according to the value of the control signal C _n−1 and the feedback output OD _n−1 . The entry data AD _n-1 including the actual data is configured, and the entry data AD _n-1 can be output to the entry selector 60 _n-1 .

On the other hand, in the other register circuit 40 _k (k is one of 0 to n−2), the three input terminals of the entry selector 60 _k are connected to the output data OD _{k + 1} of the register 50 _{k + 1 in} the previous stage and the own entry data. the output data AD _k of the control circuit 70 _k, and the output data OD _k of the register 50 _k is input. When an entry selector 60 _k selects the feedback output OD _k of the register 50 _k, the feedback loop is formed between the input terminal and the output terminal of the register 50 _k, the register 50 _k is the same bit value (entry data) Keep holding. When the entry selector 60 _k selects the output data AD _k of its own entry data control circuit 70 _k , the register 50 _k outputs the output data AD _k of its own entry data control circuit 70 _k according to the pulse edge of the clock signal. Latch (hold). When the entry selector 60 _k selects the output data OD _{k + 1} of the previous register 50 _{k + 1} , the register 50 _k latches the data OD _{k + 1} according to the pulse edge of the clock signal.

Own entry data control circuit 70 _k has a function in response to the control signal C _k, and generates a replacement data AD _k to change some or all of the entry data held in the register 50 _k. Register output data OD _k of 50 _k is also input to the self entry data control circuit 70 _k is fed back. The own entry data control circuit 70 _k includes either a valid flag having a valid value according to the value of the control signal C _k or an invalid flag, and entity data included in the feedback output OD _k. The entry data AD _k can be configured, and the entry data AD _k can be output to the entry selector 60 _n−1 .

Since the registers 50 ₀ to 50 _n−1 output the entry data group 31 including the output data OD _{0 to} OD _n−1 to the entry control circuit 13 in parallel, the entry control circuit 13 includes the registers 50 ₀ to 50 _n. All entry data held in _n-1 can be acquired at once.

The entry control circuit 13 can control the operation of the entry holding circuit 12 by supplying the control data group 32. The processing cycle that does not execute processing corresponding to the entry operation instruction such entry registration instruction or the entry delete instruction, the memory controller 133C, all entries selector _{60 0-60} registers ₅₀ to _n-1 0 _{~50 n-1} Selection control signals SEL _{0 to} SEL _n−1 for selecting the feedback outputs OD _{0 to} OD _n−1 are output. As a result, the registers 50 ₀ to 50 _n−1 continue to hold the same entry data group.

When deleting an entry from the invalidation to entry hold circuit 12 the entry data, the memory controller 133C, the register circuit 40 for holding the entry data invalidation target _d entry selector 60 _d to the self entry data control circuit 70 _d output supplies data AD _d selection control signal SEL _d to select, it supplies a control signal _{C d} to generate replacement data AD _d that contains an invalid flag in the own entry data control circuit 70 _d. Thus the register 50 _d holds the invalid flag.

When storing the entry data in the entry holding circuit 12 in response to the entry registration instruction, the memory control unit 133C generates a selection control signal SEL _n−1 that causes the highest entry selector 60 _n−1 to select the replacement data OD _n. Then, new entry data is supplied as replacement data OD _n to the entry selector 60 _n−1 . The register 50 _n−1 latches (holds) the entry data OD _n input via the entry selector 60 _n−1 in accordance with the pulse edge of the clock signal. As a result, entry data is registered in the uppermost register 50 _n−1 .

When the free space M _e in the data storage area M ₀ ~M the _n-1, the entry operation instruction in a processing cycle that does not write an entry data corresponding to the entry data including a valid flag with valid value Are rearranged. Specifically, the memory controller 133C is free space _M upper register circuit ₄₀ than order of register circuit 40 _e with _e e + 1 _{to 40} registers ₅₀ in _{n-1 e + 1 ~50 n} -1 of the output data OD Selection control signals SEL _{e to} SEL _n-2 for selecting _{e + 1 to} OD _n-1 are supplied to the entry selectors 60 _{e to} 60 _n-2 . Further, the memory controller 133C, the selection control signal to select the output data _{AD n-1} of the own entry data control circuit _{70 n-1} in the entry selector _{60 n-1} of the top-level register circuit _{40 n-1 SEL n- 1} supplies, supplies a control signal _{C n-1} to generate replacement data _{AD n-1} that contains an invalid flag in the own entry data control circuit _{70 n-1.} Thus the register ₅₀ e _{~50 n-2,} respectively, to perform a shift operation the output data _OD e + _{1 ~OD n-1} of the previous register ₅₀ e + _{1 ~50 n-1} latches (holds). Further, an invalid flag is held in the highest register 50 _n−1 .

  Next, the operation of the data storage device 11 according to the first embodiment having the above configuration will be described with reference to FIGS.

  FIG. 5 is a flowchart schematically showing a procedure of entry rearrangement processing executed when there is no entry operation instruction from the input / output device 14, and FIG. 6 shows data when the entry rearrangement processing is executed. It is a figure which shows the mode of the state transition of a storage area. FIG. 7 is a flowchart schematically showing the procedure of entry deletion processing executed in response to the entry deletion instruction. FIGS. 8 and 9 show the procedure of entry registration processing executed in response to the entry registration instruction. FIG. Note that the processing for an access request RQ that does not involve entry change, such as a data search request, a data read instruction, and a valid entry count notification instruction, is a process that can be executed at all times because the entry holding circuit 12 has a shift register circuit configuration. is there. These processes can be executed in parallel even during the process cycle period in which the entry rearrangement process, the entry deletion process, and the entry registration process are executed.

  First, an entry rearrangement process executed when there is no entry operation instruction will be described with reference to FIG. The memory control unit 133C of the entry update control unit 133 grasps the operation state of the entry holding circuit 12 based on the entry data group 31 supplied from the entry data receiving unit 132, and performs the entry rearrangement process in an appropriate processing cycle period. Start.

First, the memory control unit 133C initializes the variable i and sets a zero value to the variable i (step S101). Next, the memory control unit 133C determines whether or not the entry data held in the register circuit 40 _i having the identifier # (i) (hereinafter referred to as the entry data of the identifier # (i)) is invalid. Determination is made (step S103). When it is determined that the entry data of the identifier # (i) is valid (NO in step S103), the memory control unit 133C determines whether the variable i has reached n-2 (step S115). When the variable i reaches n−2 (YES in step S115), the entry rearrangement process ends. On the other hand, when the variable i has not reached n−2 (NO in step S115), the memory control unit 133C increments the variable i by 1 (step S117), and returns the procedure to step S103.

When invalid entry data including an invalid flag exists as a result of determining whether or not invalid (step S103) in order from the lowest entry data to the higher entry data (YES in step S103) The memory control unit 133C sets the value of the variable i to the variable j (step S105). Next, the memory control unit 133C executes control to shift the entry data of the identifier # (j + 1) to the entry of the identifier # (j) (Step S107). Specifically, the memory control unit 133C selects the entry selector 60 _j of the register circuit 40 _j having the identifier # (j) to select the output data OD _{j + 1} of the preceding register circuit 40 _{j + 1} having the identifier # (j + 1). A control signal SEL _j is supplied. Next, the variable j is incremented by 1 (step S109). Thereafter, the memory control unit 133C determines whether or not the variable j has reached the identifier number n-1 of the highest-order register circuit 40 _n-1 (step S111). If the variable j has not reached n−1 (NO in step S111), the processing procedure returns to step S107. As described above, the processes of steps S107 and S109 are repeatedly executed until it is determined in step S111 that the variable j reaches n−1 (YES in step S111). Consequently, the register ₅₀ i _{~50 n-2,} respectively, to perform a shift operation the output data _OD i + _{1 ~OD n-1} of the previous register ₅₀ i + _{1 ~50 n-1} latches (holds).

After executing the shift operation (YES in step S111), the memory control unit 133C invalidates the highest entry of the identifier # (n-1) (step S113). Specifically, the memory controller 133C, the selection control signal for selecting the output data _{AD n-1} of the own entry data control circuit _{70 n-1} in the entry selector _{60 n-1} of the most significant register circuits _{40 n-1} supplying SEL _n-1, and supplies a control signal _{C n-1} to generate replacement data _{AD n-1} that contains an invalid flag in the own entry data control circuit _{70 n-1.} As a result, the invalid flag is held in the register 50 _n-1 . Thereafter, the processing after step S117 is executed until it is determined in step S115 that the variable i reaches n-2 (YES in step S115).

6A to 6C are diagrams showing the state transition of the data storage areas M _{0 to} M ₆ when the maximum entry number n is 7 when the entry rearrangement process is executed. . As shown in FIG. 6A, in the initial state, it is assumed that entries with identifiers # (1), # (2), and # (4) are valid and other entries are invalid.

  By executing the entry rearrangement process, it is first determined that the entry data with the identifier # (i = 0) is invalid (YES in step S103). Next, the entry data of identifier # (1) is shifted to the entry of identifier # (0), the entry data of identifier # (2) is shifted to the entry of identifier # (1), and the entry of identifier # (2) is entered. The entry data of identifier # (3) is shifted, the entry data of identifier # (4) is shifted to the entry of identifier # (3), and the entry data of identifier # (5) is shifted to the entry of identifier # (4) Then, a shift operation of shifting the entry data of identifier # (6) to the entry of identifier # (5) is executed (steps S105 to S111). Thereafter, an invalidation process for the entry of identifier # (6) is executed (step S113). As a result, as shown in FIG. 6B, valid entry data is shifted to the entries of identifiers # (0), # (1), and # (3). The above shift operation and entry invalidation processing are executed within the first processing cycle period.

  In the next processing cycle period, it is determined that the entry data of identifier # (i = 2) is invalid (YES in step S103). Next, the entry data of identifier # (3) is shifted to the entry of identifier # (2), the entry data of identifier # (4) is shifted to the entry of identifier # (3), and the entry of identifier # (4) is entered. A shift operation of shifting the entry data of identifier # (5) and shifting the entry data of identifier # (6) to the entry of identifier # (5) is executed (steps S105 to S111). Thereafter, an invalidation process for the entry of identifier # (6) is executed (step S113). As a result, as shown in FIG. 6C, valid entry data is shifted to the entries of identifiers # (0), # (1), and # (2).

  In the next processing cycle period, it is determined that the entry data of identifier # (i = 3) is invalid (YES in step S103). Next, the entry data of identifier # (4) is shifted to the entry of identifier # (3), the entry data of identifier # (5) is shifted to the entry of identifier # (4), and the entry of identifier # (5) is entered. A shift operation for shifting the entry data of the identifier # (6) is executed (steps S105 to S111). Thereafter, an invalidation process for the entry of identifier # (6) is executed (step S113).

The memory control unit 133C always executes the above-described entry rearrangement processing in a processing cycle period in which entry data writing is not executed, so that a state in which valid entries are packed and arranged as shown in FIG. Can be realized. As shown in FIGS. 6A to 6C, a plurality of processing cycles are required until the rearrangement of the entry data is completed. As shown in FIG. 4, the registers 50 ₀ to 50 _{n− 1} supplies the entry data group 31 to the entry control circuit 13, so that the entry data group 31 can be read without interrupting the rearrangement process.

  Next, an entry deletion process for invalidating entry data including entity data that matches the specific data will be described with reference to FIG.

Entry holding circuit 12 has a configuration of a shift register circuit, so shifting the entry data, the entry data that existed in the data storage area M _i identifier # (i) in a certain processing cycle period, the following There is no guarantee that data storage area M _i with the same identifier # (i) exists in the processing cycle period. For this reason, in the present embodiment, a method is adopted in which a search using specific data as a search key is executed to specify an entry to be deleted. When the access request RQ including the entry deletion instruction is received from the input / output device 14, the memory control unit 133C grasps the operation state of the entry holding circuit 12 according to the entry deletion instruction, and performs an appropriate processing cycle period. Start entry deletion processing.

First, the memory control unit 133C initializes the variable i and sets a zero value to the variable i (step S201). Next, the memory control unit 133C determines whether or not the entry data of the identifier # (i) held in the register circuit 40 _i includes entity data to be deleted that matches the specific data (step S203). . If the entry data does not include the entity data to be deleted (NO in step S203), the memory control unit 133C determines whether or not the variable i has reached the identifier number n-1 indicating the highest entry (step S203). If the variable i has not reached n−1 (NO in step S209), the variable i is incremented by 1 (step S213), and the processing procedure returns to step S203. If entry data including entity data to be deleted cannot be found for all entries, the variable i reaches n−1 (YES in step S209). At this time, the memory control unit 133C notifies the input / output device 14 through the transmission / reception unit 131 that it cannot be deleted (step S211), and ends the entry deletion processing.

On the other hand, when it is determined that the entry data with identifier # (i) includes entity data to be deleted (YES in step S203), the memory control unit 133C invalidates the entry with identifier # (i) (step S205). ). Specifically, the data search unit 133A writes the invalid flag in the data storage area M _i for holding entity data to be deleted. Thereafter, the memory control unit 133C notifies the input / output device 14 of the completion of deletion via the transmission / reception unit 131 (step S207), and ends the entry deletion processing.

  The entry deletion process is applied when the same entity data is not stored redundantly in the entry holding circuit 12. Therefore, if it is determined in step S203 that the entry data with identifier # (i) includes the entity data to be deleted, it is guaranteed that the entity data to be deleted does not exist in the entry with identifier # (i + 1). When duplication of the same entity data is permitted, the memory control unit 133C can adopt a procedure of incrementing the variable i and executing step S203 after executing step S205.

  Next, an entry registration process for registering entity data in the entry holding circuit 12 will be described with reference to FIG. The memory control unit 133C grasps the operation state of the entry holding circuit 12 in response to the entry registration instruction from the input / output device 14, and starts entry registration processing in an appropriate processing cycle period.

First, the memory control unit 133C initializes the variable i and sets a zero value to the variable i (step S301). Next, the memory control unit 133C determines whether or not the entry data of the identifier # (i) held in the register circuit 40 _i includes entity data that matches the specific data to be registered (step S303). . When the entry data does not include the entity data (NO in step S303), the memory control unit 133C determines whether or not the variable i has reached the identifier number n-1 indicating the highest entry (step S321). If the variable i has not reached n−1 (NO in step S321), the variable i is incremented by 1 (step S323), and the processing procedure returns to step S303.

On the other hand, if it is determined that the entry data of identifier # (i) includes entity data that matches the specific data to be registered (YES in step S303), the memory control unit 133C selects the entry of identifier # (i). Invalidate (step S305). Specifically, the data search unit 133A writes the invalid flag in the data storage area M _i to hold the actual data. Thereafter, in the next processing cycle period, the above-described entry rearrangement process (FIG. 5) is executed, and the process waits until the entry of the identifier # (n−1) is invalidated (NO in step S307).

When the invalidation of the entry with the identifier # (n−1) is completed (YES in step S307), the memory control unit 133C performs control of writing specific data to the entry with the identifier # (n−1) (empty entry). This is performed (step S309). Specifically, the memory control unit 133C supplies a selection control signal SEL _n-1 that causes the highest-level entry selector 60 _n-1 to select the replacement data OD _n , and the entry selector 60 _n-1 includes specific data. a new entry data supplied as replacement data OD _n. As a result, the register 50 _n-1 latches (holds) the entry data OD _n input via the entry selector 60 _n-1 . Thereafter, the memory control unit 133C notifies the input / output device 14 of the update completion via the transmission / reception unit 131 (step S311), and ends the entry registration process.

  On the other hand, if entry data including entity data that matches the specific data to be registered cannot be found for all entries, the variable i reaches n−1 (NO in step S303 and YES in step S321). . At this time, the memory control unit 133C determines whether or not the highest entry of the identifier # (n−1) is invalid based on the entry data group 31 supplied from the entry data receiving unit 132 (step S325). . When the highest entry is invalid (YES in step S325), the memory control unit 133C performs control of writing specific data to the entry of the identifier # (n-1) (step S331). Thereafter, the memory control unit 133C notifies the input / output device 14 of registration completion via the transmission / reception unit 131 (step S333), and ends the entry registration process.

  When the highest entry is not invalid in step S325 (NO in step S325), the memory control unit 133C invalidates the lowest entry of the identifier # (0) (step S327). Thereafter, in the next processing cycle period, the above-described entry rearrangement process (FIG. 5) is executed, and the process waits until the entry of the identifier # (n−1) is invalidated (NO in step S329). When the invalidation of the entry with the identifier # (n−1) is completed (YES in step S329), the memory control unit 133C sequentially executes steps S331 and S333, and ends the entry registration process.

  The entry registration process in FIG. 8 is a process in the case where it is not permitted to store the same entity data in the entry holding circuit 12 redundantly. FIG. 9 is a flowchart schematically showing the procedure of the entry registration process when the entry holding circuit 12 permits the same entity data to be duplicated. The flowchart in FIG. 9 is the same as the flowchart in FIG. 8 except that steps S303 to S311 in FIG. 8 do not exist. Since the determination process in step S303 in FIG. 8 is not performed, the specific data is always registered.

When the data area 21 is functionally divided into a plurality of areas for storing a plurality of entity data as shown in FIG. 2C, the memory control unit 133C may It is possible to rewrite a part of. Specifically, the memory controller 133C supplies a selection control signal SEL _i for selecting the output data AD _i of the own entry data control circuit 70 _i in the entry selector 60 _i of the register circuit 40 _i, the self entry data control circuit 70 _i is supplied with a control signal C _i for replacing a part of the plurality of entity data in the feedback output OD _i with another entity data. Here, the memory control unit 133C can supply the other entity data to the own entry data control circuit 70 _i by including the control data C _i in the control signal C _i . For example, as described above, when the input / output device 14 is a line concentrator and the entry holding circuit 12 is used as an address search circuit for registering the correspondence between a MAC address and a communication port number, the memory control unit 133C The communication port number corresponding to can be rewritten. Further, since the memory control unit 133C can always check the contents of the entry data group 31 held in the entry holding circuit 12, the entry holding circuit 12 holds a combination of entity data having a specific correspondence relationship. You can avoid it. For example, the entry holding circuit 12 can be controlled so that a plurality of communication port numbers associated with one MAC address do not exist.

As described above, in the data storage device 11 according to the first embodiment, the memory control unit 133C of the entry control circuit 13 does not write entry data to the data storage areas M _{0 to} M _n−1 . cycle period, the entry data stored in the data storage area _M 0 _{~M n-1} higher than the order of the free space _{M e} in the data storage area _{M e + 1 ~M n-1} , the lower data storage A shift operation for shifting to an area is performed, and an invalid flag is written in the uppermost data storage area M _n−1 . Thereby, entry data including a valid flag having a valid value can be continuously arranged, and an upper data storage area including the highest data storage area M _n-1 can be made a free area. Therefore, unlike the technique disclosed in Patent Document 2 (Japanese Patent No. 4369524), it is not necessary to secure another storage area for memory management control. In addition, since the memory control unit 133C continuously rearranges valid entries to form higher free areas, the data search process, entry registration process (FIGS. 8 and 9), and entry deletion process (FIG. 7) The processing speed can be increased. When the data storage device 11 is mounted, the system can be easily designed so that operations such as registration and deletion (invalidation) of entry data do not conflict with a shift operation on entry data, and the LRU algorithm There is an advantage that it is not necessary to separately secure a storage area required for control based on a memory management algorithm.

Further, since the entry holding circuit 12 has a shift register circuit configuration, the entry control circuit 13 does not affect the operation of the memory control unit 133C on the entry holding circuit 12, and the registers 50 ₀ to 50 _n− Desired entity data can be acquired (read) from _one parallel output (entry data group 31). Further, the memory control unit 133C can perform optimal control while constantly monitoring the operation state and stored contents of the entry holding circuit 12 based on the parallel outputs of the registers 50 ₀ to 50 _n−1 .

  Therefore, the data storage device 11 according to the first embodiment can efficiently execute the control based on the memory management algorithm with a small amount of memory consumption. In particular, it is possible to efficiently execute complete control based on the LRU algorithm with low memory consumption.

Embodiment 2. FIG.
Next, a second embodiment according to the present invention will be described. The configuration of the data storage device of the second embodiment is the same as the configuration of the data storage device 11 of the first embodiment except that the operation mode is different. For the first embodiment, the flag area 22 of the data storage area M _i in the entry holding circuit 12 has been described the operation in the case of storing a single control flag (valid flag). In this embodiment, the flag area 22 of the data storage area _{M i,} as shown in FIG. 10 (A), 2 two regions 22A, as shown (B), the are functionally divided into 22B, one region 22A Stores the valid flag, and the other area 22B stores a static flag. Static flag grant value for permitting the invalidation of an entry data stored in the data storage area M _i (e.g. the value of "0"), the mask value that does not allow the disabling of the entry data (for example, "1" Value).

The memory control unit 133C of the entry update control unit 133 has a data storage area M _m (m is 0) that holds a static flag having a mask value in the entry registration process and the entry deletion process described with respect to the first embodiment. when detecting any integer) of ~n-1, the data storage area M _m not write disable flag, in other words, a function that does not invalidate the registered entries in the data storage area M _m . As a result, although the storage capacity required for the flag areas 22 of the data storage areas M _{0 to} M _n−1 increases, operations such as entry data registration and deletion (invalidation) can be performed more flexibly.

  The static flag is set when registering new entity data. After the entry data including the entity data, the invalid flag, and the static flag is registered in the entry holding circuit 12, the memory control unit 133C performs a deletion operation on the registered entry data based on the value of the static flag. You can decide whether or not. Therefore, entry data that is not changed can be stored in the entry holding circuit 12 regardless of the control based on the memory management algorithm.

  Hereinafter, the operation of the data storage device 11 according to the second embodiment will be described with reference to FIGS. FIG. 11 is a flowchart schematically showing a procedure of entry deletion processing according to the second embodiment. The flowchart in FIG. 11 has the same procedure as the flowchart in FIG. 7 except for steps S204 and S214. 12 is a flowchart schematically showing the procedure of entry registration processing according to the second embodiment. FIG. 13 is a flowchart showing the procedure of entry search processing (step S326) in FIG. The flowchart in FIG. 13 is connected to the flowchart in FIG. 12 through a connector C1. The flowchart of FIG. 12 has the same procedure as the flowchart of FIG. 8 except for steps S304, S326, S328, and S335.

  First, the entry deletion process will be described with reference to FIG. When the access request RQ including the entry deletion instruction is received from the input / output device 14, the memory control unit 133C grasps the operation state of the entry holding circuit 12 according to the entry deletion instruction, and performs an appropriate processing cycle period. Start entry deletion processing.

When it is determined in step S203 that the entry data with the identifier # (i) includes the entity data to be deleted (YES in step S203), the memory control unit 133C holds the register circuit 40 _i having the identifier # (i). It is determined whether the static flag (hereinafter referred to as the static flag of identifier # (i)) is significant (step S204). If the static flag is significant, that is, if the static flag has a mask value (YES in step S204), the memory control unit 133C invalidates the entry of the identifier # (i) (step S205). In addition, the fact that the update by the static flag is impossible is notified to the input / output device 14 via the transmission / reception unit 131 (step S214), and the entry deletion process is terminated. On the other hand, when the static flag is not significant (NO in step S204), the memory control unit 133C ends the entry deletion process after executing steps S205 and S207.

  Incidentally, the memory control unit 133C also has an operation mode for executing entry deletion without referring to the static flag. Specifically, when an access request RQ including an entry forced deletion instruction is received from the input / output device 14, the memory control unit 133C grasps the operation state of the entry holding circuit 12 according to the entry forced deletion instruction. In the appropriate processing cycle period, the entry deletion process of FIG. 7 is executed instead of the entry deletion process (FIG. 11) referring to the static flag. As a result, depending on the situation, entry data including a significant static flag can be forcibly invalidated to secure a free space.

  Next, an entry registration process for registering entry data including entity data that matches the specific data will be described with reference to FIGS. When the access request RQ including the entry registration instruction is received from the input / output device 14, the memory control unit 133C grasps the operation state of the entry holding circuit 12 according to the entry registration instruction, and performs an appropriate processing cycle period. The entry registration process of FIG. 12 is started.

If it is determined in step S303 that the entry data with the identifier # (i) includes entity data that matches the specific data to be registered (YES in step S303), the memory control unit 133C has the identifier # (i). It is determined whether or not the static flag held in the register circuit 40 _i is significant (step S304). If the static flag is significant, that is, if the static flag has a mask value (YES in step S304), the memory control unit 133C does not invalidate the entry of the identifier # (i) (step S305). Then, the input / output device 14 is notified via the transmission / reception unit 131 that the static flag cannot be updated (step S335), and the entry registration process is terminated.

  On the other hand, it is determined that the entry data of all identifiers # (0) to # (n-1) does not include entity data that matches the specific data to be registered, and the entry of identifier # (n-1) is valid. If so (NO in step S325), the memory control unit 133C executes an entry search process (step S326) to create a free area.

  Referring to FIG. 13, the memory control unit 133C sets a zero value for the variable k (step S341), and determines whether or not the static flag of the identifier # (k) is significant (step S342). When the static flag of the identifier # (k) is significant (YES in step S342), the memory control unit 133C determines whether or not the variable k has reached the identifier number n-1 indicating the highest entry. (Step S343) If the variable k has not reached n−1 (NO in Step S343), the variable k is incremented by 1 (Step S345), and the procedure returns to Step S342.

  If the static flags of all identifiers # (0) to # (n−1) are significant in the flowchart of FIG. 13, the variable k reaches n−1 (YES in step S343). In this case, the memory control unit 133C notifies the input / output device 14 that registration is impossible via the transmission / reception unit 131 (step S347), and ends the entry registration process. In place of the notification that registration is impossible (step S347), another process may be performed.

  If it is determined in step S342 that the static flag of identifier # (k) is not significant (NO in step S342), the memory control unit 133C returns the process to the flowchart of FIG. Next, the memory control unit 133C invalidates the entry of the identifier # (k) (Step S328). Thereafter, in the next processing cycle period, the above-described entry rearrangement process (FIG. 5) is executed, and the process waits until the entry of the identifier # (n−1) is invalidated (NO in step S329). When the invalidation of the entry with the identifier # (n−1) is completed (YES in step S329), the memory control unit 133C sequentially executes steps S331 and S333, and ends the entry registration process.

  By the way, the memory control unit 133C has an operation mode in which entry registration is executed without referring to the static flag. Specifically, when an access request RQ including an entry forced registration instruction is received from the input / output device 14, the memory control unit 133C recognizes the operation state of the entry holding circuit 12 according to the entry forced registration instruction. Instead of the entry registration process (FIGS. 12 and 13) referring to the static flag, the entry registration process of FIG. Thus, entry registration can be forcibly performed regardless of the value of the static flag depending on the situation.

  As described above, according to the second embodiment, specific entry data can be prevented from being changed, so that the flexibility of operations such as registration and deletion (invalidation) of entry data can be improved. it can.

Note that the memory control unit 133C writes the invalid flag to a data storage area that does not hold a significant static flag among the data storage areas M _{0 to} M _n−1 , thereby entering entry data including a static flag that is not significant. An operation for deleting all at once can be easily incorporated.

Embodiment 3 FIG.
Next, a third embodiment according to the present invention will be described. The configuration of the data storage device of the third embodiment is the same as the configuration of the data storage device 11 of the first embodiment except that the operation mode is different. For the first embodiment, the flag area 22 of the data storage area M _i in the entry holding circuit 12 has been described the operation in the case of storing a single control flag (valid flag). In this embodiment, the flag area 22 of the data storage area _{M i,} as shown in FIG. 14 (A), 2 two regions 22A, as shown (B), the are functionally divided into 22B, one region 22A Stores the valid flag, and the other area 22B stores a deletion flag. Deletion flag, the data storage area Valid values indicating that the invalidation is scheduled entry data stored in the M _i (e.g. the value of "1"), is held in the data storage area M _i Entry It has one of an invalid value (for example, a value of “0”) indicating that data invalidation is not scheduled. Hereinafter, a deletion flag having a valid value is referred to as “valid deletion flag”, and a deletion flag having an invalid value is referred to as “invalid deletion flag”.

Memory controller 133C is one whole or a part of the processing cycle period T _A in the data storage area M ₀ ~M _n-1 to write an effective deletion flag, the processing cycle after a predetermined set time period ΔT has elapsed T _B In addition, it has a function of invalidating (deleting) all the entry data including the valid deletion flag by writing the invalid flag in all the data storage areas holding the valid deletion flag. As a result, free areas can be secured together in the entry holding circuit 12. However, when any of the entry data is updated within the set period ΔT, the memory control unit 133C writes an invalid deletion flag in the data storage area that holds the updated entry data. Any entry data registered within the set period ΔT includes an invalid deletion flag. Thus, the processing cycle period T _B after a lapse of a set period [Delta] T, is not invalidated (deleted) entry data updated or registered within a set period [Delta] T.

Further, when an access request RQ including a deletion flag assignment instruction is received from the external input / output device 14, the memory control unit 133 _</ b _> C responds to the deletion flag assignment instruction in the data storage areas M _{0 to} M _n−1 . A valid deletion flag is written by writing a valid deletion flag to all or part of the data storage area and writing an invalid flag to all of the data storage areas holding the valid deletion flag in a processing cycle period after a predetermined set period ΔT has elapsed. It also has a function of deleting all the entry data including it. Also in this case, when any of the entry data is updated within the set period ΔT, the memory control unit 133C writes an invalid deletion flag in the data storage area that holds the updated entry data. In addition, any entry data registered within the set period ΔT includes an invalid deletion flag.

  Furthermore, the memory control unit 133 </ b> C responds to the free area reservation instruction from the external input / output device 14 and waits for the elapse of the set period ΔT without invalidating all data storage areas that hold valid deletion flags. It also has a function of invalidating (deleting) entry data including a valid deletion flag in a batch.

  By having the above function, the data storage device 11 can perform control to secure the free areas of the entry holding circuit 12 together. For example, even before the entry holding circuit 12 is full of valid entries, entry data that has passed for a certain period since registration or update is automatically deleted, and entry data having a lower priority is entered. It is possible to control such that it does not remain inside.

  Next, the operation of the data storage device 11 according to the third embodiment using the deletion flag will be described with reference to FIG. FIG. 15 is a flowchart schematically showing an example of the entry operation control process according to the third embodiment. When a certain time is reached, or when an access request RQ including a deletion flag assignment instruction is received from the external input / output device 14, the control processing of FIG. 15 is started accordingly.

First, the memory control unit 133C initializes the variable i and sets the variable i to a zero value (step S401). Next, the memory control unit 133C sets a valid deletion flag in the entry of the identifier # (i) (Step S403). Specifically, the memory control unit 133C causes the entry selector 60 _i of the register circuit 40 _i (FIG. 4) with the identifier # (i) to select the output data AD _i of the own entry data control circuit 70 _{i. i} supplying, supplies a control signal C _i to generate replacement data AD _i including effective deletion flag in the own entry data control circuit 70 _i. After setting a valid deletion flag (step S403), it is determined whether the variable i has reached the identifier number n-1 (step S405). If the variable i has not reached n−1 (NO in step S405), the memory control unit 133C increments the variable i by 1 (step S407), and returns the procedure to step S403.

  When the variable i reaches n−1 (YES in step S405), the memory control unit 133C waits until the set time ΔT has elapsed and the set time has come (NO in step S409). When the set time arrives (YES in step S409), the memory control unit 133C initializes the variable i and sets the variable i to a zero value (step S411). Next, the memory control unit 133C determines whether or not the deletion flag of the identifier # (i) is valid (step S413). If the deletion flag is valid (YES in step S413), the memory control unit 133C invalidates the entry of the identifier # (i) (step S415). Next, it is determined whether or not the variable i has reached n−1 (step S417). On the other hand, if the deletion flag is not valid (NO in step S413), the memory control unit 133C skips the invalidation of the entry (step S415) and determines whether or not the variable i has reached n-1. (Step S417). If the variable i has not reached n−1 (NO in step S417), the memory control unit 133C increments the variable i by 1 (step S419), and returns the procedure to step S413. Thereafter, when the variable i reaches n−1 (YES in step S417), the process ends.

  By the above processing, entry data that has not been registered or updated can be deleted after a certain period. Note that the processing of steps S401 to S407 is completed within one processing cycle period, and the processing of steps S411 to S417 is also completed within one processing cycle period.

  By the way, in the above control process, after executing invalidation of entry data including a valid deletion flag (step S415), a procedure for executing a process for setting a valid deletion flag to an entry to be invalidated later may be added. Good. Moreover, the process of said step S401-S407 and the process of step S411-S419 may be performed as a separate process. Furthermore, the processes in steps S401 to S407 may be performed after the processes in steps S411 to S419.

  As described above, if the data storage device of the third embodiment is used, the storage capacity required for entry data is increased, but entry data that has not been registered or updated within a certain period of time is deleted collectively. Can do. Further, control based on a memory management algorithm such as an LRU algorithm can be continuously executed.

Embodiment 4 FIG.
Next, a fourth embodiment according to the present invention will be described. The data storage device of the fourth embodiment has the same configuration as the data storage device 11 of the first embodiment. In the fourth embodiment, in addition to the above function, the entry update control unit 133 is referred to most recently among the entry data held in the data storage areas M _{0 to} M _n−1 in the entry holding circuit 12. The entry data is held in the uppermost data storage area M _n−1 . FIG. 16 is a flowchart schematically showing a procedure of entry update processing for realizing this function.

  When the access request RQ including the data reference request is received from the input / output device 14, the data search unit 133A receives the entity data specified by the data reference request from the entry data group 31 in response to the data reference request. The actual data is acquired and transmitted to the input / output device 14 via the transmission / reception unit 131. On the other hand, the memory control unit 133C grasps the operation state of the entry holding circuit 12 in response to the data reference request, and starts the entry update process of FIG. 16 in an appropriate processing cycle period.

First, the memory control unit 133C determines whether entry data referenced by the data reference request (hereinafter referred to as "reference data".) Access ranking data storage area M _p for holding the most significant ( Step S501). When it is determined that the reference data is stored in the highest data storage area M _n−1 (YES in step S501), the memory control unit 133C ends the entry update process. On the other hand, when it is determined that the reference data is not held in the highest data storage area M _n−1 (NO in step S501), the memory control unit 133C determines that the highest entry of the identifier # (n−1) is It is determined whether or not it is invalid (step S503). If the highest entry is invalid (YES in step S503), the memory control unit 133C executes reference data write control to the entry with the identifier # (n-1) (step S509). Specifically, the memory control unit 133C supplies a selection control signal SEL _n−1 that causes the highest-level entry selector 60 _n−1 to select the replacement data OD _n and replaces the reference data in the entry selector 60 _n−1. Supply as data OD _n . As a result, the register 50 _n-1 latches (holds) the reference data OD _n input via the entry selector 60 _n-1 .

  On the other hand, when it is determined in step S503 that the highest entry is not invalid (NO in step S503), the memory control unit 133C invalidates the entry of the identifier # (p) that holds the reference data (step S505). . Thereafter, in the next processing cycle period, the above-described entry rearrangement process (FIG. 5) is executed, and the process waits until the highest entry of the identifier # (n−1) is invalidated (NO in step S507). When the invalidation of the highest entry is completed (YES in step S507), the memory control unit 133C executes reference data write control for the highest entry (step S509), and ends the entry update process.

17A to 17D show data storage areas M _{0 to} M when the entry update process of FIG. 16 is executed for the data storage areas M _{0 to} M ₆ when the maximum number of entries is 7. ₆ is a diagram illustrating a state transition state of FIG. As shown in FIG. 17A, in the initial state, the entries of all the data storage areas M _{0 to} M ₆ are valid, and the data storage areas M _{0 to} M ₆ hold the entry data D0 to D6, respectively. doing. When the entry data D3 is referred to in response to the data reference request, as shown in FIG. 17B, the entry of the identifier # (3) holding the reference data D3 is invalidated (step S505 in FIG. 16). ). In the next processing cycle period, a shift operation and invalidation processing of the top entry are executed. As a result, as shown in FIG. 17C, the entry data D4, D5, and D6 are shifted to the entries of the identifiers # (3), # (4), and # (5), respectively. Thereafter, as shown in FIG. 17 (D), reference data D3 in the data storage area _{M 6} identifier # (6) is written (step S509 in FIG. 16).

As described above, according to the fourth embodiment, the entry data that is referred to most recently can always be held in the highest data storage area M _n−1 . Therefore, it is possible to realize a memory management algorithm that gives the highest priority to the entry data that has been referred to most recently.

Modified example of the first to fourth embodiments.
Although various embodiments according to the present invention have been described with reference to the drawings, these are examples of the present invention, and various forms other than the above can be adopted. For example, as shown in FIG. 18 (A), (B) , the flag area 22 of the data storage area _{M i} 3 one region 22A, 22B, functionally divided into 22C, the valid flag in the area 22A The static flag may be stored in the area 22B, and the deletion flag may be stored in the area 22C. Thereby, the data storage device 11 can execute processing using the valid flag, the static flag, and the deletion flag. Specifically, even for entry data that has not been registered or updated within the set period ΔT, entry data that includes a significant static flag can be excluded from batch deletion. For example, it is determined whether or not the static flag of identifier # (i) is significant. If the static flag is significant, a valid deletion flag is not set in step S403 of FIG. If not significant, a valid deletion flag may be set in step S403.

  In the first to third embodiments, the entry holding circuit 12 has a shift register circuit configuration, but is not limited to this. When the data storage device 11 is applied to a system that does not require a high access speed to the entry holding circuit 12, the entry holding circuit 12 may be constituted by a RAM (Random Access Memory).

  All or some of the functions of the entry control circuit 13 may be realized by hardware, or may be realized by a computer program executed by a microprocessor such as a CPU (Central Processing Unit). When the function is realized by a computer program, the microprocessor can realize the function by loading and executing the computer program from a computer-readable recording medium.

DESCRIPTION OF SYMBOLS 1 Data processing system, 11 Data storage device, 12 Entry holding circuit, 13 Entry control circuit, 131 Transmission / reception part, 132 Entry data receiving part, 133 Entry update control part, 133A Data search part, 133B Area | region detection part, 133C Memory control part , 14 I / O device, M _{0 to} M _n-1 data storage area, 21 data area, 40 ₀ to 40 _n-1 register circuit, 50 ₀ to 50 _n-1 register, 60 _{0 to} 60 _n-1 entry selector, 70 ₀ to 70 _n-1 Own entry data control circuit.

Claims (5)

An entry holding circuit having a plurality of data storage areas each assigned an access order, and holding entry data in each data storage area in the order of access from an external device;
An entry control circuit that executes writing of the entry data to the plurality of data storage areas in response to an access request from the external device;
Each of the data storage areas is
Valid to store a valid flag having one of a valid value for validating the entry data held in the data storage area and an invalid value for invalidating the entry data held in the data storage area Flag area,
A data area for storing the actual data of the entry data,
The entry control circuit sets the validity flag from the data storage area having the lowest access order to the data storage area having the lowest access order in order from the lowest data storage area while the entry data is not being written. Having a memory control unit for determining whether to have the invalid value;
If the result of the determination is that it does not have the invalid value, the memory control unit is the data storage that is one higher than the access order of the data storage area that has been determined not to have the invalid value. Proceed to region determination,
When the determination result is that the invalid value is included, the memory control unit has the access rank higher than the access rank of the data storage area that is determined to have the invalid value. The entry data held in the storage area is shifted to the data storage area one level lower, and the valid flag having the invalid value in the valid flag area of the highest data storage area in the access order And the process proceeds to the determination of the data storage area one level higher than the access order of the data storage area determined to have the invalid value.
A data storage device. The data storage device according to claim 1,
The entry holding circuit generates replacement data for changing part or all of the entry data, and each of the entry holding circuits rewrites the entry data held in the data storage area to the replacement data. For data storage,
A data storage device. The data storage device according to claim 1 or 2 ,
Each of the data storage areas is
A value indicating that the entry data held in each data storage area is scheduled to be invalidated, and a value indicating that the entry data held in each data storage area is not scheduled to be invalidated; A deletion flag area for storing a deletion flag having one of the values of
The memory control unit writes a deletion flag having a value indicating that the entry data is scheduled to be invalidated to any one of the plurality of data storage areas, and the entry data is invalidated after a predetermined set period. A valid flag having the invalid value is written in all of the data storage areas holding a deletion flag having a value indicating that the conversion is scheduled.
A data storage device. A data storage device according to claim 3,
The memory control unit indicates that the entry data is scheduled to be invalidated when there is a request from the external device to secure a free space in each data storage area before the predetermined set period has elapsed. Write a valid flag having the invalid value to all of the data storage areas holding the deletion flag having a value,
A data storage device. A data storage device according to any one of claims 1 to 4,
The entry control circuit further includes a data search unit that searches for the entity data held in the data area of the data storage area in which the validity flag has a valid value among the data storage areas,
When the same entity data is allowed to be stored redundantly when a new access request is made from the external device, the valid flag has an invalid value in the data storage area of the data storage area. Write the entry data entity data in response to a new access request,
When it is not permitted to store the same entity data in duplicate, the data search unit searches the entity data of the entry data corresponding to the new access request, and the entry data corresponding to the new access request When the actual data is retrieved by the data retrieval unit, the data storage area is not written.
A data storage device.

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