JP5519837B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory.

  In a nonvolatile semiconductor memory such as a flash memory, it is known to connect a local bit line to a memory cell and connect a plurality of local bit lines to a common global bit line (see, for example, Patent Documents 1-3). ). In this type of semiconductor memory, a sense amplifier is connected to the local bit line, and the logic of data held in the memory cell is read without using a reference cell. For example, in a read operation, after precharging a bit line, the voltage of the bit line is changed by a cell current flowing in a memory cell to be accessed, and data is read by detecting the change in voltage with a sense amplifier (for example, patent Reference 4-5).

  A nonvolatile semiconductor memory that changes the activation timing of a sense amplifier in a read operation in accordance with an operation mode is known (see, for example, Patent Document 6). In addition, a nonvolatile semiconductor memory is known that generates a sense amplifier activation timing by changing a voltage of a reference bit line by a current flowing in a reference memory cell in a read operation (see, for example, Patent Document 7).

  A nonvolatile semiconductor memory is known in which a switch for connecting each bit line to a ground line is provided, and a bit line adjacent to a bit line from which data is read from a memory cell is connected to the ground line via the switch (for example, (See Patent Literature 8-10.)

International Publication WO2002 / 082460 JP 2003-36203 A JP 2004-318941 A Japanese Patent Laid-Open No. 10-275489 JP 2001-160297 A JP 2002-367390 A JP 2007-87512 A JP-A-9-293389 JP 2001-325797 A JP 2004-158111 A

  The number of transistors formed in the semiconductor memory is reduced, and the chip size of the semiconductor memory is reduced.

  In one embodiment of the present invention, a semiconductor memory includes a plurality of nonvolatile memory cells each having a cell transistor including a control gate and a floating gate, a plurality of bit lines connected to the cell transistors, and a common connection to the control gate. Common to each memory cell via each bit line, a selection switch that is connected to each word line, a bit line, a selection switch that connects the bit line to a common node, a precharge switch that connects the common node to a precharge line A sense amplifier that determines the logic of data read to the node, a reset switch that connects the common node to the ground line, and a selection corresponding to a memory cell that does not read data among all the selection switches that are turned on in the read operation Switch and the reset switch that is on. After full temporarily turns on the precharge switch, and a operation control circuit for activating a word line.

  By performing the operation of resetting the bit line to the ground voltage using a selection switch used for reading and writing data and a common reset switch, the number of transistors formed in the semiconductor memory can be reduced, and the chip of the semiconductor memory The size can be reduced.

1 illustrates an example of a semiconductor memory in one embodiment. The example of the semiconductor memory in another embodiment is shown. 3 shows an example of the monitor voltage generator and the timing generator shown in FIG. 3 shows an example of the memory cell array shown in FIG. 5 shows an example of the layout of the memory cell array shown in FIG. 5 shows an example of the structure of the real cell transistor shown in FIG. An example of the structure of a normal transistor is shown. 3 shows an example of the layout of the replica unit shown in FIG. FIG. 9 shows an example of the layout of the replica portion excluding the floating gate pattern from FIG. 8. 9 shows an example of the structure of the replica cell transistor shown in FIGS. 3 shows an example of a buffer circuit formed in the memory cell array and the Y control circuit shown in FIG. 3 shows an example of erase verify operation and read operation (logic 1 read) of the semiconductor memory shown in FIG. 3 shows an example of a program verify operation and a read operation (logic 0 read) of the semiconductor memory shown in FIG. 3 shows an example of a read operation of the semiconductor memory shown in FIG. 3 shows an example of a write operation of the semiconductor memory shown in FIG. An example of a system in which the above-described semiconductor memory is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a semiconductor memory MEM in one embodiment. For example, the semiconductor memory MEM is a nonvolatile semiconductor memory such as a flash memory. The semiconductor memory MEM includes a memory cell MC, a precharge transistor PT, a sense amplifier SA, and a timing generation unit TGEN. The memory cell MC has a real cell transistor CT including a floating gate FG and a control gate CG. The control gate CG is connected to the word line WL. For example, the drain of the real cell transistor CT is connected to the bit line BL, and the source of the real cell transistor CT is connected to the source line SL.

  As shown in FIG. 2, the semiconductor memory MEM may have a memory cell array 32. At this time, the sense amplifiers SA are formed corresponding to the plurality of bit lines BL, respectively. When the bit line has a hierarchical structure, the sense amplifier SA may be formed for each global bit line formed corresponding to a predetermined number of bit lines BL.

  The precharge transistor PT is, for example, a pMOS transistor, and is turned on when a low level precharge signal PREX is received at the gate to supply a precharge voltage VPR lower than the power supply voltage VDD to the bit line BL. For example, the power supply voltage VDD is 1.2V, and the precharge voltage VPR is 0.9V. In the read operation, the sense amplifier SA operates in response to the activation of the sense amplifier enable signal SAE, and determines the logic held in the memory cell MC according to the voltage of the bit line BL. The sense amplifier SA outputs a data signal DT indicating the determined logic.

  The timing generation unit TGEN includes CMOS inverters IV1 and IV2 connected in series, and a capacitor C1 connected between the output node N01 of the CMOS inverter IV1 and the ground line VSS. The input of the CMOS inverter IV1 receives an operation enable signal RDEN that is activated to a high level during a read operation. The CMOS inverter IV1 has a replica cell transistor RCT arranged between the pMOS transistor PM and the nMOS transistor NM. That is, the drain of the pMOS transistor PM is connected to the drain of the nMOS transistor NM via the replica cell transistor RCT. The nMOS transistor NM operates as a switch transistor that connects the source of the replica cell transistor RCT to the ground line VSS when the operation enable signal RDEN is activated to a high level. The CMOS inverter IV2 operates as a buffer circuit that generates the sense amplifier enable signal SAE having a high level equal to the power supply voltage VDD in response to the change of the output node N01 from the high level to the low level.

  In the replica cell transistor RCT, a control gate and a floating gate are connected to each other. An example of the structure of the replica cell transistor RCT is shown in FIG. Replica cell transistor RCT functions as a high resistance whose resistance between source and drain changes according to control voltage VSA received at the control gate. The control voltage VSA is a constant voltage and is supplied to the control gate CG of the replica cell transistor RCT regardless of the operation of the semiconductor memory MEM. The capacitor C1 has a capacitance value corresponding to the load capacitance of the bit line BL.

  In this embodiment, in the read operation, the word line WL is activated to a high level, and the precharge signal PREX is deactivated to a high level. The precharge operation of the bit line BL is stopped by deactivation of the precharge signal PREX. When the threshold voltage of the real cell transistor CT is low (for example, holding logic 1), a cell current flows from the bit line BL to the source line SL via the real cell transistor CT in response to the activation of the word line WL. The voltage of the bit line BL gradually decreases. When the threshold voltage of the real cell transistor CT is high (for example, maintains logic 0), the cell current does not flow, and the voltage of the bit line BL maintains the precharged voltage.

  On the other hand, the operation enable signal RDEN is activated to a high level in accordance with the later timing of the activation timing of the word line WL or the deactivation timing of the precharge signal PREX. The activation of the operation enable signal RDEN stops the precharge operation of the node N01 by the pMOS transistor PM, and the nMOS transistor NM is turned on. When the nMOS transistor NM is turned on, the node N01 is connected to the ground line VSS via the replica cell transistor RCT, and the voltage of the node N01 gradually decreases. At this time, the control voltage VSA is supplied not only to the control gate CG but also to the floating gate FG. Therefore, the operation of the replica cell transistor RCT can be controlled with the same accuracy as a normal transistor. On the other hand, when the floating gate FG is interposed, the floating gate FG acts as a capacitor, so that it is difficult to control the state of the channel region by the voltage of the control gate CG.

  Furthermore, since the load capacity of the node N01 is matched with the load capacity of the bit line BL, the decrease speed of the node N01 can be matched with the decrease speed of the bit line BL. Further, since the precharge voltage of the node N01 is set to the power supply voltage VDD, the power supply voltage VDD can be supplied to the inverter IV2, and the sense amplifier enable signal SAE can be generated without interposing a level shifter or the like. On the other hand, when the node N01 is set to the same precharge voltage VPR as that of the bit line BL, it is necessary to supply the precharge voltage VPR instead of the power supply voltage VDD in order to prevent power leakage of the inverter IV2. As a result, a level shifter for converting the high level of the sense amplifier enable signal SAE from the precharge voltage VPR to the power supply voltage VDD is required, and it becomes difficult to suppress variations in the activation timing of the sense amplifier enable signal SAE. As described above, in this embodiment, the activation timing of the sense amplifier enable signal SAE can be controlled with high accuracy.

  The timing generation unit TGEN activates the sense amplifier enable signal SAE to a high level when the node ND01 changes from a high level to a low level. The sense amplifier SA operates in response to the activation of the sense amplifier enable signal SAE, inverts the logic level appearing on the bit line BL, and outputs it to the data line DT. Then, the read operation is completed. The semiconductor memory MEM performs the same operation as the read operation described above in the program verify operation during the write operation and the erase verify operation during the erase operation. That is, the program verify operation and the erase verify operation are a kind of read operation.

  As described above, in this embodiment, the activation timing of the sense amplifier enable signal SAE can always be optimally generated regardless of the variation in the manufacturing conditions of the semiconductor memory MEM. In particular, the activation timing of the sense amplifier enable signal SAE can be controlled with high accuracy by short-circuiting the floating gate FG of the replica cell transistor RCT with the control gate CG. As a result, the read margin of the semiconductor memory MEM can be improved.

  FIG. 2 shows an example of a semiconductor memory MEM in another embodiment. For example, the semiconductor memory MEM is a nonvolatile semiconductor memory such as a flash memory. The semiconductor memory MEM includes a command generation circuit 10, a test mode control circuit 12, a data input / output circuit 14, an internal voltage generation circuit 16, a CAM access control circuit 18, a CAM (Content Addressable Memory), an operation control circuit 22, and an internal address generation circuit. 24, an address selection circuit 26, a memory core 28, and a bus control circuit 30.

  The command generation circuit 10 receives the chip enable signal CEX, the write enable signal WEX, the data signal DIN00-15, and the like as command signals in synchronization with the clock signal CLK. Note that the semiconductor memory MEM may operate asynchronously with the clock signal CLK. When the command signal indicates a read command, the command generation circuit 10 outputs a read control signal RD to execute a read operation. When the command signal indicates a write command, the command generation circuit 10 outputs a program control signal PGM in order to execute a write operation. When the command signal indicates an erase command, the command generation circuit 10 outputs an erase control signal ERS in order to execute an erase operation. When the command signal indicates a test command, the command generation circuit 10 outputs a test mode signal TM.

  The test mode control circuit 12 outputs a plurality of test control signals TCNT in order to set the internal state (initial value) of the semiconductor memory MEM according to the address signal FA (FA00 to FA20) supplied together with the test command. For example, the value held in the CAM is changed by the test control signal TCNT, and the value of the internal voltage generated by the internal voltage generation circuit 16 is changed.

  The data input / output circuit 14 receives write data via the data input terminals DIN (DIN00 to DIN15) during the write operation, and outputs the received data to the input data line DTIN. The data input / output circuit 14 receives read data from the memory core 28 via the output data line DTOUT during a read operation, and outputs the received data to the data output terminals DO (DO00 to DO15). The data input terminal DIN and the data output terminal DO are not limited to 16 bits. Further, the number of bits of the data input terminal DIN and the data output terminal DO may be different. For example, the number of bits of the data output terminal DO may be four times the number of bits of the data input terminal DIN.

  The internal voltage generation circuit 16 generates internal voltages HV1, HV2, HV3, VPR, NV and the like based on the power supply voltage VDD and the ground voltage VSS. The internal voltages HV1, HV2, and HV3 are higher than the power supply voltage VDD, and their values are HV1> HV2> HV3. The internal voltage VPR is a positive value lower than the power supply voltage VDD, and the internal voltage VN is a negative voltage. In the following description, the internal voltages HV1, HV2, HV3 and VPR are also referred to as high voltages HV1, HV2, HV3 and precharge voltage VPR, respectively. For example, the high voltage HV1 is used as a high level voltage (program voltage) of the word line WL (shown in FIGS. 4 and 11, etc.) during a write operation. The high voltage HV2 is used as a high level voltage (read voltage) of the word line WL during a read operation. The high voltage HV3 is used as a high level voltage (verify voltage) of the word line WL during a write verify operation during a write operation and an erase verify operation during an erase operation. Precharge voltage VPR is used to precharge local bit line BL and global bit line GBL shown in FIG. The negative voltage NV is used as a low level voltage (erase voltage) of the word line WL during the erase operation.

  The internal voltage generation circuit 16 includes a monitor voltage generation unit MVGEN that generates control voltages VSAEV and VSARD supplied to the timing generation unit TGEN. The control voltages VSAEV and VSARD are used to determine the operation timing of the sense amplifier SA shown in FIG. An example of the monitor voltage generator MVGEN is shown in FIG. The values of the control voltages VSAEV and VSARD generated by the internal voltage generation circuit 16 can be changed according to the setting information SINF read from the test control signal TCNT (trimming signal) or CAM. The power supply voltage VDD is also supplied to other circuits in the semiconductor memory MEM. When the power supply voltage VDD is assumed to fluctuate due to the chip temperature or the like, a constant power supply voltage that does not follow the fluctuation of the power supply voltage VDD may be generated by the internal voltage generation circuit 16 using the power supply voltage VDD.

  The CAM access control circuit 18 outputs a CAM write command to the CAM in response to the test control signal TCNT in order to write the setting information SINF for setting the values of the control voltages VSAEV and VSARD to the CAM. Similar to the memory cell array 32 shown in FIG. 4, the CAM has a plurality of nonvolatile memory cells having floating gates, and stores setting information SINF. In response to the read request from the command generation circuit 10, the CAM outputs setting information SINF stored in the memory cell to the internal voltage generation circuit 16. The internal voltage generation circuit 16 latches the setting information SINF from the CAM and generates control voltages VSAEV and VSARD according to the setting information SINF.

  In this embodiment, in the manufacturing process of the semiconductor memory MEM, the test control signal TCNT is supplied to the internal voltage generation circuit 16, and the test of the semiconductor memory MEM is performed while changing the values of the control voltages VSAEV and VSARD. Then, the optimum values of the control voltages VSAEV and VSARD are found. The setting information SINF indicating the optimum values of the control voltages VSAEV and VSARD is supplied to the CAM access control circuit 18 as the test control signal TCNT and written into the CAM. At this time, the address supplied from the address terminal FA indicates a position where the setting information SINF is written. By writing the setting information SINF to the CAM, the monitor voltage generation unit MVGEN generates optimal control voltages VSAEV and VSARD for each semiconductor memory chip MEM in order to increase the operation margin of each semiconductor memory chip MEM. Then, the semiconductor memory MEM is shipped.

  Thereafter, the semiconductor memory MEM mounted in the system SYS (FIG. 16) receives an initial setting command during the power-on sequence of the system SYS. The command generation circuit 10 outputs a read request to the CAM in response to the initial setting command. Based on the setting information SINF stored in the CAM, the control voltages VSAEV and VSARD are set to optimum values.

  The operation control circuit 22 outputs a plurality of operation control signals (timing signals) for operating the memory core 28 in response to the read control signal RD, the program control signal PGM, and the erase control signal ERS from the command generation circuit 10. The operation control circuit 22 includes a timing generation unit TGEN. The timing generation unit TGEN generates the activation timing of the sense amplifier SA (FIG. 11) using the control voltage VSARD during the read operation. The timing generation unit TGEN generates the activation timing of the sense amplifier SA using the control voltage VSAEV during a program verify operation during a write operation and an erase verify operation during an erase operation. An example of the timing generation unit TGEN is shown in FIG.

  The internal address generation circuit 24 sequentially generates internal address signals IA (column address signals) for selecting a plurality of global bit lines GBL during the erase verify operation during the erase operation. The address selection circuit 26 outputs an address signal or an internal address signal IA supplied via the address terminals (FA00 to FA20) as a row address signal RA and a column address signal CA. The row address signal RA is used to select a sector SEC and a word line WL in the selected sector SEC. The column address signal CA is used for selecting the bit line BL (FIG. 4 and FIG. 11 etc.) in the selected sector SEC. In this example, the 21-bit address signal FA00-20 is supplied to the semiconductor memory MEM, but the number of bits of the address signal FA is not limited to 21 bits.

  The memory core 28 includes a memory cell array 32, an X control circuit 34, a Y control circuit 36, a replica unit REP, a read amplifier RA, and a write amplifier WA. The memory cell array 32 has a plurality of sectors SEC (for example, 16). Each sector SEC has the same configuration except that the sector address is different. An example of the sector SEC is shown in FIG. 4 and FIG. The replica unit REP has a replica cell transistor RCT (FIG. 10) having the same element structure as the real cell transistor of the memory cell formed in the memory cell array 32. In FIG. 2, the replica portion REP is formed adjacent to the memory cell array 32, but may be formed at a position away from the memory cell array 32. Examples of the replica unit REP are shown in FIGS.

  X control circuit 34 receives the operation control signal and row address signal RA from operation control circuit 22, and sets word line WL and source line SL shown in FIGS. 4 and 11 to a predetermined voltage. An example of a signal generated by the X control circuit 34 is shown in FIG. The Y control circuit 46 has a decoder YDEC that receives the operation control signal and the column address signal CA from the operation control circuit 22 and generates a selection signal SECY for selecting the bit line BL shown in FIGS. Yes. The Y control circuit 46 has a read column switch RCSW (FIG. 11) that connects the global bit line GBL indicated by the column address signal CA to the read amplifier RA. Further, the Y control circuit 46 has a write column switch WCSW (FIG. 11) for connecting the global bit line GBL indicated by the column address signal CA to the write amplifier WA.

  The read amplifier RA operates during a read operation, and outputs read data received via the global bit line GBL to the common data bus CDB. The write amplifier WA operates during a write operation and outputs write data received via the common data bus CDB to any of the global bit lines GBL. The bus control circuit 30 outputs the read data received through the common data bus CDB during the read operation to the output data line DTOUT. The bus control circuit 30 outputs write data received via the input data line DTIN to the common data bus CDB during the write operation.

  FIG. 3 illustrates an example of the monitor voltage generation unit MVGEN and the timing generation unit TGEN illustrated in FIG. The monitor voltage generation unit MVGEN includes a pMOS transistor PM1 and resistors R1-R4 connected in series between the voltage line HVDD and the ground line VSS, and a comparator CMP connected to the gate of the pMOS transistor PM1. The voltage HVDD is generated by the internal voltage generation circuit 16 and is higher than the power supply voltage VDD. The monitor voltage generator MVGEN generates a control voltage VSARD used in the read operation from the connection node of the resistors R1 and R2. The monitor voltage generator MVGEN generates a control voltage VSAEV used in the program verify operation and the erase verify operation from the connection node of the resistors R2 and R3. The control voltage VSAEV is lower than the control voltage VSARD. For example, the control voltages VSARD and VSAEV are always generated while the power supply voltage VDD is supplied to the semiconductor memory MEM and not entered in the sleep mode or the like.

  The comparator CMP compares the divided voltage VND1 generated at the connection node ND1 of the resistors R3 and R4 with the reference voltage VREF, and generates a control voltage supplied to the gate of the pMOS transistor PM1. For example, the reference voltage VREF is generated by the internal voltage generation circuit 16 shown in FIG. The comparator CMP decreases the control voltage when the divided voltage VND1 is lower than the reference voltage VREF. As a result, the resistance between the source and drain of the pMOS transistor PM1 decreases and the voltage VND1 increases. The comparator CMP increases the control voltage when the voltage VND1 is higher than the reference voltage VREF. As a result, the resistance between the source and drain of the pMOS transistor PM1 is increased, and the voltage VND1 is decreased. With the above operation, the control voltages VSARD and VSAEV are held at constant values.

  As described above, the control voltages VSARD and VSAEV can be trimmed. Therefore, in an actual circuit, the resistor R1 includes a large number of sub-resistors connected in series, and the control voltage VSARD is generated from the connection node of one sub-resistance pair selected according to the setting information SINF. Similarly, the resistor R3 includes a large number of sub resistors connected in series, and the control voltage VSAEV is generated from the connection node of one sub resistor pair selected according to the setting information SINF.

  The timing generation unit TGEN includes a first generation unit TGEN1 used during a read operation, a second generation unit TGEN2 used during a program verify operation and an erase verify operation, and an OR circuit. The timing generation unit TGEN receives the power supply voltage VDD and operates. Since the first generation unit TGEN1 and the second generation unit TGEN2 are the same circuit, the first generation unit TGEN1 will be mainly described.

  The first generation unit TGEN1 includes a capacitor C1 connected between the CMOS inverters IV1 (R) and IV2 (R) connected in series and the output node N01 (R) of the CMOS inverter IV1 (R) and the ground line VSS. (R). The input of the CMOS inverter IV1 (R) receives an operation enable signal RDEN that is activated to a high level during a read operation. The operation enable signal RDEN is generated by the operation control circuit 22 shown in FIG. In the CMOS inverter IV1 (R), the drain of the pMOS transistor PM2 is connected to the drain of the nMOS transistor NM2 via the replica cell transistor RCT (R). In the replica cell transistor RCT (R), the control gate and the floating gate are connected to each other, and are formed in the replica portion REP shown in FIG. An example of the structure of the replica cell transistor RCT (R) is shown in FIG. Replica cell transistor RCT (R) functions as a high resistance whose resistance between source and drain changes according to control voltage VSARD received at the control gate.

  The first generation unit TGEN1 charges the capacitor C1 (R) via the pMOS transistor PM2 while the operation enable signal RDEN is inactivated to a low level. The first generation unit TGEN1 discharges the capacitor C1 (R) via the replica cell transistor RCT (R) and the nMOS transistor NM2 in response to the change of the operation enable signal RDEN to the high level. The first generation unit TGEN1 sets the output signal OUT (R) to a high level when the output node N01 (R) changes to a low level due to discharge. That is, the output signal OUT (R) changes to a high level after a predetermined delay time from the change of the operation enable signal RDEN to a high level.

  The second generation unit TGEN2 receives the operation enable signal EVEN that changes to a high level during the program verify operation and the erase verify operation at the input of the CMOS inverter IV1. The operation enable signal EVEN is generated by the operation control circuit 22 shown in FIG. In the replica cell transistor RCT (EV), a control gate and a floating gate are connected to each other, and are formed in the replica portion REP shown in FIG. An example of the structure of the replica cell transistor RCT (EV) is shown in FIG. Similar to replica cell transistor RCT (R), replica cell transistor RCT (EV) functions as a high resistance whose resistance between source and drain changes according to control voltage VSAEV received at the control gate.

  Similar to the first generation unit TGEN1, the second generation unit TGEN2 charges the capacitor C1 (EV) during the deactivation of the operation enable signal EVEN, and responds to the activation of the operation enable signal EVEN to a high level. The capacitor C1 (EV) is discharged. The second generation unit TGEN2 changes the output signal OUT (EV) to a high level after a predetermined delay time from the change of the operation enable signal EVEN to a high level. The OR circuit outputs the output signal OUT (R) or the output signal OUT (EV) as the sense amplifier enable signal SAE.

  FIG. 4 shows an example of the memory cell array 32 shown in FIG. FIG. 4 shows a partial area of the sector SEC in the memory cell array 32. The memory cell array 32 includes memory cells MC (one of which is indicated by a thick dashed-dotted frame) arranged in a matrix, word lines WL and source lines SL wired in the horizontal direction in FIG. 4, and vertical cells in FIG. It has bit lines BL wired in the direction. Each memory cell MC has a real cell transistor CT including a floating gate FG and a control gate CG.

  Each word line WL is commonly connected to the control gate CG of the real cell transistors CT arranged in the horizontal direction in FIG. In the following description, the word line WL is also referred to as a control gate line CG. Each source line SL is commonly connected to one of the source and drain of the real cell transistors CT arranged in the horizontal direction in FIG. Each bit line BL is commonly connected to the other of the source and drain of the real cell transistors CT arranged in the vertical direction in FIG. Thus, the memory cell array 32 has the same structure as a so-called NOR type flash memory.

  FIG. 5 shows an example of the layout of the memory cell array 32 shown in FIG. The range shown in FIG. 5 is the same as the range shown in FIG. In FIG. 5, a thick dashed-dotted frame indicates a region where one memory cell MC is formed. A broken line pattern indicates the diffusion layer DL. The shaded pattern indicates the first polysilicon wiring layer P1 in which the floating gate FG of the memory cell MC is formed. The two-dot chain line pattern shows the second polysilicon wiring layer P2 in which the word line WL and the control gate CG of the memory cell MC are formed. The thin solid line pattern indicates the first metal wiring layer M1 in which the source line SL and the like are formed. The thick solid line pattern is formed above the first metal wiring layer M1 (on the side far from the semiconductor substrate) and indicates the second metal wiring layer M2 where the bit lines BL and the like are formed.

  Squares marked with X indicate contact regions connecting the wiring layers or between the wiring layer and the diffusion layer DL. A contact region on the source line SL connects the first metal wiring layer M1 to the diffusion layer DL. The contact region formed on the bit line BL and off the source line SL connects the second metal wiring layer M2 (bit line BL) to the diffusion layer DL. In FIG. 5, the width of the diffusion layer DL is made larger than the width of the second metal wiring layer M <b> 2 in order to prevent the lines from overlapping and make it easy to see.

  FIG. 6 shows an example of the structure of the real cell transistor CT shown in FIG. The real cell transistor CT is formed by stacking a first insulating film INS1, a floating gate FG, a second insulating film INS2, and a control gate CG on the semiconductor substrate SS. The semiconductor substrate SS has a p-type well region PWELL (p−) and an n-type diffusion layer region DL (n +) selectively formed on the surface of the p-type well region PWELL (p−). The p-type well region PWELL (p−) facing the floating gate FG functions as a channel region of the real cell transistor CT. The two n-type diffusion layer regions DL (n +) function as a source region and a drain region of the real cell transistor CT.

  FIG. 7 shows an example of the structure of a normal transistor. A normal transistor is the nMOS transistor NM2 or the like shown in FIG. The semiconductor substrate SS is the same as in FIG. In a normal transistor, an insulating film INS and a gate wiring G1 formed using a polysilicon wiring layer PL are stacked on a semiconductor substrate SS.

  FIG. 8 shows an example of the layout of the replica unit REP shown in FIG. FIG. 8 shows a layout for forming the replica cell transistor RCT (EV) shown in FIG. The layout for forming the replica cell transistor RCT (R) is the same as that of FIG. 8 except that the pattern of the control voltage VSARD is formed instead of the pattern of the control voltage VSAEV. The types of lines for identifying each layout pattern are the same as in FIG.

  The replica unit REP has a layout similar to that of the memory cell array 32 shown in FIG. The difference between the replica part REP and the memory cell array 32 is that no contact is formed on the source line SL except for the replica cell transistor RCT, and that the floating gate FG has a long and narrow pattern like the control gate line CG shown in FIG. And the replica bit line RBL meanders.

  For example, the sizes of the source region, the drain region, and the channel region that are repeatedly arranged on the semiconductor substrate on which the replica portion REP is formed are the same as the size of the source region, the drain region, and The size of each channel region is the same. As a result, when the electrical characteristics of the real cell transistor CT change due to fluctuations in the manufacturing conditions of the semiconductor memory MEM, the electrical characteristics of the replica cell transistor RCT can be changed as well. Further, when the electrical characteristics of the real cell transistor CT change due to the temperature variation of the semiconductor memory MEM, the electrical characteristics of the replica cell transistor RCT can be changed in the same manner.

  The load capacity of the meandering replica bit line RBL corresponds to the capacity C1 (EV) shown in FIG. The wiring width and length of the meandering replica bit line RBL are set to be the same as the wiring width and length of one bit line BL (FIG. 4) wired in each sector SEC. The interval between contacts formed on the meandering replica bit line RBL is equal to the interval between contacts formed on one bit line BL wired in each sector SEC. As a result, the load capacity of the meandering replica bit line RBL is set to be the same as the load capacity of one bit line BL wired in each sector SEC. As described above, when the semiconductor memory MEM is manufactured, fluctuations in the wiring width and the like of the replica bit line RBL and the bit line BL can be made the same, and fluctuations in the load capacitance can be made the same. Therefore, the electrical characteristics of the replica bit line RBL and the bit line BL can be made substantially the same regardless of variations in manufacturing conditions. The bit line BL sandwiched between the meandering replica bit lines RBL functions as a dummy counter electrode line. The patterns of the upper and lower floating gates FG in FIG. 8 are formed thick in order to prevent the influence of halation or the like when the semiconductor memory MEM is manufactured.

  Since the floating gate FG of the replica cell transistor RCT has a long pattern length, the resistance and the load capacitance are large. However, the control voltage VSAEV supplied to the floating gate FG of the replica cell transistor RCT is maintained at a constant value while the power supply voltage VDD is supplied to the semiconductor memory MEM. For this reason, it is not necessary to consider the delay time due to the longer pattern of the floating gate FG.

  The replica cell transistor RCT indicated by a thick dashed-dotted frame is formed at substantially the center of the replica portion REP. Floating gate FG of replica cell transistor RCT extends to connection region CNA of control voltage line VSAEV. The floating gate FG is connected to the control voltage line VSAEV (first metal wiring layer M1) through a contact in the connection region CNA. The control voltage line VSAEV is connected to the control gate line CG (second polysilicon layer P2) through a contact. That is, the floating gate FG and the control gate CG of the replica cell transistor RCT are connected to each other. By connecting the floating gate FG and the control gate CG away from the replica cell transistor RCT, the shape of the replica cell transistor RCT can be made substantially the same as that of the real cell transistor CT. As a result, the electrical characteristics of the replica cell transistor RCT can be made substantially the same as the electrical characteristics of the real cell transistor CT.

  FIG. 9 shows an example of the layout of the replica portion REP excluding the pattern of the floating gate FG from FIG. In FIG. 9, the contact connected to the floating gate FG is also deleted. The pattern of the control gate line CG is formed similarly to the pattern of the word line WL of the memory cell array 32 shown in FIG.

  FIG. 10 shows an example of the structure of the replica cell transistor RCT (RCT (R), RCT (EV)) shown in FIG. 3 and FIG. The structure of the replica cell transistor RCT is the same as that of the real cell transistor CT shown in FIG. 6 except that the floating gate FG and the first insulating film INS1 are formed long together with the control gate CG. Thereby, the electrical characteristics of the cell current flowing between the source and the drain of the replica cell transistor RCT can be made the same as the electrical characteristics of the cell current flowing between the source and the drain of the real cell transistor CT. For example, when the threshold voltage of the real cell transistor CT becomes higher than the standard value due to a change in manufacturing conditions of the semiconductor memory MEM, the threshold voltage of the replica cell transistor RCT also becomes high.

  In general, as the threshold voltage increases, the current flowing through the transistor decreases. When the cell current flowing through the memory cell MC decreases, it is necessary to lengthen the time until the magnitude of the cell current is detected by the sense amplifier SA (FIG. 11). In this embodiment, the cell current flowing through the replica cell transistor RCT changes similarly to the change in the cell current flowing through the memory cell MC. Therefore, as will be described with reference to FIGS. 12 and 13, the activation timing of the sense amplifier SA can always be optimally set in accordance with the variation in the cell current of the memory cell MC due to the change in the manufacturing conditions.

  FIG. 11 shows an example of the buffer circuit BUF, the read column switch RCSW, and the write column switch WCSW formed in the memory cell array 32 and the Y control circuit 36 shown in FIG. FIG. 11 shows a circuit for accessing the memory cells MC connected to the two word lines WL0 to WL1 and the eight bit lines BL0 to BL7 in the sector SEC0. The selection signal SECY (selection signals SECY0 to SECY7) is generated by the Y control circuit 36 shown in FIG. The precharge signals PR (PR0 to PR1), PREX, the read signal RD (RD0 to RD1), the reset signal RST, the sense amplifier enable signal SAE, and the activation period of the word line signal WL are the operation control circuit 22 shown in FIG. Is set according to the timing signal generated by.

  An nMOS transistor that receives selection signals SECY0 to SECY7 at its gate operates as a selection switch SSW for selecting any one of bit lines BL0 to BL7. The pMOS transistor that receives the precharge signal PREX at its gate operates as a precharge circuit that precharges the global bit line GBL to the precharge voltage VPR. The pMOS transistor that receives the precharge signal PREX is turned on when the precharge signal PREX is at a low level. Note that the precharge circuit that receives the precharge signal PREX may be arranged outside the sector SEC0. The nMOS transistors that receive the precharge signals PR0 to PR1 at their gates connect the global bit line GBL to the bit lines BL0 to BL7, and operate as precharge transistors or write transistors. When the nMOS transistor operates as a precharge transistor, the global bit line GBL is precharged to the precharge voltage VPR via a precharge circuit that receives the precharge signal PREX. When the nMOS transistor operates as a write transistor, the global bit line GBL is set to a voltage indicating the logic of write data via the write amplifier WA and the write column switch WCSW.

  The nMOS transistors that receive the read signals RD0 to RD1 at their gates operate as read switches that are turned on when reading the logic of data held in the memory cells MC. The read switch is turned on during a read operation, a program verify operation, and an erase verify operation. The nMOS transistor that receives the reset signal RST at its gate operates as a reset switch that connects the common node COM to the ground line VSS during a standby period in which the semiconductor memory MEM is not accessed. The bit lines BL0 to BL7 are clamped to a low level (VSS) during the standby period by the reset switch.

  The nMOS transistor NM3 having the common node COM connected to the gate operates as a sense amplifier SA that generates a drain voltage according to the voltage of the common node COM that changes depending on the storage state of the memory cell MC. That is, the sense amplifier SA determines the logic of data read from the memory cell MC to the common node COM via any of the bit lines BL0-7. The nMOS transistor NM4 that receives the sense amplifier enable signal SAE at its gate transmits the result of amplification by the sense amplifier SA to the global bit line GBL. In this example, the sense amplifier area SAA is arranged between two memory cell units MCU. However, the sense amplifier area SAA may be arranged at one end of the sector SEC0 (the left end or the right end of the sector SEC0 in FIG. 11).

  The buffer circuit BUF includes a CMOS transmission gate TG, a latch circuit LTC, and an inverter IV3 connected in series between the read data line RDATA and the data line DT. Latch circuit LTC and inverter IV3 operate in response to power supply voltage VDD. The CMOS transmission gate TG connects the global bit line GBL to the read data line RDATA when the latch signal LT is at a low level. The latch signal LTX is a signal having a logic opposite to that of the latch signal LT. The latch circuit LTC operates as an inverter when the latch signal LT is at a low level, and latches a logic level corresponding to the voltage of the global bit line GBL in synchronization with the rising edge of the latch signal LT. The inverter IV3 is supplied to the input of the latch circuit LTC and outputs the logic level held in the latch circuit LTC to the data line DT.

  The read column switch RCSW is an nMOS transistor that is turned on when a high level read column selection signal RYSEL0 is received at the gate and connects the global bit line GBL to the read data line RDATA of the buffer circuit BUF. The write column switch WCSW is turned on when receiving a high level write column selection signal WYSEL0, and has a CMOS transmission gate that supplies write data WDATA from the write amplifier WA to the global bit line GBL.

  FIG. 11 shows a circuit corresponding to one global bit line GBL. For example, when the memory cell array 32 has 128 global bit lines GBL, 128 circuits shown in FIG. 11 are formed. The global bit line GBL is selected by the read column switch RCSW or the write column switch WCSW that is turned on in response to the column address signal CA.

  FIG. 12 shows an example of the erase verify operation and read operation (logic 1 read) of the semiconductor memory MEM shown in FIG. When the erase verify operation and the read operation have different waveforms, the read operation waveform is indicated by a broken line. In the read operation, in order to read data at high speed, the activation voltage of the word line WL is set higher than that in the erase verify operation. Thereby, the current flowing through the real cell transistor CT can be increased, and the activation timing of the sense amplifier enable signal SAE and the latch signal LT can be advanced. As a result, read data can be output to the data output terminal DO quickly, and the access time can be shortened.

  In this example, the memory cell MC connected to the word line WL0 and the bit line BL1 of the sector SEC0 shown in FIG. 11 is accessed. For this reason, as shown in the upper right of FIG. 12, the selection signal SECY1 corresponding to the memory cell MC to be accessed is maintained at the high level VDD (for example, 1.2 V). The selection signals SECY4-7 corresponding to the memory cells MC not connected to the word line WL0 connected to the memory cell MC to be accessed are also maintained at the high level VDD. Note that the high logic level voltage of the selection signals SECY0-7 is not limited to the power supply voltage VDD. The read signal RD0 related to the accessed memory cell MC is maintained at the high level VDD, and the word line WL1 and the precharge signal PR1 not related to the accessed memory cell MC are maintained at the low level VSS. Note that the high logic level voltage of the read signal RD is not limited to the power supply voltage VDD. Source lines SL0-SL1 are set to low level VSS. The read column selection signal RYSEL0 shown in FIG. 11 is set to a high level, and the write column selection signal WYSEL0 is set to a low level.

  First, in the standby period STBY before the erase verify operation or the read operation is started, the reset signal RST, the read signal RD0-1 and the selection signal SECY0-7 are maintained at the high level VDD, and the reset switch shown in FIG. The read switch and the selection switch SSW connected to the bit lines BL0-7 are turned on (FIG. 12 (a)). Since all the selection signals SECY0-7 are activated to the high level, the bit lines BL0-BL7 are clamped to the low level VSS via the reset switch, the read switch, and the selection switch SSW.

  The global bit line GBL is precharged to a high level VPR (for example, 0.9 V) by a precharge signal PREX that is activated to a low level during the standby period STBY (FIG. 12B). The operation enable signals EVEN and RDEN are deactivated to a low level. Therefore, the nodes N01 (EV) and N01 (R) of the timing generation unit TGEN shown in FIG. 3 are set to the high level VDD, and the output signals OUT (EV) and OUT (R) are set to the low level VSS. (FIG. 12C). The output DT of the buffer circuit BUF shown in FIG. 11 is set to the high level VDD in response to the high level VPR of the global bit line GBL (FIG. 12 (d)).

  Next, the reset signal RST, the read signal RD1, and the selection signals SECY0 and 2-3 are deactivated to the low level VSS, and only the bit line BL1 is connected to the common node COM. (FIG. 12 (e)). Next, the precharge signal PR0 is activated to the high level VDD, and only the bit line BL1 is precharged via the global bit line GBL (FIG. 12 (f, g)). Before the precharge signal PR0 is deactivated to the low level VSS, the word line WL0 is activated to the high level (FIG. 12 (h)).

  After the word line WL0 is activated, the precharge signal PR0 is deactivated, and the bit line BL1 is set in a floating state in a precharged state (FIG. 12 (i)). When the threshold voltage of the memory cell MC to be erased or read is low, the cell current flows through the real cell transistor CT, so that the voltage of the bit line BL1 is lowered to the low level VSS.

  In response to the deactivation of the precharge signal PR0, the operation enable signal EVEN or RDEN is activated to a high level (FIG. 12 (j)). Note that the operation control circuit 22 shown in FIG. 2 may generate the timing signal for activating the word line WL0 after deactivating the precharge signal PR0. At this time, the operation enable signal EVEN or RDEN is activated in response to the activation of the word line WL0. That is, the operation enable signal EVEN or RDEN is activated in response to a slow timing among the deactivation timing of the precharge signal PR0 and the activation timing of the word line WL0.

  In response to the activation of the operation enable signal EVEN or RDEN, the timing generation unit TGEN illustrated in FIG. 3 passes the node N01 (EV) or N01 (R) via the replica cell transistor RCT (EV) or RCT (R). Connected to the ground line VSS. Thereby, the charge of the node N01 (EV) or N01 (R) is discharged through the replica cell transistor RCT (EV) or RCT (R). That is, the replica cell transistor RCT (EV) or RCT (R) flows a replica cell current.

  As the voltage of the node N01 (EV) or N01 (R) is decreased, the output signal OUT (EV) or OUT (R) changes to the high level VDD, and the sense amplifier enable signal SAE is activated to the high level VDD ( FIG. 12 (k, l, m)). Replica cell transistors RCT (EV) and RCT (R) are formed using the same manufacturing conditions as those of real cell transistor CT. For this reason, when the distribution of the cell current flowing through the real cell transistor CT shifts due to variations in manufacturing conditions, the replica cell current shifts in the same direction. Therefore, in the semiconductor memory chip MEM in which the cell current is relatively small and the decrease rate of the bit line BL1 is low, the activation timing of the sense amplifier enable signal SAE is also delayed. In the semiconductor memory chip MEM in which the cell current is relatively large and the decrease rate of the bit line BL1 is high, the activation timing of the sense amplifier enable signal SAE is also advanced. As a result, the activation timing of the sense amplifier enable signal SAE can always be optimally generated regardless of variations in the manufacturing conditions of the semiconductor memory MEM.

  In this embodiment, the control gate CG and the floating gate FG of the replica cell transistors RCT (EV) and RCT (R) are connected to each other. For this reason, the state of the channel region of the replica cell transistors RCT (EV) and RCT (R) can be controlled not only by the voltage of the control gate CG but also by the voltage of the floating gate FG. When the floating gate FG is not connected to the control gate CG, the insulating film INS2 and the floating gate FG shown in FIG. 10 act as a capacitor. At this time, it is difficult to control the state of the channel region by the voltage of the control gate CG. Furthermore, since the control gate CG and the floating gate FG are short-circuited, no charge is accumulated in the floating gate FG even when the semiconductor memory MEM is used for a long time. As described above, the operations of the replica cell transistors RCT (EV) and RCT (R) can be controlled with the same accuracy as a normal transistor. In other words, the activation timing of the sense amplifier enable signal SAE can be controlled with high accuracy.

  The activation of the sense amplifier enable signal SAE causes the nMOS transistor NM4 shown in FIG. 11 to connect the amplification transistor NM3 to the global bit line GBL. However, since the amplification transistor NM3 receives the low level of the bit line BL0 at the gate and is turned off, the voltage of the global bit line GBL does not change (FIG. 12 (n)). Thereafter, the latch signal LT is activated to a high level, and the logic level (VDD) of the data line DT is determined (FIG. 12 (o, p)).

  In the erase verify operation, it is determined that the threshold voltage of the memory transistor CT to be erased has been lowered to the erased state due to the high level VDD of the data line DT. When the memory cell MC is not in the erased state, the threshold voltage of the memory transistor CT is high and sufficient cell current does not flow. For this reason, as indicated by the alternate long and short dash line in FIG. 12, the voltage of the bit line BL1 is difficult to decrease (FIG. 12 (q)). As a result, the amplification transistor NM3 is turned on, the voltage of the global bit line GBL is changed to the low level VSS, and the data line DT is set to the low level VSS. At this time, the erase operation and erase verify operation are performed again.

  After the activation of the latch signal LT, the sense amplifier enable signal SAE and the word line WL0 are sequentially inactivated, and the reset signal RST, the read signal RD1, and the selection signal SECY1 are activated (FIG. 12 (r, s)). . In response to the deactivation of the reset signal RST, the semiconductor memory MEM enters the standby period STBY, and the operation enable signal EVEN or RDEN is deactivated (FIG. 12 (t)). Due to the deactivation of the operation enable signal EVEN or RDEN, the nodes N01 (EV) and N01 (R) change to a high level, and the output signals OUT (EV) and OUT (R) change to a low level VSS. Then, the erase verify operation or the read operation is completed (FIG. 12 (u, v)).

  FIG. 13 shows an example of the program verify operation and read operation (logic 0 read) of the semiconductor memory shown in FIG. Detailed descriptions of the same operations as those in FIG. 12 are omitted. When the program verify operation and the read operation have different waveforms, the read operation waveform is indicated by a broken line. In FIG. 13, similarly to FIG. 12, the memory cell MC connected to the word line WL0 and the bit line BL1 of the sector SEC0 is accessed. Except for the waveforms of the bit line BL1, the global bit line GBL, and the data line DT, they are the same as in FIG.

  In the program verify operation and the logic 0 read operation, the threshold voltage of the accessed real cell transistor CT is high. Therefore, no cell current flows and the bit line BL1 is held at the precharge voltage (FIG. 13A). The amplification transistor NM3 (that is, the sense amplifier SA) shown in FIG. 11 receives the high level of the bit line BL1. Therefore, when the sense amplifier enable signal SAE is activated, the global bit line GBL is connected to the ground line VSS and changes to a low level (FIG. 13B). The buffer circuit BUF shown in FIG. 11 outputs a low level to the data line DT in response to the low level change of the global bit line GBL (FIG. 13 (c)). The low level of the global bit line GBL is latched in synchronization with the latch signal LT (FIG. 13 (d)).

  Thereafter, in response to the activation of the reset signal RST, the precharge signal PREX shown in FIG. 11 is activated to a low level, and the global bit line GBL is set to the precharge voltage VPR in the standby period STBY ( FIG. 13 (e)). In response to the deactivation of the latch signal LT, the buffer circuit BUF takes in the low level of the global bit line GBL and outputs the high level to the data line DT (FIG. 13 (f)).

  FIG. 14 shows an example of the read operation RDOP of the semiconductor memory MEM shown in FIG. Here, the read operation RDOP includes not only a read operation associated with a read command but also a program verify operation during a program operation and an erase verify operation during an erase operation. FIG. 14 shows waveforms of bit lines BL0 and BL2-7 other than the bit line BL1 connected to the memory cell MC to be accessed in the read operation shown in FIG. FIG. 14 also shows waveforms of the precharge signal PREX, the read column selection signal RYSEL0, and the read data RDATA not shown in FIG. Note that the voltages shown in FIG. 14 are merely examples, and are not limited to these values.

  In the read operation RDOP, the precharge signal PREX is deactivated to a high level in response to the activation of the word line WL0, and the connection between the global bit line GBL and the precharge voltage line VPR is released (FIG. 14A). ). The read column selection signal RYSEL0 is activated in response to the deactivation of the reset signal RST, and deactivated after the reset signal RST is activated (FIG. 14 (b)). All the selection signals SECY0-7 are activated to a high level during the standby period STBY (FIG. 14 (c)). At this time, all the bit lines BL0-7 are connected to the ground line VSS via the selection switch SSW and the common reset switch. Using the selection switch SSW used for reading and writing data and setting the bit lines BL0-7 to the ground voltage VSS by using a common reset switch, the semiconductor memory MEM is formed to reset the bit lines BL0-7. The number of transistors to be used can be reduced. Thereby, the circuit size can be reduced and the chip size of the semiconductor memory MEM can be reduced.

  Among the selection signals SECY0-3 corresponding to the memory cell units MCU including the memory cells MC from which data is read, the selection signals SECY0, 2-3 corresponding to the memory cells MC from which data is not read out are used to deactivate the reset signal RST. It is deactivated in response (FIG. 14 (d)). Thereby, the bit lines BL0 and 2-3 are set in a low level floating state (FIG. 14E). The inactivation period of the selection signals SECY0 and 2-3 is set according to the timing signal generated by the operation control circuit 22 shown in FIG.

  Thereafter, similarly to FIG. 13, in response to the activation of the precharge signal PR0, the bit line BL1 is precharged and the read operation is executed (FIG. 14 (f)). At this time, the bit lines BL0 and BL2 adjacent to the bit line BL1 are maintained at a low level. Since the voltages of the adjacent bit lines BL0 and BL2 do not change, the voltage of the bit line BL1 is not affected by coupling noise or the like. As a result, it is possible to prevent the semiconductor memory MEM from malfunctioning during the read operation.

  FIG. 15 shows an example of the write operation WROP of the semiconductor memory MEM shown in FIG. In this example, similarly to FIGS. 12 to 14, the memory cell MC connected to the word line WL0 and the bit line BL1 of the sector SEC0 is accessed, and logic 0 is written. Note that the voltages shown in FIG. 15 are merely examples, and are not limited to these values.

  In the write operation WROP, first, the selection signals SECY0-7 corresponding to the memory cell units MCU including the memory cells MC into which data is written are deactivated to a low level (FIG. 15A). Next, the word line WL0 is activated, the precharge signal PREX and the reset signal RST are deactivated, the precharge signal PR0 is activated, and the write column selection signal WYSEL0 is activated (FIG. 15 (b, c, d, e, f)). Further, the selection signal SECY1 corresponding to the memory cell MC into which data is written is activated (FIG. 15 (g)).

  Here, the precharge signal PR0 is activated to transmit write data on the global bit line GBL to the bit line BL1, and the nMOS transistor receiving the precharge signal PR0 at the gate operates as a write transistor. When the write transistor is turned on, the global bit line GBL is connected to the low-level bit line BL1, and the voltage of the global bit line GBL decreases (FIG. 15 (h)).

  Next, the write data WDATA is transmitted to the global bit line GBL via the write column switch WCSW and further transmitted to the bit line BL1 (FIG. 15 (i, j, k)). As a result, electrons are injected into the floating gate FG of the cell transistor CT connected to the bit line BL1, and the threshold voltage of the cell transistor CT increases. That is, writing of logic 0 is performed.

  Thereafter, the supply of write data from the write amplifier WA is stopped, and the voltages of the global bit line GBL and the bit line BL1 are lowered (FIG. 15 (l, m, n)). Next, the word line WL0 is deactivated, the precharge signal PREX and the reset signal RST are activated, the precharge signal PR0 is deactivated, the write column selection signal WYSEL0 is deactivated, and the selection signal SECY1 is It is deactivated (FIG. 15 (o, p, q, r, s, t)). As the precharge signal PREX is activated, the global bit line GBL is set to the precharge voltage VPR (FIG. 15 (u)). Thereafter, the selection signals SECY0-7 are activated, the bit lines BL0-7 are reset to a low level, and the write operation WROP ends (FIG. 15 (v)).

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, by forming the replica cell transistor RCT in the replica portion REP in which the same element as that of the memory cell array 32 is formed, the tendency of variation in the electrical characteristics of the real cell transistor CT and the replica cell transistor RCT can be made the same. By connecting the floating gate FG and the control gate CG away from the replica cell transistor RCT, the electrical characteristics of the replica cell transistor RCT can be made substantially the same as the electrical characteristics of the real cell transistor CT.

  Since the capacitance C1 formed in the timing generation unit TGEN is matched with the load capacitance of the bit line BL, the decrease rate of the node ND01 can be matched with the decrease rate of the bit line BL. Since the precharge voltage of the node N01 is set to the power supply voltage VDD, the sense amplifier enable signal SAE can be generated without interposing a level shifter.

  The number of transistors formed in the semiconductor memory MEM is reduced by performing the operation of resetting the bit lines BL0-7 to the ground voltage VSS by using the selection switch SSW used for reading and writing data and the common reset switch. The chip size of the semiconductor memory MEM can be reduced.

  FIG. 16 shows an example of a system in which the above-described semiconductor memory MEM is mounted. The system SYS (user system) constitutes at least a part of a microcomputer system such as a portable device. The system SYS has a system-on-chip SoC in which a plurality of macros are integrated on a silicon substrate. Alternatively, the system SYS has a multi-chip package MCP in which a plurality of chips are stacked on a package substrate. Alternatively, the system SYS has a system-in-package SiP in which a plurality of chips are mounted on a package substrate such as a lead frame. Furthermore, the system SYS may be configured in the form of chip-on-chip CoC or package-on-package PoP.

  For example, the system SYS has a CPU, a ROM, a RAM, a memory control circuit MCNT, and the semiconductor memory MEM shown in FIG. 1 or FIG. The CPU, ROM, RAM, and memory control circuit MCNT are connected to each other by a system bus SBUS. The memory control circuit MCNT and the semiconductor memory MEM are connected to each other by a dedicated bus. Note that the CPU may have the function of the memory control circuit MCNT and the semiconductor memory MEM may be directly accessed by the CPU without using the memory control circuit MCNT.

  The CPU accesses the ROM and RAM, and also accesses the semiconductor memory MEM via the memory control circuit MCNT to control the operation of the entire system. The semiconductor memory MEM performs a write operation, a read operation, and an erase operation in response to an access request from the memory control circuit MCNT that operates according to an instruction from the CPU.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10 ... Command generation circuit; 12 ... Test mode control circuit; 14 ... Data input / output circuit; 16 ... Internal voltage generation circuit; 18 ... CAM access control circuit; 22 ... Operation control circuit; 28. Memory core; 30 ... Bus control circuit; 32 ... Memory cell array; 34 ... X control circuit; 46 ... Y control circuit; BL ... Bit line; CG ... Control gate; CT: Real cell transistor; DT: Data signal; FG: Floating gate; GBL: Global bit line; IV1, IV2: CMOS inverter; MC: Memory cell: MEM: Semiconductor memory: MVGEN: Monitor voltage generation unit: PT: Precharge Transistor: RA Read amplifier; RBL Replica bit RCSW Read column switch RCT Replica cell transistor RDEN Enable signal REP Replica part SA Sense amplifier SAE Sense amplifier enable signal SECY Select signal SL Source line SS Semiconductor substrate TGEN... Timing generation unit; TGEN1... First generation unit; TGEN2... Second generation unit; VSAEV... Control voltage; VSARD... Control voltage; WA... Write amplifier;

Claims (2)

A plurality of nonvolatile memory cells having cell transistors including a control gate and a floating gate;
A plurality of bit lines respectively connected to the cell transistors;
A word line commonly connected to the control gate;
A selection switch connected to each of the bit lines and connecting the bit lines to a common node;
A precharge switch for connecting the common node to a precharge line;
A sense amplifier for determining the logic of data read from each memory cell to each common node via each bit line;
A reset switch for connecting the common node to a ground line;
In a read operation, the precharge switch is temporarily turned on after turning off the selection switch corresponding to the memory cell that does not read data among all the selection switches that are turned on and the reset switch that is turned on. And an operation control circuit for activating the word line. All the selection switches and the reset switches are on during the standby period,
In the write operation, the operation control circuit turns off all the selection switches, then turns off the reset switch, and writes data to write to one of the memory cells the write data supplied to the common node. 2. The semiconductor memory according to claim 1, wherein a selection switch corresponding to a memory cell to be written is turned on.

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