JP2013074074A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device by which analysis is simple.SOLUTION: A semiconductor device includes: a first wiring 101 capable of transmitting an internal signal; a measurement electrode 100 electrically connected to the first wiring 101; and dummy electrodes 102, 103 which are arranged so as to adjoin the measurement electrode 100, to which ground potential VSS is applied when the internal signal is measured, and desired voltage is applied except when the internal signal is measured. For example, the measurement electrode 100 is annularly formed, the dummy electrodes have the first electrode 102 and the second electrode 103, the first electrode 102 is arranged so as to adjoin a space formed inside the measurement electrode 100, and the second electrode 103 is arranged so as to adjoin the outside of the measurement electrode 100.

Description

  Embodiments described herein relate generally to a semiconductor device.

For example, as a method of strengthening LSI security and making analysis from outside difficult, each I
An enable input pad or enable output pad corresponding to the / O pad is provided,
The signals from the enable pads corresponding to the two target I / O pads are compared by a comparator, and if the signals match as a result, the target I / O pad can be used. An external terminal access control circuit is known.

JP 2004-172173 A

  Embodiments provide a semiconductor device capable of improving security.

According to the semiconductor device of this embodiment, the first wiring capable of transmitting an internal signal, the measurement electrode electrically connected to the first wiring, and the measurement signal are arranged adjacent to the measurement electrode, and the internal signal And a dummy electrode to which a ground voltage is applied when measuring the internal signal and a desired voltage is applied when the internal signal is not measured.

1 is a block diagram illustrating a semiconductor device according to a first embodiment. The figure which shows the threshold value distribution of the memory cell of 1st Embodiment. FIG. 2 is a layout diagram illustrating a measurement electrode 100 and dummy electrodes 102 and 103 according to the first embodiment. The figure which shows the connection relation of the bias control circuit 9, the measurement electrode 100, and the dummy electrodes 102 and 103 of 1st Embodiment. The figure which shows the connection relationship of the bias control circuits 9-1 to 9-4 of 1st Embodiment, the measurement electrode 100, and the dummy electrodes 102 and 103. FIG. 6 is a correspondence table showing voltage supply of signals ENB1 to ENB4 and signals SEL1 to SEL4. The layout figure which shows the measurement electrode 100 and the dummy electrodes 102 and 103 of 2nd Embodiment.

(First embodiment)
Next, a first embodiment will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[Configuration of semiconductor device]
The semiconductor device according to the first embodiment will be described with reference to FIGS. In the first embodiment, a NAND flash memory will be described as an example. In the present embodiment, NA
The present invention is not limited to the ND flash memory, but can be applied not only to a memory other than the NAND flash memory (eg, NOR flash memory, SRAM) but also to a semiconductor device other than the memory.

1. Overall Configuration As shown in FIG. 1, a NAND flash memory includes a memory cell array 1, a row decoder 2, a driver circuit 3, a voltage generation circuit 4, a data input / output circuit 5, a control unit 6, a source line driver circuit 7, and a sense amplifier. 8. A bias control circuit 9 is provided.

1-1. Configuration example of the memory cell array 1
The memory cell array 1 includes blocks BLK0 to BLKs including a plurality of nonvolatile memory cells MT (s is a natural number). Each of the blocks BLK0 to BLKs includes a plurality of NAND strings 11 in which nonvolatile memory cells MT are connected in series. NAN
Each of the D strings 11 includes, for example, 64 memory cells MT and a selection transistor ST1.
, ST2 are included.

The memory cell MT can hold binary or higher data. The structure of the memory cell MT includes a floating gate (charge conductive layer) formed on a p-type semiconductor substrate with a gate insulating film interposed therebetween,
The FG structure includes a control gate formed on a floating gate with an inter-gate insulating film interposed. The structure of the memory cell MT may be a MONOS type. What is MONOS type?
A charge storage layer (for example, an insulating film) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and an insulating film (hereinafter referred to as a block layer) formed on the charge storage layer and having a dielectric constant higher than that of the charge storage layer And a control gate formed on the block layer.

The control gate of the memory cell MT is electrically connected to the word line WL, the drain is electrically connected to the bit line BL, and the source is electrically connected to the source line SL. Memory cell MT is an n-channel MOS transistor. The number of memory cells MT is 64.
The number is not limited to 128, 256, 512, etc., and the number is not limited.

The adjacent memory cells MT share the source and drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cells MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

The control gates of the memory cells MT in the same row are commonly connected to any of the word lines WL0 to WL63, and the gate electrodes of the select transistors ST1 and ST2 of the memory cells MT in the same row are connected to the select gate lines SGD1 and SGS1, respectively. Commonly connected. For simplification of description, the word lines WL0 to WL63 may be simply referred to as word lines WL below when not distinguished from each other. Further, the drains of the select transistors ST1 in the same column in the memory cell array 1 are commonly connected to any one of the bit lines BL1 to BL (n + 1). Hereinafter, the bit lines BL1 to BL (n + 1) are collectively referred to as a bit line BL (n: natural number) unless they are distinguished. The source of the selection transistor ST2 is the source line S
L is commonly connected.

Data is collectively written in the plurality of memory cells MT connected to the same word line WL, and this unit is called a page. Further, data is erased collectively from the plurality of memory cells MT in units of blocks BLK.

1-2. About threshold distribution of memory cell MT
The threshold distribution of the memory cell MT will be described with reference to FIG. FIG. 2 is a graph in which the horizontal axis represents the threshold distribution (voltage) and the vertical axis represents the number of memory cells MT.

As shown in the drawing, each memory cell MT can hold, for example, binary (2-levels) data (1-bit data). That is, the memory cell MT is “1” in ascending order of the threshold voltage Vth.
"And" 0 "can be stored.

The threshold voltage Vth0 of “1” data in the memory cell MT is Vth0 <V01. The threshold voltage Vth1 of “0” data is V01 <Vth1. Thus, the memory cell MT can hold 1-bit data of “0” data and “1” data according to the threshold value. The memory cell MT is set to “1” data (for example, negative voltage) in the erased state, and is set to a positive threshold voltage by writing data and injecting charge into the charge storage layer.

1-3. About row decoder 2
Returning to FIG. 1, the row decoder 2 will be described. The row decoder 2 includes a block decoder 20 and transfer transistors (N channel MOS transistors) 21 to 23.
The block decoder 20 decodes a block address given from the control unit 6 during a data write operation, a read operation, and an erase operation, and selects a block BLK based on the result. The block decoder 20 is provided for each block BLK.
A block selection signal is transferred from the block decoder 20 to the transfer transistors 21 to 23. As a result, the transfer transistors 21 to 23 are turned on. Thus, based on the block selection signal supplied from the block decoder 20, the row decoder 2 transfers the voltage supplied from the driver circuit 3 to the select gate lines SGD1 and SGS1 and the word lines WL0 to WL63, respectively.

Further, the row decoder 2 decodes the row address given from the control unit 6, and based on the result, the desired word line WL among the plurality of word lines WL in the selected block.
Select.

1-4. About Driver Circuit 3 The driver circuit 3 includes select gate line drivers 31 and 32 provided for the select gate lines SGD1 and SGS1, and a word line driver 33 provided for each word line WL. In the present embodiment, the word line driver 33 and the select gate line drivers 31 and 32 are
The blocks BLK0 to BLKs are provided.

The select gate line driver 31 transfers, for example, a signal sgd to the gate of the select transistor ST1 via the select gate line SGD1 during data writing, reading, erasing, and data verification. The signal sgd is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD (for example, 1.8 [V] when the signal is at the “H” level.
V]).

Similarly to the select gate line driver 31, the select gate line driver 32 passes through the select gate line SGS1 of the selected block BLK, for example, via the select gate line SGS1 during data writing, reading, and data verification. Signal sg
s is transferred to the gate of the selection transistor ST2. The signal sgs is “L”.
When it is “level”, it is set to 0 [V], and when it is “H” level, it is set to voltage VDD.

1-4. Voltage Generation Circuit 4 The voltage generation circuit 4 generates a voltage required for data programming, reading, and erasing by boosting or stepping down an externally applied voltage. The generated voltage is supplied to the driver circuit 3.

1-5. About the data input / output circuit 5 The data input / output circuit 5 is an address (row address, column address, block address; page including row address and column address) supplied from an external host via an I / O terminal (not shown). And the command are output to the control unit 6. The data input / output circuit 5 outputs write data to the sense amplifier 8 via the data line Dline.

Further, when outputting the data read from the memory cell array 1 to the host, the data input / output circuit 5 receives the data amplified by the sense amplifier 8 through the data line Dline based on the control of the control unit 6. After that, the data is output to the host via the I / O terminal.

1-6. About Control Unit 6 The control unit 6 controls the operation of the entire NAND flash memory. That is, the operation sequence in the data write operation, read operation, and erase operation is executed based on the address and command given from the host via the data input / output circuit 5.
The control unit 6 generates a block selection signal, a column selection signal, and a row selection signal based on the address and the operation sequence.

The control unit 6 outputs the block selection signal and the row selection signal described above to the row decoder 2.
Further, the control unit 6 outputs a column selection signal to a column decoder (not shown). The column selection signal is a signal for selecting the column direction of the sense amplifier 8.

The control unit 6 is given a control signal supplied from a host (for example, a memory controller) connected to the NAND flash memory. The control unit 6 distinguishes whether the signal supplied from the host to the data input / output circuit 5 via the I / O terminal is an address or data based on the supplied control signal.

1-7. Sense Amplifier 8 The sense amplifier 8 senses and amplifies data read from the memory cell MT to the bit line BL when reading data. Specifically, after precharging the bit line BL to a predetermined voltage, the bit line B is selected by the NAND string 11 selected by the row decoder 2.
L is discharged, and the discharge state of the bit line BL is sensed. That is, the sense amplifier 8 amplifies the voltage of the bit line BL and senses data stored in the memory cell MT.

  At the time of data writing, write data is transferred to the corresponding bit line BL.

1-8. About Column Decoder A column decoder (not shown) decodes a column address given from the control unit 6 and outputs a column selection signal to the sense amplifier 8. Based on this column selection signal, a desired latch circuit of the sense amplifier 8 is selected.

1-9. Address Buffer An address buffer (not shown) has a function of holding an address input to the control unit 6. In the NAND flash memory of this embodiment, the address buffer is the control unit 6.
However, the present invention is not limited to this, and the address may be directly supplied from the data input / output circuit 5.

1-10. Measurement Electrode and Dummy Electrode Next, the measurement electrode and the dummy electrode of the present embodiment will be described with reference to the layout diagram of FIG.

The measurement electrode 100 is an electrode provided for measuring the potential and timing of the internal signal. As shown in FIG. 3, the measurement electrode 100 is electrically connected to, for example, a wiring 101 through which an internal signal to be measured is transmitted. In FIG. 3, the measurement electrode 100 is connected to the wiring 101 through a contact. For convenience of illustration, the contacts are indicated by solid lines.

As shown in FIG. 3, the measurement electrode 100 is formed in an annular shape, and a space is formed inside.

The dummy electrode 102 is an electrode formed inside the annular shape of the measurement electrode 100. The distance a between the inner end of the measurement electrode 100 and the dummy electrode 102 is narrower than the width of the tip of the probe needle, for example. As a result, when the probe needle is applied from the inside of the measurement electrode 100 for measurement, the probe needle contacts the dummy electrode 102 simultaneously with the measurement electrode 100.

The dummy electrode 103 is an electrode formed outside the annular shape of the measurement electrode 100. The distance b between the outer end of the measurement electrode 100 and the dummy electrode 102 is, for example, narrower than the width of the tip of the probe needle, like the distance a. As a result, when the probe needle is applied from the outside of the measurement electrode 100 for measurement, the probe needle contacts the dummy electrode 103 simultaneously with the measurement electrode 100.

The dummy electrode 102 and the dummy electrode 103 are connected to the wiring 104 through a contact. The wiring 104 is connected to one end of the current path of the switching transistor SW1 shown in FIG.

1-11. Next, the bias control circuit 9 of this embodiment will be described with reference to FIG.

The bias control circuit 9 has a function of controlling the potential applied to the dummy electrodes 102 and 103. The bias control circuit 9 includes a plurality of inverter circuits INV1 and INV2. The output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV1. The output terminal of the inverter circuit INV1 is connected to the gate of a switching transistor SW1 described later. An internal control signal is input from the control unit 6 to the inverter circuit INV2.

Next, the measurement electrode 100, the dummy electrodes 102 and 103, and the bias control circuit 9 of the present embodiment.
The connection relationship with will be described with reference to FIG.

As shown in FIG. 4, the measurement electrode 100 is connected to the wiring 101. Dummy electrode 102,
103 is connected to the wiring 104 through a contact. The wiring 104 is connected to one end (drain) of the current path of the switching transistor SW1.

The other end of the current path of the switching transistor SW1 is connected to the ground potential VSS.
In the present embodiment, the other end is connected to the ground potential VSS, but is not limited thereto, and may be the power supply VCC, for example.

The gate of the switching transistor SW1 is connected to the bias control circuit 9. Specifically, as described above, the bias control circuit 9 is connected to the output terminal of the inverter circuit INV1.

[Operation of semiconductor device]
Next, when the test for measuring the internal signal of the wiring 101 is executed, the operation of the semiconductor device of this embodiment will be described with reference to FIGS.

(1) When the test for measuring the internal signal of the wiring 101 is not executed When the test for measuring the internal signal of the wiring 101 is not executed, the control unit 6 outputs the “H” level internal control signal to the bias control circuit 9. To do. Based on this internal control signal (control signal), the bias control circuit 9 is connected to “H” via a plurality of inverter circuits INV1, INV2.
A level control signal (V1) is output.

Accordingly, the switching transistor SW1 is turned on, and the dummy electrode 102,
The VSS is transferred to 103. As a result, the dummy electrodes 102 and 103 have a desired voltage.

(2) When executing a test for measuring the internal signal of the wiring 101 When executing a test for measuring the internal signal of the wiring 101, the data input / output circuit 5 receives a corresponding test command from the outside. The data input / output circuit 5 transfers this test command to the control unit 6. Then, the control unit 6 controls the bias control circuit 9 based on this test command. Specifically, the control unit 6 outputs an “L” level control signal (V 1) to the bias control circuit 9.

Accordingly, the switching transistor SW1 is turned off and cut off.
The dummy electrodes 102 and 103 are floating. As a result, in order to measure the internal signal, when the probe needle contacts the measurement electrode 100, the internal signal transmitted to the measurement electrode 100 can be accurately measured even if the probe touches the dummy electrodes 102 and 103 simultaneously.

[Effect of the first embodiment]
As described above, the embodiment can provide a semiconductor device capable of improving security. This will be specifically described below.

In the semiconductor device of the present embodiment, when the test for measuring the internal signal of the wiring 101 is not executed, the gate of the switching transistor SW1 receives the “H” level control signal (V1) and is always on. Therefore, as a result, when the probe needle contacts the measurement electrode 100, the dummy electrodes 102 and 103 are also simultaneously contacted, so that the internal signal transmitted to the measurement electrode 100 cannot be measured. On the other hand, when the test for measuring the internal signal of the wiring 101 is executed, the switching transistor SW1 is turned off and cut off. The dummy electrodes 102 and 103 are floating. As a result, when the probe needle contacts the measurement electrode 100, the measurement electrode 100 may be contacted with the dummy electrodes 102 and 103 at the same time.
It is possible to accurately measure the internal signal transmitted to.

An enable input pad or enable output pad corresponding to each I / O pad is provided, and signals from the enable pads corresponding to the two target I / O pads are compared by a comparator. If they match, the present embodiment can provide a semiconductor device capable of improving security with respect to the external terminal access control circuit (comparative example) in which the target I / O pad can be used.

In the comparative example, as the number of pads increases, it becomes difficult to recognize the position of the enable pad and the analysis becomes difficult. However, once the position of the enable pad can be recognized, the analysis becomes easier.

However, in the semiconductor device of this embodiment, the bias control circuit 9 can be controlled based on the test command to control whether a potential is applied to the dummy electrodes 102 and 103 or the floating state.

Therefore, since only a person who recognizes the test command can analyze the internal signal, this embodiment can provide a semiconductor device capable of improving security compared to the comparative example.

Further, in the comparative example, it is necessary to arrange a large number of pads in order to make analysis difficult and to provide a desired logic circuit, which increases the circuit area. However, in the semiconductor device of this embodiment, only the dummy electrodes 102 and 103 are provided inside and outside the measurement electrode 100, and it is not necessary to arrange a large number of dummy electrodes 102 and 103. As a result, the semiconductor device of this embodiment can reduce the circuit area compared to the comparative example.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. The semiconductor device of the second embodiment is provided with a plurality of bias control circuits 9-1 to 9-4 with respect to the first embodiment,
Switching transistor S corresponding to each of the plurality of bias control circuits 9-1 to 9-4
The difference is that W1 to SW4 are provided, and other configurations are the same as those of the first embodiment, and detailed description thereof is omitted.

[Configuration of semiconductor device]
The configuration of the semiconductor device of the second embodiment will be described with reference to FIG. As shown in FIG. 5, a plurality of bias control circuits 9-1 to 9-4 are provided. Multiple bias control circuits 9-
Although 1-9-4 are the same structures, the signal input from the control part 6 differs.

Each of the bias control circuits 9-1 to 9-4 includes a plurality of inverters INV1 and INV.
2 and a NAND circuit (NAND).

(1) Bias control circuit 9-1 The output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV1. The output terminal of the inverter circuit INV1 is connected to the gate of the switching transistor SW1. The input terminal of the inverter circuit INV2 is connected to the output terminal of the NAND circuit. The signal ENB1 and the signal SEL1 are input to the input terminal of the NAND circuit. The signal ENB1 and the signal SEL1 are input from the control unit 6.

(2) Bias control circuit 9-2 The output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV1. The output terminal of the inverter circuit INV1 is connected to the gate of the switching transistor SW2. The input terminal of the inverter circuit INV2 is connected to the output terminal of the NAND circuit. A signal ENB2 and a signal SEL2 are input to the input terminal of the NAND circuit. The signal ENB2 and the signal SEL2 are input from the control unit 6.

(3) Bias control circuit 9-3 The output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV1. The output terminal of the inverter circuit INV1 is connected to the gate of the switching transistor SW3. The input terminal of the inverter circuit INV2 is connected to the output terminal of the NAND circuit. A signal ENB3 and a signal SEL3 are input to the input terminal of the NAND circuit. The signal ENB3 and the signal SEL3 are input from the control unit 6.

(4) Bias control circuit 9-4 The output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV1. The output terminal of the inverter circuit INV1 is connected to the gate of the switching transistor SW4. The input terminal of the inverter circuit INV2 is connected to the output terminal of the NAND circuit. A signal ENB4 and a signal SEL4 are input to the input terminal of the NAND circuit. The signal ENB4 and the signal SEL4 are input from the control unit 6.

In each of the switching transistors SW1 to SW4, one end of the current path is connected to the dummy electrodes 102 and 103, and the other end is connected to the ground potential VSS (or the power supply VCC).

Next, the signals ENB1 to ENB4 and the signals SEL1 to SEL4 will be described with reference to FIG.

The signals ENB1 to ENB4 are at “H” level, and any of the signals SEL1 to SEL4 is set to “H”.
By setting it to “level”, only the selected switching transistor SW is cut off. As a result, the corresponding voltage VBAIS is floated.

When the signals ENB1 to ENB4 are at “L” level, or when all of the signals SEL1 to SEL4 are at “L” level, the voltage VBIAS is at the ground potential VSS.

[Effects of Second Embodiment]
The semiconductor device of the second embodiment has the same effect as that of the first embodiment for the same reason as in the first embodiment. That is, a semiconductor device capable of improving security can be provided.

Further, when measuring a desired internal signal in the semiconductor device, it is necessary to expose the measurement electrode 100 and its peripheral portion by FIB processing in order to apply the probe needle. That is, in order to expose the measurement electrode 100 and its peripheral portion, for example, an insulating film formed so as to cover the measurement electrode 100 and its peripheral portion needs to be peeled off.

The metal is scattered by the peeling of the insulating film, and the measurement electrode 100 and the dummy electrodes 102 and 103 are scattered.
May be short-circuited. In this case, in the semiconductor device of the first embodiment, the internal signals are supplied to all the dummy electrodes 102 and 103, and the dummy electrodes 102 and 103 cannot be controlled to be floating, and the internal signals are accurately measured. May not be possible.

However, in the second embodiment, a plurality of bias control circuits 9-1 to 9-4 are provided, and corresponding switching transistors SW1 to SW4 are provided. Therefore, FIB
Even if several measurement electrodes 100 and the dummy electrodes 102 and 103 are short-circuited by processing, the dummy electrodes 102 and 103 can be controlled to be floating by selecting the bias control circuits 9-1 to 9-4. The internal signal can be measured.

(Third embodiment)
Next, a third embodiment will be described with reference to FIG. The semiconductor device of the third embodiment is different from the first embodiment in that the distance between the dummy electrode 102 and the dummy electrode 103 is narrower than the width of the tip of the probe needle, and the other configuration is the first. The detailed description is omitted because it is the same as the embodiment.

As shown in FIG. 7, the distance c between the dummy electrode 102 and the dummy electrode 103 is narrower than the width of the tip of the probe needle. As a result, when the probe needle is applied to the measurement electrode 100 for measurement, the probe needle contacts both the dummy electrodes 102 and 103.

Therefore, the semiconductor device of this embodiment has the same effect as that of the first embodiment. Specifically, also in the semiconductor device of the present embodiment, it is possible to control whether the potential is applied to the dummy electrodes 102 and 103 or the floating state is controlled by controlling the bias control circuit 9 based on the test command. For this reason, a person who does not recognize the test command inserts the probe needle into the measuring electrode 1.
If it is 00, it will also contact the dummy electrodes 102 and 103, and an internal signal cannot be measured correctly.

Since only the person who recognizes the test command can analyze the internal signal, this embodiment can provide a semiconductor device capable of improving security.

In the first embodiment, when the width of the measurement electrode 100 is wider than the width of the tip of the probe needle, even if the probe needle is applied to the measurement electrode 100, the dummy electrodes 102 and 103 may not be contacted. However, in the third embodiment, the distance c between the dummy electrode 102 and the dummy electrode 103.
Is narrower than the width of the tip of the probe needle. That is, the width of the measurement electrode 100 is narrower than the width of the tip of the probe needle. As a result, when the probe needle is applied to the measurement electrode 100 for measurement,
The probe needle contacts both the dummy electrodes 102 and 103. Since only the person who recognizes the test command can analyze the internal signal, the third embodiment can provide a semiconductor device capable of improving security even when compared with the first embodiment.

In the present embodiment, when the probe needle is applied to the measurement electrode 100 for measurement, the probe needle is described as contacting the dummy electrodes 102 and 103. However, the present invention is not limited to this case. Any form may be used as long as it contacts either the dummy electrode 102 or the dummy electrode 103. In other words, the dummy electrodes 102 and 103 may be disposed so that at least a part of the probe needle contacts when the probe needle is applied to the measurement electrode 100.

Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Row decoder 3 ... Driver circuit 4 ... Voltage generation circuit 5 ... Data input / output circuit 6 ... Control part 7 ... Source line driver circuit 8 ... Sense amplifier MT ... Memory cell ST1, ST2 ... Selection transistor

Claims (5)

A first wiring capable of transmitting an internal signal;
A measurement electrode electrically connected to the first wiring;
A dummy electrode which is arranged adjacent to the measurement electrode, to which a ground potential is applied when measuring the internal signal, and to which a desired voltage is applied when measuring the internal signal. A semiconductor device. The measurement electrode is formed in an annular shape,
The dummy electrode has a first electrode and a second electrode,
The first electrode is disposed adjacent to a space formed inside the measurement electrode,
The semiconductor device according to claim 1, wherein the second electrode is disposed adjacent to the outside of the measurement electrode. A switching transistor having one end of a current path connected to the dummy electrode;
The semiconductor device according to claim 1, further comprising a bias control circuit that inputs a control signal to a gate of the switching transistor. A first wiring capable of transmitting a first internal signal;
A second wiring capable of transmitting a second internal signal different from the first internal signal;
A first measurement electrode electrically connected to the first wiring;
A second measurement electrode electrically connected to the second wiring;
A first electrode disposed adjacent to the first measurement electrode, to which a ground potential is applied when measuring the first internal signal, and a desired voltage is applied when measuring the first internal signal. A dummy electrode;
A second electrode disposed adjacent to the second measurement electrode, to which a ground potential is applied when the second internal signal is measured, and a desired voltage is applied when the second internal signal is not measured. A dummy electrode;
A first switching transistor having one end of a current path connected to the first dummy electrode;
A second switching transistor having one end of a current path connected to the second dummy electrode;
A first bias control circuit for inputting a control signal to the gate of the first switching transistor;
A second bias control circuit for inputting a control signal to the gate of the second switching transistor;
A semiconductor device comprising: 5. The semiconductor device according to claim 1, wherein a gap between the measurement electrode and the dummy electrode is narrower than a width of a tip of a probe needle.

Images