JP5506281B2 - Power supply circuit and electronic equipment - Google Patents

Description

  The present application relates to a power supply circuit that supplies power to a load such as an LED and an electronic device.

  Conventionally, there is a power supply circuit that generates a desired output voltage from an input voltage and supplies it to a load such as an LED (Light Emitting Diode). Such a power supply circuit generally includes an error amplifier that amplifies a difference between a feedback voltage corresponding to an output voltage and a reference voltage. In this configuration, the output voltage of the output transistor is controlled using the error voltage output from the error amplifier.

  In relation to this, a technique is known in which the output current is limited by providing a clamp circuit for setting an upper limit value of the error voltage output from the error amplifier, and the characteristics at the time of startup are improved.

JP2007-185065 JP 2008-178257 A

  In the power supply circuit having the above configuration, the output voltage can be adjusted by changing the reference voltage. However, when the reference voltage is suddenly changed, an overshoot occurs in the output, and a voltage exceeding the breakdown voltage of the device may be output. In addition, when an LED is driven as a load, flicker may occur due to fluctuations in output current, which is a problem. Such problems are not mentioned in the above Patent Documents 1 and 2.

  The present invention has been proposed in view of the above-described problems, and provides a power supply circuit capable of reducing overshoot that occurs in an output due to a sudden change in a reference voltage, and an electronic device including the power supply circuit. Objective.

  The power supply circuit disclosed in the present application generates an output voltage to be supplied to a load from an input voltage by driving an output inductor by on / off control of an output transistor, and adjusts the output voltage based on a reference voltage. An error amplifier that amplifies a difference between the feedback voltage according to the output voltage and the reference voltage to generate an error voltage; a comparator that compares the error voltage with a detection voltage according to a current flowing through the output inductor; A switching control unit that controls on / off of the output transistor based on an output signal of the comparator; a clamp circuit that sets an upper limit value of the error voltage based on a clamp voltage; and a clamp voltage generation circuit that generates the clamp voltage; And the clamp voltage generation circuit varies the clamp voltage according to the input voltage. Make. An electronic device disclosed in the present application includes the power supply circuit, a battery that supplies the input voltage, and an LED as the load.

  According to the disclosed power supply circuit and electronic device, the clamp voltage of the clamp circuit that sets the upper limit value of the error voltage output by the error amplifier is changed according to the input voltage, so that the output can be output along with the sudden change of the reference voltage. It is possible to reduce the overshoot that occurs.

It is a circuit block diagram of a 1st embodiment. It is a circuit block diagram which shows the specific example of a clamp circuit. It is a schematic diagram of the waveform of detection voltage SLOPEOUT. It is a schematic diagram of occurrence of overshoot. It is a schematic diagram of the effect by clamp voltage adjustment. It is a circuit block diagram which shows the specific example 1 of a clamp voltage generation circuit. It is a circuit block diagram which shows the specific example 2 of a clamp voltage generation circuit. It is a circuit block diagram which shows the specific example 3 of a clamp voltage generation circuit. It is a circuit block diagram which shows the specific example 4 of a clamp voltage generation circuit. It is a circuit block diagram which shows the specific example 5 of a clamp voltage generation circuit. It is a wave form diagram which shows the sudden change simulation result of the reference voltage Vref at the time of input voltage VIN = 2.5 [V]. It is a wave form diagram which shows the sudden change simulation result of the reference voltage Vref at the time of the input voltage VIN = 5.5 [V]. It is a circuit block diagram of a 2nd embodiment.

  FIG. 1 shows a circuit block diagram of the first embodiment. The reference voltage Vref is input to the non-inverting input terminal of the error amplifier ERRAMP. A voltage determined by the resistor R1 connected in series to the LED 40 and the current ILED flowing through the LED 40 is input as a feedback voltage to the inverting input terminal of the error amplifier ERRAMP via the resistor R2. A resistor R3 and a capacitor C2 are connected in series between the inverting input terminal and the output terminal of the error amplifier ERAMAMP. The amplification factors are adjusted by the resistors R2 and R3, and phase compensation is performed together with the capacitor C2. The error voltage ERROUT output from the error amplifier ERRAMP is input to the inverting input terminal of the comparator ICOMP.

  The slope compensation circuit 30 is a circuit that prevents oscillation that occurs when the on-duty of the n-channel MOS transistor N1 exceeds 50%. A current flowing through the inductor L1 is detected and input to the slope compensation circuit 30. Here, the detection of the current flowing through the inductor L1 is performed, for example, by providing a detection resistor in series with the n-channel MOS transistor N1 and detecting a voltage drop generated in the detection resistor. The detection voltage SLOPEOUT output from the slope compensation circuit 30 is input to the non-inverting input terminal of the comparator ICOMP.

  The clock signal CLK is input to the set terminal of the RS flip-flop 10. The output signal of the comparator ICOMP is input to the reset terminal of the RS flip-flop 10. The output signal of the RS flip-flop 10 is input to the gate of the n-channel MOS transistor N1 through the driver circuit 20.

  The above configuration is called peak current mode control. The error amplifier ERRAMP amplifies the difference between the feedback voltage corresponding to the output voltage VOUT and the reference voltage Vref and outputs the error voltage ERROUT. The comparator ICOMP compares the error voltage ERROUT and the detection voltage SLOPEOUT, outputs an L level when the detection voltage SLOPEOUT is lower than the error voltage ERROUT, and outputs an H level when the detection voltage SLOPEOUT reaches the error voltage ERROUT. . Further, the output signal of the RS flip-flop 10 becomes H level at the rising edge of the clock signal CLK and becomes L level at the rising edge of the output signal of the comparator ICOMP. Therefore, when RS flip-flop 10 is set at the rising edge of clock signal CLK having a fixed frequency, n-channel MOS transistor N1 is turned on. When n-channel MOS transistor N1 is turned on, the current flowing through inductor L1 increases, and detection voltage SLOPEOUT increases. The n-channel MOS transistor N1 is kept on until the detection voltage SLOPEOUT becomes equal to the error voltage ERROUT. When the detection voltage SLOPEOUT becomes equal to the error voltage ERROUT, the n-channel MOS transistor N1 is turned off for the remaining period of the fixed period. It becomes a state.

  The drain of n-channel MOS transistor N1 is connected to one end of inductor L1 and to the anode of diode D1. The input voltage VIN is applied to the other end of the inductor L1. The cathode of the diode D1 is connected to the LED 40 and is connected to the ground via the capacitor C1.

  When n-channel MOS transistor N1 is turned on, energy from input voltage VIN is stored in inductor L1. When the n-channel MOS transistor N1 is turned off, energy stored in the inductor L1 is released, and current flows to the capacitor C1 and the LED 40 via the diode D1. When the n-channel MOS transistor N1 is turned on again, energy is stored again in the inductor L1. At this time, a current flows through the LED 40 due to the energy accumulated in the capacitor C1, and the diode D1 prevents backflow. The power supply circuit according to the first embodiment performs on / off control of the n-channel MOS transistor N1 by the above-described peak current mode control, and supplies the output voltage VOUT higher than the input voltage VIN to the LED 40. Further, by changing the reference voltage Vref, the output voltage VOUT can be adjusted and the LED 40 can be dimmed.

  The clamp circuit 50 will be described with reference to FIG. FIG. 2 is a circuit block diagram showing a specific example of the clamp circuit 50. Clamp circuit 50 includes an operational amplifier 51 and an n-channel MOS transistor N51. A clamp voltage VCLM is input to the inverting input terminal of the operational amplifier 51, and an error voltage ERROUT is input to the non-inverting input terminal. The output terminal of the operational amplifier 51 is connected to the gate of the n-channel MOS transistor N51. The source of the n-channel MOS transistor N51 is connected to the ground, and the drain is connected to the output terminal of the error amplifier ERRAMP. Thereby, the clamp circuit 50 sets the upper limit value of the error voltage ERROUT output from the error amplifier ERRAMP to the clamp voltage VCLM output from the clamp voltage generation circuit 60.

  The relationship between the input voltage VIN and the error voltage ERROUT in the above power supply circuit will be described with reference to FIG. FIG. 3 is a schematic diagram of the waveform of the detection voltage SLOPEOUT output from the slope compensation circuit 30. When the input voltage VIN changes, the duty ratio changes so as to keep the output voltage VOUT constant. When the duty ratio is 50% or more, slope compensation is applied by the slope compensation circuit 30, and the waveform of the detection voltage SLOPEOUT becomes steep. Here, as shown in FIG. 3, when the input voltage VIN is higher than when the input voltage VIN is low, the error voltage ERROUT is stabilized at a lower position. Further, as described above, the error amplifier ERRAMP amplifies the difference between the feedback voltage corresponding to the output voltage VOUT and the reference voltage Vref and outputs the error voltage ERROUT. Therefore, the error voltage ERROUT increases as the reference voltage Vref increases, and decreases as the reference voltage Vref decreases.

  Conventionally, the clamp voltage VCLM, which is the upper limit value of the error voltage ERROUT, is set to a constant value based on the case where the input voltage VIN is low so that the target output current ILED can be drawn when the input voltage VIN is low. It was. Therefore, the output overshoot is small when the reference voltage Vref is abruptly changed when the input voltage VIN is low, but the output voltage is sharply changed when the reference voltage Vref is abruptly changed when the input voltage VIN is high. Overshoot increases.

  FIG. 4 shows an outline of the occurrence of this overshoot. Here, the vertical axis of FIG. 4 shows the behavior of the reference voltage Vref, error voltage ERROUT, output voltage VOUT, and output current ILED, respectively, and the horizontal axis shows the passage of time t. In FIG. 4, the solid line shows the behavior when the input voltage VIN is low, and the broken line shows the behavior when the input voltage VIN is high.

  When the reference voltage Vref = V1, the error amplifier ERRAMP controls the error voltage ERROUT to be a predetermined voltage 1 with respect to the reference voltage Vref = V1 according to the input voltage VIN. As a result, the output voltage VOUT and the output current ILED are maintained at target values at the reference voltage Vref = V1. When the reference voltage Vref rises steeply from V1 to V2, the error amplifier ERRAMP follows the fluctuation of the reference voltage Vref and increases the error voltage ERROUT. Eventually, the error voltage ERROUT rises to the clamp voltage VCLM. When the output voltage VOUT reaches the target value at the reference voltage Vref = V2, the error amplifier ERRAMP decreases the error voltage ERROUT. The error amplifier ERRAMP controls the error voltage ERROUT so as to be a predetermined voltage 2 with respect to the reference voltage Vref = V2 in accordance with the input voltage VIN. However, an extra output current ILED is supplied during the recovery times TR1 and TR2 until the error voltage ERROUT returns from the clamp voltage VCLM to the predetermined voltage 2, and an overshoot occurs in the output voltage VOUT.

  As described with reference to FIG. 3, the error voltage ERROUT depends on the input voltage VIN, and the error voltage ERROUT decreases as the input voltage VIN increases. Therefore, if the clamp voltage VCLM is set to a constant value based on the case where the input voltage VIN is low as in the conventional case, the input voltage VIN is higher than the recovery time TR1 when the input voltage VIN is low. In this case, the recovery time TR2 becomes longer. Therefore, overshoot becomes more prominent when the input voltage VIN is high. In particular, when the band of the error amplifier ERRAMP is narrow, the response speed of the error voltage ERROUT is reduced, so that overshoot becomes significant.

  Therefore, in the power supply circuit of the first embodiment, the clamp voltage generation circuit 60 is provided, and the clamp voltage VCLM is adjusted by the input voltage VIN. As described above, the error voltage ERROUT also varies depending on the reference voltage Vref. The higher the reference voltage Vref, the higher the error voltage ERROUT. Therefore, in the power supply circuit of the first embodiment, the clamp voltage VCLM is adjusted by the reference voltage Vref together with the input voltage VIN. As shown in FIG. 1, the input voltage VIN and the reference voltage Vref are input to the clamp voltage generation circuit 60. The clamp voltage generation circuit 60 changes the clamp voltage VCLM according to the input voltage VIN and the reference voltage Vref, and outputs it to the clamp circuit 50.

  FIG. 5 shows an outline of the effect of adjusting the clamp voltage VCLM. Here, the vertical and horizontal axes in FIG. 5 are the same as those in FIG. Also in FIG. 5, the solid line shows the behavior when the input voltage VIN is low, and the broken line shows the behavior when the input voltage VIN is high. As shown in FIG. 5, in the power supply circuit according to the first embodiment, the clamp voltage VCLM is lowered when the input voltage VIN is higher than when the input voltage VIN is low. Thereby, the recovery time TR2 when the input voltage VIN is high can be shortened to the same extent as the recovery time TR1 when the input voltage VIN is low. As described above, the power supply circuit according to the first embodiment can shorten the recovery time and reduce the overshoot by adjusting the clamp voltage VCLM according to the input voltage VIN. As described above, in the power supply circuit according to the first embodiment, the clamp voltage VCLM is also adjusted by the reference voltage Vref together with the input voltage VIN. Specifically, when the reference voltage Vref increases, the clamp voltage VCLM is increased. This prevents the clamp voltage VCLM from becoming too low. Therefore, the error voltage ERROUT does not reach the peak at a clamp voltage VCLM that is so low that it is difficult to flow the target output current ILED, and the target output current ILED can flow.

  Subsequently, a specific example of the clamp voltage generation circuit 60 for realizing the adjustment of the clamp voltage VCLM will be described. FIG. 6 shows a specific example 1 of the clamp voltage generation circuit 60. In FIG. 6, a circuit surrounded by a broken line is a part that adjusts the clamp voltage VCLM according to the reference voltage Vref, and other circuits are parts that adjust the clamp voltage VCLM according to the input voltage VIN.

  Reference voltage Vref is applied to the gate of p-channel MOS transistor P61. The drain of p-channel MOS transistor P61 is connected to the ground, and the source is connected to the drain of p-channel MOS transistor P62 via resistor R61. P-channel MOS transistor P62 forms a current mirror circuit together with p-channel MOS transistor P63. The drain of p-channel MOS transistor P63 is connected to the drain of n-channel MOS transistor N61. N channel MOS transistor N61 forms a current mirror circuit together with n channel MOS transistor N62. The input voltage VIN is applied to the drain of the n-channel MOS transistor N63 via the resistor R62. N channel MOS transistor N63 forms a current mirror circuit together with n channel MOS transistor N64. The drains of the n-channel MOS transistors N62 and N64 are connected in common and are connected to a power supply line of a predetermined constant voltage via a resistor R63. A connection point between the n-channel MOS transistors N62 and N64 and the resistor R63 is an output terminal of the clamp voltage VCLM.

  When the reference voltage Vref increases, the current flowing through the resistor R61 decreases. The current flowing through the resistor R63 decreases through the current mirror circuit including the p-channel MOS transistors P62 and P63 and the current mirror circuit including the n-channel MOS transistors N61 and N62. As a result, the clamp voltage VCLM increases. On the other hand, when the input voltage VIN increases, the current flowing through the resistor R62 increases. The current flowing through the resistor R63 increases through the current mirror circuit including the n-channel MOS transistors N63 and N64. As a result, the clamp voltage VCLM decreases. Thus, according to the first specific example of the clamp voltage generation circuit 60, the clamp voltage VCLM can be lowered when the input voltage VIN is high, and the clamp voltage VCLM can be increased when the reference voltage Vref is high. VCLM adjustment can be realized.

  FIG. 7 shows a specific example 2 of the clamp voltage generation circuit 60. The reference voltage Vref and the input voltage VIN are input to the non-inverting input terminal and the inverting input terminal of the differential amplifier 71 after being multiplied by appropriate coefficients α and β, respectively. Here, the coefficients α and β are appropriately set depending on the partial pressure or the like. Thus, the clamp voltage VCLM that is adjusted low when the input voltage VIN is high and adjusted high when the reference voltage Vref is high is obtained from the output terminal of the differential amplifier 71.

  FIG. 8 shows a third specific example of the clamp voltage generation circuit 60. Similar to the differential amplifier 71 of FIG. 7, the reference voltage Vref and the input voltage VIN are respectively input to the non-inverting input terminal and the inverting input terminal of the gm amplifier 81 after being multiplied by appropriate coefficients α and β. A resistor R81 is connected between the output terminal of the gm amplifier 81 and the ground. The gm amplifier 81 outputs a current corresponding to the difference between the input voltage VIN multiplied by β and the reference voltage Vref multiplied by α. The output current of the gm amplifier 81 is converted into a voltage by the resistor R81. As a result, the clamp voltage VCLM adjusted to be low when the input voltage VIN is high and adjusted to be high when the reference voltage Vref is high is obtained.

  FIG. 9 shows a specific example 4 of the clamp voltage generation circuit 60. Reference voltage Vref is applied to the gate of p-channel MOS transistor P91. The drain of p-channel MOS transistor P91 is connected to the ground, and the source is connected to the drain of p-channel MOS transistor P92 via resistor R91. The p-channel MOS transistor P92 forms a current mirror circuit together with the p-channel MOS transistor P93, and the input voltage VIN is applied to the sources of the p-channel MOS transistors P92 and P93. The drain of p-channel MOS transistor P93 is connected to the drain of n-channel MOS transistor N91. N channel MOS transistor N91 forms a current mirror circuit together with n channel MOS transistor N92. The drain of n-channel MOS transistor N92 is connected to a power line of a predetermined constant voltage via resistor R92. A connection point between the n-channel MOS transistor N92 and the resistor R92 is an output terminal of the clamp voltage VCLM.

  When the reference voltage Vref increases, the current flowing through the resistor R91 decreases. The current flowing through the resistor R92 decreases through the current mirror circuit including the p-channel MOS transistors P92 and P93 and the current mirror circuit including the n-channel MOS transistors N91 and N92. As a result, the clamp voltage VCLM increases. On the other hand, when the input voltage VIN increases, the current flowing through the resistor R91 increases. The current flowing through the resistor R92 increases through the current mirror circuit including the p-channel MOS transistors P92 and P93 and the current mirror circuit including the n-channel MOS transistors N91 and N92. As a result, the clamp voltage VCLM decreases. As described above, according to the fourth specific example of the clamp voltage generation circuit 60, the clamp voltage VCLM can be lowered when the input voltage VIN is high, and the clamp voltage VCLM can be increased when the reference voltage Vref is high. VCLM adjustment can be realized.

  FIG. 10 shows a specific example 5 of the clamp voltage generation circuit 60. The reference voltage Vref and the input voltage VIN are respectively multiplied by appropriate coefficients α and β and input to the inverting input terminals of the operational amplifiers 101 and 102, respectively. The output terminals of the operational amplifiers 101 and 102 are connected to the gates of the n-channel MOS transistor N101 and the p-channel MOS transistor P101, respectively. The non-inverting input terminals of the operational amplifiers are the drains of the n-channel MOS transistor N101 and the p-channel MOS transistor P101, respectively. Connected to. The drains of the n-channel MOS transistor N101 and the p-channel MOS transistor P101 are connected to each other via a resistor R101, and the sources of the transistors are connected to the ground and a power line of a predetermined constant voltage. The n-channel MOS transistor N102 has a gate connected to the n-channel MOS transistor N101 in common, a source connected to the ground, and a drain connected to a power line of a predetermined constant voltage via the resistor R102. A connection point between the n-channel MOS transistor N102 and the resistor R102 is an output terminal of the clamp voltage VCLM.

  When the reference voltage Vref increases, the output of the operational amplifier 101 decreases, and the current flowing through the resistor R102 decreases. As a result, the clamp voltage VCLM increases. On the other hand, when the input voltage VIN increases, the output of the operational amplifier 102 decreases, so that the voltage input to the non-inverting input terminal of the operational amplifier 101 increases. Therefore, since the output of the operational amplifier 101 increases, the current flowing through the resistor R102 increases. As a result, the clamp voltage VCLM decreases. Thus, according to the specific example 5 of the clamp voltage generation circuit 60, the clamp voltage VCLM can be lowered when the input voltage VIN is high, and the clamp voltage VCLM can be increased when the reference voltage Vref is high. VCLM adjustment can be realized.

  The characteristics of each specific example of the clamp voltage generation circuit 60 described so far will be described. The specific example 1 of FIG. 6 includes a part for adjusting the clamp voltage VCLM according to the reference voltage Vref and a part for adjusting the clamp voltage VCLM according to the input voltage VIN, so that the circuit is relatively matched. Easy. The specific example 2 in FIG. 7 and the specific example 3 in FIG. 8 can be said to be other specific examples comprehensively expressed. Specific example 4 in FIG. 9 can reduce the circuit scale. Moreover, since the specific example 5 in FIG. 10 is controlled using the operational amplifiers 101 and 102, the accuracy is high.

  11 and 12, the reference voltage Vref is suddenly changed between 150 [mV] and 300 [mV] when the input voltage VIN is 2.5 [V] and 5.5 [V], respectively. The simulation results of the reference voltage Vref, the error voltage ERROUT, the output voltage VOUT, and the output current ILED at the time are shown. FIGS. 11A and 12A show circuit characteristics when the clamp voltage VCLM is adjusted using the specific example of the clamp voltage generation circuit 60 described so far. For comparison, FIGS. 11B and 12B are based on the case where the input voltage VIN is low (that is, the case where the input voltage VIN = 2.5 [V] here) as in the prior art. The circuit characteristics when the clamp voltage VCLM is set to a constant value are shown.

  As shown in FIG. 11, when the input voltage VIN = 2.5 [V], the overshoot of the output voltage VOUT is 0.233 in both the case where the clamp voltage VCLM is adjusted and the conventional case. [V], which is equivalent. On the other hand, as shown in FIG. 12, when the input voltage VIN = 5.5 [V], the overshoot of the output voltage VOUT is 1.095 [V] in the conventional case, whereas this clamp In the case where the voltage VCLM is adjusted, the overshoot of the output voltage VOUT is 0.202 [V], and the overshoot is reduced to about 1/5.

Here, the correspondence with the claims is as follows.
The n-channel MOS transistor N1 is an example of an output transistor. The inductor L1 is an example of an output inductor. The LED 40 is an example of a load. The RS flip-flop 10 and the driver circuit 20 are an example of a switching control unit. The resistors R61, R62, and R63 are examples of the first resistor, the second resistor, and the output resistor, respectively. The p-channel MOS transistor P62 and the p-channel MOS transistor P63, the n-channel MOS transistor N61 and the n-channel MOS transistor N62, and the n-channel MOS transistor N63 and the n-channel MOS transistor N64 are the first, second, and third current mirror circuits, respectively. It is an example.

  As described above in detail, according to the embodiment, the clamp voltage generation circuit 60 uses the clamp voltage VCLM of the clamp circuit 50 that sets the upper limit value of the error voltage ERROUT output from the error amplifier ERRAMP as the input voltage VIN. The clamp voltage VCLM is lowered when the input voltage VIN is high. Thereby, it is possible to reduce the overshoot that occurs in the output due to the sudden change of the reference voltage Vref. The clamp voltage generation circuit 60 changes the clamp voltage VCLM according to the reference voltage Vref together with the input voltage VIN, and increases the clamp voltage VCLM when the reference voltage Vref is high. Thereby, it is possible to prevent the clamp voltage VCLM from being too low, and to reliably flow the target output current ILED.

  Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

  For example, the first embodiment is a power circuit for peak current mode control, but may be a power circuit for voltage mode control as shown in FIG. 13 as the second embodiment. Here, in FIG. 13, parts corresponding to those in FIG. The error voltage ERROUT and the clamp voltage VCLM are input to the two non-inverting input terminals of the comparator COMP. A triangular wave voltage is input to the inverting input terminal of the comparator COMP as a periodic voltage that periodically changes between a maximum value and a minimum value. The output signal of the comparator COMP is input to the gate of the n-channel MOS transistor N1 through the driver circuit 20.

  The comparator COMP compares the lower one of the error voltage ERROUT and the clamp voltage VCLM with the triangular wave voltage, and outputs an H level when the lower one of the error voltage ERROUT and the clamp voltage VCLM is higher than the triangular wave voltage. If it is low, L level is output. Therefore, the maximum on-duty of n-channel MOS transistor N1 is set by clamp voltage VCLM. The clamp voltage VCLM is adjusted by the input voltage VIN and the reference voltage Vref using the clamp voltage generation circuit 60 described in the first embodiment, so that the same applies to the voltage mode control power supply circuit of the second embodiment. An effect is obtained.

  The clamp voltage VCLM is adjusted according to the input voltage VIN and the reference voltage Vref. However, the clamp voltage VCLM may be adjusted only by the input voltage VIN. In that case, for example, in the specific example 1 of the clamp voltage generation circuit 60 of FIG. Even if the clamp voltage VCLM is adjusted only by the input voltage VIN, the effect of reducing the overshoot can be obtained.

  In addition, although the above embodiment is a step-up type power supply circuit, the gist of the present invention to reduce the overshoot by changing the clamp voltage VCLM according to the input voltage VIN and the reference voltage Vref is a step-down type or a step-up / down type. The present invention can also be applied to a pressure type power supply circuit.

  In addition, you may comprise the electronic device provided with the power supply circuit mentioned above, the battery which supplies the input voltage VIN, and LED as load.

10 RS flip-flop 20 Driver circuit 30 Slope compensation circuit 40 LED (load)
50 Clamp Circuit 60 Clamp Voltage Generation Circuit COMP Comparator ERRAMP Error Amplifier ERROUT Error Voltage ICOMP Comparator L1 Inductor (Output Inductor)
N1 n-channel MOS transistor (output transistor)
R61 resistor (first resistor)
R62 resistor (second resistor)
R63 resistance (output resistance)
SLOPEOUT Detection voltage VCLM Clamp voltage VIN Input voltage VOUT Output voltage Vref Reference voltage

Claims (5)

In a power supply circuit that drives an output inductor by on / off control of an output transistor to generate an output voltage to be supplied from an input voltage to a load, and adjusts the output voltage based on a reference voltage,
An error amplifier that amplifies the difference between the feedback voltage according to the output voltage and the reference voltage to generate an error voltage;
A comparator that compares the error voltage with a detection voltage corresponding to a current flowing through the output inductor;
A switching control unit for controlling on / off of the output transistor based on an output signal of the comparator;
A clamp circuit that sets an upper limit value of the error voltage based on a clamp voltage;
A clamp voltage generation circuit for generating the clamp voltage;
With
The power supply circuit, wherein the clamp voltage generation circuit lowers the clamp voltage when the input voltage increases and increases the clamp voltage when the reference voltage increases . The clamp voltage generation circuit includes:
The power supply circuit according to claim 1 , further comprising: a differential amplifier that uses a voltage corresponding to the input voltage and a voltage corresponding to the reference voltage as differential inputs. The clamp voltage generation circuit includes:
A p-channel MOS transistor having the reference voltage applied to the gate;
A first resistor connected to the source of the p-channel MOS transistor;
First and second current mirror circuits that relay current of the same value as the current flowing through the first resistor to an output resistor;
A second resistor to which the input voltage is applied at one end;
A third current mirror circuit that relays a current having the same value as the current flowing through the second resistor to the output resistor;
With
The power supply circuit according to claim 2 , wherein the clamp voltage is generated based on a voltage drop generated in the output resistor. In a power supply circuit that drives an output inductor by on / off control of an output transistor to generate an output voltage to be supplied from an input voltage to a load, and adjusts the output voltage based on a reference voltage,
An error amplifier that amplifies the difference between the feedback voltage according to the output voltage and the reference voltage to generate an error voltage;
A clamp voltage generation circuit for generating a clamp voltage for setting a maximum on-duty of the output transistor;
A comparator that compares the lower of the error voltage and the clamp voltage with a predetermined periodic voltage that periodically changes between a maximum value and a minimum value;
A switching control unit for controlling on / off of the output transistor based on an output signal of the comparator;
With
The power supply circuit according to claim 1, wherein the clamp voltage generation circuit lowers the clamp voltage when the input voltage increases and increases the clamp voltage when the reference voltage increases . A power supply circuit according to any one of claims 1 to 4 ,
A battery for supplying the input voltage;
An LED as the load;
An electronic device comprising:

Images