JP5502940B2 - Integrated circuit initialization apparatus, electronic device and program - Google Patents

Description

  Embodiments described herein relate generally to an integrated circuit initialization apparatus, an electronic apparatus, and a program.

  For example, CPUs (Central Processing Units) and ASICs (Application Specific Integrated Circuits) incorporated in electronic devices such as personal computers and POS (Point Of Sales) terminals are generally mainly LSI (Large Scale Integration). This is a circuit component. The specification of such a circuit component mainly composed of an LSI or the like is specified by initialization data (register value) set in an internal register of the LSI. Such initialization data (register value) is described in, for example, firmware stored in a ROM (Read Only Memory) or the like.

  Conventionally, an LSI reads initialization data (register value) when the system power is turned on and initializes its internal register. However, the initialization data (register value) is rewritten by the power supply sequence of the power supplied to the LSI. May end up.

  When the register whose register value has been rewritten is related to system activation, there is a problem that the system cannot be activated and the system is stopped. In addition, when a register whose register value has been rewritten is related to a location used by an application after system startup, there is a possibility that a system failure may occur.

  The integrated circuit initialization apparatus according to the embodiment includes a register setting unit, a value reading unit, a normal value storage unit, a determination unit, and a power supply sequence adjustment unit. The register setting means sets a register value for an internal register of an integrated circuit in which a power supply sequence for a plurality of power supplies is defined. The value reading means reads a register value set in the internal register. The normal value storage means stores in advance a normal register value to be set in the internal register. The determination means compares a register value set in the internal register with the normal register value to determine whether or not both values match. The power supply sequence adjusting means adjusts the power supply sequence when the determining means determines that the two values do not match.

FIG. 1 is a block diagram illustrating a configuration of a POS terminal according to the embodiment. FIG. 2 is a block diagram showing the configuration of the POS control unit. FIG. 3 is a functional block diagram showing functions related to the register initialization processing. FIG. 4 is a flowchart showing the flow of register initialization processing including recovery processing when a register is defective. FIG. 5 is a schematic diagram illustrating the operation of the power supply control circuit.

  Exemplary embodiments of an integrated circuit initialization apparatus, an electronic apparatus, and a program according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present embodiment, a POS (Point Of Sales) terminal installed in a store or the like is applied as an electronic device (integrated circuit initialization device). Further, as an integrated circuit, a CPU (Central Processing Unit) is applied. The electronic device (integrated circuit initialization device) is not limited to a POS (Point Of Sales) terminal, and various electronic devices such as a personal computer are applicable.

  FIG. 1 is a block diagram illustrating a configuration of a POS terminal 1 according to the embodiment. The POS terminal 1 is disposed at a checkout location of a store and is used by a cashier for sales processing, and has a configuration as shown in FIG. The POS terminal 1 includes a POS control unit 2 as a main control unit, and is configured to be able to perform online communication with each other via a LAN (not shown) from a communication interface 20 connected via a bus 19. Has been.

  The POS control unit 2 has a card for reading a magnetic card (not shown) such as a keyboard 12, a display 14 with a touch panel, and a credit card via the bus 19 and the I / O device control unit 21. A printer 22 and a hard disk drive (HDD) 18 are connected together with a reader 15 and a barcode scanner 16 for optically reading a product code. The printer 22 is a receipt / journal printer built in the main body 11 of the POS terminal 1, and issues a receipt for each transaction in accordance with the sales process, and simultaneously prints on journal paper.

  FIG. 2 is a block diagram showing a configuration of the POS control unit 2. As shown in FIG. 2, the POS control unit 2 is composed of an LSI (Large Scale Integration), and a ROM (Read ROM) that stores control programs such as a CPU 3 and firmware 4a that control each unit centrally. Only Memory (RAM) 4 and RAM (Random Access Memory) 5 are provided. The CPU 3 includes an internal register 3a that performs various settings according to register value settings.

  The firmware 4a stored in the ROM 4 also functions as a normal value storage means, and all normal register values in the normal case for the internal register 3a are set.

  The HDD 18 stores an OS (Operating System) and applications for operating the CPU 3 of the POS control unit 2.

  As shown in FIG. 2, the CPU 3 is a multi-power supply IC that includes a plurality of power supply rails and uses two different power supplies, and includes a first power supply 6 of 3.3 V for the peripheral portion and 1.0 V for the core portion. The second power source 7 is used. These power sources (first power source 6 and second power source 7) are controlled by a power source control circuit 8 connected to the CPU 3.

  The power supply control circuit 8 controls the timing for starting the first power supply 6 and the second power supply 7. The power supply control circuit 8 includes a terminal (not shown) for setting a delay time, and a delay time (for example, an initial value) from when the first power supply 6 is activated to when the second power supply 7 is activated by this terminal. 10 ms) is set in hardware.

  Next, a function that the firmware 4a stored in the ROM 4 causes the CPU 3 of the POS control unit 2 to execute will be described. Note that description of processing that is the same as processing conventionally performed is omitted. Here, a recovery process when a register is defective will be described.

  As shown in FIG. 3, the POS terminal 1 includes a firmware 4 a stored in the ROM 4 by the CPU 3 of the POS control unit 2, a register setting unit 31, a value reading unit 32, a determination unit 33, a power supply sequence adjustment unit 34, and a restart. The module has a module configuration including means 35. As actual hardware, the CPU 3 of the POS control unit 2 reads the firmware 4a from the ROM 4 and executes it to load the above-mentioned units onto the RAM 5, register setting means 31, value Reading means 32, determination means 33, power supply sequence adjustment means 34, and restarting means 35 are generated on the RAM 5.

  FIG. 4 is a flowchart showing the flow of register initialization processing including recovery processing when a register is defective. When the POS terminal 1 is powered on, the firmware 4a is loaded into the RAM 5, and as shown in FIG. 4, the CPU 3 sets the power control circuit 8 to the ON mode by the power ON / OFF signal, and the power control circuit 8 is started up. Is executed (step S1).

  Here, FIG. 5 is a schematic diagram illustrating the operation of the power supply control circuit 8 as an example. In the example shown in FIG. 5, at the time of start-up, the first power supply 6 and the second power supply 7 are started with a delay time of 10 ms which is an initial value.

  Next, as shown in FIG. 4, the CPU 3 (register setting means 31) executes a register value setting process for the internal register 3a (step S2), and the CPU 3 executes a register setting value comparison process (step S2). Step S3).

  Here, the register value set for the internal register 3a may be rewritten by the power supply sequence of the power supplied to the LSI. The power supply sequence is an order in which the power supply rail is turned on / off in an LSI such as a CPU or ASIC having a plurality of power supply rails. In such an LSI, basically, a high-voltage power supply rail is switched to a low-voltage power supply rail in turn, but if the power-on sequence and timing are incorrect, the internal register A phenomenon occurs in which the correct register value is not set for 3a. If the internal register 3a whose register value has been rewritten is related to system activation, there is a possibility that the system cannot be activated and the system is stopped. In addition, when the internal register 3a whose register value has been rewritten relates to a place where an application uses it after the system is started, there is a possibility that a system failure may occur. Therefore, in this embodiment, a register failure is determined by executing a register setting value comparison process after the register value setting process for the internal register 3a.

  In the register setting value comparison process, first, all current register values set in the internal register 3a in step S1 are read (value reading means 32) and stored in the RAM 5. Next, the normal register value to be set is read from the firmware 4a stored in the ROM 4 and compared with the current set value stored in the RAM 5 (determination means 33).

  If all the register values set in the internal register 3a are correct as a result of the comparison determination in step S3 (Yes in step S4), the CPU 3 ends the initialization of the internal register 3a and starts the system.

  On the other hand, as a result of the comparison determination in step S3, if the register value set in the internal register 3a is not correct (No in step S4), the process proceeds to step S5, and the CPU 3 (power sequence adjusting means 34) performs the power sequence adjusting process. Run.

  The power supply sequence adjustment process will be described. As the power sequence adjustment processing, the CPU 3 extends the delay time to the power control circuit 8 by a delay time setting signal by a predetermined time (for example, sets the first delay time to 15 ms by extending 5 ms) and sets the hardware. The power supply sequence is finely adjusted, and the power supply control circuit 8 is set to the OFF mode by the power supply ON / OFF signal to disconnect the first power supply 6 and the second power supply 7 in order to turn the power supply OFF → ON again. Note that the delay time is set in the ROM 4.

  After execution of the power supply sequence adjustment process as described above, the process returns to step S1, and the CPU 3 (restarting means 35) executes the startup process of the power supply control circuit 8. That is, as shown in FIG. 5, when the CPU 3 sets the power control circuit 8 to the ON mode by the power ON / OFF signal, the delay time of the first power supply 6 and the second power supply 7 is restarted at the previously set 15 ms. become. Here, the reason for extending the delay time from 10 ms to 15 ms is to change the timing of powering on the low voltage power rail.

  The processing in steps S1 to S5 is repeated until all the register values are correct as a result of the comparison determination in step S3 (Yes in step S4), that is, until the initialization of the internal register 3a is completed.

  In the present embodiment, the delay time is extended and reset until the initialization of the internal register 3a is completed. However, the number of retries is limited (for example, 3 to 5 times). Anyway.

  Thus, according to the embodiment, the register value set for the internal register 3a of the integrated circuit in which the power supply sequence for the plurality of power supply rails is defined and the normal register to be set in the internal register stored in advance When the register failure is determined by comparing with the value, and it is determined that the two values do not match, the power supply rail is adjusted to adjust the power supply sequence at a timing different from the previous time with the restart of the power supply control circuit 8 Can be turned on, and the probability of setting a correct register value for the internal register 3a can be increased. Can build a system that can.

  The firmware 4a executed by the POS terminal 1 of the present embodiment is a file in an installable format or an executable format, and is a computer such as a CD-ROM, flexible disk (FD), CD-R, DVD (Digital Versatile Disk). The information may be provided by being recorded on a recording medium that can be read by the user.

  Furthermore, the firmware 4a executed by the POS terminal 1 of the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. Further, the firmware 4a executed by the POS terminal 1 of the present embodiment may be provided or distributed via a network such as the Internet.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Integrated circuit initialization apparatus, electronic device 3 Integrated circuit 3a Internal register 4a Normal value storage means 6 1st power supply 7 2nd power supply 8 Power supply control circuit 31 Register setting means 32 Value reading means 33 Determination means 34 Power supply sequence adjustment means 35 Re Starting means

JP 05-61724 A

Claims (6)

Register setting means for setting a register value for an internal register of an integrated circuit in which a power supply sequence for a plurality of power supplies is defined;
Value reading means for reading a register value set in the internal register;
Normal value storage means for storing in advance a normal register value to be set in the internal register;
A determination means for comparing the register value set in the internal register with the normal register value to determine whether or not both values match;
When it is determined by the determination means that the two values do not match, a power supply sequence adjustment means for adjusting the power supply sequence;
An integrated circuit initialization apparatus comprising: The power supply sequence adjusting means changes a timing of starting a second power supply that supplies a power supply voltage lower than that of the first power supply after starting the first power supply.
The integrated circuit initialization apparatus according to claim 1. The power supply sequence adjustment means repeats the adjustment processing of the power supply sequence until the two values match by the determination means.
The integrated circuit initialization apparatus according to claim 1 or 2. The power sequence adjusting means limits the number of executions of the power sequence adjustment processing to a predetermined number;
The integrated circuit initialization apparatus according to claim 1 or 2. An integrated circuit having an internal register and defining a power supply sequence for a plurality of power supplies;
A first power supply for supplying power;
A second power supply for supplying a lower power supply voltage than the first power supply;
A power supply control circuit for controlling timing of starting the first power supply and the second power supply;
Register setting means for setting a register value for the internal register in accordance with a startup process of the power supply control circuit;
Value reading means for reading a register value set in the internal register;
Normal value storage means for storing in advance a normal register value to be set in the internal register;
A determination means for comparing the register value set in the internal register with the normal register value to determine whether or not both values match;
When it is determined by the determination means that the two values do not match, a power supply sequence adjustment means for adjusting the power supply sequence;
Restarting means for executing a restart for the power supply control circuit;
Electronic equipment comprising. Computer
Register setting means for setting a register value for an internal register of an integrated circuit in which a power supply sequence for a plurality of power supplies is defined;
Value reading means for reading a register value set in the internal register;
Normal value storage means for storing in advance a normal register value to be set in the internal register;
A determination means for comparing the register value set in the internal register with the normal register value to determine whether or not both values match;
When it is determined by the determination means that the two values do not match, a power supply sequence adjustment means for adjusting the power supply sequence;
Program to function as.

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