JP5492009B2 - Load control device - Google Patents

Description

  The present invention relates to a load control device for controlling driving and stopping of a load by controlling a semiconductor switch provided between a DC power supply and a load, and more particularly to a technique for preventing malfunction caused by noise.

  For example, a load control device that controls a load such as a lamp or a motor mounted on a vehicle includes a semiconductor switch such as a field effect transistor (hereinafter referred to as “FET”) between a battery (DC power supply) and the load. It is mounted and the driving and stopping of the load are controlled by switching the FET on and off. In addition, when an overcurrent flows through the load, this is detected as soon as possible and the circuit connected to the load is cut off, so that the drain (first electrode) and the source (second electrode) of the FET are disconnected. When an increase in the voltage Vds is detected, a protection circuit for turning off the FET is mounted.

  FIG. 3 is a diagram showing a load driving circuit equipped with a conventional load control device. As shown in the figure, this load driving circuit has an FET (T1) disposed between a DC power supply VB (the output voltage is also indicated by the same symbol VB) and a load RL. The driving and stopping of the load RL are controlled by switching on and off of T1).

  The drain of the FET (T1) is connected to the positive pole of the DC power supply VB via the power line, the source is connected to one end of the load RL via the load line, and the other end of the load RL is connected to the ground. Grounded. The power supply line is a wire from the positive pole of the DC power supply VB to the drain of the FET (T1), and the load line is a wire from the source of the FET (T1) to the load RL.

  Further, since the power supply line has an inductance component, this is Lw1, and since the load line similarly has an inductance component, this is Lw2. Note that the resistance values of the power supply line and the load line are extremely small and are ignored.

  The control circuit 10 includes a plus terminal P11 and a minus terminal P12, the plus terminal P11 is connected to the drain (P1) of the FET (T1), and the minus terminal P12 (voltage Vm) is grounded to the ground through the earth wire. Has been. Further, the control circuit 10 includes a comparator CMP1, a driver 11, and a charge pump 12. Since the ground wire has an inductance component as well as the power supply line and the load line, it is set to Lw3. Also, the resistance value is ignored.

  A series connection circuit of resistors R1 and R2 is provided between the plus terminal P11 and the minus terminal P12, and the connection point P4 (voltage V4) is connected to the plus side input terminal of the comparator CMP1. The negative input terminal of the comparator CMP1 is connected to the source (point P2, voltage V2) of the FET (T1). When the FET (T1) is turned on and the load RL is driven, the voltage V2 exceeds the voltage V4, so that the output signal of the comparator CMP1 becomes L level. In addition, when the load line is grounded, an overcurrent flows through the FET (T1), and the drain-source voltage Vds of the FET (T1) rises. Therefore, the source voltage V2 is lowered, so that the voltage V2 becomes equal to the voltage V4. The output signal of the comparator CMP1 becomes H level. This signal is supplied to the driver 11 as an overcurrent determination output signal.

  The output terminal of the driver 11 is connected to the gate of the FET (T1) through the resistor R3. Further, the driver 11 is connected to the plus terminal P11 via the resistor R4, and is connected to the minus terminal P12 via the input switch SW1. Therefore, when the input switch SW1 is off (open circuit), an H level signal is input to the driver 11 to turn off the FET (T1). Conversely, when the input switch SW1 is on (closed), the driver 11 is low. A level signal is input to turn on the FET (T1). Further, when an H level signal (overcurrent determination output signal) is supplied from the comparator CMP1, the FET (T1) is turned off.

  Here, a capacitor C1 is installed between the plus terminal P11 and the minus terminal P12 in order to prevent the control circuit 10 from malfunctioning due to strong radio waves or electromagnetic noise generated from various electrical components. (For example, refer to Patent Document 1).

  Next, the operation of the conventional load control device configured as described above will be described. When the input switch SW1 is turned on, the voltage of the charge pump 12 is output from the driver 11 and applied to the gate of the FET (T1). Thereby, the FET (T1) is switched from OFF to ON. In a transient state in which the FET (T1) shifts from OFF to ON, the power supply line current I1 (on the path of the power supply VB plus terminal → Lw1 → P1 → T1 → P2 → Lw2 → P3 → RL → GND → power supply VB minus terminal) Solid line) flows.

  When the FET (T1) is turned on, the current I1 starts increasing from zero and increases to a current value obtained by dividing the power supply voltage VB by the resistance of the load RL. In this process, the back electromotive force proportional to the increasing gradient is generated in the inductances Lw1 and Lw2 due to the increase in the current I1. Since the counter electromotive force generated in the inductance Lw1 pushes down the voltage V1 at the point P1, the voltage V1 at the point P1 decreases. For this reason, the voltage charged in the capacitor C1 is discharged.

  The discharge current I2 (dashed line) of the capacitor C1 flows through the path of C1 plus terminal → P11 → P1 → T1 → P2 → Lw2 → P3 → RL → GND → Lw3 → P12 → C1 minus terminal to the inductance Lw2 of the load line. Generate back electromotive force. At this time, since the discharge current of the capacitor C1 does not flow through the power supply line, no counter electromotive force is generated in the inductance Lw1 due to the discharge current I2 of the capacitor C1. When the discharge current of the capacitor C1 is increasing, the voltage V2 at the point P2 is pushed up. However, when the discharge current of the capacitor C1 starts from increasing to decreasing, it becomes a counter electromotive force that pushes down the voltage V2.

If the capacitor C1 for noise suppression is not installed, the voltage V1 becomes the lowest when the voltage V2 substantially coincides with the voltage V2, and the voltage between the power supply voltage VB and the point P3 is expressed by two inductances Lw1 and Lw2. The voltage is divided. That is, when the capacitor C1 is not installed, the minimum value of the voltage V1 can be expressed by the following equation (1).
(The lowest voltage of V1) = (VB−V3) * Lw2 / (Lw1 + Lw2) + V3 (1)

  When the inductance Lw2 is relatively small with respect to the inductance Lw1 from the equation (1), that is, when the load line length is relatively short with respect to the power supply line length, the minimum voltage of the voltage V1 becomes small. I understand that.

  On the other hand, when the noise countermeasure capacitor C1 is installed, the discharge current I2 of the capacitor C1 continues to flow even after the voltages V1 and V2 coincide with each other. Therefore, the voltage V1 decreases, and the minimum voltage of V1 is The voltage is lower than the voltage shown in the equation (1). When the discharge current I2 of the capacitor C1 continues to flow and the amount of decrease in the voltage V1 increases, the following problem occurs.

  The input terminal voltage of the comparator CMP1 depends on the magnitude of the voltage V1, and when the voltage V1 decreases, the input terminal voltage of the comparator CMP1 decreases. The lower limit value of the in-phase input range of the input terminal voltage of the comparator CMP1 is in the vicinity of 2V, and when the input voltage becomes lower than this lower limit value, the comparator CMP1 does not function. That is, the output of the comparator CMP1 becomes indefinite, and an abnormal state occurs in which an overcurrent determination detection signal is output depending on the variation of the comparator CMP1 even if it is not in an overcurrent state. As a result, there arises a problem that the FET (T1) is erroneously cut off.

  To summarize the above contents, the presence of the capacitor C1 increases the amount of decrease in the voltage V1 when the FET (T1) is turned on, whereby the input voltage of the comparator CMP1 is reduced to the lower limit of the common-mode input voltage range. If the value is lower than the value, there is a possibility that the FET (T1) is erroneously cut off. That is, although the capacitor C1 is effective as a noise countermeasure, the presence of the capacitor C1 causes another problem that the FET (T1) is erroneously cut off.

  Hereinafter, simulation results for specific voltage and current changes will be described with reference to the characteristic diagrams shown in FIGS. 4, 5A, and 5B. FIG. 4 is a characteristic diagram showing changes in each voltage and current waveform when the noise countermeasure capacitor C1 is not provided in the circuit shown in FIG. Here, the circuit constants shown in FIG. 3 are set as follows. That is, power supply voltage VB = 12 V, Lw1 = 2.5 μH (corresponding to power supply line length 2.5 m), T1 on-resistance (saturated value) = 3.5 mΩ, Lw2 = 2 μH (corresponding to load line length 2 m), load Resistance of RL = 2Ω, Lw3 = 1 μH (corresponding to 1 m of ground wire length), charge pump voltage = VB + 15V, and gate resistance R3 = 1.5 kΩ.

  In FIG. 4, the horizontal axis (X axis) represents a time axis, and the two vertical axes (Y1, Y2) represent voltage coordinates and current coordinates. The vertical axis Y1 is a voltage coordinate, showing the gate voltages of V1, T1, V2, V3, VB, and the vertical axis Y2 is a current coordinate, showing the coordinates of the power line current I1, and the drain current of T1. Yes. Note that I1 and the drain current coincide with each other. Further, the vertical axis Y1 indicates a positive voltage upward, and the vertical axis Y2 indicates a positive current downward.

  In FIG. 4, when SW1 is turned on at time 2.200 ms, the gate voltage of the FET (T1) rises, voltage V1 starts to drop and voltage V2 starts to rise from time 2.209ms. At the same time, the current I1 and the T1 drain current begin to flow. At time 2.215 ms, the voltages V1 and V2 coincide with each other, the voltage V1 becomes the lowest value (6.452 V), and then both the voltages V1 and V2 rise. Here, a point on the waveform where the waveforms of the voltages V1 and V2 coincide is referred to as “point A”.

  The voltage V3 is a voltage drop generated when the drain current of the FET (T1) flows through the resistance of the load RL, and thus is proportional to the drain current of the FET (T1). The waveforms of the voltages V1 and V2 after the point A are voltages obtained by dividing the difference voltage between the power supply voltage VB and the voltage V3 by the inductances Lw1 and Lw2. Then, a decrease in the interval between the voltages V1 and V2 immediately after the voltage V1 starts to decrease causes a decrease in the voltage V1, and an increase in the voltage V3 increases the voltage V1. Further, when the voltages V1 and V2 reach the point A, the factor that lowers the voltage V1 disappears, so the point A becomes the lowest value of the voltage V1. In FIG. 4, since the capacitor C1 is not installed, the power supply line current I1 and the T1 drain current coincide with each other.

  Next, simulation results for specific voltage and current changes in the circuit shown in FIG. 3 (circuit in which the capacitor C1 is mounted) will be described with reference to FIGS. Note that C1 = 0.1 μF.

  FIG. 5A is a characteristic diagram showing changes in each voltage waveform of the circuit shown in FIG. 3, and FIG. 5B is a characteristic diagram showing changes in each current waveform of the circuit shown in FIG. In FIG. 5B, the vertical axis represents current coordinates, and shows the coordinates of the power line current I1, the discharge current I2 of the capacitor C1, and the drain current of T1. In addition, the vertical axis of the vertical axis indicates positive current. The circuit constants are the same as those shown in FIG. 4 except for the addition of the capacitor C1.

  5 (a) and 5 (b), when the FET (T1) is turned on, the voltage V1 decreases for the above-described reason, the voltage charged in the capacitor C1 is discharged, and the discharge current I2 flows. Immediately after the FET (T1) is turned on, the discharge current I2 is limited by the drain-source voltage Vds of the FET (T1). As the voltage Vds is reduced, the limit is weakened, so that the discharge current I2 increases. When the voltage Vds is reduced and reaches a point A where the voltages V1 and V2 coincide with each other, the limit is not further weakened, so that the increase in the discharge current is stopped, and then the decrease starts. That is, the discharge current peak substantially coincides with the coincidence point (point A) between the voltages V1 and V2.

  When the current I2 flows through the capacitor C1, the power source line current I1 and the drain current of T1 that are identical in the example shown in FIG. 4 (when C1 is not provided) become inconsistent (see FIG. 5B). This is because the discharge current of the capacitor C1 flows through the load line (Lw2) but does not flow through the power supply line (Lw1), and the charging current of the capacitor C1 flows through the power supply line but does not flow through the load line. And the discharge current and the charge current of the capacitor C1 do not flow at the same time.

  When the increasing gradient of the drain current of the FET (T1) is large, the increasing gradient of the power supply line current I1 becomes small. Conversely, when the increasing gradient of the drain current of the FET (T1) becomes small, Increasing slope increases. For this reason, when the capacitor C1 exists, the voltage V1 vibrates (see FIG. 5A). At this time, the first decrease in V1 after the FET (T1) is turned on becomes the lowest value of the voltage V1. This is because the voltage V3 increases as time passes after the FET (T1) is turned on, so that the decrease in the voltage V1 is limited.

  In FIG. 4, after the point A has elapsed, the voltage V1 has changed from decreasing to increasing, but in FIG. 5 (a), the voltage V1 does not start increasing but decreases further until the discharge current of the capacitor C1 becomes zero. It is falling. The minimum value of the voltage V1 is 3.517V, which is 2.935V lower than 6.452V without the capacitor C1. The reason why the voltage V1 further decreases after the point A has elapsed is as follows.

  The discharge current I2 of the capacitor C1 that has increased to the point A starts to decrease after the point A elapses. The current change (vibration) of the capacitor C1 is performed when the capacitance of the capacitor C1 exchanges energy with the inductance associated with the path of the charge / discharge current of the capacitor C1. In order to return to this state, a discharge current decrease period as much as the period during which the discharge current increases is required. During this period, the voltage V1 must decrease in order for C1 to discharge. This is the reason why the voltage V1 decreases after the point A has elapsed.

  The drop amount of the voltage V1 at that time depends on the amount of charge released from the capacitor C1 after the point A has elapsed. As this charge amount increases, the drop amount of the voltage V1 increases. When the discharge current becomes zero, according to the law of energy conservation, the electromagnetic energy stored in the inductance of the path changes from increase to decrease, and the electromagnetic energy stored in the inductance is released, whereby the capacitor C1 is charged. Since the voltage V1 increases when the capacitor C1 is charged, the voltage V1 increases.

  The reference point (0 V) of the voltage waveform shown in FIG. 5A is not the ground level (GND) but the voltage Vm of the negative terminal P12 of the control circuit 10. The ground level is a voltage different from the voltage Vm due to the discharge current I2 flowing through the inductance Lw3 of the ground wire. When the discharge current I2 is increasing, the ground level is higher than the voltage Vm. When the discharge current I2 is decreasing and when the charging current is increasing, the ground level is lower than the voltage Vm. Yes. The decrease in the ground level from the voltage Vm lowers the minimum value of the voltage V1 when the voltage Vm is used as a reference. That is, it can be seen from the simulation result that the magnitude of the voltage (V1-Vm) is reduced by the decrease current in the discharge direction and the increase current in the charge direction of the capacitor C1 flowing in the ground line (Lw3).

JP-A-6-38368

  As described above, in the conventional load control device, by installing the noise countermeasure capacitor C1 between the plus terminal P11 and the minus terminal P12 of the control circuit 10, it is possible to prevent the influence of strong radio waves and electromagnetic noise. On the other hand, the voltage (V1-Vm) is reduced when the FET (T1) is turned on, causing a problem that the comparator CMP1 malfunctions. Therefore, there has been an increasing demand for somehow to achieve both.

  The present invention has been made in order to solve such a conventional problem, and an object of the present invention is to provide a circuit for detecting an overcurrent even when a noise countermeasure capacitor is installed. An object of the present invention is to provide a load control device that can be operated normally.

  In order to achieve the above object, according to the first aspect of the present invention, a semiconductor switch (for example, MOSFET) is provided between a DC power supply and a load, and the semiconductor switch is turned on and off to drive the load. In the load control device for controlling the stop, the first main electrode (for example, drain) of the semiconductor switch is connected to the positive electrode of the DC power source via a power line, and the second main electrode ( For example, the source) is connected to one end of the load via a load line, the other end of the load is connected to the negative pole of the DC power source, and a positive terminal connected to the first main electrode A control circuit for controlling on / off of the semiconductor switch, including a negative terminal that is grounded via a grounding wire and driven by a voltage between the positive terminal and the negative terminal. Further, the control circuit detects the occurrence of an overcurrent by comparing a reference voltage (V4) based on a voltage generated between the positive terminal and the negative terminal with a voltage generated at the second main electrode. When driving the load, the comparison means outputs a drive signal to the semiconductor switch, and when the comparison means detects the occurrence of an overcurrent, the control means (driver 11) stops outputting the drive signal. ) And a capacitor (C1) provided between the plus terminal and the minus terminal, and a diode (D1) having a forward direction from the minus terminal side to the ground side on the grounding wire, A parallel connection circuit of the insertion resistor (R5) is provided.

  According to a second aspect of the present invention, the control circuit includes a series connection circuit of a first resistor (R1) and a second resistor (R2) between the plus terminal and the minus terminal, A voltage generated at a connection point between the first resistor and the second resistor is used as the reference voltage.

  In the load control device according to the present invention, since the insertion resistor (R5) is provided in the grounding wire (earth wire) that connects the negative terminal provided in the control circuit and the ground, the first time when the input switch SW1 is turned on. Even when the voltage (V1) generated at the main electrode of the capacitor decreases and the discharge current (I2) of the capacitor (C1) flows, the voltage at the negative terminal is made relative to the ground level due to the voltage drop (VR5) of the insertion resistor. Therefore, it is possible to increase the voltage across the capacitor (C1), suppress the discharge current I2, and suppress the decrease in the voltage (V1). As a result, malfunction of the control circuit can be prevented.

It is a circuit diagram which shows the structure of the load control apparatus which concerns on one Embodiment of this invention. It is a characteristic view which shows the change of each voltage and each current of the load control apparatus which concerns on one Embodiment of this invention. It is a circuit diagram which shows the structure of the conventional load control apparatus. It is a characteristic view which shows the change of each voltage and electric current when not providing the capacitor | condenser C1 with the load control apparatus in the past. It is a characteristic view which shows the change of each voltage and each electric current at the time of providing the capacitor | condenser C1 with the load control apparatus in the past.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a load driving circuit equipped with a load control device according to an embodiment of the present invention. As shown in the figure, in this load driving circuit, an FET (T1; semiconductor switch) is arranged between a DC power supply VB (the output voltage is also indicated by the same symbol VB) and a load RL. Thus, the FET (T1) is switched on and off to control the driving and stopping of the load RL.

  The drain of the FET (T1) is connected to the positive pole of the DC power supply VB via the power line, the source is connected to one end of the load RL via the load line, and the other end of the load RL is connected to the ground. It is connected. The power supply line is a wire from the positive pole of the DC power supply VB to the drain of the FET (T1), and the load line is a wire from the source of the FET (T1) to the load RL.

  Since the power line has an inductance component, this is Lw1, and since the load line similarly has an inductance component, this is Lw2. Note that the resistance of the power supply line and the load line is negligibly small.

  The control circuit 10 includes a plus terminal P11 and a minus terminal P12. The plus terminal P11 is connected to the drain (P1) of the FET (T1), and the minus terminal P12 (voltage Vm) is a resistor R5 (insertion resistor). Are connected to the ground via a parallel connection circuit of the diode D1 and an earth wire (grounding wire). Furthermore, the control circuit 10 includes a comparator CMP1 (comparison means), a driver 11, and a charge pump 12. Since the ground wire (the electric wire from the negative terminal P12 to the ground) also has an inductance component like the power supply line and the load line, it is set to Lw3. The resistance of the ground wire is neglected because it is extremely small.

  A series connection circuit of resistors R1 (first resistor) and R2 (second resistor) is provided between the plus terminal P11 and the minus terminal P12 of the control circuit 10, and the connection point P4 (voltage V4). Are connected to the positive side input terminal of the comparator CMP1. The negative input terminal of the comparator CMP1 is connected to the source (point P2, voltage V2) of the FET (T1). When the FET (T1) is turned on and the load RL is driven, the voltage V2 exceeds the voltage V4, so that the output signal of the comparator CMP1 becomes L level. In addition, when the load line is grounded, an overcurrent flows through the FET (T1), and the drain-source voltage Vds of the FET (T1) rises. Therefore, the source voltage V2 is lowered, so that the voltage V2 becomes equal to the voltage V4. The output signal of the comparator CMP1 becomes H level. This signal is supplied to the driver 11 as an overcurrent determination output signal.

  The output terminal of the driver 11 is connected to the gate of the FET (T1) through the resistor R3. Further, the driver 11 is connected to the plus terminal P11 via the resistor R4, and is connected to the minus terminal P12 via the input switch SW1. Therefore, when the input switch SW1 is off (open circuit), an H level signal is input to the driver 11 to turn off the FET (T1). Conversely, when the input switch SW1 is on (closed), the driver 11 is low. A level signal is input to turn on the FET (T1). Further, when an H level signal (overcurrent determination output signal) is supplied from the comparator CMP1, the FET (T1) is turned off.

  Furthermore, a capacitor C1 is installed between the plus terminal P11 and the minus terminal P12 in order to prevent the load control device from malfunctioning due to strong radio waves or electromagnetic noise generated from various electrical components. Yes.

  That is, the load control device according to the present embodiment has a resistance R5 (insertion resistance) and a diode between the negative terminal P12 of the control circuit 10 and the ground line (Lw3), as compared with the conventional circuit shown in FIG. The difference is that a parallel connection circuit with D1 is provided. The direction of the diode D1 is such that the negative terminal P12 side is an anode and the ground line side is a cathode.

  Next, the operation of the load control device according to the present embodiment will be described. When the input switch SW1 is turned on, the voltage of the charge pump 12 is output from the driver 11 and applied to the gate of the FET (T1). Thereby, the FET (T1) is switched from OFF to ON. In the transient state where the FET (T1) shifts from OFF to ON, the power is supplied through the path of the power supply VB plus terminal → power supply line (Lw1) → P1 → T1 → P2 → Lw2 → P3 → RL → GND → power supply VB minus terminal. A line current I1 (solid line) flows.

  When the FET (T1) is turned on, the current I1 starts increasing from zero and increases to a current value obtained by dividing the power supply voltage VB by the resistance of the load RL. In this process, the back electromotive force proportional to the increasing gradient is generated in the inductances Lw1 and Lw2 due to the increase in the current I1. The counter electromotive force generated in the inductance Lw1 pushes down the voltage V1 at the point P1. Accordingly, the voltage V1 at the point P1 decreases, the voltage charged in the capacitor C1 is discharged, and the discharge current I2 flows.

  The discharge current I2 (dashed line) of the capacitor C1 flows through the path of C1 plus terminal → P11 → P1 → T1 → P2 → Lw2 → P3 → RL → GND → Lw3 → R5 → P12 → C1 minus terminal, and the inductance of the load line A back electromotive force is generated at Lw2. At this time, since the discharge current I2 does not flow through the power supply line, no back electromotive force due to the discharge current I2 is generated in the inductance Lw1. Since the discharge current I2 flows through the resistor R5, a voltage is generated between the negative terminal P12 of the control circuit 10 and the ground level, and the voltage Vm of the negative terminal P12 is from the ground level (the negative pole of the DC power supply VB). Also lower.

  This will be described in detail below. When the discharge current I2 of the capacitor C1 flows, voltage drops VR5 and VLw3 are generated in the resistor R5 and the ground line (Lw3), and the voltage Vm is lowered from the ground level. Thereby, the terminal voltage VC1 of the capacitor C1 can be expressed by the following equation (2).

VC1 = (V1-GND)-(Vm-GND)
= V1-Vm
= V1- (VR5 + VLw3)
= V1 + R5 * I2 + Lw3 * dI2 / dt (2)
However, the sign of I2 is positive for the discharging current of the capacitor C1 and negative for the charging current.

  In the equation (2), “R5 * I2” is positive while the capacitor C1 is discharged, that is, the voltage VC1 is decreasing, and “Lw3 * dI2 / dt” is the discharge current I2 increasing. It is positive while it is on, zero at the peak, and negative when it decreases past the peak. At this time, (R5 * I2 + Lw3 * dI2 / dt) becomes positive during most of the period during which the discharge current I2 flows, and it becomes negative only immediately before the discharge current becomes zero.

  Therefore, the voltage between the terminals of the capacitor C1 (which is referred to as “VC1”) is larger than the voltage V1 while the capacitor C1 is being discharged, and the difference is the maximum at the point A, and the magnitude thereof is the resistance R2. The peak value of the discharge current I2 is multiplied. That is, the voltage Vm is lower than the ground level.

  For this reason, voltage VC1 expands and the increase in discharge current I2 is suppressed. When the discharge current I2 decreases, the voltage VR5 generated in the resistor R5 decreases this time, thereby reducing the voltage VC1 and suppressing the decrease in the discharge current I2. That is, when the discharge current I2 of the capacitor C1 flows to the resistor R5, a voltage drop VR5 is generated, and this voltage drop VR5 suppresses the fluctuation of the discharge current I2, so that it exists in the path of the capacitance of the capacitor C1 and the discharge current I2. Therefore, the natural vibration of the charge / discharge current flowing between the inductor and the inductance is suppressed, and the vibration of the voltage V1 is eliminated.

  In other words, in the characteristic diagram of FIG. 5A shown in the conventional example, the voltage V1 oscillates greatly in the vertical direction, but this oscillation is suppressed and a rapid decrease in the voltage V1 can be suppressed, and the minimum value of the voltage V1. Can be raised.

  Further, when the voltage V1 decreases and the discharge current I2 flows, the voltage Vm at the minus terminal P12 decreases from the ground level by the voltage drop VR5 generated at the resistor R5. Accordingly, the power supply voltage of the control circuit 10 (the voltage between the positive terminal P11 and the negative terminal P12) is expanded toward the negative terminal side, and the common-mode voltage range of the comparator CMP1 is expanded correspondingly. As a result, the comparator CMP1 can be reliably operated.

  The diode D1 arranged in parallel with the resistor R5 is for bypassing the resistor R5 and eliminating the influence of the resistor R5 when the voltage V1 rises and the charging current of the capacitor C1 flows. is there. The resistor R5 is for suppressing a decrease in the voltage V1, and is not necessary when the voltage V1 increases.

  Next, simulation results for specific voltage and current changes in the circuit shown in FIG. 1 will be described with reference to FIGS. 2 (a) and 2 (b). Note that R5 = 10Ω.

  2A is a characteristic diagram showing changes in each voltage waveform of the circuit shown in FIG. 1, and FIG. 2B is a characteristic diagram showing changes in each current waveform of the circuit shown in FIG. In FIG. 2B, the vertical axis represents current coordinates, and shows the coordinates of the power line current I1, the discharge current I2 of the capacitor C1, and the drain current of T1. In addition, the vertical axis of the vertical axis indicates positive current. Each circuit constant is the same as the conditions shown in FIGS. 5A and 5B except for the addition of the resistor R5.

  The peak value of the discharge current I2 shown in FIG. 2B at the point A shown in FIG. 2A is 339 mA, which is about 1/3 of the 927 mA shown in FIG. 5B. At the same time, the natural oscillation (3 μs period) of the discharge current I2 generated in FIG. As in FIG. 5A, the voltage waveforms (V1, V2, V3, GND) are shown on the basis of the control circuit minus terminal voltage (Vm).

  Here, each voltage shown in FIG. 2A is not based on the ground, so care must be taken. The waveform of (V1-GND) indicates the ground-based voltage V1, and V1 indicates the Vm-based V1 waveform. GND (a negative terminal of the power supply VB) indicates a ground voltage waveform based on Vm.

  The waveform of the voltage V1 is larger than (V1-GND) by the waveform of the GND voltage. When the discharge current I2 becomes zero, the voltage becomes the lowest voltage, and the value is 8.39V, which is shown in FIG. 4) V is larger than the V1 minimum value 3.517 V shown in FIG. Thus, by providing the resistor R5 (insertion resistor), it is possible to suppress the decrease in the voltage V1.

  Thus, in the load control device according to the present embodiment, since the resistor R5 is provided on the ground wire (grounding wire) that connects the negative terminal P12 provided in the control circuit 10 and the ground, the input switch SW1. Even when the voltage V1 is reduced and the discharge current I2 of the capacitor C1 flows, the voltage at the negative terminal P12 can be made lower than the ground level by the voltage drop VR5 of the resistor R5. The voltage VC1 across the capacitor C1 can be increased to suppress the discharge current I2 and suppress the decrease in the voltage V1.

  For this reason, the conventional problem that the circuit for detecting the overcurrent malfunctions due to a sudden drop in the voltage V1 can be solved.

  The load control device of the present invention has been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit is replaced with an arbitrary configuration having the same function. Can do.

  For example, in the above-described embodiment, the load control device mounted on the load drive circuit for driving the load mounted on the vehicle has been described as an example, but the present invention is not limited to this, and other The present invention can also be applied to other load driving circuits.

  In the above-described embodiment, the field effect transistor (FET) has been described as an example of the semiconductor switch. However, the present invention is not limited to this, and can be applied to other semiconductor switches.

  The present invention is useful for preventing a rapid drop in the drain voltage of the FET even when a noise countermeasure capacitor is provided in the load drive circuit.

11 Driver 12 Charge pump VB DC power supply T1 FET (semiconductor switch)
RL load CMP1 comparator (comparison means)
C1 capacitor D1 diode R1 resistance (first resistance)
R2 resistance (second resistance)
R5 resistance (insertion resistance)
Lw1 Power line inductance Lw2 Load line inductance Lw3 Ground wire (grounding wire) inductance

Claims (2)

In a load control device that provides a semiconductor switch between a DC power supply and a load, switches the semiconductor switch on and off, and controls driving and stopping of the load.
The first main electrode of the semiconductor switch is connected to the positive electrode of the DC power supply via a power line, and the second main electrode is connected to one end of the load via a load line, The other end of the load is connected to the negative pole of the DC power source,
Furthermore,
A positive terminal connected to the first main electrode, and a negative terminal that is grounded via a grounding wire, and is driven by a voltage between the positive terminal and the negative terminal to turn on the semiconductor switch; A control circuit for controlling off, and the control circuit further comprises:
A comparison means for detecting the occurrence of an overcurrent by comparing a reference voltage based on a voltage generated between the positive terminal and the negative terminal and a voltage generated in the second main electrode;
Control means for outputting a drive signal to the semiconductor switch during driving of the load and stopping the output of the drive signal when occurrence of an overcurrent is detected by the comparison means;
A capacitor provided between the positive terminal and the negative terminal,
A load control device, wherein a parallel connection circuit of a diode having a forward direction from the minus terminal side to the ground side and an insertion resistor is provided on the grounding wire.   The control circuit includes a series connection circuit of a first resistor and a second resistor between the plus terminal and the minus terminal, and a voltage generated at a connection point between the first resistor and the second resistor. The load control device according to claim 1, wherein the reference voltage is used.

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