JP5481701B2 - Electronic device and method for manufacturing electronic device - Google Patents

Electronic device and method for manufacturing electronic device Download PDF

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JP5481701B2
JP5481701B2 JP2009145946A JP2009145946A JP5481701B2 JP 5481701 B2 JP5481701 B2 JP 5481701B2 JP 2009145946 A JP2009145946 A JP 2009145946A JP 2009145946 A JP2009145946 A JP 2009145946A JP 5481701 B2 JP5481701 B2 JP 5481701B2
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substrate
electronic device
bonding material
electrode post
electrode
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JP2011003749A (en
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孝 大塚
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Description

本発明は、電子装置および電子装置の製造方法に関し、さらに詳細には、表面にシールド材が接合される電子装置および当該電子装置の製造方法に関する。   The present invention relates to an electronic device and a method for manufacturing the electronic device, and more particularly to an electronic device in which a shield material is bonded to the surface and a method for manufacturing the electronic device.

従来の電子装置には、基板上に実装された電子部品を電磁波から保護するためのシールド材を備えたものがある（特許文献１、特許文献２参照）。   Some conventional electronic devices include a shielding material for protecting electronic components mounted on a substrate from electromagnetic waves (see Patent Document 1 and Patent Document 2).

ここで、図９に従来の電子装置１００の例を示す（特許文献１参照）。より詳しくは、電子装置１００は、大略すると基板１０１と、電子部品（ここでは半導体チップ）６８と、実装用端子１０５と、グラウンド端子７６と、トランスファーモールド樹脂７７と、シールド材１０７とを有した構成とされている。   Here, FIG. 9 shows an example of a conventional electronic device 100 (see Patent Document 1). More specifically, the electronic device 100 generally includes a substrate 101, an electronic component (here, a semiconductor chip) 68, a mounting terminal 105, a ground terminal 76, a transfer molding resin 77, and a shield material 107. It is configured.

基板１０１は、大略すると基材５２と、貫通ビア５３と、上部配線５４と、上部樹脂層５５と、ビア５８，８３と、ワイヤ接続部６１と、接続パッド６３，１０４と、ソルダーレジスト６６，１０３と、下部配線８１と、下部樹脂層８２とを有した構成とされている。接続パッド１０４は、ビア８３と接続されるよう下部樹脂層８２の面８２Ａに設けられている。接続パッド１０４は、実装用端子１０５を配設するためのものである。ソルダーレジスト１０３は、下部樹脂層８２の面８２Ａを覆うと共に、接続パッド１０４を露出させるよう下部樹脂層８２に設けられている。また、接続パッド６３は、ビア５８と接続されるよう上部樹脂層５５上に設けられている。   The substrate 101 is roughly composed of a base material 52, a through via 53, an upper wiring 54, an upper resin layer 55, vias 58 and 83, a wire connection portion 61, connection pads 63 and 104, a solder resist 66, 103, a lower wiring 81, and a lower resin layer 82. The connection pad 104 is provided on the surface 82 A of the lower resin layer 82 so as to be connected to the via 83. The connection pad 104 is for arranging the mounting terminal 105. The solder resist 103 is provided on the lower resin layer 82 so as to cover the surface 82A of the lower resin layer 82 and to expose the connection pads 104. The connection pad 63 is provided on the upper resin layer 55 so as to be connected to the via 58.

実装用端子１０５は、略球形状の導体であり、接続パッド１０４上に配設されている。実装用端子１０５は、マザーボード等の他の基板と電気的に接続するための外部接続端子である。   The mounting terminal 105 is a substantially spherical conductor and is disposed on the connection pad 104. The mounting terminal 105 is an external connection terminal for electrically connecting to another board such as a mother board.

グラウンド端子７６は、グラウンド電位とされた導体であり、その形状は平坦な面７６Ａを有した略球形状とされている。電極端子（グラウンド端子）７６は、接続パッド６３上に配設されている。グラウンド端子７６の平坦な面７６Ａは、トランスファーモールド樹脂７７に露出されると共に、トランスファーモールド樹脂７７の面７７Ａと略面一とされている。   The ground terminal 76 is a conductor having a ground potential, and has a substantially spherical shape having a flat surface 76A. The electrode terminal (ground terminal) 76 is disposed on the connection pad 63. The flat surface 76A of the ground terminal 76 is exposed to the transfer mold resin 77 and is substantially flush with the surface 77A of the transfer mold resin 77.

金属板を用いて形成されるシールド材１０７は、グラウンド端子７６と電気的に接続されることで、電磁波等の悪影響を抑制するシールド機能を奏するものである。シールド材１０７は、導電性接合材（例えば、はんだペースト）１０８を介してグラウンド端子７６の平坦な面７６Ａと電気的に接続されている。   The shield material 107 formed using a metal plate is electrically connected to the ground terminal 76, thereby exhibiting a shield function that suppresses adverse effects such as electromagnetic waves. The shield material 107 is electrically connected to the flat surface 76A of the ground terminal 76 via a conductive bonding material (for example, solder paste) 108.

また、シールド材１０７として金属層を用いた場合には、導電性接合材（例えば、Ａｇフィラー含有エポキシ樹脂）により金属層とグラウンド端子７６とを電気的に接続することができる。金属層としては、例えば、銅箔、Ｃｕめっき層等を用いることができる。また、Ｃｕめっき層上に保護膜としてＡｕ層を設けても良い。   When a metal layer is used as the shield material 107, the metal layer and the ground terminal 76 can be electrically connected by a conductive bonding material (for example, an Ag filler-containing epoxy resin). For example, a copper foil, a Cu plating layer, or the like can be used as the metal layer. Moreover, you may provide Au layer as a protective film on Cu plating layer.

また、図１０に従来の電子装置１００の変形例を示す（特許文献１参照）。より詳しくは、図９に示すシールド材１０７の代わりに、基板１０１の側面を覆うようなケース状のシールド材１２５を設ける構成である。このようなシールド材１２５を設けることにより、シールド材１０７を適用した場合よりも高いシールド効果を得ることができる。   FIG. 10 shows a modification of the conventional electronic device 100 (see Patent Document 1). More specifically, a case-like shield material 125 that covers the side surface of the substrate 101 is provided instead of the shield material 107 shown in FIG. By providing such a shield material 125, a higher shielding effect can be obtained than when the shield material 107 is applied.

特開２００６−１９０７６７号公報JP 2006-190767 A 特開２００８−１４７５７２号公報JP 2008-147572 A

しかし、シールド材と基板の電極端子とが、はんだペーストあるいは導電性接合材を用いて接合（電気的な接続も含む）された電子装置においては、熱衝撃（すなわち温度上昇および温度降下の繰り返し）を受けた際に、当該接合された箇所において断線が発生し得る課題があった。この断線発生の主たる要因は、シールド材とモールドパッケージ（基板上に電子部品等が実装された後、封止樹脂を用いてモールドされた状態の構造体）との熱膨張差であると考えられる。   However, in an electronic device in which the shield material and the electrode terminal of the board are joined (including electrical connection) using a solder paste or a conductive joining material, thermal shock (that is, repeated temperature rise and temperature fall) When receiving, there existed a subject which may generate | occur | produce a disconnection in the said joined location. The main cause of this disconnection is considered to be a difference in thermal expansion between the shield material and the mold package (a structure in which an electronic component or the like is mounted on a substrate and then molded using a sealing resin). .

上記事情に鑑み、本発明は、シールド材と基板の電極端子とが接合される電子装置において、接合箇所の断線を防止することが可能な電子装置およびその製造方法を提供することを目的とする。   In view of the above circumstances, an object of the present invention is to provide an electronic device capable of preventing disconnection at a joint location in an electronic device in which a shield material and an electrode terminal of a substrate are joined, and a method for manufacturing the same. .

一実施形態として、以下に開示するような解決手段により、前記課題を解決する。   As an embodiment, the above-described problem is solved by a solution as disclosed below.

開示の電子装置は、矩形状の基板と、前記基板上に実装された電子部品と、前記基板上の周縁部に立設された電極ポストと、前記電子部品および前記電極ポストを被覆して前記基板上に設けられた封止樹脂と、からなり、前記電極ポストの端面が、前記封止樹脂表面に露出した構造体を有し、前記電極ポストの端面上に配設される導電性接合材と、前記封止樹脂の表面上で且つ該電極ポストの端面露出位置と異なる位置に配設される接合材とによって、前記封止樹脂の表面にシールド材が接合されており、前記接合材は、前記導電性接合材に対して、弾性率が小さく、前記電極ポストは、前記基板の周縁部の一箇所に設けられており、前記接合材は、前記基板の異なる三つのコーナー部に配設されていることを要件とする。 The disclosed electronic device includes a rectangular substrate, an electronic component mounted on the substrate, an electrode post erected on a peripheral edge of the substrate, and the electronic component and the electrode post so as to cover the electronic device. A conductive bonding material disposed on the end face of the electrode post, the structure having a structure in which an end face of the electrode post is exposed on the surface of the sealing resin. And a bonding material disposed on the surface of the sealing resin and at a position different from the end face exposed position of the electrode post, a shield material is bonded to the surface of the sealing resin, and the bonding material is The elastic modulus is small with respect to the conductive bonding material, and the electrode post is provided at one peripheral portion of the substrate, and the bonding material is disposed at three different corner portions of the substrate. It is a requirement that

開示の電子装置によれば、シールド材と基板の電極端子とが接合される箇所の断線を防止することが可能となる。   According to the disclosed electronic device, it is possible to prevent disconnection of a portion where the shield material and the electrode terminal of the substrate are joined.

本発明の第一の実施形態に係る電子装置の例を示す概略図である。It is a schematic diagram showing an example of an electronic device concerning a first embodiment of the present invention. 図１の電子装置の変形例を示す概略図である。It is the schematic which shows the modification of the electronic device of FIG. 図１の電子装置の他の変形例を示す概略図である。It is the schematic which shows the other modification of the electronic device of FIG. 本発明の第二の実施形態に係る電子装置の例を示す概略図である。It is the schematic which shows the example of the electronic device which concerns on 2nd embodiment of this invention. 本発明の実施形態に係る電子装置の製造方法を説明するための説明図である。It is explanatory drawing for demonstrating the manufacturing method of the electronic device which concerns on embodiment of this invention. 本発明の実施形態に係る電子装置の製造方法を説明するための説明図である。It is explanatory drawing for demonstrating the manufacturing method of the electronic device which concerns on embodiment of this invention. 本発明の実施形態に係る電子装置の製造方法を説明するための説明図である。It is explanatory drawing for demonstrating the manufacturing method of the electronic device which concerns on embodiment of this invention. 本発明の実施形態に係る電子装置の製造方法を説明するための説明図である。It is explanatory drawing for demonstrating the manufacturing method of the electronic device which concerns on embodiment of this invention. 従来の実施形態に係る電子装置の例を示す概略図である。It is the schematic which shows the example of the electronic device which concerns on the conventional embodiment. 従来の実施形態に係る電子装置の例を示す概略図である。It is the schematic which shows the example of the electronic device which concerns on the conventional embodiment. 発明者が検討した電子装置の例を示す概略図である。It is the schematic which shows the example of the electronic device which the inventor examined.

本発明の第一の実施形態に係る電子装置１の概略図を図１に示す。ここで、図１（ａ）は、電子装置１の平面図（後述のシールド材６については不図示）であり、図１（ｂ）は、電子装置１の断面図（図１（ａ）のＡ−Ａ線断面図）である。   FIG. 1 shows a schematic diagram of an electronic device 1 according to the first embodiment of the present invention. Here, FIG. 1A is a plan view of the electronic device 1 (the shield material 6 described later is not shown), and FIG. 1B is a cross-sectional view of the electronic device 1 (FIG. 1A). It is an AA line sectional view).

本実施形態に係る電子装置１は、基板上に実装された電子部品を電磁波から保護するためのシールド材を備えた電子装置である。その概略構成として、電子装置１は、基板２と、電子部品４と、グラウンド電位の電極端子となる電極ポスト５と、封止樹脂３と、シールド材６とを備える。本実施形態においては、矩形状の基板２の中央部に電子部品４が搭載され、周縁部に電極ポスト５が立設されて、図１（ｂ）に示すように封止樹脂３を用いてモールドされている。なお、基板２上に電子部品４および電極ポスト５が設けられて封止樹脂３によりモールドされた構造体を、以下において「モールドパッケージ」と称する（符号７）。   The electronic device 1 according to the present embodiment is an electronic device provided with a shield material for protecting electronic components mounted on a substrate from electromagnetic waves. As its schematic configuration, the electronic device 1 includes a substrate 2, an electronic component 4, an electrode post 5 serving as a ground potential electrode terminal, a sealing resin 3, and a shield material 6. In the present embodiment, an electronic component 4 is mounted at the center of a rectangular substrate 2, and electrode posts 5 are erected on the peripheral edge, and a sealing resin 3 is used as shown in FIG. Molded. The structure in which the electronic component 4 and the electrode post 5 are provided on the substrate 2 and is molded with the sealing resin 3 is hereinafter referred to as a “mold package” (reference numeral 7).

ここで、基板２上に搭載される電子部品４の例としては、半導体チップ、チップキャパシタ、チップ抵抗等、各種電子部品が挙げられる。また、搭載の方法についても、フリップチップボンディング、ワイヤボンディング等、各種方法を適用することができる。なお、図１は、フリップチップボンディングにより、電子部品４のバンプ２８が、導電性接合材（ここでは、はんだ）２９を介して、基板２上の接続パッド２４に接合されている場合の例を示す（図９、図１０を除く他の図において同様）。   Here, examples of the electronic component 4 mounted on the substrate 2 include various electronic components such as a semiconductor chip, a chip capacitor, and a chip resistor. Also, various methods such as flip chip bonding and wire bonding can be applied to the mounting method. FIG. 1 shows an example in which the bump 28 of the electronic component 4 is bonded to the connection pad 24 on the substrate 2 through the conductive bonding material (here, solder) 29 by flip chip bonding. This is shown (the same applies to other drawings excluding FIGS. 9 and 10).

本実施形態における基板２は、下層基板２ａと上層基板２ｂとを有する多層基板である。ただし、多層基板に限定されるものではない。ここで、特に、グラウンド電位となる貫通ビア２１、２２、２３、および接続パッド２４、２５、配線パターン２６について図１（ｂ）中に図示する。
上層基板２ｂ上に実装された電子部品４のグラウンド端子（不図示）が貫通ビア２２を介して配線パターン２６と接続される。同様に上層基板２ｂ上に立設された電極ポスト５がグラウンド用の接続パッド２４および貫通ビア２３を介して配線パターン２６と接続される。配線パターン２６は、貫通ビア２１を介して下層基板２ａの一面側（図１（ｂ）中の下面側）に設けられた接続パッド２５と接続される。当該接続パッド２５には、はんだボール等の実装用端子（不図示）が配設されて、マザーボード等の他の基板と電気的に接続される。 The substrate 2 in the present embodiment is a multilayer substrate having a lower layer substrate 2a and an upper layer substrate 2b. However, it is not limited to a multilayer substrate. Here, in particular, the through vias 21, 22, 23, the connection pads 24, 25, and the wiring pattern 26 that become the ground potential are illustrated in FIG.
A ground terminal (not shown) of the electronic component 4 mounted on the upper substrate 2 b is connected to the wiring pattern 26 through the through via 22. Similarly, the electrode post 5 erected on the upper substrate 2 b is connected to the wiring pattern 26 via the ground connection pad 24 and the through via 23. The wiring pattern 26 is connected to the connection pad 25 provided on one surface side (the lower surface side in FIG. 1B) via the through via 21. The connection pads 25 are provided with mounting terminals (not shown) such as solder balls and are electrically connected to other boards such as a mother board.

ここで、電極ポスト５は、グラウンド電位とされた導体であり、一例として、Ｃｕ（銅）等の金属柱（例えば、円柱状、四角柱状等）からなる。本実施形態においては、導電性接合材（はんだ、もしくは導電性樹脂等）２７を用いて、基板２の接続パッド２４に接合される。なお、金属柱に代えて、Ｃｕめっき等により基板２の接続パッド２４上に作り込んでもよい。
一般に、電子装置では、基板の中央部に高密度に配線が引き回され、且つ各種電子部品が搭載されるため、必然的に電極ポストはコーナー部等の基板周縁部に設けざるを得ない。 Here, the electrode post 5 is a conductor having a ground potential, and includes, for example, a metal column such as Cu (copper) (for example, a columnar shape, a rectangular column shape, or the like). In the present embodiment, the conductive bonding material (solder, conductive resin or the like) 27 is used to bond to the connection pads 24 of the substrate 2. In place of the metal pillar, it may be formed on the connection pad 24 of the substrate 2 by Cu plating or the like.
In general, in an electronic device, wiring is routed at a high density in the central portion of a substrate and various electronic components are mounted. Therefore, the electrode posts are inevitably provided on the peripheral portion of the substrate such as a corner portion.

当該電極ポスト５は、貫通ビア２３と接続されていない一面側（図１（ｂ）中の上面側）の端面（以下、単に「上端面」という）が、モールドパッケージ７における封止樹脂３の表面（基板２と接しない側の面）から露出するように形成される。例えば、後述するように、封止樹脂３により電極ポスト５が覆われるようにモールドされた後に、当該電極ポスト５の上端面が露出するように封止樹脂の一部を除去することによって、上記の露出形状に形成される。この場合、封止樹脂３の表面に対して電極ポスト５の上端面が窪んだ状態となる。
本実施形態に特徴的な構成として、電極ポスト５は、図１（ａ）に示すように、基板の一つのコーナー部（ここではコーナー部Ｃ１）にのみ設けられる。なお、変形例として、図２に示すように、一つのコーナー部において、複数の電極ポスト５を近接させて設ける構成も考えられる。ここで、図２（ａ）は、電子装置１の平面図（後述のシールド材６については不図示）であり、図２（ｂ）は、電子装置１の断面図（図２（ａ）のＢ−Ｂ線断面図）である。 The electrode post 5 has an end surface (hereinafter simply referred to as “upper end surface”) on one surface side (the upper surface side in FIG. 1B) that is not connected to the through via 23, of the sealing resin 3 in the mold package 7. It is formed so as to be exposed from the surface (the surface on the side not in contact with the substrate 2). For example, as described later, after the electrode post 5 is molded so as to be covered with the sealing resin 3, a part of the sealing resin is removed so that the upper end surface of the electrode post 5 is exposed. The exposed shape is formed. In this case, the upper end surface of the electrode post 5 is recessed with respect to the surface of the sealing resin 3.
As a configuration characteristic of the present embodiment, the electrode post 5 is provided only at one corner portion (here, the corner portion C1) of the substrate, as shown in FIG. As a modification, as shown in FIG. 2, a configuration in which a plurality of electrode posts 5 are provided close to each other at one corner portion is also conceivable. Here, FIG. 2A is a plan view of the electronic device 1 (the shield material 6 described later is not shown), and FIG. 2B is a cross-sectional view of the electronic device 1 (FIG. 2A). It is a BB line sectional view).

また、シールド材６は、電極ポスト５と電気的に接続されることで、電磁波等の悪影響を抑制するシールド機能を奏するものである。一例として、導電性金属材料を用いて平板状に形成される。ここで、本実施形態に特徴的な構成として、シールド材６は、モールドパッケージ７の表面に露出している電極ポスト５の上端面の上に配設される導電性接合材１１と、モールドパッケージ７の表面上で且つ電極ポスト５の上端面が露出する位置（ここではコーナー部Ｃ１）とは異なる位置のコーナー部（ここではコーナー部Ｃ２、Ｃ３、Ｃ４）に配設される接合材１２とによって、モールドパッケージ７の表面（封止樹脂３の表面）に接続されている（図１（ａ）、図１（ｂ）参照）。   In addition, the shield material 6 is electrically connected to the electrode post 5, thereby exhibiting a shield function that suppresses adverse effects such as electromagnetic waves. As an example, a conductive metal material is used to form a flat plate. Here, as a characteristic configuration of the present embodiment, the shield material 6 includes a conductive bonding material 11 disposed on the upper end surface of the electrode post 5 exposed on the surface of the mold package 7, and a mold package. 7 and a bonding material 12 disposed in a corner portion (here, corner portions C2, C3, C4) at a position different from the position where the upper end surface of the electrode post 5 is exposed (here, the corner portion C1). Is connected to the surface of the mold package 7 (the surface of the sealing resin 3) (see FIGS. 1A and 1B).

ここで、接合材１２は、導電性接合材１１に対して、弾性率が小さい特性を有する。例えば、導電性接合材１１としては、Ａｇ（銀）やＡｕ（金）等の導電性フィラーをエポキシやポリイミド等の樹脂に含有させたものの他、各種はんだを用いることができる。一方、接合材１２としては、電子装置使用中の高温時（１００℃〜１５０℃）にガラス転移温度を越えて弾性率が低下する樹脂（エポキシ、ポリイミド等）を用いると好適である。
特に、電子装置１使用中の高温時（１００℃〜１５０℃）において、接合材１２のみがガラス転移温度を越えるように設定することによって、導電性接合材１１部分は所要の接合強度を保持しつつ、接合材１２部分で熱膨張差による応力を緩和できるため好適である。
また、特に、モールドパッケージ７の封止樹脂３にエポキシを用いる場合に、接合材１２にも同種のエポキシを用いると、接着性が向上するため好適である。
本実施形態では、導電性接合材１１はＡｇ（銀）フィラー含有エポキシ樹脂であり、接合材１２はエポキシ樹脂である。それぞれの材料における常温時（２０℃±１５℃）の弾性率を表１に示す。なお、接合箇所における接合面積は、導電性接合材１１および接合材１２のいずれも直径１［ｍｍ］程度である。 Here, the bonding material 12 has a characteristic that the elastic modulus is smaller than that of the conductive bonding material 11. For example, as the conductive bonding material 11, various solders can be used in addition to those in which a conductive filler such as Ag (silver) or Au (gold) is contained in a resin such as epoxy or polyimide. On the other hand, as the bonding material 12, it is preferable to use a resin (epoxy, polyimide, or the like) whose elastic modulus is lowered by exceeding the glass transition temperature at a high temperature (100 ° C. to 150 ° C.) during use of the electronic device.
In particular, when the electronic device 1 is in use at a high temperature (100 ° C. to 150 ° C.), by setting only the bonding material 12 to exceed the glass transition temperature, the conductive bonding material 11 portion maintains the required bonding strength. However, it is preferable because the stress due to the difference in thermal expansion can be relieved in the bonding material 12 portion.
In particular, when epoxy is used for the sealing resin 3 of the mold package 7, it is preferable to use the same kind of epoxy for the bonding material 12 because the adhesiveness is improved.
In the present embodiment, the conductive bonding material 11 is an Ag (silver) filler-containing epoxy resin, and the bonding material 12 is an epoxy resin. Table 1 shows the elastic modulus of each material at normal temperature (20 ° C. ± 15 ° C.). In addition, as for the joining area in a joining location, both the electroconductive joining material 11 and the joining material 12 are about diameter 1 [mm].

Figure 0005481701
Figure 0005481701

一方、本実施形態におけるシールド材６は、導電性を有する金属板材を用いて平板状に形成される。導電性を有する金属板材の材料としては、例えば、ステンレス合金、あるいは洋白（Ｃｕ−Ｎｉ−Ｚｎ合金）等を用いることができる。一例として、シールド材６の板厚は、５０［μｍ］〜１００［μｍ］程度である。また、シールド材６とモールドパッケージ７との隙間は５０［μｍ］〜８０［μｍ］程度である。
なお、シールド材６は、導電性を有する金属層を用いて薄膜状に形成する構造も考えられる。当該金属層の例としては、膜厚１０［μｍ］〜３０［μｍ］程度の銅箔、Ｃｕめっき層等が挙げられる。 On the other hand, the shield material 6 in the present embodiment is formed in a flat plate shape using a conductive metal plate material. As a material of the conductive metal plate material, for example, a stainless alloy or a white (Cu—Ni—Zn alloy) can be used. As an example, the plate thickness of the shield material 6 is about 50 [μm] to 100 [μm]. The gap between the shield material 6 and the mold package 7 is about 50 [μm] to 80 [μm].
The shield material 6 may be formed in a thin film shape using a conductive metal layer. Examples of the metal layer include a copper foil having a thickness of about 10 [μm] to 30 [μm], a Cu plating layer, and the like.

また、変形例として、図３に示すように、シールド材６を、基板２の側面位置まで覆うことが可能な箱状（一面側が開口する箱状）に形成してもよい。このような形状のシールド材６を設けることにより、図１（ｂ）に示すような平板状のシールド材６を適用した場合と比べて、より一層、高いシールド効果を得ることができる。   As a modification, as shown in FIG. 3, the shield material 6 may be formed in a box shape (a box shape in which one surface side is open) that can cover the side surface of the substrate 2. By providing the shield material 6 having such a shape, a higher shielding effect can be obtained as compared with the case where the flat shield material 6 as shown in FIG. 1B is applied.

ここで、比較例として、発明者が検討した電子装置２００を図１１に示す。図１１（ａ）は、電子装置２００の平面図（シールド材２０６については不図示）であり、図１１（ｂ）は、電子装置２００の断面図（図１１（ａ）のＨ−Ｈ線断面図）である。
一般的に、電子装置は、使用時に１００℃から１５０℃程度の高温に達する。このような高温環境下では、電子装置を構成する各材料間の熱膨張差（熱膨張係数差）による応力が発生する。そのため、例えば図１１に示すような、平面視矩形状の基板２０２の各コーナー部Ｃ１、Ｃ２、Ｃ３、Ｃ４に設けた電極ポスト２０５とシールド材２０６とを接合した電子装置２００においては、電極ポスト２０５とシールド材２０６との接合部で大きな応力が発生して、破断が生じ得る。
特に、最も距離が長くなる接合箇所間（例えば、電極ポスト２０５ａと電極ポスト２０５ｂとの間等）に、シールド材２０６とモールドパッケージ２０７との熱膨張差が大きく作用する。その結果、熱衝撃を受けた際に、導電性接合材２１１を用いて接合されているシールド材２０６とモールドパッケージ２０７（ここでは電極ポスト２０５ａ、２０５ｂ）との接合部に断線が発生し得る。
しかしながら、その一方で、電子装置２００に例示される一般的な電子装置では、基板の中央部に高密度に配線が引き回され、且つ各種電子部品が搭載されるため、必然的に電極ポストはコーナー部等の基板周縁部に設けざるを得ないという制約がある。 Here, as a comparative example, an electronic device 200 studied by the inventor is shown in FIG. 11A is a plan view of the electronic device 200 (the shield material 206 is not shown), and FIG. 11B is a cross-sectional view of the electronic device 200 (a cross section taken along the line HH in FIG. 11A). Figure).
Generally, an electronic device reaches a high temperature of about 100 ° C. to 150 ° C. during use. Under such a high temperature environment, a stress is generated due to a difference in thermal expansion (difference in thermal expansion coefficient) between materials constituting the electronic device. Therefore, for example, in the electronic device 200 in which the electrode post 205 and the shield material 206 provided at each corner C1, C2, C3, and C4 of the substrate 202 having a rectangular shape in plan view as shown in FIG. A large stress is generated at the joint between 205 and the shield material 206, and breakage may occur.
In particular, the difference in thermal expansion between the shield material 206 and the mold package 207 acts greatly between the joints where the distance is the longest (for example, between the electrode post 205a and the electrode post 205b). As a result, when subjected to thermal shock, disconnection may occur at the joint between the shield material 206 and the mold package 207 (here, the electrode posts 205a and 205b) that are joined using the conductive joining material 211.
However, on the other hand, in a general electronic device exemplified by the electronic device 200, wiring is routed at a high density in the center of the substrate and various electronic components are mounted. There is a restriction that it must be provided at the peripheral edge of the substrate such as a corner.

これに対して、上記の構成を備える電子装置１によれば、接合材１２は、電子装置１の使用中における高温時（１００℃〜１５０℃）にガラス転移温度を越えて、常温時（２０℃±１５℃）よりもさらに弾性率が低下し、電子装置１を構成する各材料間の熱膨張差（熱膨張係数差）による応力を緩衝することが可能となる。
すなわち、電極ポスト５を基板の周縁部の一箇所（第一の実施形態ではコーナー部Ｃ１）に設けると共に、導電性接合材１１を用いて電極ポスト５の上端面とシールド材６とを接合し、且つ当該導電性接合材１１に対して弾性率が小さい特性を有する接合材１２を用いてモールドパッケージ７の表面とシールド材６とを接合する構成によって、シールド材６とモールドパッケージ７との熱膨張差が大きく作用しても、熱衝撃の影響を接合材１２による接合部で緩和して、導電性接合材１１による接合部の断線を抑制する効果が奏される。 On the other hand, according to the electronic device 1 having the above-described configuration, the bonding material 12 exceeds the glass transition temperature at a high temperature (100 ° C. to 150 ° C.) during use of the electronic device 1 and at a normal temperature (20 The elastic modulus is further lowered than that of (° C. ± 15 ° C.), and the stress due to the difference in thermal expansion (difference in thermal expansion coefficient) between the materials constituting the electronic device 1 can be buffered.
That is, the electrode post 5 is provided at one place on the peripheral edge of the substrate (the corner portion C1 in the first embodiment), and the upper end surface of the electrode post 5 and the shield material 6 are bonded using the conductive bonding material 11. Further, the heat of the shield material 6 and the mold package 7 is obtained by joining the surface of the mold package 7 and the shield material 6 by using the bonding material 12 having a characteristic having a small elastic modulus with respect to the conductive bonding material 11. Even if the expansion difference acts greatly, the effect of thermal shock is mitigated at the joint portion by the joining material 12, and the effect of suppressing disconnection of the joint portion by the conductive joining material 11 is exhibited.

続いて、本発明の第二の実施形態に係る電子装置１の概略図を図４に示す。ここで、図４（ａ）は、電子装置１の平面図（シールド材６については不図示）であり、図４（ｂ）は、電子装置１の断面図（図４（ａ）のＦ−Ｆ線断面図）であり、図４（ｃ）は、電子装置１の断面図（図４（ａ）のＧ−Ｇ線断面図）である。
本実施形態に係る電子装置１の概略構成は、前記第一の実施形態と同様であるため、以下、構造上の相違点を中心に説明を行う。 Then, the schematic of the electronic device 1 which concerns on 2nd embodiment of this invention is shown in FIG. 4A is a plan view of the electronic device 1 (the shield material 6 is not shown), and FIG. 4B is a cross-sectional view of the electronic device 1 (F- in FIG. 4A). FIG. 4C is a cross-sectional view of the electronic device 1 (a cross-sectional view taken along the line GG in FIG. 4A).
Since the schematic configuration of the electronic device 1 according to the present embodiment is the same as that of the first embodiment, the following description will focus on the structural differences.

本実施形態に特徴的な構成として、電極ポスト５は、図４（ａ）に示すように、基板のコーナー部以外の周縁部の一箇所に設けられる。一例として、コーナー部Ｃ１とコーナー部Ｃ２との中間部であるＤ部に電極ポスト５が立設される（図４（ａ）、図４（ｃ）参照）。   As a configuration characteristic of the present embodiment, the electrode post 5 is provided at one location of the peripheral edge other than the corner of the substrate, as shown in FIG. As an example, the electrode post 5 is erected in a D portion which is an intermediate portion between the corner portion C1 and the corner portion C2 (see FIGS. 4A and 4C).

また、本実施形態では、シールド材６は、モールドパッケージ７の表面に露出している電極ポスト５の上端面の上に配設される導電性接合材１１と、モールドパッケージ７の表面上で且つ電極ポスト５の上端面が露出する位置（ここでは周縁部のＤ部）とは異なる位置のコーナー部（ここではコーナー部Ｃ１、Ｃ２、Ｃ３、Ｃ４）に配設される接合材１２とによって、モールドパッケージ７の表面に接続されている（図４（ａ）〜図４（ｃ）参照）。   In the present embodiment, the shield material 6 includes the conductive bonding material 11 disposed on the upper end surface of the electrode post 5 exposed on the surface of the mold package 7, the surface of the mold package 7 and By the bonding material 12 disposed at a corner portion (here, the corner portions C1, C2, C3, C4) different from the position where the upper end surface of the electrode post 5 is exposed (here, the D portion of the peripheral portion). It is connected to the surface of the mold package 7 (see FIGS. 4A to 4C).

上記の構成を備える本実施形態に係る電子装置１によれば、前述の第一の実施形態に係る電子装置１と同様の効果を得ることができる。   According to the electronic device 1 according to the present embodiment having the above-described configuration, the same effects as those of the electronic device 1 according to the first embodiment described above can be obtained.

続いて、本発明の実施形態に係る電子装置１の製造方法について説明する。なお、第一の実施形態（図１（ａ）、図１（ｂ）参照）の場合を例に挙げて説明するが、第二の実施形態の場合も同様である。
ここで、図５〜図８は、電子装置１の製造工程を説明するための概略図であって、図１（ｂ）と同様に基板２を対角線で切断した断面図として図示している。 Then, the manufacturing method of the electronic device 1 which concerns on embodiment of this invention is demonstrated. The case of the first embodiment (see FIGS. 1A and 1B) will be described as an example, but the same applies to the case of the second embodiment.
Here, FIG. 5 to FIG. 8 are schematic views for explaining the manufacturing process of the electronic device 1 and are shown as cross-sectional views in which the substrate 2 is cut along a diagonal line in the same manner as FIG.

先ず、図５に示すように、公知の製造方法によって、グラウンド電位となる貫通ビア２１、２２、２３、および接続パッド２４、２５、配線パターン２６を有する基板（本実施形態では、下層基板２ａと上層基板２ｂとからなる多層基板）２を形成する。なお、図の簡略化のため、信号等のラインとなる配線、貫通ビア、接続パッド等は不図示としている（図６〜図８において同様）。
次いで、上層基板２ｂ上の電子部品実装領域に電子部品４を実装する（例えば、フリップチップ実装方法を用いる）。その後、電極ポスト５を上層基板２ｂの接続パッド２４上に導電性接合材（ここでは、はんだ）２７を用いて接合する。これにより、電極ポスト５は、接続パッド２４および導電性接合材２７を介して貫通ビア２３と電気的に接続される。
ここで、本実施形態に特徴的な構成として、電極ポスト５は、基板２の一つのコーナー部にのみ立設する（図１（ａ）参照）。 First, as shown in FIG. 5, a substrate having through vias 21, 22, 23, connection pads 24, 25, and a wiring pattern 26 that become a ground potential by a known manufacturing method (in this embodiment, the lower substrate 2 a and A multi-layer substrate 2) composed of the upper substrate 2b is formed. For simplification of the drawing, wirings, through vias, connection pads, etc. that are lines for signals and the like are not shown (the same applies to FIGS. 6 to 8).
Next, the electronic component 4 is mounted on the electronic component mounting region on the upper substrate 2b (for example, using a flip chip mounting method). Thereafter, the electrode post 5 is bonded onto the connection pad 24 of the upper substrate 2b using a conductive bonding material (here, solder) 27. As a result, the electrode post 5 is electrically connected to the through via 23 via the connection pad 24 and the conductive bonding material 27.
Here, as a characteristic configuration of this embodiment, the electrode post 5 is erected only at one corner of the substrate 2 (see FIG. 1A).

なお、一例として、基板２は矩形状であって一辺の長さが６［ｍｍ］程度、厚さが０．３［ｍｍ］程度である。また、電極ポスト５は四角柱状であって基板２の実装面に平行な方向の一辺の長さが０．５［ｍｍ］程度、高さ（基板２の実装面に垂直な方向の一辺の長さ）が０．６［ｍｍ］程度である。   As an example, the substrate 2 has a rectangular shape with a side length of about 6 [mm] and a thickness of about 0.3 [mm]. The electrode post 5 has a quadrangular prism shape, and the length of one side in the direction parallel to the mounting surface of the substrate 2 is about 0.5 mm, and the height (the length of one side in the direction perpendicular to the mounting surface of the substrate 2). Is about 0.6 [mm].

次いで、図６に示すように、電子部品４等を保護するために、封止樹脂３を用いて基板２の実装面側のモールドを行う（モールドパッケージ７が形成される）。このとき、封止樹脂３の厚さは、電子部品４および電極ポスト５を覆うことのできる厚さとする。封止樹脂３の材料は特に限定されないが、配線間の短絡を防止するために、絶縁性を有するエポキシ等の樹脂であることが必要となる。   Next, as shown in FIG. 6, in order to protect the electronic component 4 and the like, the mounting surface side of the substrate 2 is molded using the sealing resin 3 (a mold package 7 is formed). At this time, the thickness of the sealing resin 3 is set to a thickness that can cover the electronic component 4 and the electrode post 5. The material of the sealing resin 3 is not particularly limited, but it is necessary to be an insulating resin such as epoxy in order to prevent a short circuit between the wirings.

次いで、図７に示すように、電極ポスト５の上端面の上方位置の封止樹脂３を除去して、モールドパッケージ７から電極ポスト５を露出させる。本実施形態においては、電極ポスト５の上端面の上方位置における封止樹脂３のみを、レーザ加工やサンドブラスト等の方法を用いて除去する。これにより、電子部品４を覆う封止樹脂３を必要最小限の厚さに形成しつつ、電極ポスト５の形成高さを低く抑えることができるため、電子装置１全体の厚さを薄くできるという効果が得られる。
なお、封止樹脂３の除去面積は、電極ポスト５の上端面の面積と同一の大きさに限定されるものではない。また、モールドパッケージ７の表面全域に渡ってグラインダーで研磨し、上層部分の封止樹脂３を除去して、電極ポスト５の上端面を露出させる方法を採用してもよい。 Next, as shown in FIG. 7, the sealing resin 3 above the upper end surface of the electrode post 5 is removed, and the electrode post 5 is exposed from the mold package 7. In the present embodiment, only the sealing resin 3 above the upper end surface of the electrode post 5 is removed using a method such as laser processing or sand blasting. Thereby, the formation height of the electrode post 5 can be kept low while the sealing resin 3 covering the electronic component 4 is formed to the minimum necessary thickness, so that the thickness of the entire electronic device 1 can be reduced. An effect is obtained.
The removal area of the sealing resin 3 is not limited to the same size as the area of the upper end surface of the electrode post 5. Alternatively, a method may be employed in which the upper surface of the electrode post 5 is exposed by polishing with a grinder over the entire surface of the mold package 7 to remove the sealing resin 3 in the upper layer portion.

次いで、図８に示すように、シールド材６を導電性接合材１１および接合材１２を用いてモールドパッケージ７の表面に接合する。ここで、本実施形態に特徴的な構成として、モールドパッケージ７の表面に露出している電極ポスト５の上端面の上に導電性接合材１１を配設する。また、モールドパッケージ７の表面上で且つ電極ポスト５の上端面が露出する位置とは異なる位置のコーナー部の封止樹脂３表面に接合材１２を配設する（図１（ａ）、図１（ｂ）参照）。
このようにして、電子装置１が製造される。 Next, as shown in FIG. 8, the shield material 6 is bonded to the surface of the mold package 7 using the conductive bonding material 11 and the bonding material 12. Here, as a characteristic configuration of the present embodiment, the conductive bonding material 11 is disposed on the upper end surface of the electrode post 5 exposed on the surface of the mold package 7. Further, the bonding material 12 is disposed on the surface of the sealing resin 3 at the corner portion at a position different from the position at which the upper end surface of the electrode post 5 is exposed on the surface of the mold package 7 (FIGS. 1A and 1). (See (b)).
In this way, the electronic device 1 is manufactured.

以上、説明した通り、開示の電子装置およびその製造方法によれば、導電性接合材を用いて接合されたシールド材と基板の電極端子との接合部が、熱衝撃（温度上昇および温度降下の繰り返し）を受けた際に、断線してしまうことを防止することができる。   As described above, according to the disclosed electronic device and the manufacturing method thereof, the bonded portion between the shield material bonded using the conductive bonding material and the electrode terminal of the substrate is subjected to thermal shock (temperature increase and temperature decrease). It is possible to prevent disconnection when receiving (repeat).

なお、本発明は、以上説明した実施例に限定されることなく、本発明を逸脱しない範囲において種々変更可能であることは言うまでもない。特に、矩形状の基板の中央部に電子部品が実装される電子装置を例に挙げて説明したが、これに限定されるものではなく、矩形状以外の形状を有する基板にも同様に適用することが可能であり、また、基板の中央部から周縁部に及ぶ位置に複数の電子部品を搭載する場合であっても同様に適用することが可能である。   Needless to say, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the present invention. In particular, an electronic device in which an electronic component is mounted on the center of a rectangular substrate has been described as an example. However, the present invention is not limited to this, and the same applies to a substrate having a shape other than a rectangular shape. In addition, even when a plurality of electronic components are mounted at positions extending from the central part to the peripheral part of the substrate, the present invention can be similarly applied.

１、２００ 電子装置
２、２０２ 基板
３、２０３ 封止樹脂
４、２０４ 電子部品
５、２０５、２０５ａ、２０５ｂ 電極ポスト
６、２０６ シールド材
７、２０７ モールドパッケージ
１１、２７、２９、２１１、２２７、２２９ 導電性接合材
１２ 接合材
２１、２２、２３、２２１、２２２、２２３ 貫通ビア
２４、２５、２２４、２２５ 接続パッド
２６、２２６ 配線パターン
２８、２２８ バンプ 1, 200 Electronic device 2, 202 Substrate 3, 203 Sealing resin 4, 204 Electronic component 5, 205, 205a, 205b Electrode post 6, 206 Shield material 7, 207 Mold package 11, 27, 29, 211, 227, 229 Conductive bonding material 12 Bonding material 21, 22, 23, 221, 222, 223 Through-via 24, 25, 224, 225 Connection pad 26, 226 Wiring pattern 28, 228 Bump

Claims (10)

矩形状の基板と、
前記基板上に実装された電子部品と、
前記基板上の周縁部に立設された電極ポストと、
前記電子部品および前記電極ポストを被覆して前記基板上に設けられた封止樹脂と、からなり、
前記電極ポストの端面が、前記封止樹脂表面に露出した構造体を有し、
前記電極ポストの端面上に配設される導電性接合材と、前記封止樹脂の表面上で且つ該電極ポストの端面露出位置と異なる位置に配設される接合材とによって、前記封止樹脂の表面にシールド材が接合されており、
前記接合材は、前記導電性接合材に対して、弾性率が小さく、
前記電極ポストは、前記基板の周縁部の一箇所に設けられており、
前記接合材は、前記基板の異なる三つのコーナー部に配設されていること
を特徴とする電子装置。 A rectangular substrate;
Electronic components mounted on the substrate;
An electrode post erected on the peripheral edge of the substrate;
A sealing resin that covers the electronic component and the electrode post and is provided on the substrate;
The end face of the electrode post has a structure exposed on the sealing resin surface,
The sealing resin includes a conductive bonding material disposed on the end surface of the electrode post and a bonding material disposed on the surface of the sealing resin at a position different from the exposed position of the end surface of the electrode post. and the shielding member is bonded to the surface of,
The bonding material has a smaller elastic modulus than the conductive bonding material,
The electrode post is provided at one location on the peripheral edge of the substrate,
The electronic device according to claim 1, wherein the bonding material is disposed at three different corner portions of the substrate . 前記電極ポストは、前記基板の一つのコーナー部に立設されていること
を特徴とする請求項１記載の電子装置。 The electrode posts, electronic apparatus according to claim 1, characterized in that it is erected on one corner portion of the substrate. 前記封止樹脂は、表面の前記電極ポストが露出する部分が窪んだ形状を有すること
を特徴とする請求項１または請求項２記載の電子装置。 The sealing resin, the electronic device according to claim 1 or claim 2, wherein the having the electrode post recessed portions exposed shape of the surface. 前記シールド材は、前記基板の側面位置まで覆う形状を有すること
を特徴とする請求項１〜３のいずれか一項記載の電子装置。 The shielding material, an electronic apparatus according to any one of claims 1-3, characterized in that it has a shape covering to a side surface position of the substrate. 前記電極ポストは、複数の電極ポストが近接させて設けられていること
を特徴とする請求項１〜４のいずれか一項記載の電子装置。 The electrode posts, electronic apparatus according to any one of claims 1-4, wherein a plurality of electrode posts are provided in proximity. 矩形状の基板に電子部品を実装する工程と、
前記基板の周縁部に電極ポストを立設する工程と、
前記電子部品および前記電極ポストを、封止樹脂を用いてモールドして、モールドパッケージを形成する工程と、
前記モールドパッケージの上層部分の封止樹脂を除去して、前記電極ポストの端面を露出させる工程と、
前記電極ポストの端面上に導電性接合材を配設する工程と、
前記封止樹脂の表面上であって、且つ前記電極ポストの端面が露出する位置とは異なる位置に接合材を配設する工程と、
前記導電性接合材と前記接合材とによって、前記封止樹脂の表面にシールド材を接合する工程と、を備え、
前記接合材は、前記導電性接合材に対して、弾性率が小さく、
前記基板の周縁部に電極ポストを立設する工程は、
前記基板の周縁部の一箇所に電極ポストを立設する工程であり、
前記接合材を配設する工程は、
前記基板の異なる三つのコーナー部に接合材を配設する工程であること
を特徴とする電子装置の製造方法。 Mounting electronic components on a rectangular substrate;
Erecting electrode posts on the peripheral edge of the substrate;
Molding the electronic component and the electrode post using a sealing resin to form a mold package;
Removing the sealing resin of the upper layer portion of the mold package to expose the end face of the electrode post; and
Disposing a conductive bonding material on an end face of the electrode post;
Disposing a bonding material on the surface of the sealing resin and at a position different from the position where the end face of the electrode post is exposed;
A step of bonding a shield material to the surface of the sealing resin by the conductive bonding material and the bonding material ,
The bonding material has a smaller elastic modulus than the conductive bonding material,
The step of standing the electrode posts on the peripheral edge of the substrate is
It is a step of standing an electrode post at one location of the peripheral edge of the substrate,
The step of disposing the bonding material includes:
A method for manufacturing an electronic device, comprising a step of disposing a bonding material at three different corner portions of the substrate . 前記モールドパッケージの上層部分の封止樹脂を除去して、前記電極ポストの端面を露出させる工程は、
前記電極ポストの立設位置の上方位置における封止樹脂のみを除去して、前記電極ポストが露出する部分を窪んだ形状にする工程であること
を特徴とする請求項６記載の電子装置の製造方法。 The step of removing the sealing resin in the upper layer portion of the mold package and exposing the end face of the electrode post is as follows:
The manufacturing method of an electronic device according to claim 6 , wherein only the sealing resin at a position above the standing position of the electrode post is removed to form a recessed portion where the electrode post is exposed. Method. 前記基板の周縁部に電極ポストを立設する工程は、
前記基板の一つのコーナー部に電極ポストを立設する工程であること
を特徴とする請求項６または請求項７記載の電子装置の製造方法。 The step of standing the electrode posts on the peripheral edge of the substrate is
8. The method of manufacturing an electronic device according to claim 6, wherein the electrode post is erected at one corner portion of the substrate. 前記シールド材は、前記基板の側面位置まで覆う形状を有すること
を特徴とする請求項６〜８のいずれか一項記載の電子装置の製造方法。 The method for manufacturing an electronic device according to claim 6 , wherein the shield material has a shape that covers the side surface of the substrate. 前記基板の周縁部に電極ポストを立設する工程は、
複数の電極ポストを近接させて立設する工程であること
を特徴とする請求項６〜９のいずれか一項記載の電子装置の製造方法。 The step of standing the electrode posts on the peripheral edge of the substrate is
The method for manufacturing an electronic device according to claim 6 , wherein the method is a step of standing a plurality of electrode posts close to each other.
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