JP5474143B2 - Semiconductor device and inverter, converter and power conversion device using the same - Google Patents

Description

  The present invention relates to a semiconductor device, a step-up chopper and a power conversion device using the semiconductor device, and more particularly to a semiconductor device including a high breakdown voltage transistor, an inverter, a converter and a power conversion device using the semiconductor device.

  Conventionally, high voltage transistors have been used in power conversion devices. There is also a method of using a plurality of high voltage transistors connected in parallel in order to increase the rated current of the power converter. In this method, in order to prevent the current from concentrating on a high breakdown voltage transistor having a low threshold voltage among a plurality of high breakdown voltage transistors, the current of each high breakdown voltage transistor is detected and the current of the plurality of high breakdown voltage transistors is When the difference between them becomes larger than a predetermined value, the gate resistance is made smaller than usual to speed up the turn-on of a plurality of high voltage transistors (for example, see Patent Document 1).

JP 2002-95240 A

  However, the conventional power conversion device has a problem that the turn-on time varies due to the variation in threshold voltage of the high voltage transistor, and the performance of the power conversion device varies.

  Further, in the method of Patent Document 1, the same number of current sensors as high withstand voltage transistors are provided, each gate resistance is configured by a variable resistance element, and a control unit that controls the gate resistance based on the detection result of the current sensor is required. There is a problem that the device configuration becomes complicated and the cost is high.

  Therefore, a main object of the present invention is to provide a semiconductor device having a small variation in turn-on time, and an inverter, a converter and a power conversion device using the semiconductor device.

  In the semiconductor device according to the present invention, a first transistor having a first electrode connected to a first node, a first electrode connected to a second electrode of the first transistor, and a second electrode A second transistor having a control electrode connected to the first control node, a first electrode connected to the second electrode of the first transistor, and a second electrode connected to the second node; And a third transistor having a control electrode connected to the second control node. The breakdown voltage between the first and second electrodes of the first transistor is higher than the breakdown voltage between the first and second electrodes of each of the second and third transistors, and the amplification factor of the second transistor is third. It is smaller than the amplification factor of the transistor.

  Preferably, a plurality of first to third transistors are provided. The control electrodes of the plurality of first transistors are connected to each other, the control electrodes of the plurality of second transistors are all connected to the first control node, and the control electrodes of the plurality of third transistors are both connected to the second control node. It is connected to the. The first electrodes of the plurality of first transistors are all connected to the first node, and the first electrodes of the plurality of second transistors are connected to the second electrodes of the plurality of first transistors, respectively. The second electrodes of the second transistors are both connected to the second node, and the first electrodes of the plurality of third transistors are connected to the second electrodes of the plurality of first transistors, respectively. The second electrodes of the third transistors are both connected to the second node.

  Preferably, the amplification factor of the second transistor is smaller than the amplification factor of the first transistor.

  Preferably, when conducting between the first and second nodes, the second transistor is turned on to turn on the first transistor, and then the third transistor is turned on.

  Preferably, when the first and second nodes are not connected, the third transistor is turned off and then the second transistor is turned off to turn off the first transistor.

  Preferably, the first node receives the first voltage, the second node receives the second voltage, and the first control signal for controlling on / off of the second transistor is the first control. A second control signal is applied to the second control node for turning on / off the third transistor.

  Also preferably, the first node receives the first voltage, the second node receives the second voltage, and the threshold voltage of the second transistor is lower than the threshold voltage of the third transistor. A control signal for ON / OFF control of the second and third transistors is applied to the first and second control nodes.

  Preferably, each of the second and third transistors is a normally-off transistor.

  Preferably, the first transistor is a normally-off transistor, and the control electrode of the first transistor receives a third voltage higher than the threshold voltage of the first transistor.

  Also preferably, a capacitor connected between the control electrode of the first transistor and the second node, a diode having a cathode connected to the control electrode of the first transistor and an anode receiving the third voltage With.

  Preferably, the first transistor is a normally-on transistor, and the control electrode of the first transistor is connected to the second node.

A converter according to the present invention includes the semiconductor device.
An inverter according to the present invention includes the semiconductor device.

  A power conversion circuit according to the present invention includes the semiconductor device.

  In the semiconductor device according to the present invention, the first electrode is connected between the first transistor connected to the first node, the second electrode of the first transistor, and the second node, and the control electrode Is connected between the second transistor connected to the first control node, the second electrode of the first transistor and the second node, and the control electrode is connected to the second control node. 3 and a breakdown voltage between the first and second electrodes of the first transistor is higher than a breakdown voltage between the first and second electrodes of each of the second and third transistors. The amplification factors of the first and third transistors are smaller than the amplification factors of the first and third transistors. Therefore, by switching the first transistor having a high withstand voltage by the second transistor having a small amplification factor, variations in the threshold voltage of the first transistor cause the first and second electrode currents of the first transistor to vary. It is possible to reduce the influence on the variation of the. For this reason, even when a plurality of semiconductor devices are connected in parallel, current can be prevented from being concentrated on one semiconductor device without providing a current sensor or the like, thereby simplifying the device configuration and reducing the cost. Can be planned.

1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the pressure | voltage rise chopper using the semiconductor device shown in FIG. It is a time chart which shows the waveform of the control signal shown in FIG. FIG. 3 is a circuit diagram showing a comparative example of the first embodiment. It is a time chart for demonstrating the effect of this invention. FIG. 6 is a circuit block diagram illustrating a modification of the first embodiment. FIG. 10 is a circuit block diagram illustrating another modification of the first embodiment. FIG. 12 is a circuit diagram showing still another modification of the first embodiment. It is a circuit diagram which shows the structure of the semiconductor device by Embodiment 2 of this invention. FIG. 10 is a circuit diagram showing a configuration of a boost chopper using the semiconductor device shown in FIG. 9. It is a circuit diagram which shows the structure of the semiconductor device by Embodiment 3 of this invention. FIG. 12 is a circuit diagram showing a configuration of a step-up chopper using the semiconductor device shown in FIG. 11. 13 is a time chart showing waveforms of currents flowing through two high voltage transistors shown in FIG. FIG. 10 is a circuit diagram showing a comparative example of the third embodiment. It is a time chart which shows the waveform of the electric current which flows into two high voltage transistors shown in FIG. It is a circuit diagram which shows the structure of the semiconductor device by Embodiment 4 of this invention. FIG. 17 is a circuit diagram showing a configuration of a boost chopper using the semiconductor device shown in FIG. 16. It is a circuit block diagram which shows the structure of the pressure | voltage fall chopper by Embodiment 5 of this invention. FIG. 10 is a circuit block diagram showing a modification of the fifth embodiment.

[Embodiment 1]
The semiconductor device according to the first embodiment includes a first transistor whose drain is connected to the first node, a second transistor whose drain is connected to the source of the first transistor, and whose source is connected to the second node. And a third transistor connected in parallel to the second transistor, the breakdown voltage between the source and drain of the first transistor is greater than the breakdown voltage between the source and drain of each of the second and third transistors. The transconductance of the second transistor is smaller than the transconductance of the third transistor. Hereinafter, the semiconductor device according to the first embodiment will be described in detail with reference to the drawings.

  As shown in FIG. 1, the semiconductor device according to the first embodiment includes N channel MOS transistors Q1, Q2 connected in series between nodes N1, N2, and an N channel MOS transistor connected in parallel to N channel MOS transistor Q2. Q3.

  The transistor Q1 is a high breakdown voltage transistor, and each of the transistors Q2 and Q3 is a low breakdown voltage transistor. The threshold voltage VTH1 of the commercially available transistor Q1 varies in the range of 3V to 5V. In addition, the threshold voltages VTH2 and VTH3 of the commercially available transistors Q2 and Q3 vary in the range of 1V to 2V. The mutual conductance Gm2 of the transistor Q2 is smaller than each of the mutual conductances Gm1 and Gm3 of the transistors Q1 and Q3. For example, Gm2 = 6S (Siemens), Gm1 = 35S, and Gm3 = 30S.

  DC voltage V1 is applied to node N1, DC voltage V2 lower than DC voltage V1 is applied to node N2, and DC voltage V3 is applied to the gate of transistor Q1. V3-V2 is set to a voltage sufficiently higher than the threshold voltage VTH1 of the transistor Q1. Control signals CNT1 and CNT2 are applied to the gates of the transistors Q2 and Q3, respectively.

  In the initial state, it is assumed that both the control signals CNT1 and CNT2 are set to the “L” level. In this case, the transistors Q1 to Q3 are all turned off, and the nodes N1 and N2 are in a non-conductive state.

  In order to make the nodes N1 and N2 conductive, first, the control signal CNT1 is raised from the “L” level to the “H” level. As a result, the transistor Q2 is turned on and the source voltage of the transistor Q1 is lowered. When the gate-source voltage of the transistor Q1 exceeds the threshold voltage VTH1 of the transistor Q1, the transistor Q1 is turned on, and between the nodes N1 and N2 Becomes conductive. Next, the control signal CNT2 is raised from the “L” level to the “H” level. Thereby, the transistor Q3 is turned on, the resistance value between the nodes N1 and N2 is reduced, and the conduction loss is reduced.

  When the node N1, N2 is changed from the conductive state to the non-conductive state, the control signal CNT2 is first lowered from the “H” level to the “L” level, and the transistor Q3 is turned off. Next, the control signal CNT2 falls from the “H” level to the “L” level. As a result, the transistor Q2 is turned off and the source voltage of the transistor Q1 rises. When the gate-source voltage of the transistor Q1 becomes smaller than the threshold voltage VTH1 of the transistor Q1, the transistor Q1 is turned off.

  In the first embodiment, by switching the transistor Q1 having a high withstand voltage by the transistor Q2 having a small mutual conductance Gm2, the influence of the variation in the threshold voltage VTH1 of the transistor Q1 on the variation in the drain current of the transistor Q1 is reduced. Thus, variation in turn-on time can be suppressed to be small.

  FIG. 2 is a circuit diagram showing a configuration of a step-up chopper using the semiconductor device shown in FIG. In FIG. 2, a boost chopper is a circuit that boosts the output voltage of the DC power supply 1 and applies the boosted voltage to the load circuit 6, and includes N-channel MOS transistors Q1 to Q3, control signal sources S1 and S2, gate resistors R1 to R3, DC A power source 2, a diode 4, and a capacitor 5 are provided.

  N channel MOS transistors Q1 and Q2 are connected in series between nodes N1 and N2, and N channel MOS transistor Q3 is connected in parallel to N channel MOS transistor Q2. Node N2 is connected to a line of ground voltage GND. Reactor 3 is connected between the positive electrode of DC power supply 1 and node N1. The anode of the diode 4 is connected to the node N1, and the cathode thereof is connected to the ground voltage GND line via the capacitor 5. The load circuit 6 is connected to the capacitor 5 in parallel.

  Gate resistor R1 is connected between the positive electrode of DC power supply 2 and the gate of transistor Q1. The gate resistor R2 is connected between the output node of the control signal source S1 and the gate of the transistor Q2. The gate resistor R3 is connected between the output node of the control signal source S2 and the gate of the transistor Q3. The negative poles of the DC power supplies 1 and 2 are grounded, and the ground nodes of the signal sources S1 and S2 are grounded.

  The reactance of the reactor 3 is, for example, 5 mH. As the diode 4, a SiC Schottky barrier diode was used. The capacitance value of the capacitor 5 is, for example, 200 μF. As the load circuit 6, a resistance element having a resistance value of 7.8Ω was used. The control signal sources S1 and S2 output control signals CNT1 and CNT2, respectively. Each of the control signals CNT1 and CNT2 is a 10 KHz rectangular wave signal.

  When turning on the transistors Q1 to Q3, as shown in FIG. 3, after raising the control signal CNT1 from the “L” level to the “H” level, the control signal CNT2 is changed from the “L” level to the “H” level. Launch. Conversely, when turning off the transistors Q1 to Q3, the control signal CNT2 is lowered from the “H” level to the “L” level after the control signal CNT2 is lowered from the “H” level to the “L” level.

  Returning to FIG. 2, when the transistors Q <b> 1 to Q <b> 3 are turned on, a DC current flows from the DC power source 1 through the reactor 3 and the transistors Q <b> 1 to Q <b> 3 to the ground voltage GND line, and electromagnetic energy is stored in the reactor 3. When the transistors Q <b> 1 to Q <b> 3 are turned off, electromagnetic energy stored in the reactor 3 is released to the capacitor 5 through the diode 4. The terminal voltage of the capacitor 5, that is, the output voltage of the boost chopper is a voltage obtained by adding the terminal voltage of the reactor 3 to the output voltage of the DC power supply 1.

  FIG. 4 is a circuit diagram showing a configuration of a conventional boost chopper as a comparative example of the first embodiment, which is compared with FIG. Referring to FIG. 4, in this step-up chopper, an N channel MOS transistor Q10 is connected between nodes N1 and N2. The gate of the transistor Q10 is connected to the output node of the control signal source S10 via the gate resistor R10. The control signal source S10 outputs a control signal S10 that is a 10 KHz rectangular wave signal. The ground node of the control signal source S10 is grounded. As the transistor Q10, a transistor having the same high breakdown voltage and high Gm as the transistor Q1 was used.

  When the control signal S10 rises from the “L” level to the “H” level, the transistor Q10 is turned on and electromagnetic energy is stored in the reactor 3. When the control signal S10 falls from the “H” level to the “L” level, the transistor Q10 is turned off, and the electromagnetic energy of the reactor 3 is released to the capacitor 5.

  5 shows the waveform of the current I1 flowing through the transistor Q1 in response to the rising edges of the control signals CNT1 and CNT2 in the boost chopper of the present application shown in FIG. 2, and the control signal CNT10 in the conventional boost chopper shown in FIG. It is a time chart which shows the waveform of the electric current I10 which flows into the transistor Q10 in response to a rising edge.

  Here, the gate voltages of the transistors Q2 and Q10 are raised from the “L” level to the “H” level at the timing of time t = 0 (ns). Further, the resistance values of the gate resistors R1, R2, R3, and R10 are set so that the current change (di / dt) during switching is the same between the boost chopper of the present application and the conventional boost chopper. The current change during switching (di / dt) is a parameter set by the allowable amount of switching noise. When the current change during switching (di / dt) increases, the switching noise also increases. Since the allowable amount of switching noise is the same in the step-up chopper of the present application and the conventional step-up chopper, circuit parameters are set so that the current change (di / dt) during switching is also the same.

  Generally, even in the same product, the threshold voltage VTH of the transistor Q varies within a predetermined range. In the commercially available high voltage transistors Q1 and Q10, the threshold voltage VTH varies in the range of 3V to 5V. In the commercially available low voltage transistors Q2 and Q3, the threshold voltage VTH varies in the range of 1V to 2V. When the control signal CNT is raised from the “L” level to the “H” level, the transistor Q is turned on when the level of the control signal CNT exceeds the threshold voltage VTH of the transistor Q. Therefore, even if the same control signal CNT is applied to the gate of the transistor Q, the transistor Q having a low threshold voltage VTH is turned on faster than the transistor Q having a high threshold voltage VTH.

  In the conventional step-up chopper, the rise of the current I10 when using the high breakdown voltage transistor Q10 with low VTH (VTH10 = 3V) is the rise of the current I10 when using the high breakdown voltage transistor Q10 with high VTH (VTH10 = 5V). 90 ns faster than Therefore, the rise time of the current I10 varies in the range of 90 ns.

  On the other hand, in the step-up chopper of the present application, a low breakdown voltage transistor Q1 having a low VTH (VTH1 = 3V), a low breakdown voltage transistor Q2 having a low VTH (VTH2 = 1V), and a low breakdown voltage transistor having a low VTH (VTH3 = 1.2V). The rise of the current I1 when Q3 is used is the high breakdown voltage transistor Q1 with high VTH (VTH1 = 5V), the low breakdown voltage transistor Q2 with high VTH (VTH2 = 2V), and the low breakdown voltage transistor with high VTH (VTH3 = 2V). It was 22 ns faster than the rise of current I1 when Q3 was used. Therefore, the rise time of the current I1 varies in the range of 22 ns.

  Therefore, by using the semiconductor device of the present invention, it was possible to suppress the variation in the rise time of the current of the boost chopper from 90 ns to 22 ns. This is because the transistor Q1 having a low mutual conductance Gm2 switches the high breakdown voltage transistor Q1, thereby reducing the influence of the variation in the threshold voltage VTH1 of the transistor Q1 on the variation in the drain current of the transistor Q1. Because.

  In general, the drain current Id of the transistor Q is expressed by the formula Id = Gm × (Vg−VTH) × Vd, where Vg is the gate voltage and Vd is the drain voltage. Therefore, in order to flow the current Id having a predetermined value through the transistor Q having a small mutual conductance Gm while keeping the drain voltage Vd constant, the current Id having the predetermined value is flowed through the transistor Q having a large mutual conductance Gm. It is necessary to increase the value of (Vg−VTH). Therefore, in the transistor Q having a small mutual conductance Gm, the gate voltage Vg is larger than the variation in the threshold voltage VTH, and the influence of the variation in the threshold voltage VTH on the drain current Id can be reduced.

  In the step-up chopper of the present application, the current I1 rises about 50 ns after the gate voltage of the low VTH transistor Q2 is raised to the “H” level. On the other hand, in the conventional step-up chopper, the current I10 rises about 140 ns after the gate voltage of the low VTH transistor Q10 is raised to the “H” level. Therefore, the boost chopper equipped with the semiconductor device of the present application has a shorter time from when the gate voltage of the transistor Q2 rises to the “H” level until the current rises, and therefore, operates at a higher frequency than the conventional boost chopper. Can do.

  Hereinafter, various modifications of the first embodiment will be described. FIG. 6 is a circuit block diagram showing a configuration of an inverter that is a modification of the first embodiment. In FIG. 6, this inverter includes switches SW1 and SW2 connected in series between a line of DC power supply voltage VCC and a line of ground voltage GND, an output terminal T1 provided between the switches SW1 and SW2, and a DC power supply. Switches SW3 and SW4 connected in series between the voltage VCC line and the ground voltage GND line, and an output terminal T2 provided between the switches SW3 and SW4. In addition, a diode (not shown) is connected in antiparallel to each switch SW. Each switch SW includes the semiconductor device shown in FIG. A load circuit 10 is connected between the output terminals T1 and T2.

  When the switches SW1 and SW4 are turned on, a current flows from the DC power supply voltage VCC line to the ground voltage GND line via the switch SW1, the load circuit 10, and the switch SW4. When the switches SW3 and SW2 are turned on, a current flows from the DC power supply voltage VCC line to the ground voltage GND line via the switch SW3, the load circuit 10, and the switch SW2. Therefore, the DC power can be converted into AC power and supplied to the load circuit 10 by alternately turning on the switches SW1, SW4 and the switches SW2, SW3 at a desired cycle. In this modified example, the variation in the turn-on time of the switch SW can be suppressed small. In this modified example, the case where the semiconductor device of the first embodiment is applied to a single-phase inverter has been described. However, the semiconductor device of the first embodiment is applied to a multi-phase inverter (for example, a three-phase inverter). It goes without saying that is also applicable.

  FIG. 7 is a circuit block diagram showing a configuration of a converter according to another modification of the first embodiment. In FIG. 7, this converter includes switches SW11 and SW12 connected in series between a node N10 and a ground voltage GND line, an input terminal T11 provided between the switches SW1 and SW2, a node N10 and a ground voltage GND. The switches SW13 and SW14 connected in series with each other line, the input terminal T12 provided between the switches SW13 and SW14, the output terminal T13, and the node N10 and the output terminal T13 connected in the forward direction. A diode 11 and a smoothing capacitor 12 connected between the output terminal T13 and the ground voltage GND line are provided. Each switch SW includes the semiconductor device shown in FIG. An AC power supply 13 is connected between the input terminals T11 and T12. A load circuit 14 is connected between the output terminal T13 and the ground voltage GND line.

  An AC voltage is supplied from the AC power supply 13 between the input terminals T11 and T12. The switches SW11 and SW14 are turned on while the voltage at the input terminal T11 is higher than the voltage at the input terminal T12, and the switches SW12 and SW13 are turned on when the voltage at the input terminal T12 is higher than the voltage at the input terminal T11.

  When the switches SW11 and SW14 are turned on, a current flows from the AC power supply 13 to the smoothing capacitor 12 via the switch SW11 and the diode 11, and the smoothing capacitor 12 is charged. When the switches SW12 and SW13 are turned on, current flows from the AC power supply 13 to the smoothing capacitor 12 via the switch SW13 and the diode 11, and the smoothing capacitor 12 is charged. Therefore, by turning on the switches SW11 and SW14 and the switches SW12 and SW13 in synchronization with the AC voltage, the AC power can be converted into DC power and supplied to the load circuit 14. In this modified example, the variation in the turn-on time of the switch SW can be suppressed small.

  FIG. 8 is a circuit diagram showing still another modification of the first embodiment, and is a diagram to be compared with FIG. In FIG. 8, this semiconductor device is different from the semiconductor device of FIG. 1 in that control signal CNT1 is applied to the gates of N-channel MOS transistors Q2 and Q3, and threshold voltage VTH3 of transistor Q3 is the threshold value of transistor Q2. This is a point higher than the voltage VTH2. Therefore, when the control signal CNT rises from the “L” level to the “H” level, the transistor Q3 is turned on after the transistor Q2 is turned on. When the control signal CNT is raised from the “H” level to the “L” level, the transistor Q2 is turned off and then the transistor Q2 is turned off. In this modified example, the same effect as in the first embodiment can be obtained, and the number of control signals CNT can be reduced.

  Each of N channel MOS transistors Q1-Q3 may be replaced with a bipolar transistor or IGBT. For example, first to third NPN bipolar transistors may be used in place of N channel MOS transistors Q1 to Q3, respectively. In this case, the collector of the first NPN bipolar transistor is connected to the node N1, the collector of the second NPN bipolar transistor is connected to the emitter of the first NPN bipolar transistor, and the third NPN bipolar transistor is connected to the second NPN bipolar transistor. The bipolar transistor is connected in parallel. The bases of the first NPN bipolar transistors receive DC voltage V3, and the bases of the second and third NPN bipolar transistors receive control signals CNT1 and CNT2, respectively. The breakdown voltage between the collector and emitter of the first NPN bipolar transistor is higher than the breakdown voltage between the collector and emitter of each of the second and third NPN bipolar transistors. The amplification factor of the second NPN bipolar transistor is smaller than the amplification factor of each of the first and third NPN bipolar transistors. In this case, the same effect as in the first embodiment can be obtained.

  Further, an IGBT (Insulated Gate Bipolar Transistor) may be used instead of the first NPN bipolar transistor. In this case, the collector of the IGBT is connected to the node N1, the emitter of the IGBT is connected to the collectors of the second and third NPN bipolar transistors, and the gate of the IGBT receives the DC voltage V3. The breakdown voltage between the collector and emitter of the IGBT is higher than the breakdown voltage between the collector and emitter of each of the second and third NPN bipolar transistors. The amplification factor of the second NPN bipolar transistor is smaller than the amplification factor of each of the third NPN bipolar transistors. In this case, the same effect as in the first embodiment can be obtained.

[Embodiment 2]
FIG. 9 is a circuit diagram showing a configuration of the semiconductor device according to the second embodiment of the present invention, which is compared with FIG. In FIG. 9, the semiconductor device is different from the semiconductor device of FIG. 1 in that the N-channel MOS transistor Q1 is replaced with a normally-on transistor Q4. As the normally-on transistor Q4, for example, a heterojunction field effect GaN transistor is used.

  N-channel MOS transistor Q1 has a positive threshold voltage VTH1 and is turned off when the gate-source voltage is 0 V, so it is called a normally-off transistor. On the other hand, the normally-on transistor Q4 has a negative threshold voltage VTH4 and is turned on when the gate-source voltage is 0V. The transistor Q4 is a high breakdown voltage and high Gm transistor.

  The threshold voltage VTH4 of the commercially available transistor Q4 varies within the range of −3V to −5V. In addition, the threshold voltages VTH2 and VTH3 of the commercially available transistors Q2 and Q3 vary within a range of 2V to 3V. The mutual conductance Gm2 of the transistor Q2 is smaller than the mutual conductances Gm3 and Gm4 of the transistors Q3 and Q4. For example, Gm2 = 6S (Siemens), Gm3 = 30S, Gm4 = 20S.

  When the control signals CNT1 and CNT2 are at “L” level, the transistors Q2 and Q3 are off. At this time, the voltage of the source (node N3) of normally-on transistor Q4 is higher than the voltage obtained by adding the absolute value of threshold voltage VTH4 to the voltage of node N2 due to the leakage current of transistor Q4. For this reason, the transistor Q4 is off.

  Next, when the control signal CNT1 rises from the “L” level to the “H” level, the transistor Q2 is turned on, and the voltage at the node N3 decreases. When the voltage difference between nodes N3 and N2 becomes smaller than the absolute value of threshold voltage VTH4 of transistor Q4, transistor Q4 is turned on, and nodes N1 and N2 become conductive. Next, when the control signal CNT2 rises from the “L” level to the “H” level, the transistor Q3 is turned on, and the resistance value between the nodes N1 and N2 decreases.

  In order to make the nodes N1 and N2 nonconductive, the control signal CNT2 is first lowered from the “H” level to the “L” level to turn off the transistor Q3. Next, the control signal CNT2 is lowered from the “H” level to the “L” level to turn off the transistor Q2. When the transistors Q2 and Q3 are turned off, the voltage at the node N3 increases due to the leakage current of the transistor Q4. When the voltage difference between nodes N3 and N2 becomes larger than the absolute value of threshold voltage VTH4 of transistor Q4, transistor Q4 is turned off and nodes N1 and N2 are rendered non-conductive.

  In the second embodiment, by switching the transistor Q4 having a high withstand voltage by the transistor Q2 having a small mutual conductance Gm2, the influence of the variation in the threshold voltage VTH4 of the transistor Q4 on the variation in the drain current of the transistor Q4 is reduced. Thus, variation in turn-on time can be suppressed to be small.

  Further, by turning on the low-breakdown-voltage transistor Q2 having a small variation in the threshold voltage VTH2, the high-breakdown-voltage transistor Q4 having a large variation in the threshold voltage VTH4 is turned on. Can do.

  Also in the second embodiment, as shown in FIG. 8, the threshold voltage VTH3 of the transistor Q3 is made higher than the threshold voltage VTH2 of the transistor Q2, and the control signal CNT1 is applied to the gates of the transistors Q2 and Q3. May be given.

  10 is a circuit diagram showing a configuration of a step-up chopper using the semiconductor device shown in FIG. 9, and is a diagram to be compared with FIG. Normally-on transistor Q4 is connected between node N1 and the drain of transistor Q2, and has its gate connected to the ground voltage GND line via gate resistor R1. Note that the gate resistor R1 may be removed and the gate of the transistor Q4 may be directly grounded.

  When the transistors Q2 to Q4 are turned on, a DC current flows from the DC power source 1 through the reactor 3 and the transistors Q2 to Q4 to the ground voltage GND line, and electromagnetic energy is stored in the reactor 3. When the transistors Q <b> 2 to Q <b> 4 are turned off, electromagnetic energy stored in the reactor 3 is released to the capacitor 5 through the diode 4. The terminal voltage of the capacitor 5, that is, the output voltage of the boost chopper is a voltage obtained by adding the terminal voltage of the reactor 3 to the output voltage of the DC power supply 1.

  In this step-up chopper, the transistor Q4 having a high mutual breakdown voltage is switched by the transistor Q2 having a small mutual conductance Gm2, thereby reducing the influence of the variation of the threshold voltage VTH4 of the transistor Q4 on the variation of the drain current of the transistor Q4. Thus, variation in the rise time of the current of the boost chopper can be suppressed small.

  Further, by turning on / off the transistor Q2 having a small variation in the threshold voltage VTH2, the transistor Q4 having a large absolute value of the threshold voltage VTH4 is turned on / off, so as in the first embodiment, Variations in the rise time of the current of the step-up chopper can be suppressed small.

  Note that the normally-on transistor Q4 may be replaced with an IGBT. Also in this case, the same effect as in the second embodiment can be obtained.

[Embodiment 3]
The semiconductor device of Embodiment 3 includes a plurality of sets of first to third transistors, the gates of the plurality of first transistors are connected to each other, and the gates of the plurality of second transistors are connected to each other. The third transistors are connected to each other, the sources of the plurality of first transistors are connected to the first node, and the sources of the plurality of second transistors are connected to the drains of the plurality of first transistors, respectively. The sources of the plurality of second transistors are all connected to the second node, and the plurality of third transistors are respectively connected in parallel to the plurality of second transistors. Hereinafter, the semiconductor device according to the third embodiment will be described in detail with reference to the drawings.

  FIG. 11 is a circuit diagram showing the configuration of the semiconductor device according to the third embodiment, which is compared with FIG. In FIG. 11, this semiconductor device is obtained by connecting a plurality of the semiconductor devices of FIG. 9 in parallel. That is, the drains of the plurality of transistors Q4 are all connected to the node N1, and their gates are both connected to the node N2. The sources of the plurality of transistors Q2 are all connected to the node N2, and their gates both receive the control signal CNT1. The sources of the plurality of transistors Q3 are all connected to node N2, and their gates both receive control signal CNT2.

  When the control signal CNT1 rises from the “L” level to the “H” level, all the transistors Q2 are turned on and all the transistors Q4 are turned on. At this time, since the transistor Q2 having a low breakdown voltage and a low Gm is turned on and the transistor Q4 having a high breakdown voltage and a high Gm is turned on, all the transistors Q4 can be turned on. Note that if a high Gm transistor is used as the transistor Q2, the current may be concentrated in one transistor Q4, and the current may not flow through the other transistor Q4.

  Since the current driving capability of the transistor Q2 is smaller than the current driving capability of the transistor Q4, the capability of the transistor Q4 cannot be fully exhibited as it is. Therefore, next, the control signal CNT2 is raised from the “L” level to the “H” level, and the low breakdown voltage and high Gm transistor Q3 is turned on. As a result, the nodes N1 and N2 become conductive.

  In order to make the nodes N1 and N2 non-conductive, first, the control signal CNT2 is lowered from the “H” level to the “L” level, and all the transistors Q3 are turned off. Next, the control signal CNT2 is lowered from the “H” level to the “L” level to turn off all the transistors Q2 and Q4.

  In the third embodiment, since the low-breakdown-voltage and low-Gm transistor Q2 is turned on and the high-breakdown-voltage and high-Gm transistor Q4 is turned on, the low-breakdown-voltage and high-Gm transistor Q3 is turned on. Current can be distributed to the transistor Q4, and current can be prevented from concentrating on one transistor Q4. In addition, since there is no need to provide a current sensor or the like as in Patent Document 1, the apparatus configuration can be simplified and the cost can be reduced.

  12 is a circuit diagram showing a configuration of a step-up chopper using the semiconductor device shown in FIG. 11, which is compared with FIG. In FIG. 12, three semiconductor devices shown in FIG. 9 are connected in parallel. Each of the gates of the three normally-on transistors Q4 is connected to the node N2 via the gate resistor R1. Each of the gates of the three transistors Q2 is connected to the output node of the control signal source S1 via the gate resistor R2. Each of the gates of the three transistors Q3 is connected to the output node of the control signal source S2 via the gate resistor R3.

  The transconductances Gm of the transistors Q2, Q3, and Q4 are 6S, 30S, and 20S, respectively. The threshold voltages VTH4 of the three transistors Q4 are −4.2V, −4.0V, and −4.0V, respectively. The threshold voltages VTH2 of the three transistors Q2 are 2.2V, 2.4V, and 2.4V, respectively. The threshold voltages VTH3 of the three transistors Q3 are 2.4V, 2.6V, and 2.6V, respectively. The resistance value of the gate resistor R1 is 10Ω, and the resistance values of the gate resistors R2 and R3 are both 100Ω.

  When the transistors Q2 to Q4 are turned on, a DC current flows from the DC power source 1 through the reactor 3 and the transistors Q2 to Q4 to the ground voltage GND line, and electromagnetic energy is stored in the reactor 3. When the transistors Q <b> 2 to Q <b> 4 are turned off, electromagnetic energy stored in the reactor 3 is released to the capacitor 5 through the diode 4. The terminal voltage of the capacitor 5, that is, the output voltage of the boost chopper is a voltage obtained by adding the terminal voltage of the reactor 3 to the output voltage of the DC power supply 1.

  FIG. 13A shows the voltage Vds between the nodes N1 and N2 when the transistors Q2 to Q4 are turned on, the current IA flowing through the left transistor Q4 in FIG. 12, and the current flowing through the center transistor Q4 in FIG. It is a time chart which shows a waveform with IB. In FIG. 13A, when the transistors Q1, Q2, and Q4 are turned on at a certain time, the voltage Vds between the nodes N1 and N2 suddenly decreases, and both the currents IA and IB increase.

  FIG. 13B shows the voltage Vds between the nodes N1 and N2 when the transistors Q2 to Q4 are turned off, the current IA flowing through the left transistor Q4 in FIG. 12, and the central transistor Q4 in FIG. It is a time chart which shows a waveform with electric current IB. In FIG. 13B, when the transistors Q1, Q2, and Q4 are turned off at a certain time, the voltage Vds between the nodes N1 and N2 suddenly increases, and both the currents IA and IB decrease. As can be seen from FIGS. 13 (a) and 13 (b), currents of substantially the same value flowed through the two transistors Q4 at substantially the same timing both at turn-on and at turn-off.

  FIG. 14 is a circuit diagram showing a configuration of a conventional boost chopper which is a comparative example of the third embodiment, and is a diagram to be compared with FIG. Referring to FIG. 14, in this step-up chopper, three normally-on transistors Q4 are connected in parallel between nodes N1 and N2. Each of the gates of the three transistors Q4 is connected to the output node of the control signal source S11 via the gate resistor R1. The control signal source S11 outputs a control signal CNT11 that is a 10 KHz rectangular wave signal. The ground node of the control signal source S11 is grounded.

  The mutual conductance Gm of the three transistors Q4 is both 20S. The threshold voltages VTH4 of the three transistors Q4 are −4.2V, −4.0V, and −4.0V, respectively. The resistance values of the three gate resistors R1 are both 100Ω. The parasitic inductances of the gates of the three transistors Q4 are the same, the parasitic inductances of their drains are the same, and the parasitic inductances of their sources are the same.

  When control signal S11 rises from “L” level (for example, −6V) to “H” level (for example, −2V), transistor Q4 is turned on, and electromagnetic energy is stored in reactor 3. When the control signal S11 falls from the “H” level to the “L” level, the transistor Q4 is turned off, and the electromagnetic energy of the reactor 3 is released to the capacitor 5.

  FIG. 15A shows the voltage Vds between the nodes N1 and N2 when the transistor Q4 is turned on, the current IA flowing through the left transistor Q4 in FIG. 14, and the current IB flowing through the center transistor Q4 in FIG. It is a time chart which shows the waveform. In FIG. 15A, when the control signal CNT11 is raised from the “L” level to the “H” level at a certain time, the left transistor Q4 having a low threshold voltage is turned on before the central transistor Q4. The current IA of the left transistor Q4 suddenly increases, and the voltage Vds suddenly decreases. Next, when the central transistor Q4 having a high threshold voltage is turned on and the current IB of the central transistor Q4 increases, the current IA of the left transistor Q4 decreases.

  15B shows the voltage Vds between the nodes N1 and N2 when the transistor Q4 is turned off, the current IA flowing through the left transistor Q4 in FIG. 14, and the current IB flowing through the center transistor Q4 in FIG. It is a time chart which shows the waveform. In FIG. 15B, when the control signal CNT11 falls from the “H” level to the “L” level at a certain time, the central transistor Q4 having a high threshold voltage is turned off before the left transistor Q4. As the current IB decreases, the current IA increases rapidly. Next, the left transistor Q4 having a low threshold voltage is turned off, and the current IA decreases.

  Thus, in the conventional step-up chopper, current concentrates on one transistor Q4 having a low threshold voltage among the plurality of transistors Q4 connected in parallel. Although a method of measuring the threshold voltage of the transistor Q4 in advance and constructing a boost chopper using a plurality of transistors Q4 having the same threshold voltage is conceivable, the cost increases. Moreover, in the method of patent document 1, as above-mentioned, an apparatus structure becomes complicated and it becomes expensive.

  On the other hand, in the step-up chopper according to the present invention, it is possible to allow current to flow uniformly to the plurality of transistors Q4 with a simple configuration at low cost, and to prevent the transistor Q4 from being damaged due to current concentration.

[Embodiment 4]
FIG. 16 is a circuit diagram showing a configuration of the semiconductor device according to the fourth embodiment of the present invention, which is compared with FIG. In FIG. 16, this semiconductor device is obtained by connecting a plurality of the semiconductor devices of FIG. 1 in parallel. That is, the drains of the plurality of transistors Q1 are all connected to node N1, and their gates both receive DC voltage V3. The sources of the plurality of transistors Q2 are all connected to the node N2, and their gates both receive the control signal CNT1. The sources of the plurality of transistors Q3 are all connected to node N2, and their gates both receive control signal CNT2.

  When the control signal CNT1 rises from the “L” level to the “H” level, all the transistors Q2 are turned on and all the transistors Q1 are turned on. At this time, since the low-breakdown-voltage and low-Gm transistor Q2 is turned on and the high-breakdown-voltage and high-Gm transistor Q1 is turned on, all the transistors Q1 can be turned on. Note that when a high Gm transistor is used as the transistor Q2, the current may be concentrated in one transistor Q1, and the current may not flow in the other transistor Q1.

  Since the current driving capability of the transistor Q2 is smaller than the current driving capability of the transistor Q1, the capability of the transistor Q1 cannot be fully exhibited as it is. Therefore, next, the control signal CNT2 is raised from the “L” level to the “H” level, and the low breakdown voltage and high Gm transistor Q3 is turned on. As a result, the nodes N1 and N2 become conductive.

  In order to make the nodes N1 and N2 non-conductive, first, the control signal CNT2 is lowered from the “H” level to the “L” level, and all the transistors Q3 are turned off. Next, the control signal CNT2 is lowered from the “H” level to the “L” level to turn off all the transistors Q1 and Q2.

  In the fourth embodiment, the low-breakdown-voltage and low-Gm transistor Q2 is turned on to turn on the high-breakdown-voltage and high-Gm transistor Q1, and then the low-breakdown-voltage and high-Gm transistor Q3 is turned on. Current can be distributed to the transistor Q1, and the current can be prevented from concentrating on one transistor Q1. In addition, since there is no need to provide a current sensor or the like as in Patent Document 1, the apparatus configuration can be simplified and the cost can be reduced.

  FIG. 17 is a circuit diagram showing a configuration of a step-up chopper using the semiconductor device shown in FIG. 16, and is a diagram contrasted with FIG. In FIG. 17, three semiconductor devices shown in FIG. 1 are connected in parallel. Each of the gates of the three transistors Q1 is connected to the positive electrode of the DC power source 2 via the gate resistor R1 and receives the DC voltage V3. Each of the gates of the three transistors Q2 is connected to the output node of the control signal source S1. Each of the gates of the three transistors Q3 is connected to the output node of the control signal source S2.

  The transconductances Gm of the transistors Q1, Q2, and Q3 are 35S, 6S, and 30S, respectively. The threshold voltages VTH1 of the three transistors Q1 are 4.2V, 4.0V, and 4.0V, respectively. The threshold voltages VTH2 of the three transistors Q2 are 1.2V, 1.4V, and 1.4V, respectively. The threshold voltages VTH3 of the three transistors Q3 are 1.4V, 1.6V, and 1.6V, respectively. The resistance value of the gate resistor R1 is 10Ω, and the resistance values of the gate resistors R2 and R3 are both 100Ω.

  When the transistors Q1 to Q3 are turned on, a direct current flows from the DC power source 1 to the ground voltage GND line via the reactor 3 and the transistors Q1 to Q3, and electromagnetic energy is stored in the reactor 3. When the transistors Q <b> 1 to Q <b> 3 are turned off, electromagnetic energy stored in the reactor 3 is released to the capacitor 5 through the diode 4. The terminal voltage of the capacitor 5, that is, the output voltage of the boost chopper is a voltage obtained by adding the terminal voltage of the reactor 3 to the output voltage of the DC power supply 1. In this step-up chopper as well, as in the step-up chopper of the third embodiment, current flows evenly through the three transistors Q1.

[Embodiment 5]
FIG. 18 is a circuit diagram showing the configuration of the step-down chopper according to the fifth embodiment of the present invention, and is compared with FIG. 18, in this step-down chopper, a plurality of semiconductor devices shown in FIG. 9 (three in FIG. 18) are connected in parallel as in the step-up chopper shown in FIG. The step-down chopper includes three gate resistors R1, a DC power source 1, a reactor 3, a diode 4, a capacitor 5, control signal sources S1 and S2, and a gate driver 15.

  The drains of the three normally-on transistors Q4 are both connected to the node N1. The gate of each transistor Q4 is connected to the node N2 via the gate resistor R1. The drains of the three N-channel MOS transistors Q2 are connected to the sources of the three transistors Q4, respectively, their sources are both connected to the node N2, and their gates both receive the control signal CNT1A. The drains of the three transistors Q3 are respectively connected to the sources of the three transistors Q4, the sources of which are both connected to the node N2, and the gates of which receive the control signal CNT2A.

  Node N1 is connected to the positive electrode of DC power supply 1 and receives DC voltage V1 (for example, 300V). The negative electrode of DC power supply 1 receives ground voltage GND. Control signal sources S1 and S2 generate control signals CNT1 and CNT2, respectively. The gate driver 15 generates control signals CNT1A and CNT2A based on the voltage V2 of the node N2 and the control signals CNT1 and CNT2. The “L” level voltages of the control signals CNT1A and CNT2A are the same as the voltage V2 of the node N2. The “H” level voltages of the control signals CNT1A and CNT2A are the same as the voltages obtained by adding the voltage V2 of the node N2 to the voltage (12V) of the control signals CNT1 and CNT2, respectively.

  The anode of the diode 4 is connected to the line of the ground voltage GND, and its cathode is connected to the node N2. One terminal of reactor 3 is connected to node N2. Capacitor 5 is connected between the other terminal of reactor 3 and the line of ground voltage GND. The load circuit 6 is connected to the capacitor 5 in parallel.

  When the control signal CNT1A is raised from the “L” level to the “H” level, all the transistors Q2 are turned on and all the transistors Q4 are turned on. At this time, since the transistor Q2 having a low breakdown voltage and a low Gm is turned on and the transistor Q4 having a high breakdown voltage and a high Gm is turned on, all the transistors Q4 can be turned on. Note that if a high Gm transistor is used as the transistor Q2, the current may be concentrated in one transistor Q4, and the current may not flow through the other transistor Q4.

  Since the current driving capability of the transistor Q2 is smaller than the current driving capability of the transistor Q4, the capability of the transistor Q4 cannot be fully exhibited as it is. Therefore, next, the control signal CNT2A is raised from the “L” level to the “H” level to turn on the transistor Q3 having a low breakdown voltage and a high Gm. As a result, the nodes N1 and N2 become conductive.

  In order to make the nodes N1 and N2 nonconductive, first, the control signal CNT2A is lowered from the “H” level to the “L” level, and all the transistors Q3 are turned off. Next, the control signal CNT2A is lowered from the “H” level to the “L” level to turn off all the transistors Q2 and Q4.

  When the transistors Q2 to Q4 are turned on as described above, a DC current flows in a path from the positive electrode of the DC power supply 1 to the negative electrode of the DC power supply 1 through the transistors Q4, Q2, Q3, the reactor 3, and the capacitor 5. The capacitor 5 is charged and electromagnetic energy is stored in the reactor 3. When the transistors Q <b> 2 to Q <b> 4 are turned off, a direct current flows through the path of the reactor 3, the capacitor 5, and the diode 4 by the electromagnetic energy stored in the reactor 3. The voltage across the capacitor 5, that is, the output voltage of the step-down chopper is applied to the load circuit 6.

  Transistors Q2-Q4 are turned on / off at a predetermined cycle. When the ratio of the on time and the off time of the transistors Q2 to Q4 in one cycle is increased, the voltage between terminals of the capacitor 5 is increased. Conversely, when the ratio of the on-time to the off-time of the transistors Q2 to Q4 in one cycle is reduced, the voltage between the terminals of the capacitor 5 is reduced. Therefore, the voltage between the terminals of the capacitor 5 can be adjusted to a desired voltage between the DC voltage V3 and the ground voltage GND by adjusting the ratio between the on time and the off time of the transistors Q2 to Q4 within one cycle. . Even in this step-down chopper, currents flowed equally through the three transistors Q4.

  Note that it is also possible to form an inverter by configuring each of the upper arm and the lower arm with a semiconductor device including the three sets of transistors Q2 to Q4 shown in FIG.

  FIG. 19 is a circuit block diagram showing a step-down chopper that is a modification of the fifth embodiment, and is a diagram to be compared with FIG. Referring to FIG. 19, this step-down chopper is different from the step-down chopper of FIG. 18 in that each normally-on type transistor Q4 is replaced with an N-channel MOS transistor Q1, and a DC power supply 2, a diode 16, and three capacitors C1 is added.

  The negative electrode of DC power supply 2 receives ground voltage GND. The anode of the diode 16 is connected to the positive electrode of the DC power supply 2 and receives a DC voltage V3 (for example, 12V). DC voltage V3 is sufficiently higher than the threshold voltage of transistor Q1. Each capacitor C1 is connected between the cathode of the diode 16 and the node N2. Each gate resistor R1 is connected between the gate of the corresponding transistor Q1 and the cathode of the diode 16. As a result, a voltage that is higher than the node N2 by the DC voltage V2 is applied to the gate of the transistor Q1, so that the transistor Q1 is reliably turned on when the control signal CNT1A is set to the “H” level and the transistor Q2 is turned on. Can be turned on. Since other configurations and operations are the same as those of the step-down circuit of FIG. 18, the description thereof will not be repeated. Even in this step-down chopper, currents flowed evenly through the three transistors Q1.

  It is also possible to form an inverter by configuring each of the upper arm and the lower arm with the semiconductor device including the three sets of transistors Q1 to Q3 shown in FIG.

  Needless to say, the first to fifth embodiments may be appropriately combined with various modified examples.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  Q1-Q3, Q10 N-channel MOS transistor, 1, 2 DC power supply, 3 reactors, 4, 11, 16 diode, 5, 12, C1 capacitor, 6, 10, 14 load circuit, 13 AC power supply, 15 gate driver, S1 , S2, S10 control signal source, R1 to R3 gate resistance, SW1 to SW4, SW11 to SW14 switch, Q4 normally on transistor.

Claims (14)

A first transistor having a first electrode connected to a first node;
A second transistor having a first electrode connected to the second electrode of the first transistor, a second electrode connected to the second node, and a control electrode connected to the first control node;
A third transistor having a first electrode connected to a second electrode of the first transistor, a second electrode connected to the second node, and a control electrode connected to a second control node; With
The breakdown voltage between the first and second electrodes of the first transistor is higher than the breakdown voltage between the first and second electrodes of each of the second and third transistors;
The amplification factor of the second transistor is minor than the amplification factor of said third transistor,
When conducting between the first and second nodes , a semiconductor device in which the second transistor is turned on to turn on the first transistor and then the third transistor is turned on . The first transistor is turned off when the third transistor is turned off and then the second transistor is turned off to turn off the first transistor when the first and second nodes are made non-conductive. Semiconductor device. A first transistor having a first electrode connected to a first node;
A second transistor having a first electrode connected to the second electrode of the first transistor, a second electrode connected to the second node, and a control electrode connected to the first control node;
A third transistor having a first electrode connected to a second electrode of the first transistor, a second electrode connected to the second node, and a control electrode connected to a second control node; With
The breakdown voltage between the first and second electrodes of the first transistor is higher than the breakdown voltage between the first and second electrodes of each of the second and third transistors;
The amplification factor of the second transistor is smaller than the amplification factor of the third transistor,
In the case where the first and second nodes are made non-conductive, a semiconductor device in which the third transistor is turned off and then the second transistor is turned off to turn off the first transistor. A plurality of sets of the first to third transistors;
Control electrodes of the plurality of first transistors are connected to each other;
The control electrodes of the plurality of second transistors are all connected to the first control node,
The control electrodes of the plurality of third transistors are all connected to the second control node,
The first electrodes of the plurality of first transistors are both connected to the first node;
The first electrodes of the plurality of second transistors are respectively connected to the second electrodes of the plurality of first transistors;
A second electrode of each of the plurality of second transistors is connected to the second node;
The first electrodes of the plurality of third transistors are respectively connected to the second electrodes of the plurality of first transistors;
4. The semiconductor device according to claim 1, wherein second electrodes of the plurality of third transistors are all connected to the second node. 5. The amplification factor of the second transistor is smaller than the amplification factor of the first transistor, the semiconductor device according to any one of claims 1 to 4. The first node receives a first voltage;
The second node receives a second voltage;
A first control signal for controlling on / off of the second transistor is provided to the first control node;
6. The semiconductor device according to claim 1, wherein a second control signal for controlling on / off of the third transistor is supplied to the second control node. 7. The first node receives a first voltage;
The second node receives a second voltage;
The threshold voltage of the second transistor is lower than the threshold voltage of the third transistor;
6. The semiconductor device according to claim 1, wherein a control signal for controlling on / off of the second and third transistors is supplied to the first and second control nodes. 7.   8. The semiconductor device according to claim 6, wherein each of the second and third transistors is a normally-off transistor. The first transistor is a normally-off transistor;
The semiconductor device according to claim 6, wherein the control electrode of the first transistor receives a third voltage higher than a threshold voltage of the first transistor. A capacitor connected between the control electrode of the first transistor and the second node;
The semiconductor device according to claim 9, further comprising: a cathode connected to a control electrode of the first transistor, and an anode receiving the third voltage. The first transistor is a normally-on transistor;
The semiconductor device according to claim 6, wherein a control electrode of the first transistor is connected to the second node.   A converter comprising the semiconductor device according to claim 1.   An inverter comprising the semiconductor device according to any one of claims 1 to 11.   A power converter device comprising the semiconductor device according to claim 1.

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