JP5466396B2 - Appearance inspection device - Google Patents

Description

  The present invention relates to an appearance inspection apparatus for inspecting a surface state of a substrate.

  For example, in a semiconductor integrated circuit device, a memory element is miniaturized according to a demand for high integration, wiring is densified, and a circuit pattern formed on a semiconductor wafer (substrate) is miniaturized. Along with this, the demand for improving the image processing capability of an appearance inspection apparatus for inspecting the surface state of a substrate is increasing year by year.

As a technique for improving the image processing capability, Patent Document 1 reports a semiconductor appearance inspection apparatus that uses a plurality of processor elements and performs parallel image processing.
Further, the development of fault tolerance technology against the failure of the parallel processor element is widely performed mainly in the field of enterprise servers, and a technical report called degeneration processing has been reported. (For example, Non-Patent Document 1)
JP 2005-274172 A Masayoshi Nagashima and five others, “Overview of Express server middleware (VALUMOware)” NEC Technical Journal, NEC Corporation, Vol. 58, no. 1/205, p. 62-p. 66

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for speeding up the appearance inspection by dividing a huge amount of image data and performing image processing in parallel. In a semiconductor visual inspection apparatus using parallel processor elements, a failure of a processor element (PE) is a fatal error, and inspection data is not recorded, so that a reliable inspection result cannot be obtained. Therefore, at present, when the PE fails, the inspection is immediately stopped.

  Due to the emergency stop of the inspection device, TAT from analysis by the worker, replacement of parts, and restarting exists as a time cost. Further, it is considered that the demand for an increase in image processing capacity due to the miniaturization of the semiconductor process will continue in the future, and the increase in the number of PEs associated with them is also considered. Increasing the number of parts used will increase the probability of failure.

The technique described in Non-Patent Document 1 is such that when one PE fails, a normal PE takes over the processing.
What is reported here is that normal PEs take over the processing of failed PEs while switching tasks, so that the processing capacity is reduced to 50%, but the influence of the failure is not affected to the entire server. This is one of the fault tolerance technologies.
The degeneration processing reported by the server or the like is intended for a system that has data to be processed in advance, such as a database application, and sequentially processes it.

  However, the degeneration processing used in the server field cannot be directly applied to real-time data generation and processing systems such as semiconductor visual inspection equipment. This is because the processing time is set in the image processing apparatus of the semiconductor appearance inspection apparatus, and when the degeneration process is simply performed, an error state such as overflow of detected image data is caused.

  An object of the present invention is to improve fault tolerance of a processor element in an appearance inspection apparatus such as a semiconductor appearance inspection apparatus that requires real-time processing. It is another object of the present invention to provide an appearance inspection apparatus capable of displaying the presence / absence of a failure of a processor element and the processing speed (or time until the end of the inspection) of the inspection at the time of the processor element failure.

  As a form of an appearance inspection apparatus that improves fault tolerance for a processor element, a sample stage on which a substrate to be inspected is mounted, a detection unit that detects information reflecting the surface state of the substrate to be inspected, and storing the detected information An image processing unit including a plurality of processor elements to be processed; a user interface unit that displays an output from the image processing unit; an overall control that controls the sample stage, the detection unit, the image processing unit, and the user interface unit An image inspection unit that monitors a connection state of the plurality of processor elements, and performs image division / distribution control according to the connection state of the processor elements. The image distribution control unit to perform and the detection process according to the image division / distribution status of the processor element. A detection speed setting unit for setting a speed, and when the processor element fails, the image distribution control unit stores information to be stored by the failed processor element so that the connected normal processor element stores the information. The detection speed setting unit resets the detection speed in response to the redistribution, and the inspection is continued at the reset speed.

  Further, as one form of an appearance inspection apparatus capable of displaying a failure of a processor element, a detection unit that detects information reflecting a surface state of a substrate to be inspected and a plurality of processor elements that store and process the detected information are included. An appearance inspection apparatus having an image processing unit, a user interface unit that displays an output from the image processing unit, the detection unit, the image processing unit, and an overall control unit that controls the user interface unit, When the processor element fails, processor appearance information is displayed on the user interface unit, and the appearance inspection apparatus has a function of continuing the inspection.

  An image processing unit including a detection unit that images a wafer surface and a parallel processor element that processes the captured data as one form of a semiconductor device appearance inspection apparatus that improves fault tolerance and can display a failure for the processor element A visual inspection apparatus for a semiconductor element having a user interface unit that displays a captured image and an image processing result, and an overall control unit that controls the entire visual inspection apparatus, wherein the image processing unit includes: An image distribution control unit that performs image distribution control according to the state, a detection speed setting unit that sets a detection system speed to a desired image detection speed according to the processing capacity of the image processing apparatus that varies depending on the number of connected processor elements, and The overall control unit includes the unit when an area incapable of image processing occurs on the wafer. A semiconductor device visual inspection apparatus having a function of instructing the interface apparatus to indicate that an image non-processable area has occurred, and continuing inspection processing without stopping; To do.

  Even if a processor element failure occurs, inspection can be continued without interrupting inspection on the semiconductor manufacturing line, mask manufacturing line, and other manufacturing lines that require visual inspection (improved fault tolerance) ). Further, it is possible to know whether or not a processor element has failed without interrupting the inspection.

  Examples will be described below.

The first embodiment will be described below.
FIG. 1 is an example of an appearance inspection apparatus using a scanning electron microscope (SEM). Examples of the semiconductor inspection apparatus include an optical type and SEM type visual inspection apparatus and an SEM length measuring apparatus.

The SEM type visual inspection apparatus 52 includes an image processing section 54, a control section 39, and a secondary electron detection section 55 in addition to the inspection room 1 and a spare room (not shown in the present embodiment). The inside of the examination room 1 is composed of an electron gun 4, an extraction electrode 3 for an electron beam 5, a condenser lens 2, a blanking deflector 6, a scanning deflector 8, an aperture 7, an objective lens 13, a reflector 9, and an ExB deflector 12. Has been.
Of the secondary electron detector 55, the secondary electron detector 10 is disposed above the objective lens 13 in the examination room 1. The output signal of the secondary electron detector 10 is amplified by a preamplifier 20 installed outside the examination room 1 and converted into digital data by an AD converter 21.
The examination room 1 is also composed of a sample stage 15, an X stage 17, and a Y stage 18. The X stage 17 and the Y stage 18 are controlled by a stage drive control unit 28 that performs drive control in the xy axis directions based on a stage control signal obtained from the overall control unit 39.
The deflection frequency, deflection width, and the like of the electron beam by the scanning deflector 8 are controlled by the deflection control unit 25 to two-dimensionally scan the electron beam 5 on the target substrate 16 based on a command from the overall control unit 39. The

The numerical aperture of the objective lens 13 is controlled by the objective lens control unit 26 based on a command from the overall control unit 39.
Operation commands and operation conditions of each part of the apparatus are input / output from the overall control unit 39.
In order to acquire an image of the substrate 16 to be inspected, the substrate 16 to be inspected is irradiated with a finely focused electron beam 5 to generate secondary electrons 11, which are scanned by the electron beam 5 and the X stage 17, Y By detecting in synchronization with the movement of the stage 18, an image of the inspected substrate 16 is obtained.
The electron beam 5 is accelerated by applying a high negative potential to the electron gun 4.

As a result, the electron beam 5 travels in the direction of the sample stage 15 with energy corresponding to the potential, is converged by the condenser lens 2, and is further narrowed down by the objective lens 13 to be X stage 17 and Y stage on the sample stage 15. The substrate 16 to be inspected mounted on 18 is irradiated. The substrate 16 to be inspected is a substrate having a fine circuit pattern such as a semiconductor wafer, a chip, a liquid crystal, or a mask.
The blanking deflector 6 is connected to a deflection control unit 25 that generates a scanning signal and a blanking signal.

Secondary electrons 11 generated by irradiating the inspection substrate 16 with the electron beam 5 are accelerated by a negative voltage applied to the inspection substrate 16.
An ExB deflector 12 for bending the trajectory of the secondary electrons without affecting the trajectory of the electron beam 5 by both the electric field and the magnetic field is disposed above the substrate 16 to be inspected. The electrons 11 are deflected in a predetermined direction. This amount of deflection can be adjusted by the strength of the electric field and magnetic field applied to the ExB deflector 12.
The secondary electrons 11 deflected by the ExB deflector 12 collide with the reflecting plate 9 under a predetermined condition. When the accelerated secondary electrons 11 collide with the reflector 9, second secondary electrons having an energy of several eV to 50 eV are generated from the reflector 9.

The secondary electron detector 55 includes a secondary electron detector 10 disposed in the evacuated inspection chamber 1, a preamplifier 20 disposed outside the inspection chamber 1, an AD converter 21, a high voltage power supply 24, and a preamplifier drive. The power source 22, the AD converter drive power source 23, and the reverse bias power source 19 are configured.
The secondary electron detector 10 is configured to detect second secondary electrons generated when the secondary electrons 11 collide with the reflector 9 in conjunction with the scanning timing of the electron beam 5. The output signal of the secondary electron detector 10 is amplified by a preamplifier 20 installed outside the examination room 1 and converted into digital data by an AD converter 21.
The AD converter 21 is configured to convert the analog signal detected by the secondary electron detector 10 into a digital signal immediately after being amplified by the preamplifier 20 and to transmit the digital signal to the image processing unit 54.
Note that when the electron beam 5 needs to be blanked, the blanking deflector 6 deflects the electron beam 5 so that the electron beam does not pass through the diaphragm 7.

The AD converted SEM image is processed by the image processing means.
For example, in the case of a SEM for length measurement, the image processing unit 54 measures the distance between patterns in a designated image.
In the case of an SEM for observation (appearance inspection based on an SEM image), the image processing unit 54 performs processing such as image enhancement.

Next, a general inspection flow of the wafer appearance inspection apparatus will be described with reference to FIGS.
Each component operates according to an instruction from the overall control unit 39.
First, the wafer 16 that is the substrate to be inspected is taken out from the wafer cassette (not shown) by a loader (not shown) (1702).
Next, the wafer 16 is mounted on the sample stage 15 in the sample chamber 1 and positioned (1703).
Subsequently, the inside of the sample chamber 1 is evacuated (1704), and the conditions of the electron optical system are set (1705).
Next, the sample stage 15 moves to the scanning start position 1801 of the area to be inspected of the mounted wafer 16 (1706).
Next, the Y stage 18 is scanned in the Y direction, and in synchronization with the stage scanning, the electron beam 5 is scanned in the X direction by the scanning deflector 8 (1707). During effective scanning of the die 300, voltage application to the blanking deflector 6 is interrupted, and the surface of the wafer 16 is irradiated with the electron beam 5 and scanned (1708).

The secondary electrons 11 generated from the wafer 16 by the irradiation of the electron beam 5 are detected by the secondary electron detector 10 (1709). The output signal from the secondary electron detector 10 is amplified by the preamplifier 20, then A / D converted by the AD converter 21, and stored in the buffer memory 30 as digital image data (1710).
Next, after the X stage is moved by the width of the die 201 in the X direction, processes 1707 to 1710 are executed. This stage scan is repeated until the entire required area is inspected and the stage position reaches the inspection end position 1802.
When the inspection of the entire surface of the wafer 16 is completed, the scanning of the X stage 17, the Y stage 18, and the scanning deflector 8 is stopped.
Thereafter, the vacuum in the sample chamber 1 is released, and the wafer 16 is taken out from the sample table 15 by a loader and stored in a cassette.
Thus, the inspection of one wafer including a plurality of dies is completed.

The configuration of the image processing apparatus will be described below with reference to FIG.
The internal configuration of the image processing apparatus 54 includes an image distribution control unit 32, a path switch 42 for switching the path of image data divided by the image distribution control unit, and processor elements 48, 49, 50,. . . , 51.
The image distribution control unit 32 cuts out the continuous image data in units of basic images and assigns them to a plurality of processors to perform defect inspection.
The captured electron beam image or optical image is displayed on the monitor 53.
The image signal of the inspected substrate 16 detected by the secondary electron detector 10 is sent to the buffer memory 30, the image distribution control unit 32, or the processor elements 48, 49, 50,. . . , 51.

  A configuration of a processor element to be used, hereinafter referred to as a processor element, is shown in FIG. The processor element 900 has one or more processor devices 903, an image memory 902, and one or more input / output controllers 901 for connecting to a network used for image data transmission in the image processing device. Exchange data. Each processor element has a unique ID 904 so that the processor element can be identified individually.

Returning to FIG. 1, the configuration of the image distribution control unit will be described.
The image distribution control unit 32 has a function of dividing continuous image data as processing unit images and distributing them to predetermined processor elements. Reference numeral 30 denotes a buffer memory for temporarily storing output data from the secondary electron detection unit 55, and reference numeral 34 denotes a path through which continuous image data output from the buffer memory is input to the distribution setting unit 33. The distribution setting unit 33 includes a plurality of distribution tables 40.

A division range, a division size, a distribution destination processor element, and the like of continuous image data are collected in each distribution table 40 in the image distribution control unit 32.
The continuous image data 134 is divided in accordance with the distribution table 40, header information indicating ID numbers indicating individual processor elements is added, and the processor element corresponding to the corresponding ID number is passed through the image data path 43 and the path switch 42. Stored in the memory.
The transmission data structure is shown in FIG. It includes the ID 800 of the transfer destination processor element, the division number 801 on the wafer, the image coordinates 802 on the wafer, the transfer image size 803, and the wafer image data 804.
The transmission data has an individual ID number, is route-switched by a switch device, and is transferred to an individual processor element.

Details of the distribution process will be described with reference to FIG.
FIG. 4 shows the operation of image distribution control. Here, a process for dividing a die unit input image into a certain amount will be described. In FIG. 4, five processor elements 306 to 310 and an image memory 305 in each processor element are shown. Further, the scan image 303 of the die 300 includes image data 311-315, and the scan image 321 of the die 301 includes image data 316-320.

Of the continuous image data, the first image 311 is sent to the processor element 306, the second image 312 of the die scan continuous image data is sent to the processor element 307, and the third image 313 of the die scan continuous image data is sent to the processor element 308. Then, the fourth image 314 of the die scan continuous image data is transferred to the processor element 309, and the fifth image 315 of the die scan continuous image data is transferred to the processor element 310.
The previously transferred data is defined as first image data.

The scan on the wafer continues, the scan image 321 of the next die 301, the first image 316 of the die scan continuous image data to the processor element 306, and the second image 317 of the die scan continuous image data to the processor element 307. The third image 318 of the die scan continuous image data is sent to the processor element 308, the fourth image 319 of the die scan continuous image data is sent to the processor element 309, and the fifth image 320 of the die scan continuous image data. Is transferred to the processor element 310.
Next, the transferred data is set as second image data.
The image distribution method has been described above.

Subsequently, a defect inspection as a function of image processing will be described by taking die comparison as an example. In addition, using the same idea, it is possible to inspect cell comparison and dicell mixture comparison.
For example, the cutout image 311 is in the processor element 306, the cutout image 312 is in the processor element 307, the cutout image 313 is in the processor element 308, the cutout image 314 is in the processor element 309, the cutout image 315 is in the processor element 310, and the cutout image 316 Are arranged in the processor element 306, the cutout image 317 is arranged in the processor element 307, the cutout image 318 is arranged in the processor element 308, and so on.

The processor elements 306, 307, 308, 309, and 310 perform various image processing for aligning the first image signal and the second image signal stored in the image memory, normalizing the signal level, and removing the noise signal. And comparing the two image signals.
Further, defect determination processing is performed in each of the processor elements 306, 307, 308, 309, and 310, and the absolute value of the difference image signal that has been subjected to the comparison operation is compared with a predetermined threshold value. When the difference image signal level is high, the pixel is determined as a defect candidate.
The types and characteristics of the defects are displayed separately on the object wafer map 1103 by changing the symbol, chromaticity, brightness, etc. (FIG. 5).

Returning to FIG. 1, the processor elements 48 to 51 to which continuous image data is input have the same function. Each processor element performs defect determination processing for each image segmented and cut out in units of basic image data, and stores defect information detected therein in the overall control unit 39 through the path switch 42.
The overall control unit 39 displays the position, the number of defects, and the like on the monitor 53 in FIG. The defect information is displayed on the user interface 1100 shown in FIG. 5 during the inspection. The user interface 1100 may be a dedicated display unit, but the monitor 53 may be shared.

Next, an embodiment of a semiconductor visual inspection apparatus that continues processing in response to a decrease in the number of processing processor elements, such as a processor element failure or a missing processor element, will be described with reference to the drawings.
The sequence is shown in FIG.
First, processor element failure detection standby is performed in sequence 211.
When a failure occurs, the image distribution table is set from sequence 212 to sequence 216. Next, in the sequences 217 to 218, the detection speed of the detection system is reset.
Finally, in the sequence 219, these situations are displayed on the user interface.

Hereinafter, detailed operations in each sequence 220 will be described.
The image processing apparatus 54 in FIG. 1 has a processor state monitoring unit 38.
An embodiment of means for managing the connection state of individual processor elements connected in parallel in the processor state monitoring unit 38 will be described.
As a method of detecting a failure of the individual processor elements 48, 49, 50, 51, there is a method of monitoring a network connection state. For example, in the InfiniBand network, the connection status identification register of the Channel Adapter device is monitored, and if the connection status becomes disconnected during the data transmission process, it is determined that the connection to the processor element has been disconnected.

  There is also a means having a signal line for inverting the state of the signal 41 when an error occurs in an individual processor element. When the state of the signal line is reversed, for example, from the Low state to the High state, or vice versa, it is determined that some error has occurred in the processor element and data processing cannot be continued.

Further, these are not only a failure of the processor element but also a detection means when the processor element is pulled out at an arbitrary timing.
By these detecting means, the failure or missing state of the processor element detected by the processor state monitoring unit 38 is registered in the distribution table 40 by the table setting unit 36.

FIG. 7 shows one embodiment of the means for updating information on the distribution table 40 when the processor connection state monitoring unit 38 detects a decrease in the number of processor elements.
Assume that processor element ID No. 5 has failed. In this case, the fifth row in the column of the transfer destination processor element ID 201 is searched, and the row 209 corresponds.
The ID of the transfer destination processor element in the row 209 is registered as the ID of another valid processor element. In the example of FIG. 7, a substitute processor element is assigned to ID No. 3, and the transfer destination processor element is rewritten to 3.
In the table 40, the wafer division numbers 200 are different, and rows 207 and 209 having the same ID of the transfer destination processor element 201 are created.
The number of rows having the same ID of the distribution destination processor element is counted, and the number of rows 2 is registered in the processing load 202.

FIG. 8 shows an example of distribution of die image data when information on the distribution table 40 is rewritten.
Since the processor element 340 has failed, the die image 345 and the die image 350 are stored in the image memory of the processor element 338.
The processor element 338 stores the die image data twice. The die comparison processing time is shown in FIG. In the processor element to which the die-divided image is transferred twice, the processing time for die comparison is doubled. When the die-divided image is transferred twice, the processing speed as the image processing apparatus is 50%.
The detection speed is changed to cope with the decrease in the processing speed of the image processing apparatus.

An example of the operation of the detection system 1 when the distribution table 40 of the image distribution control unit 32 is updated will be described.
When the processor state monitoring unit 38 detects a decrease in the number of processor elements such as a processor element failure, it instructs the detection speed setting unit 31 to set the detection system speed.
The detection speed setting unit 31 searches the processing load field of the distribution table 40 to obtain the maximum processing load value.
The general control unit 39 is instructed so that the speed of the detection system becomes 1 / maximum processing load value.
In response to this, the overall control unit 39 changes the axial drive speed of the X stage 17 and the Y stage 18, changes the deflection speed of the electron beam with respect to the deflection coil 8, etc., and sets the signal capture timing of the secondary electron detector 55. change.

  For example, in the distribution table 40, when the processing load value is 2 and the processing speed of the image processing apparatus 54 is halved, the overall control unit performs setting so that the detection speed is halved. Specifically, the xy axis direction drive speed is halved, the change speed is halved, and the signal capture timing of the secondary electron detector is halved.

  In the sequence 212 of FIG. 6, when there are a plurality of failed processor element IDs in the distribution table, the subsequent sequences 213 and 214 are executed for the plurality of rows. As a result, the sequence 220 shown in the figure is effective even when a plurality of processor elements fail.

It is conceivable that a difference occurs in the inspection result depending on when the failure of the processor element occurs in timing.
When the on-wafer divided image 43 is distributed to the processor elements 48, 49, 50,... 51 and image processing is being performed, if a failure or the like of the processor element occurs, the image being processed in the processor element Since the processing is interrupted, the processing result is not sent to the overall control unit 39. As a result, the coordinates of the image are determined as an unprocessed area in the overall control unit 39 and are displayed on the user interface 53 to that effect. Further, in the image processing method used in the present embodiment, a defect inspection of a certain image index n requires a divided image on the wafer of index n−1 distributed immediately before that. For this reason, the area determined as the inspection unprocessed area is not only the on-wafer divided image existing in the processor elements 48, 49, 50,. Since there is no image data to be inspected and compared, the inspection cannot be executed, and the processing result cannot be sent to the overall control unit. Therefore, the overall control unit 39 determines that the region is not inspected. Will be displayed.

  Further, there is a case where a failure of the distribution destination processor elements 48, 49, 50,... 51 occurs while the image distribution control unit 32 divides the scanned image on the wafer 16. In this case, the divided image data transmission to the processor element is interrupted due to an error, and control is transferred to the next divided image data transmission. In addition, since an image that is scheduled to be processed in the processor elements 48, 49, 50,... 51 is not processed, the processing result is not sent to the overall control unit 39. As a result, the coordinates of the image are determined as an unprocessed area in the overall control unit 39 and are displayed on the user interface 53 to that effect. Further, in the image processing method used in the present embodiment, a defect inspection of a certain image index n requires a divided image on the wafer of index n−1 distributed immediately before that. Therefore, the area determined as the unprocessed area is not only the on-wafer divided image 43 that disappeared in the processor elements 48, 49, 50,. Even in the image, since there is no image data to be inspected and compared, the inspection cannot be executed, and the processing result cannot be sent to the overall control unit 39. This is displayed on the user interface 53.

  According to the present embodiment, the overall control unit 39 does not shift to the FAIL state, that is, the state in which the operation cannot be continued as a device, and continues the operation. Therefore, the number of processor elements decreases due to a failure or the like. Even in this case, the apparatus does not stop and the operation is continued. As a result, TAT is shortened, and operation costs can be reduced.

  The second embodiment will be described below. The matters described in the first embodiment and not described in the present embodiment are the same as those in the first embodiment.

  The overall control unit 39 counts the number of lines when scanning on the wafer. After the scan is completed, the image processing result of the wafer coordinates is not sent to the overall control unit 39 due to a processor element failure. In this case, the wafer coordinates are determined as unprocessed data, and a message to that effect is displayed. Here, an example in which the monitor 53 is shared with the user interface 1100 is shown.

Items displayed on the user interface 1100 will be described with reference to FIG. FIG. 5 shows an example of a screen displayed on the user interface 1100, and a field for displaying a map is provided.
In the field of the wafer map 1103 on the user interface 1100, the field for displaying the unprocessed area 1105 is displayed in a format distinguishable from the field for displaying other defects 1104 and the like.
Each of these fields monitors and displays the transfer destination processor element and the processing load state in the distribution table 40.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Further, the failure of the processor element is displayed on the user interface 1100 separately from the defect display on the substrate to be processed.

  The third embodiment will be described below. The matters described in Example 1 or 2 but not described in the present Example are the same as in Example 1 or 2.

  Status display is performed on the monitor 53 for the detected speed instructed from the detected speed setting unit 31 due to a decrease in the number of processor elements such as processor element failure. Also in this embodiment, the monitor 53 is shared with the user interface 1100. This will be described with reference to FIG. FIG. 5 shows an example of a screen displayed on the user interface 1100. A field for displaying the processing speed and a field for displaying the number of processor elements (PE) are provided. It has at least one of a field 1101 for displaying the processing speed on the user interface 1100 and a field 1102 for displaying the number of connected processor elements.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Further, the user interface 1100 displays the processing speed and the number of connected processor elements (PE).

  The fourth embodiment will be described below. The matters described in the first, second, or third embodiment but not described in the present embodiment are the same as those in the first, second, or third embodiment.

An embodiment will be described in which individual processor elements are newly connected to the image processing apparatus after the number of processing processor elements is decreased, such as processor element failure or processor element missing.
The new connection of an individual processor element is to newly connect a processor element to the semiconductor device appearance inspection apparatus and its image processing apparatus in operation and execute image processing.

This will be described with reference to FIG.
There is a method of communicating the connection status of individual processor elements to the processor status monitoring unit 38 using a signal 41. When the state of the signal line is valid, for example, from the Low state to the High state, the state monitoring circuit 1300 determines a new processor element connection and increases the total number of processor elements. For example, the state monitoring circuit 1300 means a circuit configured by, for example, hard wired.

Another embodiment will be described with reference to FIG.
For example, in a network such as the InfiniBand standard, one or more devices 1301 that collectively manage the connection status, the number of connected I / O controllers connected to the network, and the IDs of the connected I / O controllers exist on the network. To do.
The network management device 1301 is connected to the other processor elements 48 to 51 and the processor state monitoring unit 38 by the path switch 42.
When an individual processor element is newly connected to the network, the device 1301 automatically recognizes the newly connected processor element.
As described above, the connection state of the individual processor elements on the network is always managed automatically and collectively by the device 1301 that collectively manages them.

FIG. 1 shows an embodiment of the updating means of the distribution table 40 when an increase in the number of processor elements is detected by the processor element connection state management unit 38.
This is indicated by the sequence 240 in FIG.
First, the processor element new connection standby is performed in the sequence 231.
When a new connection occurs, the image distribution table is set from sequence 232 to 236.
Next, in the sequences 237 to 238, the detection speed of the detection system is reset.
Finally, in the sequence 239, these situations are displayed on the user interface.

Hereinafter, detailed operations in each sequence will be described.
After obtaining the ID value of the newly connected processor element, the processor element connection state monitoring unit 38 instructs the table setting unit 36 to add a processor element. The table setting unit 36 changes the image distribution configuration of the distribution table 40.

This will be described with reference to FIG. The ID of the newly connected processor element is 6. First, the load state field 212 in the distribution table 40 is searched, and the row of the wafer division number whose load state is 2 or more is searched.
If there is no row with a wafer division number having a load state of 2 or more, the process is terminated. Rows 217 and 219 of the divided image data index having a load state of 2 or more are found.
One of them, this time, the ID of the distribution destination processor element in the row 217 is rewritten to the ID 6 of the newly connected processor element.
Then, the rows where the IDs of the distribution destination processor elements overlap are counted and registered in the area representing the load state of the number of rows.

Since the distribution table 40 of the image distribution control unit 32 has been updated, the detection speed setting unit 31 is instructed to set the detection system speed.
The detection speed setting unit 31 searches the processing load field of the distribution table 40 to obtain the maximum processing load value.
The general control unit 39 is instructed so that the speed of the detection system becomes 1 / maximum processing load value.
In response to this, the overall control unit 39 changes the axial drive speed of the X stage 17 and the Y stage 18, changes the deflection speed of the electron beam with respect to the deflection coil 8, etc., and sets the signal capture timing of the secondary electron detector 55. change.

In this embodiment, the processing load value in the distribution table 40 is 1, and the processing speed of the image processing apparatus 54 is 1. The overall control unit is set so that the detection speed is 1.
Specifically, the xy axis direction drive speed is 1, the change speed is 1, and the signal capture timing of the secondary electron detector is 1.
The overall control unit 39 counts the number of lines when scanning on the wafer. After the scan is completed, the image processing result of the wafer coordinates is not sent to the overall control unit 39 due to a processor element failure. In this case, the wafer coordinates are determined as unprocessed data, and a message to that effect is displayed on the user interface 53.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Furthermore, the processing load value can be reduced by additionally connecting a new processor element.

  The fifth embodiment will be described below. The matters described in the first, second, or third embodiment but not described in the present embodiment are the same as those in the first, second, or third embodiment.

Another embodiment of the update contents of the information on the distribution table when the change in the number of processor elements is detected by the processor element connection state management unit will be described. This is an example of inspection device degeneration processing corresponding to a processor element failure, and is load distribution processing by changing the data width and changing the data amount distribution amount to the connected processor elements.
When the number of processor elements decreases, image width division is performed.

A sequence 1400 is shown in FIG.
First, processor element failure detection standby is performed in sequence 1402. When a failure occurs, the image distribution table is set from sequence 1403 to 1406.
Next, in the sequences 1407 to 1408, the detection speed of the detection system is reset.
Finally, in sequence 1409, these situations are displayed on the user interface.
An embodiment in which the processor connection state monitoring unit 38 detects a decrease in the number of processor elements is the same as in the first embodiment.

The update of the distribution table 40 will be described with reference to FIG.
Assume that processor element ID No. 5 has failed.
In this case, the fifth row in the column of the ID 221 of the transfer destination processor element is searched, and the row 229 corresponds. Since the line 229 is invalid, it is deleted.

Next, image division is performed on the remaining processor elements.
First, the image division coordinates 223 are changed. In this embodiment, the image division coordinates are increased by 125. The value of the image coordinate field 223 is changed from line 225 to line 228.
Next, the distribution image size is also changed. The divided image size is 125 per processor element. The value of the image size field 224 is changed from line 225 to line 228.
Finally, the processing load field 222 of each individual processor element is similarly changed from row 225 to row 228.
This is to calculate how much processing load is applied to one processor element after changing the number of processor elements, assuming that the default processing capacity after startup of the apparatus is 1, and set that value.
After sequence 1407, the detection speed change and the status display on the user interface are the same as in the embodiment.

  An example of distribution of die image data when information on the distribution table 40 of FIG. 15 is rewritten is shown in FIG. The scanned image 333 on the die 360 obtains divided images 371 to 374 by updating information on the distribution table. These divided images are stored in the image memories of the processor elements 366 to 369.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Further, by evenly allocating the processing load value to each processor element, it is possible to minimize a decrease in processing speed.

  The sixth embodiment will be described below. The matters described in the first, second, or third embodiment but not described in the present embodiment are the same as those in the first, second, or third embodiment.

An embodiment will be described in which a processor element is added to the image processing apparatus again after the number of processing processor elements has decreased, such as a processor element failure shown in the embodiment or a missing processor element.
A load distribution process is performed to change the data width and distribute the data to the connected processor elements.
When the number of processor elements increases, image width division is performed. Specifically, this changes the image division size of the die.

A sequence 1500 is shown in FIG.
First, the processor element new connection standby is performed in the sequence 1502.
When a new connection occurs, the image distribution table is set from sequence 1503 to 1505.
Next, in the sequences 1506 to 1507, the detection speed of the detection system is reset.
Finally, in sequence 1508, these situations are displayed on the user interface.

Hereinafter, detailed operations in each sequence will be described.
The processor element new connection standby is the same as in the fourth embodiment.

The update of the distribution table 40 will be described with reference to FIG. Assume that processor element ID 6 is added.
In this case, a row 1209 of the transfer destination processor element is newly added.
Next, image division setting is performed.
First, the image division coordinates 1203 are changed. In this embodiment, the image dividing coordinates are increased by 100. The value of the image coordinate field 1203 is changed from line 1205 to line 1209. Next, the distribution image size is also changed. In this embodiment, the number is 100 per processor element. The value of the image size field 1204 is changed from line 1205 to line 1209.
Finally, the processing load field 1202 of each processor element is similarly changed from row 1205 to row 1209.
This is to calculate how much processing load is applied to one processor element after changing the number of processor elements, assuming that the default processing capacity after startup of the apparatus is 1, and set the value.
After sequence 1407, the detection speed change and the status display on the user interface are the same as in the fourth embodiment.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Furthermore, since all the failed processor elements are replaced with new ones, the processing speed can be restored to the original value.

  The seventh embodiment will be described below. The matters described in the first, second, or third embodiment but not described in the present embodiment are the same as those in the first, second, or third embodiment.

An embodiment in which the number of processor elements is increased and the processing capacity of the apparatus is increased will be described.
The sequence 1500 is the same as that in the sixth embodiment.
Hereinafter, detailed operations in each sequence will be described.
The processor element new connection standby is the same as in the fourth embodiment.

The update of the distribution table 40 will be described with reference to FIG.
Assume that processor element ID No. 7 is added.
In this case, a row 1210 of the transfer destination processor element is newly added. Next, image division is performed. First, the image division coordinates 1203 are changed. In this embodiment, the image division coordinates are increased by 83. The value of the image coordinate field 1203 is changed from line 1205 to line 1210.
Next, the distribution image size is also changed. In this embodiment, since it is 83 per processor element, the value of the image size field 1204 is changed from row 1205 to row 1210.
Finally, the processing load field 1202 of each processor element is similarly changed from row 1205 to row 1210.
This is to calculate how much processing load is applied to one processor element after changing the number of processor elements, assuming that the default processing capacity after startup of the apparatus is 1, and set the value.

If the detection time is the same even if the number of processor elements is increased, the processing performance as an appearance inspection apparatus is not improved. When the number of processor elements is increased, it is necessary to create a room for increasing the detection time.
In the figure, the processing load is 1 or less. In other words, this means that the processor load value is empty. Therefore, an instruction to increase the detection speed can be issued to the detection system 1.
After sequence 1407, the detection speed change and the status display on the user interface are the same as in the fourth embodiment.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Furthermore, since the number of new processor elements exceeding the number of processor elements at this location is added, the processing speed can be made larger than the initial value.

  The eighth embodiment will be described below. The matters described in the first, second, or third embodiment but not described in the present embodiment are the same as those in the first, second, or third embodiment.

As an example of image processing corresponding to a processor element failure, an embodiment of an image processing apparatus having redundancy is shown.
In this embodiment, the distribution table 40 shown in FIG. 20 is used.
A sequence 1600 is shown in FIG.
First, processor element failure detection standby is performed in sequence 1602.
When a failure occurs, the image distribution table 40 is set from sequence 1603 to 1609.
Finally, in a sequence 1610, these situations are displayed on the user interface.
An embodiment in which the processor connection state monitoring unit 38 detects a decrease in the number of processor elements is the same as in the first embodiment.

The update of the distribution table 40 will be described with reference to FIG.
Assume that processor element ID # 3 has failed.
In this case, the third row in the column of the transfer destination processor element ID 1221 is searched, and the row 1227 corresponds. The row 1227 is invalidated.
Next, the spare processor element field 1231 is searched for a value “1”, that is, a redundant processor element.
In this embodiment, the row 1230 corresponds. From the invalidated row 1227, the values of the wafer division number field 1220, the processing load field 1222, the image coordinate field 1223, and the image size field 1224 are copied to the row 1230.
Finally, the value of the spare processor element field 1231 in the row 1230 is set to “0”, that is, a non-redundant processor element setting.
In this embodiment, since the processing capacity does not change, an instruction to change the detection speed to the detection system 1 does not occur.
As a result, even if a processor element breaks down, the apparatus does not stop and the processing performance does not deteriorate, so that redundant processing can be achieved.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Further, the processing load value can be reduced by additionally connecting a spare processor element. Further, in the case of redundant processor elements, there is an advantage that the characteristics are uniform because they are created in the same process as other processor elements. The redundant processor element can also be used as a new processor element in the sixth and seventh embodiments.

It is a schematic block diagram which shows one Example of a SEM type external appearance inspection apparatus. It is a block diagram of a processor element. It is a figure which shows the data transmission format to a processor element. It is a figure which shows the operation | movement of image distribution control. It is a user interface schematic. It is a figure which shows the degeneration process sequence at the time of the number of processor elements decreasing. It is a figure which shows one Example among the update means of the information on a distribution table. It is a figure which shows the example of distribution of die image data. It is a comparison processing time schematic diagram. It is a figure which shows one Example of a processor element connection state monitoring means. It is a figure which shows one Example of a processor element connection state monitoring means. It is a figure which shows the sequence at the time of a processor element new connection. It is a figure which shows one Example among the update means of the information on a distribution table. It is a figure which shows the degeneration process sequence at the time of the number of processor elements decreasing. It is a figure which shows one Example among the update means of the information on a distribution table. It is a figure which shows the example of distribution of die image data. It is a figure which shows the sequence at the time of the increase in the number of processor elements. It is a figure which shows one Example among the update means of the information on a distribution table. It is a figure which shows one Example among the update means of the information on a distribution table. It is a figure which shows one Example among the update means of the information on a distribution table. It is a figure which shows the redundant processing sequence at the time of the number of processor elements decreasing. It is a wafer external appearance inspection sequence flow chart It is a figure which shows an example of a wafer test | inspection start and an end position.

Explanation of symbols

1 ... Laboratory,
2 ... condenser lens,
3 ... Electron beam extraction electrode,
4 ... electron gun,
5 ... electron beam,
6 ... Blanking deflector,
7 ... Aperture,
8: Scanning deflector,
9 ... reflector,
10 ... Secondary electron detector,
11 ... secondary electrons,
12 ... ExB deflector,
13 ... Objective lens,
15 ... Sample stage,
16 ... Subject substrate,
17 ... X stage,
18 ... Y stage,
19: Reverse bias power supply,
20 ... Preamplifier,
21 ... AD converter,
22 ... Preamplifier drive power supply,
23: AD converter drive power supply,
24 ... High voltage power supply,
25... Deflection control unit,
26: Objective lens control unit,
28: Stage drive control unit,
30 ... Buffer memory,
32... Image distribution control unit,
33: Distribution setting unit,
39: Overall control unit,
40 ... distribution table,
42... Path switch,
48, 49, 50, 51, 900 ... processor elements,
52... SEM type visual inspection device,
53 ... Monitor,
54 Image processing unit
55 ... Secondary electron detector continuous image data ... 134
306, 307, 308, 309, 310 ... processor elements,
901 ... I / O controller,
902 ... Image memory 902,
903 ... Processor device,
904: Processor element ID,
800 ... ID of the destination processor element,
801: a division number on the wafer,
802: Image coordinates on the wafer,
803: Transfer image size,
804 ... wafer image data,
1700: Wafer visual inspection apparatus operation sequence flow,
1701, ..., 1714 ... Individual sequence of wafer visual inspection apparatus,
1801 ... Scan start position,
1802 ... Scan end position.

Claims (10)

A sample stage on which a substrate to be inspected is mounted, a detection unit for detecting information reflecting the surface state of the substrate to be inspected, an image processing unit including a plurality of processor elements for storing and processing the detected information, and the image processing A visual inspection apparatus comprising: a user interface unit that displays an output from a unit; and an overall control unit that controls the sample stage, the detection unit, the image processing unit, and the user interface unit,
The image processing unit includes: a processor element state monitoring unit that monitors connection states of the plurality of processor elements; an image distribution control unit that performs image division / distribution control according to the connection state of the processor elements; and A detection speed setting unit that sets the detection processing speed according to the situation of image division / distribution,
When the processor element fails,
The image distribution control unit redistributes information to be stored by the failed processor element so that the connected normal processor element stores the information, and another connected normal processor. Redistribute the elements so that they also store the information that the failed processor element was supposed to store,
The detection speed setting unit resets the detection speed in response to the redistribution,
Inspection continues at the reset speed,
An appearance inspection apparatus, wherein processor fault information is displayed on the user interface unit. The appearance inspection apparatus according to claim 1,
The visual inspection apparatus according to claim 1, wherein the processor fault information is at least one of information on a processor element fault , a processor element missing, an inspection processing speed, and a number of processor elements. The appearance inspection apparatus according to claim 1,
Wherein when the processor element has failed, further, the appearance inspection apparatus number processor elements connected without checking processing speed and the fault is characterized Rukoto displayed on the user interface. The appearance inspection apparatus according to any one of claims 1 to 3 ,
Profile processor elements improves image processing speed when newly connected, the appearance inspection apparatus characterized that you increase throughput. In the appearance inspection apparatus of claim 1 Symbol placement,
When one of the processor elements fails,
The appearance inspection apparatus, wherein the image distribution control unit subdivides and redistributes the image information so that the storage amount of the image information of all other normal processor elements connected is equal . The appearance inspection apparatus according to claim 1,
The image processing apparatus includes an unconnected processor element for reducing the storage amount of a processor element whose initial information storage amount is increased by image division / distribution of the image distribution control unit,
When the processor element state monitoring unit detects that the unconnected processor element is connected,
The image distribution control unit redistributes the information storage destination from the processor element having the increased processing load value to the newly detected processor element by storing the information of the failed processor element together. Feature visual inspection device. The appearance inspection apparatus according to claim 1,
The image processing apparatus includes an unconnected processor element for reducing the storage amount of a processor element whose initial information storage amount is increased by image division / distribution of the image distribution control unit,
When the processor element state monitoring unit detects that the unconnected processor element is connected,
The image distribution control unit subdivides and redistributes the image information so that the storage amount of the image information of all the other normal processor elements connected including the newly detected processor element is equal. An appearance inspection apparatus characterized by that. The appearance inspection apparatus according to claim 7 ,
The appearance inspection apparatus according to claim 1, wherein the number of detected new processor elements is equal to the number of failed processor elements . The appearance inspection apparatus according to claim 7 ,
An appearance inspection apparatus, wherein the number of detected new processor elements exceeds the number of failed processor elements. The appearance inspection apparatus according to any one of claims 7 to 9 ,
Before SL new shelf processor elements, the appearance inspection apparatus is characterized in that shall have redundant provided as a spare in the plurality of the processor elements.

Images