JP5464865B2 - Image display device - Google Patents

Description

  The present invention relates to an image display device.

  2. Description of the Related Art An image display device having a thin film transistor (TFT) formed of amorphous or polycrystalline silicon or the like and a current control type light emitting element such as an organic light emitting diode (OLED) in each pixel circuit is known. In general, in such an image display device, a drive method (simultaneous light emission method) in which images of each frame are displayed by light emission from all pixel circuits at the same time, or an operation of sequentially emitting light from the top to the bottom of the display panel. Is used to display a moving image (progressive method).

  In the simultaneous light emission type image display device, a plurality of scanning signal lines for supplying scanning signals to a large number of pixel circuits are provided. In general, scanning signals are supplied to a plurality of scanning signal lines by a shift register, but a shift register is not provided in a circuit that applies potentials to other wirings (power supply lines or the like). Therefore, the circuit configuration of the so-called Y driver can be simplified. However, in order to write image signals to all the pixel circuits in a limited period, it is necessary to prepare a frame buffer and increase the driving frequency of the so-called X driver. In addition, since the pixel circuits of the entire panel are repeatedly turned on and off at the same time, flicker with a flickering screen is easily seen. In addition, since a state where current flows instantaneously and a state where current does not flow are repeated for all the pixel circuits, a large-capacity power source suitable for supplying a large current is required.

  A progressive image display device generally requires a shift register for sequentially applying various signals to a plurality of pixel columns. For this reason, the Y driver is complicated and the manufacturing cost is increased. Further, the number of elements (transistors and capacitors) constituting each pixel circuit is relatively large (for example, Patent Document 1). For this reason, the configuration of each pixel circuit is complicated. However, since the potential of the image signal is applied to a plurality of pixel columns in accordance with each input timing of the image signal, a frame buffer is unnecessary and there is no need to increase the driving frequency of the X driver. In addition, a flashing image appears instantaneously on the display panel, and this band-like image is shifted from the top to the bottom of the display panel, causing flickering on the entire screen at the same time. The flicker is inconspicuous. In addition, since a current for light emission is supplied only to a part of the pixel circuits instantaneously, a power source suitable for supplying a relatively small current can be used.

  Considering the above various advantages and disadvantages, it is considered that the progressive method is more suitable for an image display apparatus having a large screen.

JP 2007-206273 A

  In a progressive-type image display device, in order to realize an operation in which a band-like image is shifted from the upper part to the lower part of the display panel, the pixel circuit lines (pixel lines) that are usually arranged in the horizontal direction are usually provided. An operation of switching a signal (driving signal) to be supplied to the pixel circuit is performed. That is, an external circuit (Y driver or the like) for applying various drive signals to each pixel line for a large number of pixel circuits arranged in the entire display panel is required.

  Here, if a plurality of pixel lines are made into a block and a signal applied to each block is made common, an output pin for outputting various signals in an external circuit (Y driver or the like) can be reduced. It is considered that the configuration can be simplified.

  However, in order to synchronize the drive timing for applying various signals to each pixel line with the horizontal synchronization signal (HSYNC), the number of pixel lines constituting the display panel and the number of so-called blanking lines corresponding to the vertical blanking period. The total number of lines (total number of lines) must be divisible by the number of pixel lines constituting each block. For example, when the number of pixel lines constituting the display panel is 480 and the number of blanking lines is 3, the number of pixel lines constituting each block can be set to 3, but it is not a divisor of 483. It was not possible to make this number.

If the number of pixel lines constituting each block is other than the divisor of 483, for example, four, for example, driving for four lines is forcibly performed in the display period for three blanking lines, and the drive signal The waveform is distorted. In the display period corresponding to the blanking line, an operation for compensating the threshold voltage _Vth of the drive transistor is performed in at least one of the pixel lines of the display panel. Therefore, the length of the period for compensating the threshold voltage V _th (V _th compensation period) differs between the specific pixel line and the other pixel lines, and the light emission luminance of the specific pixel line is the light emission of the surrounding pixel lines. A significant difference is likely to occur between brightness and adverse effects.

  SUMMARY An advantage of some aspects of the invention is that it provides a progressive image display apparatus capable of suppressing deterioration in image quality.

  In order to solve the above-described problem, an image display device according to a first aspect of the present invention includes a display unit including a plurality of pixel lines each configured by arranging a plurality of pixel circuits each including a light emitting element in one direction. And a potential setting unit that sets a potential state according to an image signal for each of the pixel circuits. Further, the image display device divides the display unit into a plurality of pixel line groups, and supplies a power supply voltage for causing each pixel circuit to emit light to each pixel circuit for each pixel line group. A temporal relationship between a voltage supply unit to be performed, a writing execution period in which the potential state is set by the potential setting unit, and a light emission period in which the power supply voltage is supplied by the voltage supply unit is expressed as the pixel line. A control unit that controls the potential setting unit and the voltage supply unit is provided so as to be different for each group.

  An image display device according to a second aspect of the present invention is the image display device according to the first aspect, wherein the number of the plurality of pixel line groups is a total number of pixel lines constituting the display unit. A time interval from the write execution period to the light emission period in each of the pixel line groups according to the order in which the plurality of pixel line groups are arranged is a number other than a divisor. The potential setting unit and the voltage supply unit are controlled so as to become longer sequentially.

  An image display device according to a third aspect of the present invention is the image display device according to the second aspect, wherein when the number of pixel line groups constituting the plurality of pixel line groups is N, There are N types of temporal relationships between the writing execution period and the light emitting period in a plurality of pixel line groups.

  An image display device according to a fourth aspect of the present invention is the image display device according to any one of the first to third aspects, wherein the control unit is synchronized with a horizontal synchronization signal related to the image signal. The potential setting unit is controlled to set the potential state according to the image signal for each of the pixel circuits, and the frequency related to the light emission period in the plurality of pixel line groups is The voltage supply unit is controlled so as to have a frequency that is a natural multiple of the frequency at which the frame is displayed on the display unit in accordance with the signal.

  An image display device according to a fifth aspect of the present invention is the image display device according to any one of the first to fourth aspects, wherein the control unit includes the potential setting unit in each of the pixel line groups. The potential setting is performed so that the writing execution period shorter than the writable period is provided in the writable period in which the potential state can be set for each of the pixel circuits according to the image signal. And the voltage supply unit are controlled.

  The image display device according to a sixth aspect of the present invention is the image display device according to the fifth aspect, in which the control unit includes the first pixel line group of the plurality of pixel line groups, A vertical blanking period and the writing execution period are provided in this order within the writable period, and in the last pixel line group of the plurality of pixel line groups, the writing execution period is included in the writable period. The potential setting unit and the voltage supply unit are controlled so that the vertical blanking period is provided in this order.

  According to the present invention, it is possible to suppress deterioration of image quality without causing distortion in the waveform of the drive signal by making the temporal relationship between the writing execution period and the light emission period different for each pixel line group. A progressive image display apparatus can be provided.

1 is a schematic diagram illustrating a schematic configuration of an image display device according to an embodiment of the present invention. It is a figure which illustrates the structure of the pixel circuit for 1 pixel which comprises an organic EL display part. It is a timing chart which shows the signal waveform at the time of making an organic EL element light-emit in a pixel circuit. It is a figure explaining operation | movement of the pixel circuit in a preparation period. It is a figure explaining operation | movement of the pixel circuit in a threshold voltage compensation period. It is a diagram illustrating the operation of a pixel circuit in an OLED initialization / C _s 2 initialization period. It is a figure explaining operation | movement of the pixel circuit in a writing / OLED initialization period. It is a figure explaining operation | movement of the pixel circuit in the light emission period. It is a figure which shows typically the structure of a panel part, and its peripheral circuit. It is a figure which shows typically the structure of a gate circuit group. It is a timing chart which shows the waveform of the potential given to a power line. It is a timing chart which shows the waveform of the electric potential given to a compensation control line. It is a timing chart which shows the waveform of the electric potential provided to a scanning line. It is a timing chart which shows the timing of a writing implementation period. It is a figure which shows the relationship between a writable period and a write implementation period.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

<1. Schematic configuration of image display device>
FIG. 1 is a diagram showing a functional configuration of an image display apparatus 1 according to an embodiment of the present invention. The image display device 1 constitutes a device (organic EL device) using light emission of an organic EL element.

  The image display device 1 mainly includes a control circuit group 2, a panel unit 3, and a power supply circuit 6. The panel unit 3 includes a dedicated driver circuit 4, an X driver circuit 5, and an organic EL display unit 30. In the image display device 1, the image signal is composed of signals relating to the three primary colors of red (R), green (G), and blue (B), and the organic EL display unit 30 emits red light. A light emitting element that emits green light and a light emitting element that emits blue light.

  The control circuit group 2 includes various circuits that control the operation of the image display device 1. Specifically, the control circuit group 2 includes circuits such as γ converters 21R, 21G, and 21B, a timing generator (TG) 22, and the like.

γ conversion unit 21R, 21G, 21B, each color value corresponding to each pixel (i.e. the gradation values) accepts D _r, D _g, the input image signal is a D _b, performs so-called gamma correction. Here, for example, the gradation values D _r , D _g , and D _{b of} the respective colors are converted into values that are raised to the power of about 2.2. Specifically, for example, a 6-bit input image signal (an image signal having a gradation value of 0 to 63) is converted into a 10-bit output image signal (an image signal having a gradation value of 0 to 1023). The converted output image signal is input to the X driver circuit 5.

The TG 22 is realized by a programmable LSI such as an FPGA (Field Programmable Gate Array), and in response to the input of the vertical synchronization signal V _sync and the horizontal synchronization signal H _sync related to the input image signal, the dedicated driver circuit 4 and X Signals for controlling the operations of the dedicated driver circuit 4 and the X driver circuit 5 are output to the driver circuit 5. In the present embodiment, the TG 22 corresponds to the “control unit” of the present invention.

  Here, the control circuit group 2 has been described as being configured by various circuits, but is not limited thereto. For example, in a control unit including a CPU, a ROM, a RAM, and the like, a function realized by the control circuit group 2 may be realized by reading and executing a program in the ROM by the CPU.

  The organic EL display unit 30 is an organic EL display (organic electroluminescence display) having a substantially rectangular outline, and includes a self-luminous light emitting element that emits light when the current flows through the organic material. That is, the organic EL display unit 30 constitutes a display unit (self-luminous display unit) including a self-luminous light emitting element.

  A large number of pixel circuits 31 are arranged in the organic EL display unit 30, and each pixel circuit 31 includes a light emitting element (here, an organic EL element). And many light emitting elements are arranged in the shape of a lattice, for example. Specifically, the organic EL display unit 30 is formed with pixel lines (pixel lines, hereinafter also referred to as “horizontal lines”) composed of a plurality of pixel circuits 31 arranged in one direction (here, the horizontal direction). Has been.

In the present embodiment, it is assumed that n (n is an arbitrary natural number) horizontal lines are arranged on the organic EL display unit 30, and an example in which n = 480 will be described below. The input image signal will be described assuming that the number of so-called blanking lines corresponding to the vertical blanking period is three. That is, in the present embodiment, the number of horizontal lines (here, 480) constituting the panel unit 3 and the number of blanking lines (here, 3) corresponding to the vertical blanking period are summed (hereinafter referred to as the number of lines). N _total ) (referred to as “total number of lines”) is 483.

Further, the organic EL display unit 30 is provided with a plurality of image signal lines L _DATA (see FIG. 2) for supplying an output image signal corresponding to the light emission luminance to each pixel circuit 31. The organic EL display unit 30 is provided with a plurality of scanning lines L _SS (see FIG. 2) that are substantially orthogonal to the plurality of image signal lines L _DATA . Here is one scanning line L _SS is provided for each horizontal line, sequentially scanning signals to the scanning lines L _SS is supplied. Note that the scanning signal is a signal that controls the timing of setting the potential related to the output image signal in each pixel circuit 31 via the image signal line _LDATA .

Further, the organic EL display unit 30 is provided with a power supply line L _VDD (see FIG. 2) for supplying a voltage necessary for light emission between both electrodes of the organic EL element OLED (see FIG. 2) included in each pixel circuit 31. ing. Further, the organic EL display unit 30 performs an operation (hereinafter referred to as “threshold voltage compensation operation”) for compensating for variations in the threshold voltage V _th of the drive transistor T _d (see FIG. 2) included in each pixel circuit 31. For this purpose, a compensation control line L _TH (see FIG. 2) for supplying a signal necessary for this purpose is provided.

The dedicated driver circuit 4 includes a power supply line driving circuit 4 _DD , a compensation control line driving circuit 4 _TH , and a scanning line driving circuit 4 _SS . Here, the power supply line driving circuit 4 _DD supplies a power supply voltage supplied from the power supply circuit 6 between both electrodes of the organic EL element OLED included in each pixel circuit 31 via the power supply line _{LVDD (} that is, the power supply line LVDD). Corresponds to a voltage supply unit). The compensation control line drive circuit 4 _TH is a circuit that supplies a signal (compensation control signal) necessary for the threshold voltage compensation operation to each compensation control line L _TH (that is, corresponds to a compensation control signal supply unit). The scanning line driving circuit 4 _SS is a circuit that supplies a scanning signal to each scanning line L _SS . A voltage is also appropriately supplied from the power supply circuit 6 to the compensation control line driving circuit 4 _TH and the scanning line driving circuit 4 _SS .

The X driver circuit 5 is a circuit (image signal line drive circuit) that is electrically connected to a plurality of image signal lines L _DATA and controls the timing of supplying an output image signal to each image signal line L _DATA .

  The power supply circuit 6 is a circuit that supplies a power supply voltage to the dedicated driver circuit 4 and the like.

<2. Configuration of pixel circuit>
FIG. 2 is a diagram illustrating the configuration of the pixel circuit 31 for one pixel that constitutes the organic EL display unit 30. As shown in FIG. 2, the pixel circuit 31 includes an organic EL element OLED, a drive transistor T _d , a threshold voltage compensation transistor T _th , a first capacitor C _S , a first switching transistor T _S , and a second capacitor C _S 2. , and is configured to include a second switching transistor T _m.

  The organic EL element OLED has a characteristic that a current flows between the anode electrode and the cathode electrode when a potential difference equal to or higher than the threshold voltage of the organic EL element OLED is applied between the anode electrode and the cathode electrode. It is an element having. Specifically, the organic EL element OLED includes an anode electrode layer and a cathode electrode layer formed of Al, Cu, Ne, Mg, Ag, ITO (Indium Tin Oxide), or an alloy thereof, and these anode electrodes. And a light emitting layer formed of an organic material such as phthalocyanine, trisaluminum complex, benzoquinolinolato, and beryllium complex between the cathode layer and the cathode electrode layer, and injected into the light emitting layer It has a function of generating light by recombination of holes and electrons.

The drive transistor _Td is a transistor that controls the light emission luminance of the organic EL element OLED. Specifically, the drive transistor _{Td functions} as a control electrode, a first electrode that functions as a drain electrode when the organic EL element OLED emits light, and a source electrode when the organic EL element OLED emits light. And the other electrode. Then, by adjusting the voltage between the gate electrode and the other electrode (so-called gate voltage), the amount of current flowing between one electrode and the other electrode of the drive transistor _Td is adjusted, so that the organic EL element OLED The light emission brightness is controlled.

Threshold voltage compensation transistor T _th is a gate voltage of the driving transistor T _d, the driving transistor T _d in by setting the voltage (threshold voltage) V _th the current starts to flow, the driving transistor between a plurality of pixel circuits 31 This transistor compensates for variations in the threshold voltage _Vth of _Td .

Here, since the threshold voltage V _th of the drive transistor T _d varies to some extent between the plurality of pixel circuits 31, there is a tendency that luminance unevenness occurs in an image displayed on the panel unit 3. Therefore, immediately before the organic EL element OLED emits light, the threshold voltage compensation transistor T _th sets the gate voltage of each drive transistor T _{d to} the threshold voltage V _th , so that the drive transistor between the plurality of pixel circuits 31 is set. The influence of variations in the threshold voltage _Vth of _Td is compensated. As a result, the occurrence of uneven brightness in the image displayed on the panel unit 3 is suppressed.

Specifically, the threshold voltage compensation transistor T _th is a driving transistor when a current can flow between the drain electrode and the source electrode of the threshold voltage compensation transistor T _th (conduction state). It has a function of electrically connecting the gate electrode of _Td and the one electrode. Then, until the potential difference between the gate electrode and the source electrode of the driving transistor T _d is the threshold voltage V _th of the driving transistor T _d, by passing a current toward the drain electrode from the gate electrode of the driving transistor T _d, The gate voltage of the drive transistor _Td is set to the threshold voltage _Vth .

The first capacitor C _S is a capacitor that holds the threshold voltage in order to hold the gate voltage of the drive transistor T _d at the threshold voltage.

The first switching transistor T _S is a transistor that controls application of a voltage (output image signal voltage) corresponding to an output image signal from the image signal line L _DATA .

The second capacitor C _S 2 is a capacitor that holds the output image signal voltage supplied from the image signal line L _DATA .

The second switching transistor _Tm has a gate electrode connected to the compensation control line _LTH , one electrode other than the gate electrode (drain electrode or source electrode) connected to one electrode of the second capacitor C _S 2, and The other electrode (source electrode or drain electrode) other than the gate electrode is connected to the other electrode of the second capacitor C _S 2.

The drive transistor T _d , the threshold voltage compensation transistor T _th , the first switching transistor T _S , and the second switching transistor T _m are configured by so-called thin film transistors, for example. In each drawing referred to below, the type (n-type or p-type) of the channel of each thin film transistor is not clearly shown, but it is either n-type or p-type. In the present embodiment, the case where each transistor is an n-type transistor will be described as an example.

The power line L _VDD supplies a predetermined voltage to the organic EL element OLED and the driving transistor _Td .

The compensation control line L _TH causes the threshold voltage compensating transistor T _th and the second switching transistor T _m to pass between a state where no current flows between the drain electrode and the source electrode (non-conductive state) and a conductive state. A compensation control signal for switching the state is supplied.

The scanning line L _SS supplies a signal for switching the first switching transistor T _S between a conductive state and a non-conductive state.

The image signal line L _DATA supplies the output image signal voltage to the second capacitor C _S 2.

In the present embodiment, as shown in FIG. 2, in order to supply a predetermined voltage to the organic EL element OLED, the organic EL element OLED is interposed between the high-potential power line _LVDD and the low-potential ground line. However, the present invention is not limited to this. For example, a configuration in which the low potential side is a power supply line and the high potential side is a ground line to be a fixed potential, or a configuration in which the potentials of both are switched may be employed.

<3. Driving Method of Pixel Circuit>
FIG. 3 is a timing chart showing a signal waveform (drive waveform) when the organic EL element OLED emits light in the pixel circuit 31. In FIG. 3, the horizontal axis indicates time, and in order from the top, (I) potential (V _dd ) applied to the power supply line L _VDD , (II) potential (V _TH ) applied to the compensation control line L _TH , The waveforms of (III) potential (V _SS ) applied to the scanning line L _SS and (IV) potential (V _DATA ) applied to the image signal line L _DATA are shown.

Here, the state in which the high potential V _gH is applied to the compensation control line L _TH corresponds to the state in which a compensation control signal is applied from the compensation control line drive circuit 4 _TH to the pixel circuit 31. Further, the state in which the high potential V _gH is applied to the scanning line L _SS corresponds to the state in which the scanning signal is applied to the pixel circuit 31 from the scanning line driving circuit 4 _SS . Further, the state where a positive potential to the image signal line L _DATA is applied corresponds to the state where the output image signal to the pixel circuit 31 from the image signal line L _DATA is applied.

In addition, FIG. 3 shows a drive waveform for causing the organic EL element OLED to emit light once. The period related to one light emission is a preparation period P1 (time t _{a to} t _b ) in time sequence, C _S / C _S 2 initialization period P2 (time t _{b to} t _c ), threshold voltage compensation period P3 (time t _{c to} t _d ), writing / OLED initialization period P4 (time t _{d to} t _e ), light emission A period P5 (time t _e ˜) is provided. In this example, the period P5 is a half period of a period (hereinafter referred to as “frame display period”) T _f in which one light emission (display of one frame) constituted by the periods P1 to P5 is performed. I will explain it as an occupancy.

Note that the potential V _DATA in the writing / OLED initialization period P4 is an arbitrary value determined by the light emission luminance of each organic EL element OLED. Therefore, in FIG. 3, mesh-like hatching is added to a range where the potential can exist. Has been. Furthermore, since the potential V _DATA in the period other than the write / OLED initialization period P4 may be an arbitrary value, it is indicated by a broken line in FIG. This arbitrary value means that the image signal line L _DATA may be set to any potential, and the degree of freedom in design or control increases. Further, since the potential V _SS in the writing / OLED initialization period P4 may be applied at any timing in the period P4, in FIG. 3, the period during which the potential can be applied is hatched.

4 to 8 are diagrams illustrating the direction of the current flowing in the pixel circuit 31 in each period when the organic EL element OLED emits light in the pixel circuit 31 with black arrows. In FIGS. 4 to 8, a portion of the pixel circuit 31 that contributes to the current flow is indicated by a thick line, and a portion that hardly contributes to the current flow is indicated by a thin line. 4 to 8, a capacity (organic EL element capacity) C _OLED inherent to the organic EL element _OLED is added.

  Hereinafter, a driving method of the pixel circuit 31 according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4 to 8 as appropriate.

○ Preparation period P1:
The operation during the preparation period P1 (hereinafter abbreviated as “period P1”) will be described with reference to FIGS. In the period P1, the power supply line L _VDD is set to a low potential (−V _p ), the compensation control line L _TH is set to a low potential (V _gL ), and the scanning line L _SS is set to a low potential (V _gL ). Note that the potential of the image signal line L _DATA is set to an arbitrary value. With this potential setting, as shown in FIG. 4, the threshold voltage compensation transistor T _th is set to the off state and the drive transistor T _d is set to the on state. As a result, a current flows through a path of the ground line → the drive transistor T _d → the organic EL element capacitance C _OLED, charge is accumulated in the organic EL element capacitance C _OLED. The reason why charges are accumulated in the organic EL element capacitor C _OLED during this period P1 is that one electrode (here, drain electrode) and the other electrode (here, source electrode) of the drive transistor T _d during the threshold voltage compensation period P3 described later. Is set to a state in which no current flows between them (that is, a state in which the potential difference between the gate electrode and the source electrode of the drive transistor _Td is equal to the threshold voltage _Vth ), the organic EL element capacitance C _{OLED is set} to the drive transistor. This is to act as a supply source of a current flowing between one electrode and the other electrode of _Td .

○ C _S / C _S 2 initialization period P2:
Next, the operation of the C _S / C _S 2 initialization period P2 (hereinafter abbreviated as “period P2”) will be described with reference to FIGS. In the period P2, the low potential (−V _p ) of the power supply line L _VDD and the low potential (V _gL ) of the scanning line L _SS are maintained, while the compensation control line L _TH is set to the high potential (V _gH ). The Further, the potential of the image signal line L _DATA is set to an arbitrary value. With this potential setting, as shown in FIG. 5, the driving transistor T _d is kept on, and the threshold voltage compensation transistor T _th is set to the on state, whereby the driving transistor T _d. The gate electrode and the one electrode are set in a state of being energized, and a part of the electric charge accumulated in the first capacitor C _S is discharged. Further, when the second switching transistor _Tm is turned on, the charge remaining in the second capacitor C _S2 is also discharged. Even if the drive transistor T _d is maintained in the on state, the potential of the power supply line L _VDD is maintained in a low potential (−V _p ) state, and thus is stored in the organic EL element capacitor C _OLED . The charge is retained.

○ Threshold voltage compensation period P3:
Next, the operation of the threshold voltage compensation period P3 (hereinafter referred to as “period P3”) will be described with reference to FIGS. In the period P3, with (in this case zero potential) power line L _VDD is a reference potential is set to a high potential of the compensation control line L _TH (V _gH) is maintained. Further, the low potential (V _gL ) of the scanning line L _SS is maintained. Note that the potential of the image signal line L _DATA is set to an arbitrary value as in the periods P1 and P2. By setting such a potential, as shown in FIG. 6, the threshold voltage compensation transistor T _th is kept on, and the potential of the gate electrode with respect to the other electrode (here, the source electrode) of the drive transistor T _d is driven. Until the threshold voltage V _th of the transistor T _d is reached, the charge accumulated in the organic EL element capacitor C _OLED is discharged, and a current flows through the path of the driving transistor T _d → ground line. Then, the potential difference between the gate electrode and the other electrode of the driving transistor T _d reaches a threshold voltage V _th of the driving transistor T _d, the driving transistor T _d is turned off. At this time, since the on-state of the second switching transistor T _m is maintained, the charge is not accumulated in the second capacitor C _S 2.

○ Write / OLED initialization period P4:
Next, the operation of the write / OLED initialization period P4 (hereinafter abbreviated as “period P4”) will be described with reference to FIGS. In the period P4, with zero potential of the power supply line L _VDD is maintained, compensation control line L _TH is set to a low potential (V _gL). The potential of the output image signal by the scanning signal and the image signal line L _DATA by the scanning line L _SS (predetermined level corresponding to the output image signal) is supplied. By setting such a potential, as shown in FIG. 7, the first switching transistor T _S is set to the on state, the current flows through the path of the first switching transistor T _S → the second capacitor C _S 2, A voltage corresponding to the output image signal is held in the two capacitors C _S 2. Further, when the output image signal voltage corresponding to the output image signal is written in the second capacitor C _S 2, the electric charge accumulated in the organic EL element capacitor C _OLED is discharged. That is, in this period P4, a process for discharging the charge accumulated in the organic EL element capacitor C _OLED (OLED initialization process) is performed together with the writing process of the output image signal voltage. In this way, in the present embodiment, the scanning line driving circuit 4 _SS corresponding to the potential setting unit and the X driver circuit 5 cooperate with each pixel circuit 31 in a potential state corresponding to the output image signal. Set up.

○ Light emission period P5:
Finally, the operation in the light emission period P5 (hereinafter, abbreviated as “period P5”) will be described with reference to FIGS. In the period P5, along with the power supply line L _VDD is set to a high potential (V _DD), a low potential of the compensation control line L _TH and (V _gL), a low potential (V _gL) of the scanning line L _SS and is maintained The Further, the potential of the image signal line L _DATA is set to an arbitrary value as in the periods P1, P2, and P3. At this time, the first capacitor C _S that holds the threshold voltage of the drive transistor T _d and the second capacitor C _S 2 that holds the voltage corresponding to the output image signal (output image signal voltage) are connected in series. The sum of voltages is applied between the gate electrode and the other electrode (here, the source electrode) of the driving transistor _Td . For this reason, as shown in FIG. 8, the drive transistor T _d is set to the on state, current flows through the path of the power line L _VDD → the organic EL element OLED → the drive transistor T _d → the ground line, and the second capacitor C _The organic EL element OLED emits light with a luminance corresponding to the output image signal voltage held in _S2 .

  By repeating such periods P1 to P5, light emission of each organic EL element OLED is repeated. Accordingly, a moving image composed of a plurality of frames corresponding to the output image signal is displayed on the panel unit 3. The panel unit 3 displays a moving image by displaying a predetermined number M (60 in this case) of frames per second. That is, the frequency at which the plurality of frames are sequentially displayed on the panel unit 3 (hereinafter referred to as “frame frequency”) is 60 Hz.

<4. Configuration of panel section and peripheral circuit>
FIG. 9 is a diagram schematically showing the configuration of the panel unit 3 and its peripheral circuits. In the present embodiment, as shown in FIG. 9, a power supply line drive circuit 4 _DD is provided along one long side of the panel unit 3, and a compensation control line drive circuit is provided along the other long side of the panel unit 3. 4 _TH and a scanning line driving circuit 4 _SS are provided. An X driver circuit 5 is provided along one short side of the panel unit 3. The compensation control line driving circuit 4 _TH , the scanning line driving circuit 4 _SS , and the X driver circuit 5 are integrally formed on the same plane as the organic EL display unit 30. That is, the panel unit 3 is configured such that the compensation control line driving circuit 4 _TH and the scanning line driving circuit 4 _SS are embedded, and the X driver circuit 5 is IC-mounted.

As described above, the organic EL display unit 30 is provided with 480 horizontal lines each including a plurality of pixel circuits 31. Then, when the output image signal according to the video in the organic EL display 30 is visually output the scanning line driving circuit 4 _SS corresponds to the 480 of each horizontal line of the organic EL display unit 30 for each scan line L _SS, in order from the upper side of the horizontal line of the organic EL display unit 30, and supplies a scan signal in a time and gradually shifted timing.

In addition, the organic EL display unit 30 has an N (here, N = 4) horizontal line group (the “pixel line group” of the present invention) in which a plurality of horizontal lines are grouped in order from the horizontal line on the upper side. ”). Specifically, 480 horizontal lines are divided into four first to fourth horizontal line groups 30 _BL1 to 30 _BL4 each including 120 horizontal lines. When the output image signal relating to the moving image is visibly output to the organic EL display unit 30, the potential (V _dd ) applied to the power supply line L _VDD and the compensation control line L _TH shown in FIG. potential (V _TH) applied to, is applied to the horizontal line group 30 _BL1 to 30 per _BL4 respectively.

Here, the configuration and operation of the power supply line driving circuit 4 _DD , the compensation control line driving circuit 4 _TH , and the scanning line driving circuit 4 _SS will be described sequentially.

<4-1. Power line drive circuit>
Power line driving circuit 4 _DD so as to correspond to each group of horizontal lines 30 _BL1 to 30 _BL4, and a pin Pn ₁ to PN ₄ for gate circuits W1~W4 and output. Each gate circuit groups W1 to W4, is supplied potential and current from the power supply circuit 6, in response to a control signal from the TG 22, the pin Pn ₁ to PN ₄ of potential and current from the power supply circuit 6 for each output _Are output to the power supply line L _{VDD of} the corresponding horizontal line groups 30 _BL1 to 30 _BL4 .

FIG. 10 is a diagram schematically showing the configuration of the gate circuit groups W1 to W4. Since the gate circuit groups W1 to W4 have the same configuration, the gate circuit group W1 corresponding to the first horizontal line group _30BL1 will be described as an example here.

  The gate circuit group W1 includes three transistors T1 to T3. The transistors T1 to T3 are configured by single-function transistors (corresponding to so-called discrete semiconductors) whose specifications are standardized. Here, an example in which each of the transistors T1 to T3 is configured by an n-type transistor will be described.

The drain electrodes of the transistors T1 to T3 are electrically connected to the power supply circuit 6. A high potential (V _DD ) is applied to the drain electrode of the transistor T1, a reference potential (zero potential) is applied to the drain electrode of the transistor T2, and a low potential (−) is applied to the drain electrode of the transistor T3. V _p ) is given. The source electrode of each transistor T1~T3 are electrically connected to pin Pn ₁ for output. Further, a control signal is applied from the TG 22 to the gate electrodes of the transistors T1 to T3. Then, any one of the three transistors T1 to T3 is set in a conductive state, so that the output pin Pn _{1 is connected} to the power supply line L _{VDD of} the first horizontal line group 30 _BL1 . Any one of a high potential (V _DD ), a reference potential (zero potential), and a low potential (−V _p ) is selectively applied.

Then, the power supply line driving circuit 4 _{DD applies} the potential (V _dd ) having the waveform shown in FIG. 3 to the power supply line L _VDD at a timing gradually shifted for each horizontal line group. In other words, the power supply line drive circuit 4 _DD corresponding to the voltage supply unit that supplies the power supply voltage supplies the organic EL display unit 30 to a plurality of horizontal line groups (specifically, the first to fourth horizontal line groups 30 _BL1 to 30 _BL1 . 30 _BL4 ), and for each horizontal line group, a power supply voltage for causing the organic EL element OLED to emit light is supplied to each pixel circuit 31.

FIG. 11 is a diagram illustrating waveforms of first to fourth power supply potentials (V _{dd1 to} V _dd4 ) _applied to the power supply lines L _VDD of the first to fourth horizontal line groups 30 _BL1 to 30 _BL4 , respectively.

As shown in FIG. 11, the waveforms of the first to fourth power supply potentials (V _{dd1 to} V _dd4 ) indicate a period (frame display period) T _f related to one light emission composed of periods P 1 to P 5. The period is sequentially shifted by a period (here, 1/4 of the frame display period _Tf ) divided by the division number N of 3 (N = 4 in this case). In FIG. 11, the start times of the period P1 of the first to fourth horizontal line groups 30 _BL1 to 30 _BL4 are indicated by times t _{a1 to} t _a4 , respectively.

In particular, the period P1 of the first group of horizontal lines 30 _BL1 starts at time _{t a1, 1/4 (T f /} 4 of frame display period T _f from the time t _a1, in particular 1/240 seconds ) period P1 of the second group of horizontal lines 30 _BL2 starts to time t _a2 to time has elapsed, the period P1 of the third horizontal line group 30 _BL3 starts at time t _a3 that has elapsed from the time t _a2 to time 1/240 seconds, The period P1 of the fourth horizontal line group 30 _BL4 starts at time t _a4 when 1/240 seconds have elapsed from the time t _a3 .

By such driving, a high potential (V _DD ) is applied to the power supply line L _VDD of two adjacent horizontal line groups at the same time. Then, two horizontal line groups in which a high potential (V _DD ) is applied to the power supply line L _VDD are sequentially shifted from the upper part to the lower part of the organic EL display unit 30. That is, the two horizontal line groups in which the organic EL elements OLED are lit are sequentially shifted from the upper part to the lower part of the organic EL display unit 30, so that the lit band is present in the panel unit 3. Then, the organic EL display unit 30 is sequentially shifted from the upper part toward the lower part.

In the panel unit 3, the frame display period _Tf is 1/60 second, and the period in which the pixel circuits 31 included in the horizontal line groups _30BL1 to _30BL4 emit light is 1/120 second.

Accordingly, the plurality of pixel circuits 31 included in the first horizontal line group 30 _BL1 and the second horizontal line group 30 _BL2 emit light for 1/240 seconds. Next, the plurality of pixel circuits 31 included in the second horizontal line group 30 _BL2 and the third horizontal line group 30 _BL3 emit light for 1/240 seconds. Next, the plurality of pixel circuits 31 included in the third horizontal line group 30 _BL3 and the fourth horizontal line group 30 _BL4 emit light for 1/240 seconds. Next, the plurality of pixel circuits 31 included in the fourth horizontal line group 30 _BL4 and the first horizontal line group 30 _BL1 emit light for 1/240 seconds. Then, by repeating such an operation, a moving image composed of a plurality of frames is visually output.

Further, in order to realize such an operation, the power line drive circuit 4 _DD is controlled by the TG 22 so as to be synchronized with the vertical synchronization signal V _sync . In particular, the frequency of the start of the emission period P5 in the power supply line L _VDD of the first to fourth horizontal line group 30 _BL1 to 30 _BL4 has become a natural number multiple of the frequency of the frame frequency. Thus, the blanking line can be divided into each horizontal line group by setting the frequency related to the start of the light emission period P5 in the power supply line _LVDD to a frequency that is a natural number multiple of the frame frequency. The “natural number” here is 4 corresponding to the division number of the panel section 3. Note that 4 is a number other than a divisor of the total number of lines.

  Such a frequency that is a natural number multiple of the frame frequency can be generated using the frame frequency and the image frequency. The image frequency is a frequency of a clock sent together with the output image signal. For a pulse having a frequency that is a natural number multiple of the frame frequency, if the number of waves of the image frequency emitted during the period of one frame can be divided by a number that is a natural number multiple of the frame frequency, In addition, it is possible to output pulses at equal intervals of the number of divisions. In addition, when the number of image frequency waves emitted during the period of one frame is not divisible by a natural multiple of the frame frequency, the remainder is dispersed in time, and the number of quotients is periodically set. By varying, it is possible to output pulses at equal intervals of a natural number substantially corresponding to the number of divisions during the period of one frame. A frequency that is a natural number multiple of the frame frequency is substantially realized by this pulse.

  Here, a specific example will be described for a case where the number of waves of the image frequency emitted during one frame period is divisible by a natural number multiple of the frame frequency. For example, when the image display is 60 frames per second, the frame frequency is 60 Hz, the horizontal line is 480 lines, the blanking line is 3 lines, and the number of clocks per line is 768, the image frequency is 60 × 483 × 768 = 22256640 Hz. It becomes. When driving a horizontal line group divided into four, 60 (frame frequency) × 4 (number of horizontal line groups) = 240 Hz is required. Here, when the image frequency is divided by 240 Hz, it is divisible by 222564040/240 = 92736. For this reason, in this case, if the image frequency is divided by 92736 and one pulse is output every time 92736 clocks of the image frequency come, the frequency of the pulse can be set to 240 Hz.

  Next, a case where the number of waves of the image frequency emitted during the period of one frame is not divisible by a natural number multiple of the frame frequency will be described with a specific example. For example, when the image display is 60 frames per second, the frame frequency is 60 Hz, the horizontal line is 480 lines, the blanking line is 3 lines, and the number of clocks per line is 769, the image frequency is 60 × 483 × 769 = 222585620 Hz. It becomes. When driving a horizontal line group divided into four, 60 (frame frequency) × 4 (number of horizontal line groups) = 240 Hz is required. Here, when the image frequency is divided by 240 Hz, 2228560/240 = 92856 is too much, which is not divisible. Therefore, the number of clocks is distributed to the four divided horizontal line groups, for example, 92856, 92857, 92857, and 92857 with the remainder 3 distributed, and a pulse is generated each time the number of clocks of the distributed image frequency is generated. If one is output, the frequency of the pulse can be about 240 Hz. The 240 Hz is handled as a frequency that is a natural number multiple of the frame frequency.

By such an operation, the state where the organic EL elements OLED included in the two horizontal line groups (that is, 240 horizontal lines) are lit is maintained during the moving image display. Therefore, the current output from the power supply line driving circuit 4 _DD tends not to change with time. Therefore, the current supplied from the power supply circuit 6 to the power supply line drive circuit 4 _DD is made uniform, and the power supply circuit 6 and the power supply line drive circuit 4 _DD can be easily designed.

<4-2. Compensation control line drive circuit>
The compensation control line drive circuit 4 _TH is provided with a shift register and the like, and applies the potential (V _TH ) of the waveform shown in FIG. 3 to the compensation control line at a timing gradually shifted for each horizontal line group. _Give to L _TH . Specifically, the compensation control line driving circuit 4 _TH divides the organic EL display unit 30 into first to fourth horizontal line groups 30 _BL1 to 30 _BL4 , and for each pixel circuit 31 for each horizontal line group. Supply compensation control signal.

FIG. 12 is a diagram illustrating waveforms of first to fourth compensation control line potentials (V _{TH1 to} V _TH4 ) applied to the compensation control lines L _TH of the first to fourth horizontal line groups 30 _BL1 to 30 _BL4 , respectively. .

As shown in FIG. 12, the waveforms of the first to fourth compensation control line potentials (V _{TH1 to} V _TH4 ) indicate a period (frame display period) T _f related to one light emission constituted by periods P 1 to P 5. The period is shifted sequentially by a period (here, 1/240 seconds) divided by 4 which is the division number of the panel unit 3. Then, in FIG. 12, the start time of the period P2 in the fourth horizontal line group 30 _BL1 to 30 _BL4 is shown at time t _b1 ~t _b4, period in the fourth horizontal line group 30 _BL1 to 30 _BL4 P3 end time of the is shown at time t _d1 ~t _d4.

In particular, the period P2 of the first horizontal line group 30 _BL1 starts at time t _b1, the period P2 of the second horizontal line group 30 _BL2 starts at time t _b2 has elapsed from the time t _b1 1/240 seconds , the time t from _b2 to time t _b3 has elapsed 1/240 seconds period P2 of the third horizontal line group 30 _BL3 starts, the fourth group of horizontal lines at time t _b4 that has elapsed from the time t _b3 1/240 seconds A period P2 of 30 _BL4 starts. Also, the period P3 of the first horizontal line group 30 _BL1 is completed at time t _d1, the period P3 of the second horizontal line group 30 _BL2 is completed at time t _d2 has elapsed from the time t _d1 1/240 seconds, the The period P3 of the third horizontal line group 30 _BL3 ends at time t _d3 when 1/240 second has elapsed from time t _d2 , and the fourth horizontal line group 30 _{BL4 at} time t _d4 after 1/240 second has elapsed from time t _d3. This period P3 ends.

By such driving, a high potential (V _gH ) is applied to the compensation control line L _TH of two adjacent horizontal line groups at the same time. Then, two horizontal line groups in which a high potential (V _gH ) is applied to the compensation control line L _TH are sequentially shifted from the upper part to the lower part of the organic EL display unit 30. Then, by repeating such an operation, a moving image composed of a plurality of frames is visually output.

In order to realize such an operation, the compensation control line drive circuit 4 _TH is controlled by the TG 22 so as to be synchronized with the vertical synchronization signal V _sync . In particular, the frequency of the termination and the start and duration P3 of periods P2 in the compensation control line L _TH of the first to fourth horizontal line group 30 _BL1 to 30 _BL4 has a frequency of four times the frame frequency.

<4-3. Scan Line Drive Circuit>
The scanning line driving circuit 4 _SS is configured to include a shift register and the like, and applies a potential (V _SS ) to the scanning line L _SS for each horizontal line in accordance with a clock signal from the TG 22. Specifically, a scanning signal is sequentially applied to each horizontal line from the upper part to the lower part of the organic EL display unit 30.

Figure 13 is a timing chart showing one imparting the signal waveform to the scanning lines L _SS included in the group of horizontal lines (the driving waveform) when emit light organic EL element OLED in the pixel circuit 31. Specifically, the timing chart shown in FIG. 13, the timing chart shown in FIG. 3, is applied against the 120 scanning lines L _SS included in each horizontal line group 30 _BL1 to 30 _BL4 scanning It is the timing chart which specified the signal waveform of the signal.

As shown in Figure 13, in each horizontal line group 30 _BL1 to 30 _BL4, in the period P4 (time t _d ~t _e), successively with respect to 120 scanning lines L _SS included in one horizontal line groups Is provided with a scanning signal.

In order to realize such an operation, the operation of the scanning line driving circuit 4 _SS is controlled by the TG 22 so as to be synchronized with both the vertical synchronization signal V _sync and the horizontal synchronization signal H _sync . Specifically, in synchronization with the horizontal synchronization signal H _sync related to the input image signal, the scanning line driving circuit 4 _SS sets the potential state corresponding to the output image signal for each pixel circuit 31 of each horizontal line. To be controlled. In the image display device 1, since the total number n _total including blanking lines is 483, the frequency related to the output of the scanning signal from the scanning line driving circuit 4 _SS is 28980 (= M × n _total = 60 × 483) Hz. From another point of view, 483 clock signals are applied from the TG 22 to the scanning line driving circuit 4 _{SS in} the frame display period T _f (1/60 second).

<5. Timing of writing period>
For each horizontal line group 30 _BL1 to 30 _BL4, period P4 in response to application of a scanning signal from the scanning line L _SS, corresponding to the output image signal to each pixel circuit 31 from the image signal line L _DATA This is a period during which the potential state can be set (hereinafter referred to as a “writable period”). A part of the period included in the period P4 is a period in which the potential state is set for each pixel circuit 31 in accordance with the output image signal (hereinafter referred to as a “writing execution period”).

The TG 22 corresponding to the control unit controls the power supply line driving circuit 4 _DD , the compensation control line driving circuit 4 _TH , the scanning line driving circuit 4 _SS , and the X driver circuit 5, so that the writing execution period and the period P 5 The temporal relationship is made different for each horizontal line group.

FIG. 14 is a timing chart showing the timing of the writing execution period. Specifically, in FIG. 14, in order from the top, (i) the first power supply potential V _{dd1 applied} to the power supply line L _VDD of the first horizontal line group 30 _BL1 , and (ii) the second horizontal line group 30 _{BL2 respectively.} Second power supply potential V _{dd2 applied} to each power supply line L _VDD , (iii) third power supply potential V _{dd3 applied to} power supply line L _VDD of the third horizontal line group 30 _BL3 , and (iv) fourth horizontal power supply Each waveform of the fourth power supply potential V _{dd4 applied} to the power supply line L _VDD of the line group 30 _BL4 is shown. In FIG. 14, the waveforms of the first to fourth power supply potentials V _{dd1 to} V _{dd4 applied} to the horizontal line groups 30 _BL1 to 30 _BL4 are shown for two periods (2T _f ).

Further, in FIG. 14, in each horizontal line group 30 _BL1 to 30 per _BL4, period P1 to P5, and the fourth write Period P _w1 to P _w4 are shown. The first writing execution period P _w1 is a writing execution period in the first horizontal line group 30 _BL1 , the second writing execution period P _w2 is a writing execution period in the second horizontal line group 30 _BL2 , and the third The write execution period P _w3 is a write execution period in the third horizontal line group 30 _BL3 , and the fourth write execution period P _w4 is a write execution period in the fourth horizontal line group 30 _BL4 .

In FIG. 14, in the first to fourth horizontal line groups 30 _BL1 to 30 _BL4, times when the period P1 is sequentially started are indicated by times t _{a1 to} t _a8 . Specifically, the time when the period P1 is started in the first horizontal line group 30 _BL1 is indicated by times t _a1 and t _a5 , and the time when the period P1 is started in the second horizontal line group 30 _BL2 is time t _{The time} indicated by _a2 and t _a6 and the time when the period P1 starts in the third horizontal line group 30 _BL3 is indicated by time t _a3 and t _a7 , and the time when the period P1 starts in the fourth horizontal line group 30 _{BL4 Are} shown at times t _a4 and t _a8 .

As described above, the period P5 related to the first horizontal line group 30 _BL1 , the period P5 related to the second horizontal line group 30 _BL2 , the period P5 related to the third horizontal line group 30 _BL3 , and the fourth horizontal line group 30. _A period P5 related to _BL4 occurs in this order with a shift of 1/240 seconds. That is, the lighting states in the first to fourth horizontal line groups 30 _BL1 to 30 _BL4 are switched at a frequency of 240 Hz.

Further, as shown in FIG. 14, the first writing execution period P _w1 related to the first horizontal line group 30 _BL1 , the second writing execution period P _w2 related to the second horizontal line group 30 _BL2 , and the third horizontal line The third writing execution period P _w3 related to the group 30 _BL3 and the fourth writing execution period P _w4 related to the fourth horizontal line group 30 _BL4 are successively generated in this order. Then, the first to fourth writing execution periods P _{w1 to} P _w4 are repeated.

Specifically, when the first write execution period P _w1 ends, the second write execution period P _w2 starts, and when the second write execution period P _w2 ends, the third write execution period P _w3 starts, When the write execution period P _w3 ends, the fourth write execution period P _w4 starts. When the vertical blanking period P _b corresponding to three blanking lines has elapsed, the next first writing execution period P _w1 is started. In such a manner, the first to fourth writing execution periods P _{w1 to} P _w4 are repeated. Each writing execution period P _{w1 to} P _w4 corresponds to a period of 120/483 of the frame display period T _f .

Incidentally, as described above, 483 clock signals are applied from the TG 22 to the scanning line driving circuit 4 _SS in the frame display period T _f (1/60 seconds). In each writing execution period P _{w1 to} P _w4 , 120 clock signals are applied from the TG 22 to the scanning line driving circuit 4 _SS . On the other hand, the writable period P4 is a period including a period in which 123 clock signals are applied from the TG 22 to the scanning line driving circuit 4 _SS .

Further, before the write period P4 of the first horizontal line group 30 _BL1 is completed, the writing period P4 of the second group of horizontal lines 30 _BL2 is started. The writable period P4 related to the third horizontal line group _30BL3 is started before the writable period P4 related to the second horizontal line group _30BL2 ends. Further, the writable period P4 related to the fourth horizontal line group 30 _BL4 is started before the writable period P4 related to the third horizontal line group 30 _BL3 ends. Then, before the write period P4 of the fourth horizontal line group 30 _BL4 is completed, the writing period P4 of the following first group of horizontal lines of 30 _BL1 is started.

Therefore, under the control of the TG 22, write execution periods P _{w1 to} P _w4 that are shorter than the write enable period P4 are provided within the write enable period P4. Control is performed so that the temporal relationship between the writable period P4 and the write execution period differs for each horizontal line group.

FIG. 15 is a diagram focusing on the relationship between the first to fourth write execution periods P _{w1 to} P _w4 with respect to the write enable period P4.

As shown in FIGS. 14 and 15, in the writable period P4, the period from the TG 22 to the fourth to 123rd clock signal applied to the scanning line driving circuit 4 _SS corresponds to the first write execution period P _w1 . To do. Further, in the writable period P4, a period during which the third to 122th clock signal is applied from the TG 22 to the scanning line driving circuit 4 _SS corresponds to the second writing execution period P _w2 . Further, in the writable period P4, a period during which the second to 121st clock signal is applied from the TG 22 to the scanning line driving circuit 4 _SS corresponds to the third writing execution period P _w3 . Further, in the writable period P4, a period in which the first to 120th clock signals are applied from the TG 22 to the scanning line driving circuit 4 _SS corresponds to the fourth write execution period P _w4 .

From another perspective, the writing period P4 of the first horizontal line group 30 _BL1, when the vertical blanking period P _b of the first three lines has elapsed, the first write implementation period P _w1 is started The In other words, in the first first horizontal line group 30 _BL1 among the first to fourth horizontal line groups 30 _BL1 to 30 _BL4 , the period corresponding to the vertical blanking period P _b and the first writing execution in the writable period P4. Periods P _w1 are provided in this order.

Further, in the writable period P4 related to the second horizontal line group 30 _BL2 , a period in which the first, second clock signal and the last 123rd clock signal are applied from the TG 22 to the scanning line driving circuit 4 _SS . is not performed write processing of the output image signal voltage in P _21, P _22.

In the writable period P4 related to the third horizontal line group 30 _BL3 , the first clock signal and the last 122 and 123th clock signals are applied from the TG 22 to the scanning line driving circuit 4 _SS . In P ₃₁ and P ₃₂ , the output image signal voltage writing process is not performed.

Further, in the writing period P4 of the fourth horizontal line group 30 _BL4, in the vertical blanking period P _b of 121-123 th clock signal the end it is applied to the scanning line driving circuit 4 _SS from TG22 output The image signal voltage writing process is not performed. That is, at the end of the fourth horizontal line group 30 _BL4 of the first to fourth horizontal line group 30 _BL1 to 30 _BL4, a fourth write implementation period P _w4 in the write period in the P4, in the vertical blanking interval P _b Corresponding periods are provided in this order.

Thus, the temporal relationship between the light emitting period P5 and write Period P _w1 to P _w4 in each horizontal line group 30 _BL1 to 30 _BL4 becomes four.

More From another point of view, from the top of the panel section 3 in accordance with the first to fourth order horizontal line group 30 _BL1 to 30 _BL4 are arranged sequentially toward the bottom, each group of horizontal lines 30 _BL1 to 30 _The time interval from the writing execution period P _{w1 to} P _w4 to the light emission period P5 in _BL4 is sequentially increased.

As described above, in the image display device 1 according to the embodiment of the present invention, the temporal relationship between the write execution periods P _{w1 to} P _w4 and the light emission period P5 is changed for each of the horizontal line groups 30 _BL1 to 30 _BL4 . . As a result, it is possible to increase the number of horizontal lines that are lit at the same timing without causing distortion in the waveform of the drive signal. Accordingly, it is possible to provide a progressive type image display apparatus capable of increasing the number of horizontal lines that are turned on at the same timing while suppressing deterioration in image quality.

In addition, the number of horizontal lines constituting each horizontal line group is as large as 120. For this reason, the types of waveforms of the potential (V _dd ) to be output from the dedicated driver circuit 4 to the power supply line L _VDD are reduced, and the number of output pins can be reduced. For this reason, resource saving and cost reduction in the manufacture of the dedicated driver circuit 4 can be achieved.

Further, by reducing the number of output pins, at least a part of the dedicated driver circuit 4 is not composed of an IC transistor or the like, and a single-function transistor whose specifications are standardized (corresponding to a so-called discrete semiconductor) Can be easily configured. Specifically, the power supply line drive circuit 4 _DD constituting the dedicated driver circuit 4 can be formed using general-purpose components. Note that control of the power supply line drive circuit 4 _DD can be easily performed by changing programming in the FPGA that realizes the TG 22, and the degree of freedom in controlling the potential (V _dd ) output to the power supply line L _VDD is increased. Therefore, the power supply line driving circuit 4 _DD having the same configuration can be applied to panel portions having different specifications.

<6. Modification>
For example, in the embodiment described above, the panel unit 3 is divided into the four horizontal line groups 30 _BL1 to 30 _BL4 , but is not limited thereto. For example, the number of horizontal line groups may be a number other than a divisor of the total number of lines. If the number of divisions of the panel unit 3 is N, which is a natural number other than a divisor of the total number of lines, the temporal relationship between the light emission period P5 and the writing execution period in a plurality of horizontal line groups becomes N types. . Then, a period in which no writing process is performed in each writable period P4 may be a period in which N−1 clock signals are applied from the TG 22 to the scanning line driving circuit.

  In the above embodiment, the number of horizontal lines constituting each horizontal line group is 120. However, the present invention is not limited to this. For example, the number of horizontal lines constituting each horizontal line group may be 10 or more. However, when the number of horizontal lines constituting each horizontal line group decreases, the number of divisions N of the panel portion increases. In each writable period P4, the period during which the writing process is not performed becomes long, and as a result, the number of blanking lines needs to be increased. From this point of view, it is desirable to increase the number of horizontal lines constituting each horizontal line group as much as possible and reduce the division number N.

In the above embodiment, the write execution periods P _{w1 to} P _w4 shorter than the write enable period P4 are provided in the write enable period P4. However, the present invention is not limited to this. For example, by changing various lengths of various processing periods provided before and after the writing execution periods P _{w1 to} P _w4 , the temporal relationship between the writing execution period and the period P5 is made different for each horizontal line group. Anyway. As a method of changing the length of the period before the writing execution periods P _{w1 to} P _w4 , for example, a method of changing the length of the periods P1, P2, etc. can be considered. In addition, as a method of changing the length of the period after the writing execution periods P _{w1 to} P _w4 , for example, a method of changing the length of the period by providing a period for performing other processing is conceivable.

In the above embodiment, the timing of the periods P1 to P5 is controlled at 240 Hz, which is a natural number multiple of the frame frequency, but is not limited thereto. For example, one or more of the periods P2 to P4 are used as the horizontal synchronization signal H _sync by a method such as synchronizing the driving of the compensation control line drive circuit 4 _TH constituting the dedicated driver circuit 4 with the horizontal synchronization signal H _sync . It may be started at a synchronized timing.

DESCRIPTION OF SYMBOLS 1 Image display apparatus 2 Control circuit group 3 Panel part 4 Dedicated driver circuit 4 _DD power supply line drive circuit 4 _TH compensation control line drive circuit 4 _SS scanning line drive circuit 5 X driver circuit 21R, 21G, 21B gamma conversion part 22 Timing generator 30 the organic EL display unit 30 _BL1 to 30 _BL4 first to fourth horizontal line group P4 writing period P _b vertical blanking period P _w1 to P _w4 first to fourth write period

Claims (6)

A display unit composed of a plurality of pixel lines each configured by arranging a plurality of pixel circuits each including a light emitting element in one direction;
A potential setting unit configured to set a potential state according to an image signal for each of the pixel circuits;
A voltage supply unit configured to divide the display unit into a plurality of pixel line groups and supply a power supply voltage for causing each of the pixel circuits to emit light for each pixel line group;
A temporal relationship between a writing execution period in which the potential state is set by the potential setting unit and a light emission period in which the power supply voltage is supplied by the voltage supply unit is made different for each pixel line group. A control unit for controlling the potential setting unit and the voltage supply unit;
In each of the pixel line groups, a time period between a writable period during which the potential setting unit can set a potential state in accordance with the image signal by the potential setting unit and the writing execution period. The relationship is controlled differently ,
The voltage supply unit simultaneously supplies the same power supply voltage to each power supply line forming one pixel line group, and supplies a high potential (V _DD ) to a power supply line (L _VDD ) forming a certain pixel line group. Unlike time and another power supply line to form a pixel line group (L _VDD) to begin to supply the high potential (V _DD) time to start the high potential (V _DD) is a predetermined period of time, two adjacent pixels an image display device comprising Rukoto simultaneously supplied to the respective power supply line to form a line group (L _VDD).
The image display device according to claim 1,
The number of the plurality of pixel line groups is a number other than a divisor of the total number of pixel lines constituting the display unit,
The control unit is
In accordance with the order in which the plurality of pixel line groups are arranged, the potential setting unit and the voltage are set so that the time interval from the writing execution period to the light emission period in each pixel line group is sequentially increased. An image display device that controls a supply unit.
The image display device according to claim 2,
When the number of pixel line groups constituting the plurality of pixel line groups is N, the temporal relationship between the writing execution period and the light emission period in the plurality of pixel line groups is N types. A characteristic image display device.
The image display device according to any one of claims 1 to 3, wherein
The control unit is
Controlling the potential setting unit so as to set the potential state according to the image signal for each of the pixel circuits in synchronization with a horizontal synchronization signal related to the image signal,
Controlling the voltage supply unit such that a frequency related to the light emission period in the plurality of pixel line groups is a natural number multiple of a frequency at which a frame is displayed on the display unit in accordance with the image signal. An image display device characterized by the above.
The image display device according to any one of claims 1 to 4, wherein:
The control unit is
The image display device, wherein the potential setting unit and the voltage supply unit are controlled so that the writing execution period shorter than the writable period is provided within the writable period.
The image display device according to claim 5,
The control unit is
In the first pixel line group of the plurality of pixel line groups, a vertical blanking period and the writing execution period are provided in this order within the writable period, and among the plurality of pixel line groups, In the last pixel line group, the potential setting unit and the voltage supply unit are controlled so that the writing execution period and the vertical blanking period are provided in this order within the writable period. An image display device.

Images