JP5462810B2 - Switching power supply device and switching power supply system using the same - Google Patents

Description

  The present invention relates to a switching power supply device having a function of performing a synchronous operation by connecting a plurality of units, and a switching power supply system using the same.

  When a power supply system is configured using a plurality of switching power supply devices, there is a problem that beat noise having a frequency that is a difference between switching frequencies of the switching power supply devices is generated in the output. For example, when an input voltage is supplied from one input power source to two switching power supply devices, the input ends of each other are connected, and the control systems of the main switching elements interfere with each other through the input ends. Even if the two switching frequencies are both designed with a central value of 400 kHz, in reality, they vary to some extent due to individual differences in the characteristics of internal components (for example, a width of about 10%). Low frequency beat noise with ripple voltage below kHz is generated. In order to reduce this low-frequency beat noise, a large low-pass filter with a low pole frequency must be provided, which hinders miniaturization and cost reduction of the switching power supply device and power supply system. Further, when the low frequency beat noise becomes an audible frequency band (about 20 Hz to 20 kHz), noise may be generated due to the vibration of structures such as circuit components.

  In order to prevent the above problems, conventionally, the control systems of a plurality of switching power supply units constituting the power supply system are operated in synchronization by a predetermined method to optimize the relationship between the switching frequencies, and the mutual interference of the control systems. Techniques have been proposed that try to suppress the occurrence of beat noise due to. For example, as disclosed in Patent Document 1, there is a power supply device including a plurality of switching power supplies connected to each other and signal generation means for centrally controlling the switching frequency of each switching power supply. The signal generation means of this power supply apparatus includes an oscillator that generates an oscillation signal obtained by multiplying a reference frequency by a (a is a natural number), and an oscillation multiple of the reference frequency by dividing the oscillation signal of the oscillator by b (b is a natural number). A frequency divider for generating a frequency-divided signal having a frequency and a control unit that is equipped with a CPU and controls the oscillator and the frequency divider. The frequency of the frequency-divided signal generated by the frequency divider becomes the switching frequency of the switching power supply as it is. Therefore, frequency dividers b (b1, b2,...) Corresponding to each switching power supply are assigned to the frequency dividers, and frequency dividing signals based on the frequency dividing numbers b are individually generated and handled. Output to each switching power supply.

  For example, when the power supply apparatus is composed of four switching power supplies and each switching frequency is set to 300 k, 300 k, 400 k, and 500 kHz, the reference frequency of the oscillator of the signal generating means is set to 300 kHz, and the multiplier a is set to 20. The frequency dividing number b of the frequency divider is set to 20, 20, 15, 12 respectively. In this power supply apparatus, since the switching frequency of each switching power supply is determined based on a common reference frequency, the two units whose switching frequencies are to be set to 300 kHz almost exactly match each other. Low frequency beat noise due to is not generated. Further, looking at the relationship with other switching power supplies, there is a difference of 100 k or 200 kHz in each switching frequency, so it is considered that beat noise of 100 k or 200 kHz occurs. However, with this beat noise, since it is a high frequency close to the switching frequency, it can be reduced even with a small low-pass filter.

JP 2008-118737 A

  In the case of the power supply device of Patent Document 1, one predetermined signal generating means must be provided regardless of the number of switching power supplies to be used. For example, when there is a signal generating means equipped with a multi-output type frequency divider capable of synchronously operating seven switching power supplies, the use of a power supply device composed of one or two switching power supplies can reduce costs and It becomes excessive in terms of performance. Conversely, even if there is a signal generating means capable of synchronously operating the three switching power supplies, the synchronous operation of the seven switching power supply devices cannot be performed. As described above, the power supply device of Patent Document 1 has a problem that it lacks versatility because the configuration of the signal generating means must be changed according to the number of switching power supplies to be used.

  In addition, since this power supply device transmits individual frequency-divided signals from one frequency divider to each switching power supply, wiring that connects each switching power supply and signal generating means in a one-to-one relationship is required. . For example, when an on-board type switching power supply is mounted on a single board substrate to configure a power supply device, each switching power supply is mounted on the board substrate at a predetermined interval, and is limited on the board substrate. Since the power lines and various signal lines are wired in the space, it becomes more difficult to perform frequency-divided signal wiring as the number of switching power supplies increases. In addition, there is a problem that the wiring pattern to the switching power supply located at a position away from the signal generating means becomes long and is easily affected by external noise.

  In order to solve this wiring problem, for example, a part of the circuit configuration of the power supply device of Patent Document 1 is reviewed, and instead of the multi-output type frequency divider provided in the signal generating means, each switching power supply is individually provided. An output type frequency divider is provided, and the oscillation signal (one type of signal) of the oscillator in the signal generating means is distributed to each frequency divider, and each frequency divider generates a frequency-divided signal based on a specific frequency division number b. A method of making it possible is conceivable. With such a configuration, a simple connection such as connecting the signal generating means and each switching power source with a single wiring pattern is possible, and wiring can be performed relatively easily. However, the signal passing through the wiring pattern from the signal generating means to the switching power supply is replaced with the oscillation signal of the oscillator having a very high frequency compared with the switching frequency from the divided signal corresponding to the switching frequency. Therefore, it is likely to be affected by the impedance of the wiring pattern, and there is a possibility that a new problem will occur.

  For example, in the power supply apparatus using the four switching power supplies described above, since the switching frequencies are 300 k, 300 k, 400 k, and 500 kHz, the oscillation signal of the oscillator is set to 6 MHz corresponding to the least common multiple. If there is a situation where one of the switching frequencies is changed and the four switching frequencies are to be set to 300 k, 300 k, 400 k, and 550 kHz, the oscillation signal of the oscillator is a very high frequency of 13.2 MHz corresponding to the least common multiple thereof. Will be set to. When such a high-frequency oscillation signal is transmitted through a long wiring pattern, the signal is likely to be attenuated due to the influence of wiring inductance, capacitance, and the like. Therefore, even in the switching power supply device farthest from the signal generation circuit, the oscillator output is made extremely low impedance, the oscillation signal is increased in power, etc. so that the oscillation signal is reliably transmitted through a long wiring pattern. New measures are needed. In addition, the switching frequency is an important parameter for achieving a well-balanced demand for reducing the size of magnetic components and smoothing filters inside the switching power supply and reducing the loss of power components such as the main switching element. If a certain restriction is provided on the selection of the switching frequency in order to suppress the signal to a low frequency, there is a possibility that the performance of the switching power supply and the power supply device as a whole is lowered.

  The present invention has been made in view of the above-mentioned background art, and has a function of synchronous operation for preventing the occurrence of low-frequency beat noise, and a switching power supply device having versatility that can correspond to various power supply system forms. And it aims at providing the switching power supply system using the same.

  The present invention includes a converter circuit that converts an input voltage into a DC output voltage by a switching operation of the main switching element and outputs the output voltage, a main switching element control circuit that drives the main switching element, and performs predetermined digital arithmetic processing A CPU that regulates the ON timing of the main switching element by the main switching element control circuit, an operation mode setting signal input terminal to which an operation mode setting signal is input from the outside, and a synchronous clock signal input from which an external clock signal can be input An oscillation circuit that outputs an oscillation clock signal of a predetermined frequency, and a signal from the synchronous clock signal input terminal and the oscillation clock circuit based on a selection command from the CPU by setting the operation mode setting signal input terminal. Select and output one of the signals A selection circuit, a frequency multiplication circuit for outputting a system clock signal obtained by multiplying any one of the signals output from the selection circuit by a multiplication number n (n is a natural number), and the system clock signal output from the frequency multiplication circuit A synchronous operation control circuit provided with a first frequency dividing circuit that generates a drive clock signal divided by a frequency division number m (m is a natural number) and outputs the drive clock signal to the main switching element control circuit It is a switching power supply device.

  Further, the frequency multiplication circuit is configured using a PLL (Phase Locked Loop) circuit.

The present invention also includes a plurality of the switching power supply devices, wherein the plurality of switching power supply devices are connected with the same multiplication factor n, and the plurality of switching power supply devices are connected to one master power supply. The master power supply divides the system clock signal into its own synchronous operation control circuit by a frequency division number n which is a natural number equal to the multiplication number n. A second frequency dividing circuit for generating a synchronized clock signal and a synchronizing clock signal output terminal for outputting the synchronizing clock signal to the outside; and the operation mode setting signal input terminal receives the oscillation from the selection circuit. An operation mode setting signal for outputting a clock signal is input, and the slave power supply is connected to the operation mode setting signal input terminal. The operation mode setting signal for outputting the synchronous clock signal is input from a circuit, and the synchronous clock signal synchronized with the oscillation clock signal of the master power supply is input to its own synchronous clock signal input terminal It is a power supply system.

  Provided in each synchronous operation control circuit of the master power supply and the slave power supply, provided with an activation control terminal for transmitting to the slave power supply that the master power supply has been activated by interconnection, the master power supply of the master power supply The synchronous operation control circuit outputs a start signal indicating that the main switching element of the own power supply is turned on when the input power source is turned on via the start control terminal of the self operation, and the synchronous operation control circuit of the slave power supply Is a switching power supply system that starts the operation of its own main switching element when the start signal of the master power supply is input via its own start control terminal.

Further, the master power supply and the slave power supply to which the frequency division number m equal to each other is used, the input terminals of the converter circuits are connected in parallel, and the synchronous operation control circuit of the master power supply is A signal is output through its own start control terminal, and the on-timing phase of the main switching element with respect to the on-timing of the main switching element of the master power supply is set in the synchronous operation control circuit of the slave power supply. A phase setting signal input terminal to which a phase setting signal for external input is provided, and the CPU of the slave power supply receives the phase setting signal through the phase setting signal input terminal and outputs the phase setting signal to the phase setting signal. A drive control signal for realizing the prescribed phase is output to the first frequency divider circuit.

The master power supply and the slave power supply each generate a synchronous clock signal obtained by dividing the system clock signal by a frequency division number n which is a natural number equal to the multiplication number n in each synchronous operation control circuit. And a synchronous clock signal output terminal that enables external output of the synchronous clock signal, and the CPU of the slave power supply outputs the synchronous clock signal from its selection circuit. The switching power supply system stops the frequency dividing operation of the second frequency dividing circuit when receiving the signal.

  Further, some of the plurality of slave power supplies have their own synchronous clock signal input terminal connected to the synchronous clock signal output terminal of the master power supply, and the synchronization of the some slave power supplies. A clock signal output terminal is connected to a synchronous clock signal input terminal of a part of the slave power supply other than the slave power supply, and relays the synchronous clock signal output from the master power supply. A switching power supply system may be used.

  The CPU of the slave power supply excluding the slave power supply that relays the synchronous clock signal from the master power supply receives each operation mode setting signal to output the synchronous clock signal from its selection circuit. It is preferable to stop the calculation operation of the second frequency dividing circuit.

  The switching power supply device of the present invention can not only perform a synchronous operation by connecting a plurality of the power supply devices to configure a power supply system, but also can use the power supply device alone. There is no need to provide a centralized control device such as the signal generating means of one power supply device outside.

  In addition, even when a power supply system is configured using a plurality of switching power supply devices, it is possible to prevent the occurrence of low-frequency beat noise, and wiring that interconnects the power supply devices for synchronous operation and startup control. It can be as short as possible. Furthermore, the synchronous clock signal for synchronous operation transmitted and received between the power supply devices can be fixed in synchronization with a predetermined frequency that can be easily handled, and the influence of the impedance of the wiring can be minimized. Similarly, for the signal for controlling the mode setting of each power supply device and the timing for starting the switching operation, a signal for switching between “high level” and “low level” can be used, and the setting is easy and the wiring is possible. It can be made to be hardly affected by the impedance of the.

  Furthermore, in a power supply system using a plurality of the power supply devices, by adding an interleave operation function using a predetermined phase setting signal to each power supply device, the burden on the input power supply, input capacitor, etc. in the previous stage of the power supply system is reduced. Can be easily reduced.

1 is a circuit diagram showing a power supply system using a plurality of switching power supply devices according to a first embodiment of the present invention. It is a block diagram which shows the structure of the power converter part of the switching power supply device of 1st embodiment. The block diagram (a) which shows the structure of the synchronous operation control circuit of the switching power supply device of 1st embodiment, the circuit diagram (b) which shows the external connection of an operation mode setting terminal, and the chart (c) explaining an operation mode setting signal is there. It is a block diagram which shows the structure of the PLL circuit which is an example of the frequency multiplication circuit of the synchronous operation control circuit of Fig.3 (a). It is a time chart which shows operation | movement of the 1st frequency divider circuit of the synchronous operation control circuit of Fig.3 (a). It is a circuit diagram which shows the power supply system which uses two or more switching power supply apparatuses of 2nd embodiment of this invention. The block diagram (a) which shows the structure of the synchronous operation control circuit of the switching power supply apparatus of 2nd embodiment, the circuit diagram (b) which shows the external connection of two operation mode setting terminals, and the chart explaining an operation mode setting signal (c) ). The block diagram (a) which shows the structure of the modification of the synchronous operation control circuit of the switching power supply device of 2nd embodiment, the circuit diagram (b) which shows the external connection of two operation mode setting terminals, and an operation mode setting signal is demonstrated. It is a chart (c). It is a circuit diagram which shows the power supply system which uses multiple switching power supply devices of 3rd embodiment of this invention. It is a block diagram (a) showing the composition of a synchronous operation control circuit of a switching power supply of a third embodiment, a circuit diagram (b) showing external connection of an operation mode setting terminal, and a chart (c) explaining a phase setting signal. . Time chart (a) for explaining the interleaving operation of the switching power supply device according to the third embodiment, time chart (b) for explaining the operation without the interleave operation function, and circuit diagram (c) for explaining the current of each power supply device It is.

  Hereinafter, a first embodiment of a switching power supply device and a switching power supply system using the same according to the present invention will be described with reference to FIGS. As shown in FIG. 1, the power supply system 10 is a system that receives power from one input power supply 12 and outputs a predetermined voltage and current for each of the four loads 14. Four switching power supply devices 16 are used. The switching power supply device 16 converts the input voltage received from the input power supply 12 into a DC output voltage and supplies it to the load 14 to synchronize the switching operation between itself and another switching power supply device 16. The synchronous operation control circuit 20 is provided. In FIG. 1, for convenience of explanation, four switching power supply devices are denoted by reference numerals 16 (1), 16 (2), 16 (3), and 16 (4), and are related to each power supply device. Each component to be identified is also distinguished by adding (1), (2), (3), (4) to the end of the reference numeral.

  As shown in FIG. 2, the power converter 18 includes a converter circuit 22, an output voltage detector 24, and a main switching element control circuit 28 that controls and drives the switching operation of the main switching element 22 a. The converter circuit 22 is, for example, an isolated ON / ON converter, an ON / OFF converter, or various types of insulated chopper circuits, and the input side is connected to the input power supply 12 and the output side is connected to the load 14 to be turned on / off. And a main switching element 22a such as an FET for intermittently inputting the input voltage. Here, the input power supply 12 is a DC power supply, but in the case of an AC power supply, a rectifier circuit is inserted in the input stage of the converter circuit 22. The output voltage detector 24 detects the output voltage of the converter circuit 22 and outputs an output voltage signal to the main switching element control circuit 28. The main switching element control circuit 28 receives the output voltage signal from the output voltage detector 24, performs a predetermined process, sets the on time and the off time of the main switching element 22a so that the output voltage is kept constant, A drive pulse for turning on and off the main switching element 22a with the set on-time and off-time is generated and output toward the drive terminal of the main switching element 22a.

  As shown in FIG. 3A, the synchronous operation control circuit 20 has an operation mode setting signal input terminal A, a synchronous clock signal input terminal B, and a synchronous clock signal output terminal C which are external connection terminals of the switching power supply device 16. In addition, a CPU 26, an oscillation circuit 30, a selection circuit 32, a frequency multiplication circuit 34, a first frequency dividing circuit 36, and a second frequency dividing circuit 38 are provided therein. The synchronous operation control circuit 20 is composed of, for example, a one-chip microcomputer, and the apparatus can be made compact.

  The operation mode setting signal input terminal A is a terminal to which a high level or low level operation mode setting signal Sa is fixedly input from the outside. For example, when it is desired to fix the operation mode setting signal input terminal A at a high level, as shown in FIG. 3B, a DC power supply 40 such as an operation power supply for the CPU 26 is connected via a pull-up resistor 42. If you want to fix it at a low level, connect it to ground. The operation mode setting signal Sa inputted externally is sent to the CPU 26 through the first input port 44 which is a digital input port.

  The synchronous clock signal input terminal B is a terminal to which a predetermined synchronous clock signal Sb is input from the outside. In the power supply system 10 of FIG. 1, no signal is input to the synchronous clock signal input terminal B1 of the switching power supply device 16 (1), but the other three switching power supply devices 16 (2), 16 (3), 16 (4 ) Is inputted with a predetermined synchronous clock signal Sb and sent to one input terminal of the selection circuit 32. The synchronous clock signal Sb is a clock signal output from the switching power supply device 16 (1), and is a rectangular pulse that repeats a high level and a low level at a frequency of 1 MHz and a time ratio of 50%, for example. The synchronous clock signal Sb will be described later.

  The oscillation circuit 30 generates an oscillation clock signal having a constant frequency and outputs it to the other input terminal of the selection circuit 32. Here, the oscillation clock signal is, for example, a rectangular pulse that repeats a high level and a low level at a frequency of 1 MHz and a duty ratio of 50%.

  The selection circuit 32 receives a selection command from the CPU 26 and selectively outputs one of an external clock signal Sb and an oscillation clock signal of the oscillation circuit 30. The selection command of the CPU 26 is determined by the logic (high level or low level) of the operation mode setting signal Sa.

The frequency multiplication circuit 34 receives the oscillation clock signal output from the selection circuit 32 and outputs a system clock signal having a frequency multiplied by n. The multiplication number n is a natural number. Here, for example, it is assumed that n = 40. Since the clock signal output from the selection circuit is 1 MHz regardless of which is selected, the frequency of the system clock signal is 40 MHz.

  As the frequency multiplication circuit 34, for example, a PLL circuit 46 (Phase Locked Loop circuit) as shown in FIG. 4 can be used. The PLL circuit 46 includes a phase comparator 46a, a loop filter 46b, a voltage controlled oscillator 46c, and a frequency divider 46d. The frequency divider 46d receives the rectangular pulse output from the voltage controlled oscillator 46c, converts it into a rectangular pulse having a frequency multiplied by 1 / n (divided by n), and outputs the rectangular pulse. The phase comparator 46a compares the rectangular pulse output from the frequency divider 46d with the rectangular pulse having a predetermined frequency input from the outside, and outputs a pulsed phase difference signal representing the phase difference. The loop filter 46b is an integration circuit to which a predetermined time constant is given, and converts the pulse signal output from the phase comparator 46a into a substantially DC phase difference signal and outputs it. The voltage controlled oscillator 46c adjusts its own oscillation frequency based on the phase difference signal sent from the loop filter, and outputs a rectangular pulse obtained by multiplying the rectangular pulse externally input to the phase comparator 46a by n. Therefore, when the PLL circuit 46 is applied to the synchronous operation control circuit 20 of FIG. 3, the clock signal output from the selection circuit 32 is input to the phase comparator 46a of the PLL circuit 46, and the clock signal is accurately multiplied by n. The system clock signal is extracted from the output of the voltage controlled oscillator 46c.

The first frequency divider 36 receives the system clock signal output from the frequency multiplier 34, converts it to a drive clock signal having a frequency multiplied by 1 / m (frequency division), and outputs it. The drive clock signal is sent to the main switching element control circuit 28, and the frequency is handled as the switching frequency of the main switching element 22a. The frequency division number m is a natural number. Here, for example, m = 100 is set, and the frequency of the drive clock signal is 400 kHz.

For example, the first frequency dividing circuit 36 uses a counter that counts the pulses of the system clock signal that is an input signal, and 50 counts, which is half the frequency division number m , as the first register setting value, and divides as the second register setting value. The same 100 count as the number m is given. Then, as shown in FIG. 5, the drive clock signal as an output signal is held at a high level until the count number of the counter reaches the first register set value (between 1 and 50 counts), and the count number is It is held at the low level until it exceeds the first register set value and reaches the second register set value (between 51 and 100 counts). When the count exceeds 100, the count is reset and returned to 1 count. By repeating this operation, the system clock signal, which is a rectangular pulse with a 50% duty ratio, is converted into a driving clock signal with a frequency of 1/100 and a rectangular pulse with a duty ratio of 50% (divided by 100) and output. be able to. Although an example in which a drive clock signal that is a rectangular pulse with a 50% duty ratio is generated is shown here, the duty ratio may be appropriately selected in consideration of the configuration of other circuits constituting the switching power supply device. it can. Further, if a waveform shaping circuit is inserted between the second frequency dividing circuit 38 and the synchronous clock signal output terminal C, and between the synchronous clock signal input terminal B and the selection circuit 32, the synchronous clock signal is converted into a sine wave pulse or a triangular wave. It can also be a pulse.

The system clock signal output from the frequency multiplying circuit 34 is also input to the second frequency dividing circuit 38, converted into a synchronous clock signal having a frequency multiplied by 1 / n (divided by n), and directed to the synchronous clock signal output terminal C. Output. This frequency division number n is a natural number equal to the multiplication number n of the frequency multiplication circuit 34. That is, the second frequency dividing circuit 38 receives the signal multiplied by n by the frequency multiplying circuit 34, divides it by n, and performs the operation of returning to the original frequency. Since n = 40 is set here, the frequency of the synchronous clock signal is 1 MHz. Therefore, the synchronous clock signal Sb output from the synchronous operation control circuit 20 is always synchronized with the oscillation clock signal of the oscillation circuit 30 and set to the same frequency.

  Next, the power supply system 10 using the four switching power supply devices 16 will be described with reference to FIG. In the power line of the power supply system 10, the inputs of the power converters 18 (1) to 18 (4) are wired in parallel to the output of the input power supply 12, and the loads 14 (1) to 14 (4) are connected to the power converter 18. (1) to 18 (4) are individually connected to the outputs. In the signal line, the synchronous clock signal output terminal C1 of the switching power supply device 16 (1) is connected to the synchronous clock signal input terminals B2, B3, B4 of the other switching power supply devices 16 (2), 16 (3), 16 (4). Wired in parallel.

  The operation mode setting signal input terminals A1 to A4 are externally connected as shown in FIG. 3B, and the operation mode setting signals Sa1 to Sa4 shown in FIG. In the case of the switching power supply device 16 (1), the operation setting mode setting signal Sa1 is held at the low level “L”, and the selection circuit 32 (1) always selects the oscillation circuit 30 (1) and its oscillation clock. Output a signal. Therefore, since the switching power supply 16 (1) does not use the synchronous clock signal Sb, no external signal is input to the synchronous clock signal input terminal B1.

  On the other hand, the operation mode setting signal input terminals A2 to A4 of the switching power supply devices 16 (2), 16 (3) and 16 (4) hold the operation setting mode setting signals Sa2, Sa3 and Sa4 at the high level “H”. The selection circuits 32 (2), 32 (3), and 32 (4) always select the synchronous clock signal input terminals B2, B3, and B4. As a result, the synchronous clock signal Sb from the synchronous operation control circuit 20 (1) is output to the frequency multiplying circuit 34 of the switching power supply devices 16 (2), 16 (3), and 16 (4). The synchronous clock signal Sb input to the synchronous clock signal input terminals B2, B3, B4 is input to the frequency multiplication circuit 34 of the switching power supply devices 16 (2), 16 (3), 16 (4), and the first and second The signal is output through the frequency dividing circuits 36 and 38, and the output of the first frequency dividing circuit 36 is output to each main switching element control circuit 28 as a drive clock signal. Since the synchronous clock signal Sb is not used in the switching power supply devices 16 (2), 16 (3), and 16 (4), the output of the second frequency dividing circuit 38 is opened at the synchronous clock signal output terminals C2, C3, and C4. ing.

  The power supply system 10 configured as described above operates as follows. The switching power supply 16 (1) generates the 1 MHz oscillation clock signal output from its own oscillation circuit 30 (1) through the selection circuit 32 (1), multiplied by 40, and further divided by 100. With the 400 kHz drive clock, the switching frequency of the power converter 18 (1) becomes 400 kHz. Accordingly, the switching power supply device 16 (1) serves as a master power supply whose own switching frequency is determined based on its own oscillation clock signal.

  On the other hand, in the case of the switching power supply device 16 (2), 16 (3), 16 (4), the selection circuit 32 (2), 32 (3), 32 (4) outputs from the switching power supply device 16 (1). The synchronized clock signal Sb is output. The synchronous clock signal Sb is a signal obtained by multiplying the oscillation clock signal of the oscillation circuit 30 (1) of the switching power supply device 16 (1) by 40 and further dividing it by 40, and the frequency is the oscillation clock of the oscillation circuit 30 (1). It matches exactly 1MHz of the signal. Therefore, the switching frequency of the power converters 18 (2), 18 (3), and 18 (4) of the switching power supply devices 16 (2), 16 (3), and 16 (4) depends on the oscillation circuit 30 (1 ) And a drive clock signal generated based on the 1 MHz oscillation clock signal, the frequency becomes 400 kHz. That is, the switching power supply devices 16 (2), 16 (3), and 16 (4) are slave power supplies whose own switching frequency is determined based on the oscillation clock signal of the master power supply.

  Even if there is variation in the frequency of the oscillation clock signal generated individually by the oscillation circuits 30 (1) to 30 (4) of the switching power supply devices 16 (1) to 16 (4), Since the switching frequency of the power converters 18 (1) to 18 (4) is 400 kHz of the drive clock signal generated based on the oscillation clock signal of the oscillation circuit 30 (1) of the master power supply, The switching frequency matches exactly. Therefore, it is possible to prevent the occurrence of low frequency beat noise due to the difference between the switching frequencies.

  According to this switching power supply device 16, even when a plurality of the power supply devices 16 are arranged apart from each other, the signal lines interconnecting the power supply devices 16 for synchronous operation are arranged in parallel with the master power supply and the slave power supply group. Wiring can be performed easily, and wiring can be simple and short.

  Even if the number of slave power supplies increases or the wiring of the signal line becomes relatively long due to other mounting reasons, the frequency of the synchronous clock signal Sb transmitted and received through the signal line is relatively easy to handle (here Therefore, problems such as signal attenuation due to the impedance of the wiring can be easily avoided.

  According to this switching power supply device 16, when assembling the power supply system 10 in a production factory, it is only necessary to prepare four identical switching power supply devices, so that material procurement and inventory management are easy. However, in the switching power supply devices 16 (2), 16 (3), and 16 (4) used as the slave power supply, the second frequency dividing circuit 38 that is not functionally required operates steadily. There is a possibility that wasteful power consumption occurs and the processing speed of the entire control circuit is also reduced. Therefore, when it is desired to suppress unnecessary power consumption and increase the processing speed as much as possible, for example, when the operation mode setting signal Sa is at a high level “H”, the division of the second frequency dividing circuit 38 according to the command of the CPU 26. It is advisable to stop the circumferential operation. Further, although there are two types of switching power supply devices, the switching power supply device 16 is used as the master power supply, and the switching power supply device 16 that does not include the second frequency divider circuit 38 from the beginning as the slave power supply group. By using it, it is possible to reduce the loss and speed of the control circuit.

  Furthermore, according to the switching power supply device 16, the switching power supply devices 16 (1) to 16 (4) of the power supply system 10 can be set to different switching frequencies. In this case, the individual first frequency dividing circuits are used. It is only necessary to individually change the frequency division number m set to 36. For example, even if the frequency division number m is changed in order to adjust the switching frequency of a specific switching power supply device 16 in the process of design evaluation of the power supply system, the frequency of the clock signal transmitted / received between the power supply devices 16 ( 1 MHz) does not need to be changed, and the other switching power supply devices 16 are not affected. Therefore, there is an advantage that it does not take time to review the setting of the other switching power supply device 16.

  The switching power supply 16 uses the PLL circuit 48 shown in FIG. 4 as the frequency multiplication circuit 46. Therefore, for example, even if a situation occurs in which a pulse missing from the clock signal output from the selection circuit 32 occurs due to external noise or the like, and the phase information of the clock signal is not properly input to the frequency multiplication circuit 46, the period Since a predetermined system clock signal is continuously output by the free-running oscillation operation of the PLL circuit 48, a system failure in which the operation of itself or another switching power supply device 16 is stopped can be prevented. However, the frequency multiplying circuit 46 is not limited to the configuration of the PLL circuit 48. When there is no concern about the missing pulse of the clock signal as described above, the frequency multiplying circuit 46 has a simple function of multiplying the frequency by n. Simple circuit can be used.

  The switching power supply device 16 can be used not only in combination, but also in a single unit. When used alone, the operation mode setting signal Sa1 is fixed to a low level “L” as in the switching power supply device 16 (1), and the synchronous clock signal output terminal A1 is connected to the switching power supply device 16 (2 ). Unlike the signal generating means used in the power supply device of Patent Document 1, it is not necessary to provide a special device outside.

  Next, a second embodiment of the switching power supply device and the switching power supply system according to the present invention will be described with reference to FIGS. Here, the same configurations as those of the switching power supply device 16 and the power supply system 10 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 6, the power supply system 50 is a system that receives power from one input power supply 12 and outputs a predetermined voltage and current for each of the five loads 14. Five switching power supply devices 52 are used. The switching power supply device 52 converts the input voltage received from the input power supply 12 into a DC output voltage and supplies it to the load 14 in order to synchronize the switching operation between itself and another switching power supply device 52. The synchronous operation control circuit 54 is provided.

  As shown in FIG. 7A, the synchronous operation control circuit 54 includes operation mode setting signal input terminals A_1 and A_2, a synchronous clock signal input terminal B, and a synchronous clock signal output terminal that are external connection terminals of the switching power supply device 54. C, and includes a CPU 26, an oscillation circuit 30, a selection circuit 32, a frequency multiplication circuit 34, a first frequency divider circuit 36, and a second frequency divider circuit 38. That is, the configuration is different from the above-described synchronous operation control circuit 20 in that it has two operation mode setting signal input terminals.

  The operation mode setting signal input terminals A_1 and A_2 are terminals to which high level or low level operation mode setting signals Sa_1 and Sa_2 are fixedly input from the outside. For example, when the operation mode setting signal input terminals A_1 and A_2 are fixed at a high level, as shown in FIG. 7B, a DC power supply 40 such as an operation power supply for the CPU 26 is connected via a pull-up resistor 42. To do. When it is fixed at a low level, it is connected to the ground. Externally input operation mode setting signals Sa_1 and Sa_2 are sent to the CPU 26 via first and second input ports 56 and 58 which are digital input ports.

  As described above, the synchronous clock signal input terminal B is a terminal to which a predetermined synchronous clock signal Sb can be input from the outside. In the power supply system 50 of FIG. 6, no signal is input to the synchronous clock signal input terminal B1 of the switching power supply device 52 (1), but the other four switching power supply devices 52 (2) to 52 (5) are respectively predetermined. The synchronous clock signal Sb is input and sent to one input terminal of the selection circuit 32. The synchronous clock signal Sb input to the switching power supply devices 52 (2) and 52 (3) is the synchronous clock signal Sb output from the switching power supply device 52 (1). The synchronous clock signal Sb input to the switching power supply devices 52 (4) and 52 (5) is the synchronous clock signal Sb output from the switching power supply device 52 (3), and is high at a frequency of 1 MHz and a time ratio of 50%, respectively. It is a rectangular pulse that repeats level and low level.

  As described above, the selection circuit 32 receives a selection command from the CPU 26 and selectively outputs one of the synchronous clock signal Sb and the oscillation clock signal. Here, the selection command of the CPU 26 is determined by a combination of logic (high level or low level) of the operation mode setting signals Sa_1 and Sa_2.

  Next, a power supply system 50 using five switching power supply devices 52 will be described with reference to FIG. The power line of the power supply system 50 is wired in parallel to the inputs of the power converters 18 (1) to 18 (5) at the output of the input power supply 12, and the loads 14 (1) to 14 (5) are connected to the power converter 18. (1) to 18 (5) are individually connected to the outputs. Here, the switching power supply devices 52 (1), 52 (2), 52 (3) are arranged in the vicinity, and the remaining switching power supply devices 52 (4), 52 (5) are the switching power supply devices 52 (1), 52 (1), It is located at a position away from 52 (2) and close to the switching power supply 52 (3).

  In the signal line, the synchronous clock signal input terminals B2 and B3 of the switching power supply devices 52 (2) and 52 (3) are wired in parallel to the synchronous clock signal output terminal C1 of the switching power supply device 52 (1). The synchronous clock signal input terminals B4 and B5 of the switching power supply devices 52 (4) and 52 (5) are wired in parallel to the synchronous clock signal output terminal C3 of 52 (3).

  The operation mode setting signal input terminals A11 to A51 and A12 to A52 are externally connected as shown in FIG. 7B, and the operation mode setting signals Sa11 to Sa51 and Sa12 to Sa52 shown in FIG. ing. In the case of the switching power supply 52 (1), since the operation setting mode setting signals Sa11 and Sa12 are held at the low level “L”, the CPU 26 recognizes the state through the first and second input ports 56 and 58, A selection command is sent to the selection circuit 32 (1) to always select the oscillation circuit 30 (1) and output the oscillation clock signal. Therefore, no external signal is input to the synchronous clock signal input terminal B1.

  In the switching power supply devices 52 (2), 52 (4), 52 (5), the operation setting mode setting signals Sa21, Sa41, Sa51 are at the high level “H”, and the operation setting mode setting signals Sa22, Sa42, Sa52 are at the low level. It is held at “L”. Thereby, the selection circuits 32 (2), 32 (4), 32 (5) always select the synchronous clock signal input terminals B2, B4, B5, and the frequency multiplication circuit 34 of the switching power supply 52 (2). The synchronous clock signal Sb from the synchronous operation control circuit 54 (1) is output to the frequency multiplication circuit 34 of the switching power supply devices 52 (4) and 52 (5) as will be described later. The synchronous clock signal Sb from 54 (3) is output.

  In the switching power supply 52 (3), the operation setting mode setting signal Sa31 is held at the low level “L”, and the Sa32 is held at the high level “H”, and the selection circuit 32 (3) is always connected to the synchronous clock signal input terminal B3. Connected to. The synchronous clock signal Sb input to the synchronous clock signal input terminal B3 is input to the frequency multiplying circuit 34 of the switching power supply device 52 (3), and is output as the synchronous clock signal Sb through the second frequency dividing circuit 38. Then, the synchronous clock signal Sb output from the synchronous clock signal output terminal C3 of the switching power supply device 52 (3) is input to the synchronous clock signal input terminals B4 and B5 of the switching power supply devices 52 (4) and 52 (5). The Here, since the synchronous clock signal Sb output from the second frequency dividing circuit 38 of the switching power supply devices 52 (2), 52 (4), 52 (5) is not used, the synchronous clock signal output terminals C2, C4, C5 are used. Is open.

  The power supply system 50 configured as described above operates as follows. The switching power supply 52 (1) generates the 1 MHz oscillation clock signal output from its own oscillation circuit 30 (1) by passing through the selection circuit 32 (1), multiplying it by 40, and further dividing it by 100. The switching frequency of the power converter 18 (1) becomes 400 kHz by the 400 kHz drive clock signal. That is, the switching power supply 50 (1) serves as a master power supply whose own switching frequency is determined based on its own oscillation clock signal.

  In the case of the switching power supply devices 52 (2) and 52 (3), the synchronization clock signal Sb of the power supply device 52 (1) is output from the selection circuits 32 (2) and 32 (3). The synchronous clock signal Sb is a signal obtained by multiplying the oscillation clock signal of the oscillation circuit 30 (1) of the switching power supply 52 (1) by 40 and further dividing it by 40, and the frequency is the oscillation clock of the oscillation circuit 30 (1). It matches exactly 1MHz of the signal. Therefore, the switching frequency of the power converters 18 (2) and 18 (3) of the switching power supply devices 52 (2) and 52 (3) is generated based on the 1 MHz oscillation clock signal of the oscillation circuit 30 (1). The frequency of the drive clock signal is 400 kHz. That is, the switching power supply devices 52 (2) and 52 (3) are slave power supplies whose own switching frequency is determined based on the oscillation clock signal of the master power supply.

  In addition, the switching power supply 52 (3) outputs the synchronous clock signal Sb from the synchronous clock signal output terminal C3 via the second frequency dividing circuit 38. The synchronous clock signal Sb is obtained by multiplying the synchronous clock signal Sb obtained by multiplying the oscillation clock signal of the oscillation circuit 30 (1) of the switching power supply 52 (1) by 40 and further dividing the frequency by 40, and multiplying the synchronous clock signal Sb by 40 again to obtain 40 The frequency-divided signal has a frequency that exactly matches 1 MHz of the oscillation clock signal of the oscillation circuit 30 (1). Therefore, the switching power supply device 52 (3) relays and outputs the synchronous clock signal from the master power supply, and relays the synchronous clock signal Sb to the switching power supply devices 52 (4) and 52 (5). It is a power supply.

  Then, the switching power supply devices 52 (4) and 52 (5) have the switching frequency of the power converters 18 (4) and 18 (5) set to 1 MHz of the oscillation circuit 30 (1) by the operation of the relay slave power supply. The frequency of the drive clock signal generated based on the oscillation clock signal is 400 kHz. Accordingly, the switching power supply devices 52 (4) and 52 (5) are slave power supplies whose own switching frequency is determined based on the oscillation clock signal of the master power supply.

  This power supply system 50 can prevent the occurrence of low-frequency beat noise due to the difference between the switching frequencies, similar to the power supply system 10 of the above embodiment. Further, according to this switching power supply device 52, even when a large number of the power supply devices 16 are arranged largely apart from each other, they are divided into slave power supply groups including a master power supply and a relay slave power supply, and the master power supply is a slave power supply. A large number of groups can be connected in parallel, a part of the slave power supply group can be used as a relay slave power supply, and the slave power supply group can be connected in parallel. Thereby, the interconnection of the signal lines can be simply and shortly wired. In addition, the same excellent effects as those of the switching power supply device 16 can be obtained.

  In the above embodiment, the switching power supply 52 (2), 52 (4), 52 (5) used purely as a slave power supply has a second frequency dividing circuit 38 that is not functionally required. Operate. Therefore, in order to suppress unnecessary power consumption or increase the processing speed of the entire control circuit, the frequency dividing operation of the unnecessary second frequency dividing circuit 38 may be stopped by a selection command from the CPU 26. In that case, it is necessary for the CPU 26 of each switching power supply 52 to recognize whether it is assigned to a master power supply, a slave power supply, or a relay slave power supply. Here, in FIG. ), The identification is based on the combination of the operation mode setting signals Sa_1 and Sa_2 indicating the high level “H” or the low level “L”.

  The configuration for performing this identification is not limited to the configuration of the synchronous operation control circuit 54. For example, in the case of the synchronous operation control circuit 60 in FIG. 8A, as shown in FIG. 8B, an operation mode setting signal Sa, which is a predetermined analog voltage, is externally supplied to one operation mode setting signal input terminal A. It is inputted and sent to the CPU 26 through the AD converter 62 which is an analog / digital converter. Here, as shown in FIG. 8C, when the operation mode voltage signal Sa is in the range of 0 to Vc, it is the master power supply, and when it is in the range of Vc to 2Vc, it is in the range of the slave power supply and 2Vc to 3Vc. Sometimes the operation mode is selected such as relay slave power supply. Furthermore, among the slave power supplies, when it is desired to identify the slave power supply connected to the relay slave power supply, the voltage range may be divided into four.

  Next, a switching power supply device and a switching power supply system according to a third embodiment of the present invention will be described with reference to FIGS. Here, the same configurations as those of the switching power supply device 16 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 9, the power supply system 70 is a system that receives power from one input power supply 12 and outputs a predetermined voltage and current for each of the three loads 14. Four switching power supply devices 72 are used. The switching power supply device 72 synchronizes the switching operation between the power conversion unit 18 that converts the input voltage received from the input power supply 12 into a DC output voltage and supplies the output voltage to the load 14 and the other switching power supply device 72. And a synchronous operation control circuit 74 for controlling the start timing when the input is turned on and the phase at which the main switching element is turned on.

  In addition to the configuration of the synchronous operation control circuit 20 illustrated in FIG. 3, the synchronous operation control circuit 74 includes a start control terminal D that serves as an external connection terminal of the switching power supply device 72 and a phase setting signal input as illustrated in FIG. A terminal E is provided.

  The activation control terminal D is interconnected with the activation control terminal D of another switching power supply device, and outputs an activation signal Sd sent from the CPU 26 through the input / output port 76 when itself is a master power supply. The activation signal Sd includes information indicating the timing at which the input power supply 12 is turned on and the power converter 18 of the self starts switching. On the other hand, when the power supply itself is a slave power supply, the start signal Sd output from the master power supply is received via its own start control terminal D and sent to the CPU 26. The slave power supply CPU 26 receives the start signal Sd from the master power supply, and sets the phase of the drive clock signal of the first frequency dividing circuit 36 with respect to the drive clock signal of the master power supply. Whether the power supply itself is a master power supply or a slave power supply is determined based on the state of the operation mode setting signal Sa input by the CPU 26 to the operation mode setting signal input terminal A, as described with reference to FIG. Do.

  The phase setting signal input terminal E is a terminal to which a phase setting signal Se that is a predetermined analog voltage is fixedly input from the outside. For example, as shown in FIG. 10B, a phase setting signal Se obtained by dividing a power supply voltage of a DC power supply 40, which is an operation power supply for the CPU 26, by a resistance at a predetermined ratio is externally input to a phase setting signal input terminal E. Then, it is sent to the CPU 26 through the AD converter 78 which is an analog / digital converter. This phase setting signal Se is a signal for setting the phase at which the main switching element 22a turns on in one switching period, and as shown in FIG. It is stipulated that

  Next, a power supply system 70 using four switching power supply devices 72 will be described with reference to FIG. In the power line of the power supply system 70, the inputs of the power conversion units 18 (1) to 18 (4) are wired in parallel to the output of the input power supply 12, and the loads 14 (2) and 14 (4) are connected to the power conversion unit 18. (2) and 18 (4) are individually connected to the outputs, and the load 14 (1) is connected to the outputs of the power converters 18 (1) and 18 (3) in parallel operation.

  In the signal line, the synchronous clock signal output terminals C1 of the switching power supply 72 (1) and the synchronous clock signal input terminals B2, B3, B4 of the switching power supply 72 (2), 72 (3), 72 (4) are in parallel. Wired. Furthermore, the start control terminal D1 of the switching power supply 72 (1) is wired in parallel to the start control terminals D2, D3, D4 of the switching power supply 72 (2), 72 (3), 72 (4).

  The external connection of the operation mode setting signal input terminals A1 to A4 is the same as that shown in FIGS. 3B and 3C. The switching power supply 72 (1) serves as the master power supply, and the switching power supply 72 (2), 72 ( 3) and 72 (4) are set to be slave power supplies.

  The power supply system 70 configured as described above operates as follows. When the input power supply 12 is turned on, switching of the switching power supply 72 (1) is started, and an activation signal control signal Sd1 for informing the slave power supply accordingly is output. The CPU 26 of the switching power supply 72 (2), 72 (3), 72 (4), which is a slave power supply, receives the activation signal Sd and divides the main switching element 22a immediately or after a predetermined time. A start signal is output to the first frequency dividing circuit 36, and the main switching element 22a starts switching at a predetermined timing (phase difference) via the main switching control circuit 28. In this way, the four switching power supply devices 72 can be accurately started according to a preset startup sequence.

  At this time, the CPU 26 of the switching power supply 72 (2), 72 (3), 72 (4) recognizes the start timing of one cycle of switching of the switching power supply 72 (1) from the start signal Sd and adjusts accordingly. The start timing of one cycle of self switching is determined. Therefore, the four switching power supply devices 72 have the same switching frequency and relatively different phases in one cycle. In the case of the switching power supply 72 (1) of the master power source serving as a reference, the phase setting signal as shown in FIG. 10C is set for the phase at which the main switching element 22a turns on during one switching cycle. Se1 is defined in the range of 0 to Vc, and the CPU 26 outputs a drive control signal to the first frequency divider 36 so that the phase at which the main switching element 22a turns on becomes 0 degrees. In the case of the master power supply, the setting may be fixed so that the drive control signal is output to the first frequency dividing circuit 36 so that the phase becomes 0 degrees regardless of the value of the phase setting signal Se1. In the case of the switching power supply 72 (2), the phase setting signal Se2 is defined in the range of Vc to 2Vc, and the phase is set to 90 degrees with respect to the switching operation of the switching power supply 72 (1). Similarly, in the case of the switching power supply 72 (3), in the case of the switching power supply 72 (4), in the case of the switching power supply 72 (4), the phase setting signal Se3 is defined in the range of 2Vc to 3Vc and the phase is 180 degrees. Each CPU 26 outputs a predetermined frequency dividing operation start signal to the first frequency dividing circuit 36 so that the signal Se4 is defined in the range of 3Vc to 4Vc and the phase becomes 270 degrees.

  Specifically, in this embodiment, since the first frequency dividing circuit 36 that has received the drive control signal defined by the phase setting signal Se has one cycle of switching of 100 counts of the system clock signal, For example, when the phase of the switching start of the switching power supply 72 (1) is 0 degree and the phase is 90 degrees, the switching power supply 72 (2) is started so that the main switching element 22a is turned on at the 26th count. The rising timing of the drive clock signal of the first frequency dividing circuit 36 is set. Similarly, each of the switching power supply devices 72 (3), 72 (3), 72 (3), and 72 (3), starts turning on the main switching element 22a at the 51st count when the phase is set to 180 degrees and at the 76th count when the phase is set to 270 degrees. (4) The rising timing of the drive clock signal of the first frequency divider 36 is set.

  As described above, since the switching frequencies of the four switching power supply devices 72 are equal and the phases at which the main switching elements 22a turn on are shifted by 90 degrees from each other, as shown in FIG. An interleaving operation is performed in which the timing at which the switching currents I1 to I4 of 72 (1) to 72 (4) flow is dispersed in one cycle T. As a result, as shown in FIG. 11C, the amplitude of the current Ic flowing through the input capacitor 80 (corresponding to a capacitor obtained by synthesizing the input capacitors incorporated in each switching power supply device 72) is reduced. 80 heat generation and ripple voltage can be greatly reduced. The same effect can be obtained with respect to the output smoothing capacitors of the switching power supply devices 72 (1) and 72 (3) whose outputs are connected in parallel.

  Here, the current Ic of the input capacitor 80 is compared with the power supply system 10 of FIG. The power supply system 10 uses the switching power supply device 16 of the first embodiment that does not include the start control terminal D and the phase control terminal E, and the switching frequency of each switching power supply device 16 is the same, but each main switching element 22a. The ON timing of is indefinite. If the phase at which each main switching element 22a turns on matches as shown in FIG. 11 (b), the amplitude of the current Ic flowing through the input capacitor 80 becomes very large, and heat generation and ripple of the interphase capacitor 80 occur. Voltage can be a problem. Accordingly, when configuring a power supply system that outputs particularly large power, it is preferable to perform an appropriate interleave operation using the switching power supply device 72 of the third embodiment in order to avoid the problem of the input capacitor 80.

  Since the power supply system 70 uses four switching power supply devices 72, the phase at which the main switching element 22a is turned on is shifted by 90 degrees, but the setting is changed depending on the number of units used. For example, it is preferable to shift by 120 degrees in the case of three units and by 60 degrees in the case of six units so that the switching currents of the respective switching power supply devices 72 flow at substantially equal timings.

  The main switching element control circuit of the switching power supply device of the present invention can be appropriately selected from those controlled by an analog circuit, digitally controlled using a CPU, and those using both. The synchronous operation control circuit preferably uses a one-chip microcomputer, but it may be a discrete combination of a CPU and other digital elements. Various setting signals to be input to the synchronous operation control circuit can also be input using an appropriate circuit, and are not limited to the above embodiment.

10, 50, 70 Power supply system 16, 52, 72 Switching power supply 18 Power converter 20, 54, 60, 74 Synchronous operation control circuit 22 Converter circuit 22a Main switching element 26 CPU
28 main switching element control circuit 30 oscillation circuit 32 selection circuit 34 frequency multiplication circuit 36 first frequency division circuit 38 second frequency division circuit 46 PLL circuit A, A_1, A_2 operation mode setting signal input terminal B synchronization signal input terminal C synchronization signal Output terminal D Start control terminal E Phase setting signal input terminals Sa, Sa_1, Sa_2 Operation mode setting signal Sb Synchronous clock signal Sd Start signal Se Phase setting signal

Claims (8)

A converter circuit that converts the input voltage into a DC output voltage by the switching operation of the main switching element, and outputs it;
A main switching element control circuit for driving the main switching element;
A CPU for performing predetermined digital arithmetic processing and defining on-timing of the main switching element by the main switching element control circuit;
An operation mode setting signal input terminal to which an operation mode setting signal is input from the outside;
Synchronous clock signal input terminal that can input a clock signal from the outside,
An oscillation circuit that outputs an oscillation clock signal of a predetermined frequency;
A selection circuit that selects and outputs either a signal from the synchronous clock signal input terminal or a signal from the oscillation clock circuit based on a selection command from the CPU by setting the operation mode setting signal input terminal When,
A frequency multiplication circuit that outputs a system clock signal obtained by multiplying any signal output from the selection circuit by a multiplication number n (n is a natural number);
A first frequency divider circuit that generates a drive clock signal obtained by dividing the system clock signal output from the frequency multiplier circuit by a frequency division number m (m is a natural number) and outputs the drive clock signal to the main switching element control circuit; A switching power supply device comprising a synchronous operation control circuit provided with.   The switching power supply device according to claim 1, wherein the frequency multiplication circuit is configured using a PLL circuit. A plurality of the switching power supply devices according to claim 1 or 2,
The plurality of switching power supply devices are connected with the same multiplication factor n, and the plurality of switching power supply devices are divided into one master power supply and another slave power supply to constitute a power supply system. And
The master power source generates, in its own synchronous operation control circuit, a second frequency dividing circuit that generates a synchronous clock signal obtained by dividing the system clock signal by a frequency division number n which is a natural number equal to the multiplication number n , A synchronization clock signal output terminal for outputting a synchronization clock signal to the outside, and an operation mode setting signal for outputting the oscillation clock signal from the selection circuit is input to the operation mode setting signal input terminal;
The slave power supply has the operation mode setting signal input terminal to which the operation mode setting signal for outputting the synchronous clock signal from the selection circuit is input, and the synchronous power signal input terminal of the master power supply The switching power supply system, wherein the synchronous clock signal synchronized with the oscillation clock signal is input. Provided in each synchronous operation control circuit of the master power supply and the slave power supply, provided with a start control terminal for transmitting to the slave power supply that the master power supply is started by interconnecting,
The synchronous operation control circuit of the master power supply outputs a start signal to the effect that the main switching element of the master power supply is turned on via the start control terminal of the self power supply,
4. The switching power supply according to claim 3, wherein the synchronous operation control circuit of the slave power supply starts the operation of its own main switching element when the start signal of the master power supply is input via its own start control terminal. system. Using the master power supply and the slave power supply to which the frequency division number m equal to each other is used, the input ends of the converter circuits are connected in parallel,
The synchronous operation control circuit of the master power supply outputs the activation signal including information on switching start timing of its main switching element via its own activation control terminal,
A phase setting signal input for externally inputting a phase setting signal for setting the on timing of the main switching element with respect to the on timing of the main switching element of the master power supply to the synchronous operation control circuit of the slave power supply Terminals are provided,
The CPU of the slave power supply receives its own phase setting signal via the phase setting signal input terminal, and supplies a drive control signal for realizing the phase defined by the phase setting signal to the first frequency divider circuit. The switching power supply system according to claim 4, which outputs the switching power supply system. The master power supply and the slave power supply each generate a synchronous clock signal obtained by dividing the system clock signal by a frequency division number n which is a natural number equal to the multiplication number n in each synchronous operation control circuit. And a synchronous clock signal output terminal that enables external output of the synchronous clock signal,
The CPU of the slave power supply stops the frequency dividing operation of the second frequency dividing circuit when receiving the operation mode setting signal for outputting the synchronous clock signal from the selection circuit. Item 6. The switching power supply system according to any one of Items 3 to 5.   Some of the plurality of slave power supplies have their own synchronous clock signal input terminal connected to the synchronous clock signal output terminal of the master power supply, and the synchronous clock signal of the partial slave power supply The output terminal is connected to a synchronous clock signal input terminal of a part of the slave power supply other than the part of the slave power supply, and relays the synchronous clock signal output from the master power supply. The switching power supply system according to any one of 3 to 5. The master power source and the slave power source generate the synchronous clock signal obtained by dividing the system clock signal by a frequency division number n which is a natural number equal to the multiplication number n in the synchronous operation control circuit of the master power source and the slave power source. A frequency dividing circuit, and a synchronous clock signal output terminal that enables external output of the synchronous clock signal;
The CPU of the slave power supply excluding the slave power supply that relays the synchronous clock signal from the master power supply receives each operation mode setting signal to output the synchronous clock signal from its selection circuit. 8. The switching power supply system according to claim 7, wherein the frequency dividing operation of the second frequency dividing circuit is stopped when the second frequency dividing circuit is on.

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