JP5462524B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a through electrode layer is formed on a semiconductor substrate.

  In recent years, miniaturization of packages (semiconductor devices) has been required in integrated circuits used in electronic devices. As an example of downsizing, for the purpose of reducing the package area of an integrated circuit, a through electrode penetrating a semiconductor substrate of a semiconductor device is used instead of conventional wire bonding.

  FIG. 9 is a partial cross-sectional view showing an example of a conventional semiconductor device.

  In FIG. 9, the semiconductor device 101 is formed in a semiconductor substrate 102 such as silicon, a via hole 107 reaching the pad electrode 105 from the back surface 102 b of the semiconductor substrate 102, a side wall 107 a of the via hole 107, and a back surface 102 b of the semiconductor substrate 102. The second oxide film 109 is roughly constituted by a barrier layer 110 and a rewiring layer 111 formed in the via hole 107 and on the back surface 102b of the semiconductor substrate 102.

  FIG. 10 is a flowchart showing a conventional method for manufacturing a semiconductor device, and FIGS. 11A to 12D are partial cross-sectional views for explaining a conventional method for manufacturing a semiconductor device.

  First, as shown in FIG. 11A, after the pad electrode 105 and the passivation film 104 are formed on the first oxide film 106 on the surface 102a of the semiconductor substrate 102 on which an electronic circuit (not shown) is formed, the passivation is performed. The support substrate 103 is bonded onto the film 104 via an adhesive (not shown) (see step S101 in FIG. 10).

  Next, as shown in FIG. 11B, a resist 112 is formed on the back surface 102b of the semiconductor substrate 102 in order to open a position corresponding to the pad electrode 105 (see step S102 in FIG. 10).

  Then, as shown in FIG. 11C, the via hole 107 reaching the first oxide film 106 is formed by etching the semiconductor substrate 102 using the resist 112 as a mask (see step S103 in FIG. 10).

  Subsequently, as shown in FIG. 11D, the first oxide film 106 is etched using the resist 112 as a mask, thereby forming a via hole 107 reaching the pad electrode 105 (see step S104 in FIG. 10).

  Next, as shown in FIG. 12A, the resist 112 is removed from the back surface 102b of the semiconductor substrate 102 (see step S105 in FIG. 10).

  Then, as shown in FIG. 12B, a second oxide film 109 is formed on the side wall 107a of the via hole 107 and the back surface 102b of the semiconductor substrate 102 (see step S106 in FIG. 10).

  Next, as shown in FIG. 12C, the pad electrode 105 is exposed again by etching the second oxide film 109 at the bottom of the via hole 107 (see step S107 in FIG. 10).

  Subsequently, as shown in FIG. 12D, a barrier layer 110 and a redistribution layer 111 are sequentially formed on the second oxide film 109 (see step S108 in FIG. 10).

  The pad electrode 105 is electrically connected to the back surface 102 b of the semiconductor substrate 102 through the through electrode 108 constituted by the barrier layer 110 and the rewiring layer 111.

  The pad electrode 105 and the through electrode 108 are in contact with each other in an area corresponding to the inner diameter of the via hole 107, and the resistance value between the pad electrode 105 and the through electrode 108 is determined by this contact area.

JP 2005-235860 A

  However, in the conventional configuration, since the resistance value between the pad electrode 105 and the through electrode 108 depends on the inner diameter of the via hole 107, the resistance value varies due to variations in the inner diameter of the via hole 107. have.

  The present invention solves the above-described conventional problems, and an object of the present invention is to provide a highly reliable semiconductor device in which the resistance value between the pad electrode and the through electrode does not depend on the variation in the inner diameter of the via hole. And

  In order to achieve the above object, the present invention is configured as follows.

According to the first aspect of the present invention, the first insulating film formed on the surface of the semiconductor substrate;
An electrode portion formed in the first insulating film and having an external connection terminal;
A via hole penetrating from the back surface of the semiconductor substrate to the front surface;
A second insulating film formed on a sidewall of the via hole and the back surface of the semiconductor substrate;
A through electrode layer formed on the second insulating film on the sidewall of the via hole, the second insulating film on the back surface of the semiconductor substrate, and the first insulating film on the bottom surface of the via hole;
A silicide layer formed between the electrode portion and the through electrode layer and connected to the electrode portion and the through electrode layer;
With
The semiconductor device is characterized in that the relation between the width A of the silicide layer and the width B of the bottom of the via hole in a cross section cut along a plane including the central axis of the via hole is A ≦ B.

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the silicide layer and the electrode portion are connected via a contact electrode .

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the width of the silicide layer and the width of the contact electrode are equal in the plane including the central axis of the via hole. I will provide a.

According to a fourth aspect of the present invention, in any one of the first to third aspects, in the plane including the central axis of the via hole, the width of the electrode portion is larger than the width of the bottom portion of the via hole . A semiconductor device according to one aspect is provided.

According to a fifth aspect of the present invention, the electrode portion is
A body portion of the electrode portion;
The semiconductor device according to any one of the first to fourth aspects, further comprising a first barrier layer disposed between the main body portion of the electrode portion and the first insulating film. .

According to a sixth aspect of the present invention, the electrode portion is
A body portion of the electrode portion;
A first barrier layer disposed between the main body portion of the electrode portion and the first insulating film and in contact with the silicide layer;
One of the first to fourth aspects, further comprising: a pad electrode portion that is disposed on the outer surface side of the first insulating film and on the outer surface of the main body portion of the electrode portion and functions as the external connection terminal. to provide a semiconductor device mounting serial to embodiment.

According to a seventh aspect of the present invention, the silicide layer is formed on any one of the semiconductor substrate, a polysilicon film, or an amorphous silicon film.
To provide a semiconductor device mounting serial to a sixth one of the aspects.

According to an eighth aspect of the present invention, the silicide layer is made of any of tungsten silicide, titanium silicide, cobalt silicide, or nickel silicide.
To provide a semiconductor device mounting serial to first to seventh any one aspect.

According to a ninth aspect of the present invention, the main body portion of the electrode portion is made of tungsten, aluminum, an alloy thereof, or copper.
Providing a semiconductor device mounting serial to aspects of the seventh or eighth.

According to a tenth aspect of the present invention, the first barrier layer is composed of a laminated film of titanium, titanium nitride, titanium tungsten, tantalum, tantalum nitride, or a refractory metal.
To provide a semiconductor device mounting serial to a sixth aspect of.
According to an eleventh aspect of the present invention, the through electrode layer comprises:
A second barrier layer formed on the second insulating film on the side wall of the via hole, the second insulating film on the back surface of the semiconductor substrate, and the first insulating film on the bottom surface of the via hole;
A rewiring layer formed on the second barrier layer,
The second barrier layer is composed of titanium, titanium nitride, titanium tungsten, tantalum, tantalum nitride, or a laminated film of a refractory metal.
A semiconductor device according to any one of the first to tenth aspects is provided.
According to a twelfth aspect of the present invention, the electrode portion is composed of a single contact electrode member or a plurality of contact electrode members.
A semiconductor device according to any one of the first to eleventh aspects is provided.
According to the thirteenth aspect of the present invention, the pad electrode is composed of aluminum, copper, or an alloy thereof, and any of titanium, titanium nitride, tantalum, tantalum nitride, a refractory metal, or a compound thereof. Characterized by
A semiconductor device according to a sixth aspect is provided.

  As described above, according to the semiconductor device of the present invention, the resistance value between the electrode portion including the pad electrode and the through electrode layer has the width of the silicide layer connected to the electrode portion and the through electrode layer (for example, Depends on the dimension of the diameter when the silicide layer is circular) and does not depend on the variation of the width of the via hole (for example, the inner diameter when the via hole is circular). Can be provided.

  Also, the width of the via hole (for example, the inner diameter when the via hole is circular) can be made larger than the width of the pad electrode (for example, the diameter when the pad electrode is circular) of the electrode portion. It is also possible to reduce the aspect ratio.

  Furthermore, the width of the via hole (for example, the inner diameter when the via hole is circular) can be made larger than the width of the pad electrode of the electrode portion (for example, the diameter when the pad electrode is circular). By reducing the size of the pad electrode in the electrode portion, the area of a semiconductor chip as an example of a semiconductor device can be reduced.

Partial sectional view of the semiconductor device in the first embodiment of the present invention Flowchart showing a method for manufacturing a semiconductor device in the first embodiment of the present invention. The fragmentary sectional view which shows the process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention FIG. 3A is a partial cross-sectional view showing the steps of the method for manufacturing the semiconductor device in the first embodiment of the present invention, following FIG. 3A. 3B is a partial cross-sectional view showing the process of the method for manufacturing the semiconductor device in the first embodiment of the present invention, following FIG. 3B. FIG. 3C is a partial cross-sectional view showing the process of the method for manufacturing the semiconductor device in the first embodiment of the present invention, following FIG. 3C. 3D is a partial cross-sectional view showing the process of the method for manufacturing the semiconductor device in the first embodiment of the present invention, following FIG. 3D. 4A is a partial cross-sectional view showing the process of the method for manufacturing the semiconductor device in the first embodiment of the present invention, following FIG. 4A. 4B is a partial cross-sectional view showing the process of the method for manufacturing the semiconductor device in the first embodiment of the present invention, following FIG. 4B. The fragmentary sectional view which shows the semiconductor device in the modification 1 of Embodiment 1 of this invention The fragmentary sectional view which shows the semiconductor device in the modification 2 of Embodiment 1 of this invention The fragmentary sectional view which shows the semiconductor device in the modification 3 of Embodiment 1 of this invention Sectional drawing of the semiconductor device in Embodiment 2 of this invention The flowchart which shows the manufacturing method of the semiconductor device in Embodiment 2 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 2 of this invention 7A is a partial cross-sectional view showing the method for manufacturing the semiconductor device in the second embodiment of the present invention, following FIG. 7A. 7B is a partial cross-sectional view showing the method for manufacturing the semiconductor device in the second embodiment of the present invention, following FIG. 7B. 7C is a partial cross-sectional view showing the method for manufacturing the semiconductor device in the second embodiment of the present invention, following FIG. 7C. 7D is a partial cross-sectional view showing the method for manufacturing the semiconductor device in the second embodiment of the present invention, following FIG. 7D. 8A is a partial cross-sectional view showing the method for manufacturing the semiconductor device in the second embodiment of the present invention, following FIG. 8A. 8B is a partial cross-sectional view showing the method for manufacturing the semiconductor device in the second embodiment of the present invention, following FIG. 8B. The fragmentary sectional view which shows the semiconductor device in the modification 1 of Embodiment 2 of this invention The fragmentary sectional view which shows the semiconductor device in the modification 2 of Embodiment 2 of this invention The fragmentary sectional view which shows the semiconductor device in the modification 3 of Embodiment 2 of this invention Partial sectional view of a conventional semiconductor device A flowchart showing a conventional method of manufacturing a semiconductor device Sectional drawing which shows the process of the manufacturing method of the conventional semiconductor device FIG. 11A is a partial cross-sectional view showing the steps of the conventional method for manufacturing a semiconductor device, following FIG. FIG. 11B is a partial cross-sectional view showing the steps of the conventional method for manufacturing the semiconductor device, following FIG. FIG. 11C is a partial cross-sectional view showing the process of the conventional method for manufacturing a semiconductor device, following FIG. 11C FIG. 11D is a partial cross-sectional view showing a process of the conventional semiconductor device manufacturing method following FIG. 11D FIG. 12A is a partial cross-sectional view showing a process of the conventional semiconductor device manufacturing method following FIG. FIG. 12B is a partial cross-sectional view showing the steps of the conventional method for manufacturing the semiconductor device, following FIG. FIG. 12C is a partial cross-sectional view showing the steps of the conventional method for manufacturing the semiconductor device, following FIG. The semiconductor device of Embodiment 1 of this invention WHEREIN: When forming a silicide before contact electrode formation, the fragmentary sectional view which shows the example whose contact electrode is a several contact electrode member The semiconductor device of Embodiment 1 of this invention WHEREIN: When forming a silicide after contact electrode formation, the fragmentary sectional view which shows the example whose contact electrode is a several contact electrode member The semiconductor device of Embodiment 2 of this invention WHEREIN: When forming silicide before contact electrode formation, the fragmentary sectional view which shows the example whose contact electrode is a several contact electrode member In the semiconductor device of Embodiment 2 of this invention, when forming a silicide after contact electrode formation, the fragmentary sectional view which shows the example whose contact electrode is a several contact electrode member

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals and description thereof is omitted.

(Embodiment 1)
FIG. 1 is a partial cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

  In FIG. 1, the semiconductor device 1 includes a semiconductor substrate 2, a first oxide film 8, an electrode portion 18 (pad electrode 5, contact electrode 6, first barrier layer 7), silicide layer 9, and via hole 10. And the second oxide film 12, the through electrode layer 11 (the second barrier layer 13 and the rewiring layer 14), the support substrate 3, and the passivation film 4 which is an example of an insulating film.

The first oxide film 8 is made of, for example, SiO ₂ and is formed on the surface (lower surface in FIG. 1) 2a of the semiconductor substrate 2 as an example of an insulating film, and insulates the semiconductor substrate 2 and the pad electrode 5 from each other. have.

  The pad electrode 5 functions as an example of an external connection terminal of the electrode portion, is made of a conductive material described later, and is formed on the surface of the first oxide film 8 so as to protrude from the surface of the first oxide film 8.

  The contact electrode 6 functions as an example of a main body portion of the electrode portion, is made of a conductive material, which will be described later, is formed inside the first oxide film 8, and the outer surface is in contact with the pad electrode 5 to contact the pad electrode 5. It is connected. In FIG. 1, the contact electrode 6 is formed to have a smaller width than the pad electrode 5.

  The first barrier layer 7 constitutes a part of the electrode portion, is made of a conductive material described later, and covers all other surfaces (side surfaces and inner surfaces) of the contact electrode 6 except for the outer surface connected to the pad electrode 5. Thus, the first oxide film 8 and the contact electrode 6 have a function of improving the adhesion. The first barrier layer 7 may be formed on the outer surface connected to the pad electrode 5.

The silicide layer 9 has a conductive material composed of an alloy of metal and silicon as will be described later, and is disposed on the inner surface side of the contact electrode 6 via the first barrier layer 7. The silicide layer 9 is intended for low resistance between the contact electrode 6 and the through electrode layer 11. That is, it is formed between the first barrier layer 7 on the contact electrode 6 and a through electrode layer 11 described later, and is formed so as to be connected to the through electrode layer 11 and the first barrier layer 7. The purpose of disposing the silicide layer 9 is to prevent the resistance value between the pad electrode 5 and the through electrode layer 11 from depending on the inner diameter of the via hole 10. Therefore, the material of the silicide layer 9 is TiSi ₂ or the like for the purpose of low resistance.

  The silicide layer 9 in the present embodiment is formed slightly protruding from the bottom surface of the via hole 10 toward the inside of the via hole 10 (upward from the surface 2a), but forms silicide without interdiffusing with Si. In the case of the material to be used, it is not always necessary to protrude.

  The via hole 10 extends from the back surface (upper surface in FIG. 1) 2b of the semiconductor substrate 2 to the front surface (lower surface in FIG. 1) 2a, that is, to reach the silicide layer 9 and the first oxide film 8. It penetrates and is formed. As shown in FIG. 1, the via hole 10 is formed so that the side wall 10a has a conical surface shape with a slightly tapered shape in which the side wall 10a is inclined so that the inner diameter gradually decreases from the back surface 2b toward the front surface 2a. Has been.

The second oxide film 12 is made of, for example, SiO ₂ and is formed on the entire side wall 10a of the via hole 10 and the back surface 2b of the semiconductor substrate 2 as an example of an insulating film. Has the function of insulation.

  The through electrode layer 11 includes a second barrier layer 13 and a rewiring layer 14.

  The second barrier layer 13 is for enhancing the adhesion between the second oxide film 12 and the redistribution layer 14 and is made of a material as described later, and is the bottom surface of the via hole 10 (that is, the surface of the semiconductor substrate 2). 2a and the silicide layer 9), on the second oxide film 12 on the side wall 10a of the via hole 10 and on the second oxide film 12 on the back surface 2b of the semiconductor substrate 2, and on the bottom surface of the via hole 10 It is connected to the silicide layer 9. In the portion connected to the silicide layer 9, the second barrier layer 13 is formed in a state where the silicide layer 9 slightly protrudes from the bottom surface of the via hole 10 by the amount that the silicide layer 9 protrudes slightly from the bottom surface of the via hole 10.

  The rewiring layer 14 is formed on the second barrier layer 13. That is, the second barrier layer 13 on the bottom surface of the via hole 10, the second barrier layer 13 on the second oxide film 12 on the sidewall 10 a of the via hole 10, and the second oxide film 12 on the back surface 2 b of the semiconductor substrate 2. A rewiring layer 14 is formed integrally with each of the second barrier layers 13. The rewiring layer 14 is formed for the purpose of electrical wiring from the pad electrode 5 (substrate surface) to the back surface of the substrate, and is made of, for example, Cu.

  Therefore, the pad electrode 5 and the through electrode layer 11 are electrically connected through the contact electrode 6, the first barrier layer 7, and the silicide layer 9, and other portions are electrically connected by the first oxide film 8. Insulated.

  The semiconductor substrate 2 and the through electrode layer 11 are electrically insulated by a second oxide film 12 formed on the side wall 10 a of the via hole 10 and the back surface 2 b of the semiconductor substrate 2.

  The pad electrode 5 and the contact electrode 6 may be any material that reduces the resistance between the pad electrode 5 and the contact electrode 6. As an example, the pad electrode 5 is formed as a laminated film of a conductive material composed of aluminum, copper, or an alloy thereof, and titanium, titanium nitride, tantalum, tantalum nitride, a refractory metal, or a compound thereof. Has been. The contact electrode 6 is made of a conductive material such as tungsten, aluminum or an alloy thereof, or copper.

  The contact electrode 6 may be composed of a single thick contact electrode member. Instead, as shown in FIGS. 13 to 14, the single contact electrode member 6 is divided into a plurality of thin contact electrode members 6A. You may make it comprise with such a several contact electrode member. FIG. 13 is a partial cross-sectional view showing an example in which the contact electrode is a plurality of contact electrode members when silicide is formed before the contact electrode is formed in the semiconductor device according to the first embodiment of the present invention. FIG. 14 is a partial cross-sectional view showing an example in which the contact electrode is a plurality of contact electrode members when silicide is formed after the contact electrode is formed in the semiconductor device according to the first embodiment of the present invention.

  The diameter when the contact electrode 6 is circular does not necessarily need to be smaller than the diameter when the pad electrode 5 is circular, and may be larger or the same. Since the resistance value between the contact electrode 6 and the pad electrode 5 is determined by the contact area between the contact electrode 6 and the pad electrode 5, this diameter is determined based on the contact area for achieving the target resistance value. .

  The first barrier layer 7 is formed of a laminated film of titanium, titanium nitride, titanium tungsten, tantalum, tantalum nitride, or a refractory metal in order to improve the adhesion between the first oxide film 8 and the contact electrode 6. Has been.

  The semiconductor substrate 2 is made of a material such as silicon, and may be conductive, insulating, or semi-insulating.

  The silicide layer 9 is formed on the contact electrode 6 on the surface 2a of the semiconductor substrate 2, and is formed of tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, or the like for the purpose of low resistance.

  The diameter when the silicide layer 9 is circular is not necessarily the same as the diameter when the contact electrode 6 is circular.

  The relationship between the width A of the silicide layer 9 and the width B of the bottom of the via hole 10 in the cross section (for example, FIG. 1) cut along the plane including the central axis of the via hole 10 is the following relationship (Equation 1). Like that. Specifically, the following relationship (Equation 1) is established between the diameter A when the silicide layer 9 is circular and the inner diameter B at the bottom of the via hole 10. This is because the silicide layer 9 can be reliably separated physically and electrically from the semiconductor substrate 2 if such a relational expression is established.

第２バリア層１３は、第２酸化膜１２と再配線層１４との密着性を高めるために、チタン、チタンナイトライド、チタンタングステン、タンタル、タンタルナイトライド、又は、高融点金属などの導電性材料の積層膜で形成されている。

The second barrier layer 13 is made of a conductive material such as titanium, titanium nitride, titanium tungsten, tantalum, tantalum nitride, or a refractory metal in order to improve the adhesion between the second oxide film 12 and the rewiring layer 14. It is formed of a laminated film of materials.

  Next, a method for manufacturing the semiconductor device 1 described above will be described with reference to the drawings. FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 3A to 4C illustrate steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG.

  First, as shown in FIG. 3A, a silicide layer 9, a first barrier layer 7, and a contact electrode 6 are formed in a first oxide film 8 on a surface 2a of a semiconductor substrate 2 on which an electronic circuit (not shown) is formed. Then, the pad electrode 5 and the passivation film 4 are formed (see step S1 in FIG. 2).

  The silicide layer 9 may be formed by heat-treating the first barrier layer 7, or after another film (for example, tungsten, titanium, cobalt, nickel, or the like) is formed on the surface 2a of the semiconductor substrate 2. By heat treatment, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, or the like may be formed. When the silicide layer 9 is formed on the surface 2a of the semiconductor substrate 2 by heat-treating the first barrier layer 7, the diameter when the silicide layer 9 is circular is equal to the hole diameter when the contact electrode 6 is circular. On the other hand, when the silicide layer 9 is formed on the surface 2a of the semiconductor substrate 2 by performing a heat treatment after depositing tungsten, titanium, cobalt, nickel, or the like, the diameter of the contact electrode 6 is circular when the silicide layer 9 is circular. In this case, the hole diameter may or may not be equal.

  And the support substrate 3 is adhere | attached on the passivation film 4 via an adhesive agent not shown (refer FIG. 3A).

  Next, as shown in FIG. 3B, a resist 15 is formed on the back surface 2b of the semiconductor substrate 2 in order to open a position corresponding to the pad electrode 5 (see step S2 in FIG. 2).

  Then, as shown in FIG. 3C, the via hole 10 reaching the silicide layer 9 and the first oxide film 8 is formed by etching the semiconductor substrate 2 using the resist 15 as a mask. Etching of the semiconductor substrate 2 may be wet etching or dry etching (see step S3 in FIG. 2).

  The silicide layer 9 is physically and electrically separated from the semiconductor substrate 2 by satisfying the relationship of (Formula 1) between the diameter A of the silicide layer 9 and the inner diameter B of the via hole 10. . The processing accuracy of the via hole 10 and the silicide layer 9 is different, and the variation of the inner diameter of the via hole 10 is about 1 μm, whereas the processing variation of the diameter of the silicide layer 9 is about 1 nm.

  Further, since the silicide layer 9 is exposed as a conductive layer by etching the semiconductor substrate 2, the etching of the first oxide film 8 is unnecessary.

  Next, as shown in FIG. 3D, the resist 15 is removed from the back surface 2b of the semiconductor substrate 2 (see step S4 in FIG. 2). The removal of the resist 15 may be a wet process or a dry process.

  Then, as shown in FIG. 4A, the second oxide film 12 is formed on the sidewall 10a of the via hole 10 and the back surface 2b of the semiconductor substrate 2 (see step S5 in FIG. 2). The formation of the second oxide film 12 may be a thermal oxidation method, a CVD method, or a sputtering method.

  Next, as shown in FIG. 4B, the silicide layer 9 is exposed again by etching the silicide layer 9 and the second oxide film 12 on the first oxide film 8 (see step S6 in FIG. 2). The second oxide film 12 on the first oxide film 8 may remain without being etched. The etching of the second oxide film 12 is preferably dry etching. This is because anisotropic etching is necessary to etch only the oxide film at the bottom of the via hole without etching the oxide film on the side wall of the via hole.

  Subsequently, as shown in FIG. 4C, the second barrier layer 13 and the redistribution layer 14 are formed (see step S7 in FIG. 2). The formation of the second barrier layer 13 may be a CVD method or a sputtering method. The rewiring layer 14 is formed by a plating method, but may be a CVD method, a sputtering method, or a combination thereof. The rewiring layer 14 may have a shape in which the via hole 10 is incompletely embedded or a shape in which the via hole 10 is completely embedded.

  Numerical examples of the semiconductor device 1 of the first embodiment are as follows. The thickness of the semiconductor substrate 2 is 250 μm, the thickness of the support substrate 3 is 500 μm, the thickness of the passivation film 4 is 1 μm, and the size of the pad electrode 5 is a square having a side of 150 μm (although not necessarily a square). The thickness is 500 nm, the diameter of the contact electrode 6 is 100 μm (not necessarily circular), the thickness is 1000 nm, the thickness of the first barrier layer 7 is 10 nm, the thickness of the first oxide film 8 is 1 μm, and the silicide. The thickness of the layer 9 is 10 nm, the diameter is 80 μm (not necessarily circular), the diameter of the via hole 10 is 200 μm (not necessarily circular), the thickness of the second oxide film 12 is 500 nm, The thickness of the 2 barrier layer 13 is 20 nm, the thickness of the rewiring layer 14 is 20 μm, and the thickness of the resist 15 is 20 μm.

  According to the configuration according to the first embodiment, the resistance value between the pad electrode 5 and the through electrode layer 11 depends on the diameter dimension of the silicide layer 9 and does not depend on the inner diameter dimension of the via hole 10. Therefore, the resistance value between the pad electrode 5 and the through electrode layer 11 is not affected by variations in the inner diameter of the via hole 10, and a semiconductor device having excellent reliability can be provided. The processing accuracy of the via hole 10 and the silicide layer 9 is different, and the variation of the inner diameter dimension of the via hole 10 is about 1 μm, whereas the processing variation of the diameter dimension of the silicide layer 9 is about 1 nm, which is different by three digits. Therefore, the semiconductor device 1 according to the first embodiment can reduce the variation in resistance value between the pad electrode 5 and the through electrode layer 11 as compared with the related art.

  Further, in the semiconductor device 1 according to the first embodiment, since the inner diameter of the via hole 10 can be made larger than the diameter of the pad electrode 5, the aspect ratio of the via hole 10 can be reduced. By reducing the size of the pad electrode 5, the area of a semiconductor chip as an example of a semiconductor device can be reduced. That is, in the first embodiment, if the aspect ratio between the dimension in the central axis direction (longitudinal direction) of the via hole 10 and the width of the bottom (for example, the diameter of the circular via hole 10) is set to be the same as the conventional one, the silicide layer 9 The width (for example, the diameter of the circular silicide layer 9) can be made smaller than the width of the bottom of the via hole 10, and the semiconductor chip area can be reduced. Conversely, if the width of the silicide layer 9 (for example, the diameter of the circular silicide layer 9) is set to be the same as the width of the connecting portion between the conventional pad electrode and the width (diameter) of the bottom of the via hole, the via hole 10 The width (diameter) may be larger than the conventional one, and the via hole 10 can be easily processed.

  On the other hand, in the conventional semiconductor device, even if the accuracy of the width (diameter) dimension of the bottom of the via hole is to be improved, the width (diameter) dimension of the bottom of the via hole cannot be controlled. Only the width (diameter) dimension of the opening side opposite to the bottom could be controlled. In general, a via hole generally has an inclined tapered side surface, so that it is very difficult to control the width (diameter) dimension of the bottom of the via hole.

(Modification 1 of Embodiment 1)
In the first embodiment, the first barrier layer 7 and the contact electrode 6 are formed separately. However, the present invention is not limited to this, and a modification 1 of the first embodiment is shown in FIG. 4D. In addition, the first barrier layer 7 and the contact electrode 6 may be integrated. That is, the first barrier layer 7 may be thinned or omitted. In describing the first modification, it is assumed that a laminated film in which a TiN layer and a Ti layer are laminated is used as an example of the first barrier layer 7.

The Ti layer of the first barrier layer 7 has a function of forming an ohmic contact (connection in which Ohm's law is established) with an Si substrate as an example of the semiconductor substrate 2, and the first oxide film 8 and the first barrier layer 7. It has a function of improving the adhesion with the TiN layer. As a function of forming an ohmic contact, for example, if a silicide layer 9 of TiSi ₂ is formed by a thermal reaction between Ti of the Ti layer and Si of the semiconductor substrate 2, an ohmic contact is obtained. If the silicide layer 9 is formed other than the first barrier layer 7, this Ti layer becomes unnecessary.

  The TiN layer of the first barrier layer 7 has a function of preventing diffusion of tungsten or the like of the contact electrode 6 to the semiconductor substrate 2 (Si substrate). If a contact electrode material that does not diffuse into the semiconductor substrate 2 (Si substrate) and has good adhesion can be used as the contact electrode 6, the TiN layer is unnecessary.

  Therefore, as described above, if the silicide layer 9 is formed other than the first barrier layer 7, the Ti layer of the first barrier layer 7 can be omitted and only the TiN layer can be formed. If a contact electrode material that does not diffuse into the semiconductor substrate 2 (Si substrate) and has good adhesion is used as the contact electrode 6, the TiN layer of the first barrier layer 7 can be omitted and only the Ti layer can be formed. . In the case where the silicide layer 9 is formed other than the first barrier layer 7 and a contact electrode material that does not diffuse into the semiconductor substrate 2 (Si substrate) and has good adhesion is used as the contact electrode 6, Only the contact electrode 6 can be formed without forming the barrier layer 7 itself (see FIG. 4D).

  Thus, forming the first barrier layer 7 and the contact electrode 6 separately is one means for solving the above-described problems in the manufacturing method. It is possible to reduce the thickness of the barrier layer 7 or to omit it, and the contact electrode 6 can be enlarged accordingly.

(Modification 2 of Embodiment 1)
In the first embodiment, the first barrier layer 7, the contact electrode 6 and the pad electrode 5 are separately formed. However, the present invention is not limited to this, and as a modification 2 of the first embodiment, FIG. As shown in 4E, the first barrier layer 7, the contact electrode 6, and the pad electrode 5 may be integrated. Since the integration of the first barrier layer 7 and the contact electrode 6 is the same as that of the first modification, the integration of the contact electrode 6 and the pad electrode 5 will be mainly described here.

  In the second modification, the contact electrode 6 is connected to the semiconductor substrate 2 (Si substrate) and the pad electrode 5 with low resistance. The pad electrode 5 is connected to the contact electrode 6 with a low resistance, and is necessary from the viewpoint of securing a flat portion when performing wire bonding. That is, by providing the pad electrode 5 separately from the contact electrode 6, the flatness can be improved as compared with the case where only the contact electrode 6 is used as the external electrode terminal.

  However, if it is connected to the semiconductor substrate 2 (Si substrate) with a low resistance, the contact electrode 6 and the pad electrode 5 may be integrated so that the pad electrode 5 has a convex longitudinal section as shown in FIG. 4E. It becomes possible. Further, when wire bonding is not used, the pad electrode 5 does not need to be flat.

  Thus, forming the first barrier layer 7, the contact electrode 6, and the pad electrode 5 separately is one means for solving the above-described problems in the manufacturing method, and therefore the above-mentioned problems can be solved respectively. Then, the first barrier layer 7, the contact electrode 6, and the pad electrode 5 can be formed integrally.

(Modification 3 of Embodiment 1)
In the first embodiment, the second barrier layer 13 and the redistribution layer 14 are formed separately. However, the present invention is not limited to this, and a modification 3 of the first embodiment is shown in FIG. 4F. As described above, the second barrier layer 13 and the rewiring layer 14 may be integrated. 4F is a diagram in which the third modification is applied to the second modification of FIG. 4E, but the present invention is not limited to this, and the third modification is not limited to the first embodiment or the first embodiment shown in FIG. 1 is also applicable.

  In the third modification, the second barrier layer 13 (for example, a layer made of Ti) has a function of preventing the redistribution layer 14 from diffusing into the semiconductor substrate 2 (Si substrate), the second oxide film 12 and the redistribution layer. 14 and the function of improving the adhesive strength with. Further, the rewiring layer 14 (for example, a layer made of Cu) has a low resistance and a function of mounting a solder ball. If a redistribution material having a function of preventing diffusion to the semiconductor substrate 2 (Si substrate) and good adhesion can be used as the redistribution layer 14, the second barrier layer 13 is not necessary, as shown in FIG. 4F. In addition, the rewiring layer 14 can be formed as thick as the second barrier layer 13.

  Thus, forming the second barrier layer 13 and the redistribution layer 14 separately is one means for solving the above-described problems in the manufacturing method. Therefore, if each of the above problems can be solved, It is also possible to form the second barrier layer 13 and the rewiring layer 14 integrally.

(Embodiment 2)
FIG. 5 is a partial cross-sectional view of the semiconductor device according to the second embodiment of the present invention. In FIG. 5, the same components as those in FIGS.

  A characteristic part of the second embodiment is that the silicide layer 9 is formed closer to the pad electrode 5 than the surface 2a of the semiconductor substrate 2 as compared with the first embodiment. The bottom electrode shape of the through electrode layer 11 connected to is convex downward. That is, in the second embodiment, the silicide layer 9 is located in the middle portion of the first oxide film 8 in the thickness direction, and the first barrier layer 7 and the contact electrode 6 are disposed on the outer surface side of the silicide layer 9. The center portion of the bottom portion of the through electrode layer 11 enters the inner surface side of the silicide layer 9. In contrast, in the first embodiment, since the silicide layer 9 is formed on the side farther from the pad electrode 5 than the surface 2a of the semiconductor substrate 2, the through electrode layer 11 connected to the silicide layer 9 is provided. The bottom shape is convex upward.

  Since the bottom shape of the through electrode layer 11 is convex downward in this manner, the manufacturing method of the semiconductor device 1 according to the second embodiment will be described with reference to the drawings. FIG. 6 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment, and FIGS. 7A to 8C are partial cross-sectional views for explaining the method for manufacturing a semiconductor device according to the second embodiment. 7A to 8C, the same components as those in FIGS. 1 to 4C are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 7A, a polysilicon film 16, a silicide layer 9, and a first barrier layer are formed in a first oxide film 8 on a surface 2a of a semiconductor substrate 2 on which an electronic circuit (not shown) is formed. 7 and the contact electrode 6 are formed, and then the pad electrode 5 and the passivation film 4 are formed (see step S11 in FIG. 6). The polysilicon film 16 is a film for forming silicide on the polysilicon film 16, and is unnecessary after the silicide is formed. However, it is not necessary to remove completely, and if it does not short-circuit with the Si substrate, there is no problem even if it remains after silicide formation.

  The polysilicon film 16 is preferably formed before the first oxide film 8 is formed, but may be formed after the first oxide film 8 is formed.

  The silicide layer 9 may be formed by heat-treating the first barrier layer 7 or after another film (for example, tungsten, titanium, cobalt, or nickel) is formed on the polysilicon film 16. By heat treatment, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, or the like may be formed. When the silicide layer 9 is formed on the polysilicon film 16 by heat-treating the first barrier layer 7, the diameter when the silicide layer 9 is circular is equal to the hole diameter when the contact electrode 6 is circular. On the other hand, when the silicide layer 9 is formed on the polysilicon film 16 by performing a heat treatment after forming tungsten, titanium, cobalt, nickel, or the like, the diameter of the contact electrode 6 is circular when the silicide layer 9 is circular. In this case, the hole diameter may or may not be equal.

  The contact electrode 6 may be composed of a single thick contact electrode member. Instead, as shown in FIGS. 15 to 16, the single contact electrode member 6 is divided into a plurality of thin contact electrode members 6A. A plurality of contact electrode members 6A may be used. The diameter when the contact electrode 6 is circular does not necessarily need to be smaller than the diameter when the pad electrode 5 is circular, and may be larger or the same. FIG. 15 is a partial cross-sectional view showing an example in which the contact electrode is a plurality of contact electrode members when silicide is formed before the contact electrode is formed in the semiconductor device according to the second embodiment of the present invention. FIG. 16 is a partial cross-sectional view showing an example in which the contact electrode is a plurality of contact electrode members when silicide is formed after the contact electrode is formed in the semiconductor device according to the second embodiment of the present invention.

  And the support substrate 3 is adhere | attached on the passivation film 4 via an adhesive agent not shown (refer FIG. 7A).

  Next, as shown in FIG. 7B, a resist 15 is formed on the back surface 2b of the semiconductor substrate 2 in order to open a position corresponding to the pad electrode 5 (see step S12 in FIG. 6).

  Then, as shown in FIG. 7C, the via hole 10 reaching the silicide layer 9 and the first oxide film 8 is formed by etching the semiconductor substrate 2 and the polysilicon film 16 using the resist 15 as a mask (FIG. 6). Step S13). Here, the bottom shape of the through electrode layer 11 connected to the silicide layer 9, which is a feature of the second embodiment, is downwardly convex. Etching of the semiconductor substrate 2 and the polysilicon film 16 may be wet etching or dry etching.

  By making the relationship of the above-mentioned (Formula 1) hold between the diameter A of the silicide layer 9 and the inner diameter B of the via hole 10, the silicide layer 9 is physically formed from the semiconductor substrate 2 and the polysilicon film 16. It is also electrically separated. The processing accuracy of the via hole 10, the silicide layer 9 and the polysilicon film 16 is different, and the variation in the inner diameter of the via hole 10 is about 1 μm, whereas the processing variation in the diameter of the silicide layer 9 is about 1 nm. Further, the processing variation of the diameter of the polysilicon film 16 is equivalent to that of the silicide layer 9 and is about 1 nm.

  Since the inner diameter of the via hole 10 can be made larger than the diameter of the pad electrode 5, the aspect ratio of the via hole 10 can be reduced. Further, by reducing the size of the pad electrode 5, the semiconductor device can be reduced. As an example, the area of a semiconductor chip can be reduced.

  Further, since the silicide layer 9 is exposed as a conductive layer by etching the semiconductor substrate 2 and the polysilicon film 16, the etching of the first oxide film 8 is unnecessary.

  Next, as shown in FIG. 7D, the resist 15 is removed from the back surface 2b of the semiconductor substrate 2 (see step S14 in FIG. 6). The removal of the resist 15 may be a wet process or a dry process.

  Then, as shown in FIG. 8A, the second oxide film 12 is formed on the side wall 10a of the via hole 10 and the back surface 2b of the semiconductor substrate 2 (see step S15 in FIG. 6). The formation of the second oxide film 12 may be a thermal oxidation method, a CVD method, or a sputtering method.

  Next, as shown in FIG. 8B, the silicide layer 9 is exposed again by etching the silicide layer 9 and the second oxide film 12 on the first oxide film 8 (see step S16 in FIG. 6). The second oxide film 12 on the first oxide film 8 may remain without being etched. Further, the second oxide film 12 formed on the side wall of the first oxide film 8 may be left without being etched. The etching of the second oxide film 12 is preferably dry etching.

  Subsequently, as shown in FIG. 8C, the second barrier layer 13 and the redistribution layer 14 are formed (see step S17 in FIG. 6). The formation of the second barrier layer 13 may be a CVD method, a sputtering method, or a combination thereof. The rewiring layer 14 is preferably formed by a plating method, but may be a CVD method, a sputtering method, or a combination thereof. The rewiring layer 14 may have a shape in which the via hole 10 is incompletely embedded or a shape in which the via hole 10 is completely embedded.

  In the numerical example of the semiconductor device 1 of the second embodiment, in addition to the numerical example of the first embodiment, the thickness of the polysilicon film 16 is 150 nm (with or without doping).

  According to the configuration according to the second embodiment, the resistance value between the pad electrode 5 and the through electrode layer 11 depends on the diameter dimension of the silicide layer 9 and does not depend on the inner diameter dimension of the via hole 10. Therefore, the resistance value between the pad electrode 5 and the through electrode layer 11 is not affected by variations in the inner diameter dimension of the via hole 10. The processing accuracy of the via hole 10 and the silicide layer 9 is different, and the variation of the inner diameter dimension of the via hole 10 is about 1 μm, whereas the processing variation of the diameter dimension of the silicide layer 9 is about 1 nm, which is different by three digits. Therefore, the semiconductor device 1 according to the second embodiment can reduce the variation in resistance value between the pad electrode 5 and the through electrode layer 11 as compared with the related art.

  Furthermore, since the semiconductor device 1 according to the second embodiment has a shorter contact electrode 6 between the pad electrode 5 and the first barrier layer 7 than the semiconductor device 1 according to the first embodiment, the pad The resistance value between the electrode 5 and the through electrode layer 11 can also be reduced.

  Also in the semiconductor device 1 according to the second embodiment, since the inner diameter of the via hole 10 can be made larger than the diameter of the pad electrode 5, the aspect ratio of the via hole 10 can be reduced. By reducing the size of the pad electrode 5, the area of a semiconductor chip as an example of a semiconductor device can be reduced. That is, also in the present second embodiment, if the aspect ratio between the dimension in the central axis direction (longitudinal direction) of the via hole 10 and the width of the bottom (for example, the diameter of the circular via hole 10) is set to be the same as the conventional one, the silicide layer 9 The width (for example, the diameter of the circular silicide layer 9) can be made smaller than the width of the bottom of the via hole 10, and the semiconductor chip area can be reduced. Conversely, if the width of the silicide layer 9 (for example, the diameter of the circular silicide layer 9) is set to be the same as the width of the connecting portion between the conventional pad electrode and the width (diameter) of the bottom of the via hole, the via hole 10 The width (diameter) may be larger than the conventional one, and the via hole 10 can be easily processed.

  On the other hand, in the conventional semiconductor device, even if the accuracy of the width (diameter) dimension of the bottom of the via hole is to be improved, the width (diameter) dimension of the bottom of the via hole cannot be controlled. Only the width (diameter) dimension of the opening side opposite to the bottom could be controlled. In general, a via hole generally has an inclined tapered side surface, so that it is very difficult to control the width (diameter) dimension of the bottom of the via hole.

  In the second embodiment, the same effect can be obtained even if the polysilicon film 16 is an amorphous silicon film or a single crystal silicon film.

(Modification 1 of Embodiment 2)
In the second embodiment, the first barrier layer 7 and the contact electrode 6 are formed separately. However, the present invention is not limited to this, and a modification 1 of the second embodiment is shown in FIG. 8D. In addition, the first barrier layer 7 and the contact electrode 6 may be integrated. That is, the first barrier layer 7 may be thinned or omitted. In describing the first modification, it is assumed that a laminated film in which a TiN layer and a Ti layer are laminated is used as an example of the first barrier layer 7.

The Ti layer of the first barrier layer 7 improves the function of forming an ohmic contact with an Si substrate as an example of the semiconductor substrate 2 and the adhesion between the first oxide film 8 and the TiN layer of the first barrier layer 7. It has a function to make it. As a function of forming an ohmic contact, for example, if a silicide layer 9 of TiSi ₂ is formed by a thermal reaction between Ti of the Ti layer and Si of the semiconductor substrate 2, an ohmic contact is obtained. If the silicide layer 9 is formed other than the first barrier layer 7, the Ti layer becomes unnecessary.

  The TiN layer of the first barrier layer 7 has a function of preventing diffusion of tungsten or the like of the contact electrode 6 to the semiconductor substrate 2 (Si substrate). If a contact electrode material that does not diffuse into the semiconductor substrate 2 (Si substrate) can be used as the contact electrode 6, the TiN layer is not necessary.

  Therefore, as described above, if the silicide layer 9 is formed other than the first barrier layer 7, the Ti layer of the first barrier layer 7 can be omitted and only the TiN layer can be formed. If a contact electrode material that does not diffuse into the semiconductor substrate 2 (Si substrate) and has good adhesion is used as the contact electrode 6, the TiN layer of the first barrier layer 7 can be omitted and only the Ti layer can be formed. . In the case where the silicide layer 9 is formed other than the first barrier layer 7 and a contact electrode material that does not diffuse into the semiconductor substrate 2 (Si substrate) and has good adhesion is used as the contact electrode 6, Only the contact electrode 6 can be formed without forming the barrier layer 7 itself (see FIG. 8D).

  Thus, forming the first barrier layer 7 and the contact electrode 6 separately is one means for solving the above-described problems in the manufacturing method. It is possible to reduce the thickness of the barrier layer 7 or to omit it, and the contact electrode 6 can be enlarged accordingly.

(Modification 2 of Embodiment 2)
In the second embodiment, the first barrier layer 7, the contact electrode 6 and the pad electrode 5 are separately formed. However, the present invention is not limited to this, and as a second modification of the second embodiment, FIG. As shown in 8E, the first barrier layer 7, the contact electrode 6, and the pad electrode 5 may be integrated. Since the integration of the first barrier layer 7 and the contact electrode 6 is the same as that of the first modification, the integration of the contact electrode 6 and the pad electrode 5 will be mainly described here. In the second modification, the contact electrode 6 is connected to the semiconductor substrate 2 (Si substrate) and the pad electrode 5 with low resistance. The pad electrode 5 is connected to the contact electrode 6 with a low resistance, and is necessary from the viewpoint of securing a flat portion when performing wire bonding. That is, by providing the pad electrode 5 separately from the contact electrode 6, the flatness can be improved as compared with the case where only the contact electrode 6 is used as the external electrode terminal. However, if it is connected to the semiconductor substrate 2 (Si substrate) with low resistance, the contact electrode 6 and the pad electrode 5 may be integrated so that the pad electrode 5 has a convex longitudinal section as shown in FIG. 8E. It becomes possible. Further, when wire bonding is not used, the pad electrode 5 does not need to be flat.

  Thus, forming the first barrier layer 7, the contact electrode 6, and the pad electrode 5 separately is one means for solving the above-described problems in the manufacturing method, and therefore the above-mentioned problems can be solved respectively. Then, the first barrier layer 7, the contact electrode 6, and the pad electrode 5 can be formed integrally.

(Modification 3 of Embodiment 2)
In the second embodiment, the second barrier layer 13 and the redistribution layer 14 are formed separately. However, the present invention is not limited to this, and a modification 3 of the second embodiment is shown in FIG. 8F. As described above, the second barrier layer 13 and the rewiring layer 14 may be integrated. 8F is a diagram in which the third modification is applied to the second modification in FIG. 8E. However, the present invention is not limited to this, and the third modification is not limited to the first embodiment or the embodiment described in FIG. 2 is also applicable.

  In the third modification, the second barrier layer 13 (for example, a layer made of Ti) has a function of preventing the redistribution layer 14 from diffusing into the semiconductor substrate 2 (Si substrate), the second oxide film 12 and the redistribution layer. 14 and the function of improving the adhesive strength with. Further, the rewiring layer 14 (for example, a layer made of Cu) has a low resistance and a function of mounting a solder ball. If a redistribution material having a function of preventing diffusion to the semiconductor substrate 2 (Si substrate) and good adhesion can be used as the redistribution layer 14, the second barrier layer 13 is not required, as shown in FIG. 8F. In addition, the rewiring layer 14 can be formed as thick as the second barrier layer 13.

  Thus, forming the second barrier layer 13 and the redistribution layer 14 separately is one means for solving the above-described problems in the manufacturing method. Therefore, if each of the above problems can be solved, It is also possible to form the second barrier layer 13 and the rewiring layer 14 integrally.

  It is to be noted that, by appropriately combining any of the above-described various embodiments, the effects possessed by them can be produced.

  The semiconductor device of the present invention has a highly reliable through electrode layer in which the resistance value between the pad electrode and the through electrode layer does not depend on the variation in the inner diameter of the via hole. The present invention can be widely applied to semiconductor devices for forming layers.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Support substrate 4 Passivation film 5 Pad electrode 6 Contact electrode 7 1st barrier layer 8 1st oxide film 9 Silicide layer 10 Via hole 10a Side wall 11 Through-electrode layer 12 2nd oxide film 13 2nd barrier layer 14 Rewiring layer 15 Resist 16 Polysilicon film 18 Electrode portion

Claims (13)

A first insulating film formed on the surface of the semiconductor substrate;
An electrode portion formed in the first insulating film and having an external connection terminal;
A via hole penetrating from the back surface of the semiconductor substrate to the front surface;
A second insulating film formed on a sidewall of the via hole and the back surface of the semiconductor substrate;
A through electrode layer formed on the second insulating film on the sidewall of the via hole, the second insulating film on the back surface of the semiconductor substrate, and the first insulating film on the bottom surface of the via hole;
A silicide layer formed between the electrode part and the through electrode layer and connected to the electrode part and the through electrode layer;
A semiconductor device, wherein a relation between a width A of the silicide layer and a width B of the bottom of the via hole in a cross section cut along a plane including the central axis of the via hole is A ≦ B. The semiconductor device according to claim 1, wherein the silicide layer and the electrode portion are connected via a contact electrode. 3. The semiconductor device according to claim 2, wherein the width of the silicide layer is equal to the width of the contact electrode in the plane including the central axis of the via hole. 4. The semiconductor device according to claim 1, wherein a width of the electrode portion is larger than a width of the bottom portion of the via hole in the plane including the central axis of the via hole. The electrode part is
A body portion of the electrode portion;
5. The semiconductor device according to claim 1, further comprising: a first barrier layer disposed between the main body portion of the electrode portion and the first insulating film. The electrode part is
A body portion of the electrode portion;
A first barrier layer disposed between the main body portion of the electrode portion and the first insulating film and in contact with the silicide layer;
The pad electrode part which is arrange | positioned on the outer surface side of the said 1st insulating film and is arranged in the outer surface of the said main-body part of the said electrode part, and functions as the said external connection terminal is provided. The semiconductor device described in one. The semiconductor device according to claim 1, wherein the silicide layer is formed on any one of the semiconductor substrate, a polysilicon film, and an amorphous silicon film. The semiconductor device according to claim 1, wherein the silicide layer is made of tungsten silicide, titanium silicide, cobalt silicide, or nickel silicide. 9. The semiconductor device according to claim 7, wherein the main body portion of the electrode portion is made of tungsten, aluminum, an alloy thereof, or copper. The semiconductor device according to claim 6 , wherein the first barrier layer is made of a laminated film of titanium, titanium nitride, titanium tungsten, tantalum, tantalum nitride, or a refractory metal. The through electrode layer includes:
A second barrier layer formed on the second insulating film on the side wall of the via hole, the second insulating film on the back surface of the semiconductor substrate, and the first insulating film on the bottom surface of the via hole;
A rewiring layer formed on the second barrier layer,
The said 2nd barrier layer consists of a laminated film of titanium, titanium nitride, titanium tungsten, tantalum, tantalum nitride, or a refractory metal, It is any one of Claims 1-10 characterized by the above-mentioned. Semiconductor device. The semiconductor device according to claim 1, wherein the electrode unit is configured by a single contact electrode member or a plurality of contact electrode members. 7. The pad electrode according to claim 6, wherein the pad electrode is made of aluminum, copper, or an alloy thereof, and titanium, titanium nitride, tantalum, tantalum nitride, a refractory metal, or a compound thereof. Semiconductor device.

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