JP5456887B2 - Power converter - Google Patents

Description

  The present invention relates to a technique for storing power supplied from a DC power supply having a maximum power point in a storage battery.

  FIG. 1A shows an output current-output voltage characteristic of a general solar cell, and FIG. 1B shows an output current-output power characteristic. As shown in FIG. 1A, the output voltage of the solar cell has a characteristic that gradually decreases as the output current increases, but rapidly decreases when the output current exceeds a predetermined value. From such characteristics, as shown in FIG. 1B, the output power P (= output voltage V × output current I) increases until the output current reaches a predetermined value, but exceeds the predetermined value. And decreases rapidly. Even when the voltage is considered as a reference, the output power P rapidly decreases when a predetermined voltage value is exceeded.

  A DC power source such as a solar cell having such characteristics needs to efficiently use output power. For this reason, it is necessary for the above-described DC power supply to transmit power to a load such as a storage battery at the maximum power point at which the power is maximum. That is, maximum power point tracking control is required, and there are several techniques for this purpose.

  For example, Japanese Patent Application Laid-Open No. 63-57807 discloses a maximum point tracking method that detects the output voltage and output current of a solar cell and uses the differential value of the output voltage. This technique utilizes the fact that the differential value at the maximum power point is zero, detects the voltage and current when a slight displacement is applied to the control signal at the current operating point, and analog / digital (A / D) ) After conversion, a differential value of power is obtained by calculation, and control is performed so that this differential value of power becomes zero. This technology is expensive because it requires a microcomputer and a DSP (Digital Signal Processor) for A / D conversion and computation.

  Japanese Patent Laid-Open No. 62-85312 discloses a maximum power point tracking method using a so-called hill-climbing method. In this method, the voltage and current values at two points are measured, the power at each point is calculated, the power values are compared, the control point is moved to the higher power value, and the control point moving direction is It is a control method that stabilizes at the point of alternately rising and falling. In this control method, the amount of movement cannot be increased because the amount of movement of the control point continues to fluctuate across the maximum power point. If the movement amount is too small, it takes time to move the control point to the vicinity of the maximum power point, and it becomes impossible to follow the change in the output power characteristics of the solar cell.

  Furthermore, Japanese Patent Laid-Open No. 7-072941 discloses a method in which three or more voltage / current points are detected, the respective powers are calculated, the maximum power point is estimated by an approximate expression, and control is performed at this estimated point. Yes. This method is a method of calculating each power from three or more voltage / current values according to a change in characteristics of the solar cell and finding a provisional maximum power point by an approximate expression. However, according to this method, it is necessary that at least one voltage current point exceeds the maximum power point, and at least one voltage current point does not exceed the maximum power point. There is. Therefore, it is necessary to move the control point to such a voltage / current point, and the control circuit for that purpose becomes complicated and expensive.

  Japanese Laid-Open Patent Publication No. 7-129264 discloses a method of tracking the maximum power point by detecting the operating point position from the fluctuation tendency of the output voltage of the solar cell and the output current of the power converter. In this method, because the output voltage of the solar cell and the output current of the power conversion unit tend to fluctuate by ΔV with respect to the command value for controlling the power conversion unit, the output change amount of the power conversion unit is digital. Will fluctuate. This is because, with respect to the characteristic change of the solar cell due to changes in the amount of solar radiation, etc., if ΔV is large, the output change amount of the power conversion unit will be large, so flapping will occur. If ΔV is small, it will take time to stabilize Therefore, there is a problem that the fixed ΔV cannot be controlled quickly and stably. Further, since the command value is changed after detecting the operating position of the solar cell from the fluctuation tendency, the delay becomes large and the responsiveness is poor.

  In addition, a storage battery such as a lead storage battery or a lithium ion secondary battery is often connected to a solar battery or the like, but a technique for efficiently storing electricity in the storage battery has not been studied.

JP-A 63-57807 JP-A-62-85312 Japanese Patent Application Laid-Open No. 7-072941 JP 7-129264 A

  As described above, the conventional technology efficiently stores power output from a DC power source such as a solar battery or a wind power generator whose output power fluctuates according to weather conditions or the like according to the characteristics of the storage battery. Such a system is not described.

  Accordingly, an object of the present invention is to provide a technique for efficiently storing electric power output from a DC power source such as a solar battery or a wind power generator whose output power fluctuates according to weather conditions or the like according to characteristics of the storage battery. It is to be.

  A power conversion device according to one aspect of the present invention includes: (A) a D / D converter circuit that DC / DC converts an output voltage from a DC power supply having a maximum power point and outputs the converted voltage to a storage battery; A storage battery charging current detection circuit for detecting a current value of a current flowing in a storage battery storing power output from the D converter circuit; and (C) tracking the maximum power point according to the output voltage of the D / D converter circuit. And a voltage control circuit for controlling the D / D converter circuit, and (D) controlling the D / D converter circuit so that the current value becomes constant according to the current value detected by the storage battery charging current detection circuit. The constant current control circuit and (E) if the storage battery is being charged and the current value detected by the storage battery charging current detection circuit is less than a predetermined value, the control of the voltage control circuit is enabled, the storage battery is being charged and the storage battery is charged Current detection times Current value detected is a control switching circuit for enabling the control of the constant current control circuit when a predetermined value or more by the.

  By performing such control switching, charging can be performed efficiently not only when sufficient power is supplied from the DC power supply but also when power is not sufficiently supplied from the DC power supply. .

  Moreover, you may make it the power converter device mentioned above further have a storage battery voltage detection circuit which detects the output voltage of a storage battery. In that case, the control switching circuit described above may be configured such that the current value detected by the storage battery charging current detection circuit is not less than a predetermined value and the output voltage detected by the storage battery voltage detection circuit is not less than the second predetermined value. If the control of the voltage control circuit is validated and the current value detected by the storage battery charging current detection circuit is equal to or greater than a predetermined value and the output voltage detected by the storage battery voltage detection circuit is less than the second predetermined value, it is determined. You may make it validate control of a current control circuit.

  Even when sufficient power is supplied from the DC power supply, it is preferable to switch the control during full charge and during charge.

  Furthermore, the power conversion device described above may further include a storage battery voltage detection circuit that detects an output voltage of the storage battery. At this time, the fact that the storage battery is being charged may be specified by the output voltage detected by the storage battery voltage detection circuit being less than the second predetermined value. If it does in this way, a charge condition can be detected correctly.

  Furthermore, the power converter described above may further include an output voltage detection circuit that outputs an output signal having a voltage corresponding to the output voltage of the D / D converter circuit. The voltage control circuit described above includes a constant voltage control circuit that controls the D / D converter circuit according to a difference between the voltage of the output signal of the output voltage detection circuit and a reference comparison voltage, and a constant voltage control An adjustment circuit for forcibly narrowing the potential difference between the voltage of the output signal of the output voltage detection circuit and the reference comparison voltage when the voltage of the output signal of the output voltage detection circuit decreases despite the control by the circuit. May be.

  By employing such a voltage control circuit, the maximum power point can be traced with an inexpensive circuit.

  Further, the adjustment circuit described above is in a state where the duty ratio of the signal for controlling the switching of the switch included in the D / D converter circuit becomes a predetermined maximum value in accordance with the voltage drop of the output signal of the output voltage detection circuit. A duty ratio maximum detection circuit to detect, and a voltage adjustment circuit that changes the voltage of the output signal of the output voltage detection circuit or a reference comparison voltage in accordance with the frequency or rate at which the detection signal is output within a predetermined period from the duty ratio maximum detection circuit You may make it have.

  By introducing the duty ratio maximum detection circuit in this way, it becomes possible to easily identify the situation in which power is drawn from the DC power supply beyond the maximum power point. In addition, since the frequency or rate at which the detection signal is output from the maximum duty ratio detection circuit within a predetermined period corresponds to the degree exceeding the maximum power point, the voltage or reference voltage of the output voltage detection circuit is appropriately set. Will be able to adjust.

  Further, the voltage adjustment circuit described above may include a circuit that switches to discharge from the discharge circuit for a period according to the frequency or ratio of the detection signal output from the maximum duty ratio detection circuit within a predetermined period. Adjustment is smoothly performed according to the time constant of the discharge circuit.

  Further, the voltage adjusting circuit described above includes a first inverting circuit for inverting the polarity of the output signal of the output voltage detecting circuit, and a voltage for the output signal of the first inverting circuit from the duty ratio maximum detecting circuit. Is inverted according to the frequency or rate at which the signal is output within a predetermined period, and the second inverter circuit that inverts the polarity of the output signal of the first inverter circuit whose voltage is reduced by the inverter signal adjusting circuit. You may do it. In this way, the voltage of the output signal of the output voltage detection circuit can be adjusted appropriately.

  In addition, when the detection signal is output from the maximum duty ratio detection circuit, the adjustment circuit described above includes a limit circuit that controls the switching of the switch included in the D / D converter circuit and limits the power supplied. Further, it may be included.

  When the output voltage of the D / D converter circuit decreases, the constant voltage control circuit controls to increase the ON period of the switch of the D / D converter circuit. However, as described above, in a situation where the power is drawn beyond the maximum power point, the switch ON period is shortened as described above, and the target output of the D / D converter circuit is quickly reached. If the voltage is lowered, maximum power point tracking is performed at high speed.

  Further, the constant voltage control circuit described above compares the error voltage corresponding to the difference between the voltage of the output signal of the output voltage detection circuit and the reference comparison voltage with a predetermined triangular wave signal, and the error voltage is You may make it include the circuit which produces | generates the signal which turns on the switch contained in a D / D converter circuit during the period exceeding the voltage of a triangular wave signal. At this time, the adjustment circuit described above may further include a limiting circuit that lowers the error voltage according to the frequency or rate at which the detection signal is output from the maximum duty ratio detection circuit within a predetermined period.

  By introducing such a limiting circuit, an OFF period of the switch of the D / D converter circuit is formed at an appropriate timing, so that power consumption can be reduced.

  Furthermore, the adjustment circuit described above may gradually decrease the amount of change after forcibly changing the voltage of the output signal of the output voltage detection circuit or the reference comparison voltage. In this way, the extent to which power is drawn beyond the maximum power point is gradually reduced.

  Hereinafter, one aspect of the present invention described above will be described more specifically, but the present invention is not limited to the following description.

FIGS. 1 (a) and 1 (b) are schematic diagrams showing characteristics of solar cells. FIG. 2 is a functional block diagram of the system according to the first embodiment. 3 (a) and 3 (b) are diagrams for explaining the charging method of the rechargeable battery. FIG. 4 is a diagram for explaining control switching for the storage battery. FIG. 5 is a diagram illustrating another example of the voltage control circuit. FIG. 6 is a functional block diagram of a system according to the second embodiment. FIG. 7 is a diagram illustrating an example of the function f. FIG. 8 is a functional block diagram of a system according to the third embodiment. FIGS. 9 (a) and (b) are schematic diagrams showing the characteristics of the solar cell. FIGS. 10A to 10D are waveform diagrams for explaining the operation of the system according to the third embodiment. FIG. 11 is a diagram illustrating a circuit example according to an example of the third embodiment. FIG. 12 is a diagram illustrating a circuit example according to an example of the third embodiment. FIGS. 13A to 13G are waveform diagrams showing the operation of the circuit according to the example of the third embodiment. FIGS. 14A to 14H are waveform diagrams showing the operation of the circuit according to the example of the third embodiment. FIGS. 15A to 15H are waveform diagrams showing the operation of the circuit according to the example of the third embodiment. FIGS. 16A to 16G are waveform diagrams showing the operation of the circuit according to the example of the third embodiment. FIGS. 17A to 17I are waveform diagrams showing the operation of the circuit according to the example of the third embodiment. FIG. 18 is a diagram illustrating another example of the third embodiment. FIG. 19 is a functional block diagram of a system according to the fourth embodiment. FIG. 20 is a diagram illustrating a specific circuit example according to an example of the fourth embodiment. FIGS. 21A to 21G are waveform diagrams for explaining the operation of the example of the fourth embodiment. 22A to 22I are waveform diagrams for explaining the operation of the example of the fourth embodiment. FIG. 23 is a functional block diagram of a system according to the fifth embodiment. 24A to 24E are waveform diagrams for explaining the operation of the system according to the fifth embodiment. FIG. 25 is a diagram illustrating a specific circuit example according to an example of the fifth embodiment. FIGS. 26A to 26G are waveform diagrams for explaining the operation of a specific circuit example according to the example of the fifth embodiment. FIGS. 27A to 27I are waveform diagrams for explaining the operation of a specific circuit example according to the example of the fifth embodiment. FIG. 28 is a diagram illustrating another specific circuit example of the example according to the fifth embodiment. FIG. 29 is a functional block diagram of a system according to the sixth embodiment. FIG. 30 is a diagram illustrating a specific circuit example of the example according to the sixth embodiment. FIGS. 31A to 31G are waveform diagrams for explaining the operation of a specific circuit example according to the example of the sixth embodiment. FIGS. 32A to 32I are waveform diagrams for explaining the operation of a specific circuit example according to the example of the sixth embodiment. FIG. 33 is a functional block diagram of a system according to the seventh embodiment. FIG. 34 is a diagram illustrating a specific circuit example of the example according to the seventh embodiment. FIGS. 35A to 35I are waveform diagrams showing the operation of the circuit according to the example of the seventh embodiment. FIG. 36 is a functional block diagram of a system according to the eighth embodiment. FIG. 37 is a diagram showing a specific circuit example of the example according to the eighth embodiment.

[Embodiment 1]
In FIG. 2, the functional block diagram of the system containing the power converter device which concerns on this Embodiment is shown. That is, the system shown in FIG. 2 is a solar cell system, and is connected to the output of the solar cell 100, the power conversion device 1000 that performs power conversion on the output from the solar cell 100, and the output of the power conversion device 1000. A load storage battery 300 and various loads A to C. The solar cell 100 and the load storage battery 300 are the same as the conventional one. Further, the loads A to C are a device with a D / D converter circuit, a device with a D / A inverter circuit, and the like, and these are the same as conventional ones. Note that the solar cell 100 is an example, and may be another natural energy generator such as a wind power generator.

  The power conversion apparatus 1000 includes (A) a D / D converter circuit 110 that DC / DC converts an output voltage from the solar battery 100, and (B) an output signal having a voltage corresponding to the output voltage of the D / D converter circuit 110. An output voltage detection circuit 120 for outputting, (C) a storage battery charging current detection circuit 130 for detecting a current flowing in the load storage battery 300, (D) a storage battery voltage detection circuit 140 for detecting a charging voltage for the load storage battery 300, and (E ) A control switching circuit 150 that outputs a control switching instruction according to the output from the storage battery charging current detection circuit 130 and the output from the storage battery voltage detection circuit 140; and (F) according to the output from the storage battery charging current detection circuit 130. A constant current control circuit 160 for performing constant current control on the D / D converter circuit 110 and (G) an output from the output voltage detection circuit 120. A voltage control circuit 170 for controlling the D / D converter circuit 110 so as to perform maximum power point tracking (MPPT), and (H) a voltage control circuit in accordance with an instruction from the control switching circuit 150 170 or a switching circuit 180 that outputs the output from the constant current control circuit 160 to the D / D converter circuit 110.

  Next, FIG. 3A shows an example of a charging method for a lithium ion secondary battery. In FIG. 3A, the horizontal axis represents time, and the vertical axis represents charging voltage or current. As can be seen from FIG. 3A, the charging current is controlled to be constant until the battery is fully charged. At this time, the voltage rises while drawing a curve as shown. On the other hand, when the battery is fully charged, the charging voltage is controlled to be constant. As a result, the charging current rapidly decreases. Similarly, FIG. 3B shows an example of a charging method for a control valve type lead-acid battery. Similar to FIG. 3A, also in FIG. 3B, the horizontal axis represents time, and the vertical axis represents charging voltage or current. Basically, lead-acid batteries are charged in the same manner as lithium ion secondary batteries.

  Considering such a charging method of the load storage battery 300 and the power supply state of the solar battery 100, it is possible to efficiently store electricity by performing control switching as shown in FIG. That is, constant voltage control is performed when the generated power of the solar battery 100 is sufficient (when the generated power is satisfied) and the load storage battery 300 is fully charged. However, the MPPT does not operate when the full-charge voltage is the target voltage for voltage control. Further, when the generated power of the solar battery 100 is sufficient (when the generated power is satisfied) and the load storage battery 300 is being charged (that is, charging is not completed), constant current control is performed. That is, when sufficient power is supplied from the solar battery 100, the control is switched as shown by the bidirectional arrow A in FIG. 4 between when the battery is fully charged and when it is not fully charged.

  Furthermore, when the generated power of the solar battery 100 is not sufficient (when the generated power is insufficient) and the load storage battery 300 is fully charged, constant voltage control with MPPT is performed. Further, when the generated power of the solar battery 100 is insufficient (when the generated power is insufficient) and the load storage battery 300 is being charged (that is, charging is not completed), constant voltage control with MPPT is performed. Thus, when the generated power of the solar cell 100 is not sufficient (when the generated power is insufficient), it is not necessary to switch control.

  However, when the load storage battery 300 is being charged, the control is switched as shown by the bidirectional arrow B in FIG. 4 depending on whether the generated power of the solar battery 100 is sufficient or not. In particular, since the control switching indicated by the bidirectional arrow B is being charged, the charging is efficiently performed by switching appropriately.

  Next, the operation of the power conversion apparatus 1000 shown in FIG. 2 will be described. The storage battery voltage detection circuit 140 detects the charging voltage of the load storage battery 300 and outputs a voltage signal corresponding to the charging voltage to the control switching circuit 150. The storage battery charging current detection circuit 130 detects the current value of the charging current of the load storage battery 300 and outputs a voltage signal corresponding to the current value to the control switching circuit 150 and the constant current control circuit 160.

  If the control switching circuit 150 indicates that charging is in progress from at least the output from the storage battery voltage detection circuit 140, indicates that the output from the storage battery charging current detection circuit 130 is in a state of less than a predetermined current value. Alternatively, it is confirmed whether or not the current state is equal to or greater than a predetermined current value. If the electric power supplied from the solar battery 100 is sufficient, it indicates that the output from the storage battery charging current detection circuit 130 is in a state of a predetermined current value or more. Therefore, the control switching circuit 150 is required to perform constant current control. The switching circuit 180 is instructed to output the output from the constant current control circuit 160 to the D / D converter circuit 110. In response to this instruction, the switching circuit 180 performs switching so as to output the output from the constant current control circuit 160 to the D / D converter circuit 110.

  The constant current control circuit 160 controls the D / D converter circuit 110 according to the value detected by the storage battery charging current detection circuit 130 according to the output from the storage battery charging current detection circuit 130. .

  On the other hand, if the power supplied from the solar battery 100 is insufficient, the output from the storage battery charging current detection circuit 130 is in a state of less than a predetermined current value. Accordingly, the control switching circuit 150 instructs the switching circuit 180 to output the output from the voltage control circuit 170 to the D / D converter circuit 110 in order to perform constant voltage control with MPPT. In response to this instruction, the switching circuit 180 performs switching so as to output the output from the voltage control circuit 170 to the D / D converter circuit 110.

  The voltage control circuit 170 controls the D / D converter circuit 110 so as to perform MPPT using the output from the output voltage detection circuit 120 or the like. The voltage control circuit 170 in the present embodiment may be any circuit. A circuit as specifically described in the following embodiment may be employed.

  For example, from FIGS. 3A and 3B, if the voltage of the output signal from the storage battery voltage detection circuit 140 is less than a predetermined voltage, it is considered that charging is in progress, and the voltage is equal to or higher than the predetermined voltage. If there is, it may be considered that the battery is fully charged.

  In addition, when the control switching circuit 150 finds that the power supplied from the solar battery 100 is sufficient from at least the output of the storage battery charging current detection circuit 130, the output from the storage battery voltage detection circuit 140 is less than a predetermined voltage. It is confirmed whether or not it indicates that the voltage is higher than a predetermined voltage. When the battery is fully charged, it indicates that the output from the storage battery voltage detection circuit 140 is equal to or higher than a predetermined voltage. Therefore, in order to perform constant voltage control with MPPT, the control switching circuit 150 includes a switching circuit 180, Instructs the D / D converter circuit 110 to output the output from the voltage control circuit 170. In response to this instruction, the switching circuit 180 performs switching so as to output the output from the voltage control circuit 170 to the D / D converter circuit 110.

  On the other hand, when the battery is not fully charged but is being charged, it indicates that the output from the storage battery voltage detection circuit 140 is less than a predetermined voltage. Accordingly, the control switching circuit 150 instructs the switching circuit 180 to output the output from the constant current control circuit 160 to the D / D converter circuit 110 in order to perform constant current control. In response to this instruction, the switching circuit 180 performs switching so as to output the output from the constant current control circuit 160 to the D / D converter circuit 110.

  In addition, for example, if the voltage of the output signal from the storage battery charging current detection circuit 130 is equal to or higher than a predetermined voltage (that is, a predetermined current value or higher), the power supply from the solar cell 100 is regarded as sufficient, If it is less than a predetermined voltage (that is, less than a predetermined current value), it may be considered that power is insufficient.

  By performing such control switching, it is possible to efficiently store electricity in the storage battery.

[Modification of Embodiment 1]
For example, a circuit as shown in FIG. 5 may be adopted for the voltage control circuit 170 in FIG. That is, the voltage control circuit 170 outputs an instruction signal to the switching circuit 180 according to the difference between the voltage of the output signal of the output voltage detection circuit 120 and the reference voltage. The configuration is that the constant voltage control circuit 1712 that controls the D / D converter circuit 110 and the output voltage detection circuit 120 when the voltage of the output signal of the output voltage detection circuit 120 decreases despite the control by the constant voltage control circuit 1712. And an adjustment circuit 1711 for forcibly narrowing the potential difference between the output signal voltage and the reference voltage.

  In the case of a DC power supply having a maximum power point such as the solar battery 100, the constant voltage control circuit 1712 drives the D / D converter circuit 110 in an attempt to extract power beyond the power supply capability of the solar battery 100. As a result, the output voltage of the D / D converter circuit 110 is lowered despite the control by the constant voltage control circuit 1712, and the voltage of the output signal of the output voltage detection circuit 120 is also lowered.

  Thus, when the voltage of the output signal of the output voltage detection circuit 120 decreases, the adjustment circuit 1711 forcibly narrows the potential difference between the voltage of the output signal of the output voltage detection circuit 120 and the reference voltage. Then, the constant voltage control circuit 1712 determines that the effect of its own control has appeared, and returns the drive of the D / D converter circuit 110 to the state before the voltage drop of the output signal of the output voltage detection circuit 120. That is, a phenomenon occurs in which the target output voltage of the D / D converter circuit 110 is lowered. As a result, the power drawn from the solar cell 100 is also reduced below its power supply capability, so that the output voltage of the D / D converter circuit 110 rises.

  Such an operation is repeated to track the maximum power point of the solar cell 100. In addition, since such a power conversion device can be configured without using expensive elements such as a microprocessor and a DSP, a circuit can be manufactured at low cost.

[Embodiment 2]
FIG. 6 shows a functional block diagram of a system according to the second embodiment. That is, the system shown in FIG. 6 is a solar cell system, and performs power conversion on the solar cell 100, a power detection circuit 200 that detects output power from the solar cell 100, and an output from the solar cell 100. Of the power conversion device 3000, the storage battery charge / discharge control circuit 400 that performs charge / discharge control for the load storage battery 300 and the output of signals required by the power conversion device 3000 by the output from the power conversion device 3000, and the storage battery charge / discharge control circuit 400 A load storage battery 300 connected to the output and various loads A to C are included. The solar cell 100 and the load storage battery 300 are the same as the conventional one. Also, the loads A to C are the same as those in the first embodiment.

  The power detection circuit 200 includes a solar cell voltage detection circuit 201 that detects an output voltage from the solar cell 100, a solar cell current detection circuit 202 that detects an output current from the solar cell 100, a solar cell voltage detection circuit 201, and a solar cell. A power calculation circuit 203 that calculates power from the output of the battery current detection circuit 202, a memory circuit 204 that stores a power value calculated by the power calculation circuit 203, and a power value calculated by the power calculation circuit 203 A power change amount calculation circuit 205 that calculates a power change amount from the power value one unit time before stored in the memory circuit 204;

  The power conversion device 3000 also includes a D / D converter circuit 310 that DC / DC converts the output voltage from the solar battery 100, and an output voltage that outputs an output signal having a voltage corresponding to the output voltage of the D / D converter circuit 310. A detection circuit 320, a voltage error detection circuit 350 that generates a signal corresponding to the difference between the voltage of the output signal of the output voltage detection circuit 320 and the reference voltage, and an initial reference voltage according to the output from the power variation calculation circuit 205 The reference voltage adjustment circuit 360 that outputs the adjusted reference voltage to the voltage error detection circuit 350, and the voltage according to the difference between the output of the storage battery charging current from the storage battery charge / discharge control circuit 400 and the reference current value A current error detection circuit 340 for generating a current error signal and a current error detection circuit 340 or a voltage error detection according to a control switching signal from the storage battery charge / discharge control circuit 400 In response to the output from the switching circuit 370 for switching the output of the path 350 and the current error detection circuit 340 or the voltage error detection circuit 350, a drive signal for the D / D converter circuit 310 is generated and output to the D / D converter circuit 310. Drive signal generation circuit 330.

  The storage battery charge / discharge control circuit 400 includes a storage battery voltage detection circuit 410 that detects a supply voltage to the storage battery, and a full charge protection circuit 420 that performs a full charge protection operation for the load storage battery 300 according to an output from the storage battery voltage detection circuit 410. The overdischarge protection circuit 430 that performs the overdischarge protection operation of the load storage battery 300 according to the output from the storage battery voltage detection circuit 410, the storage battery charge current detection circuit 450 that detects the current flowing through the load storage battery 300, and the full charge protection And a control switching circuit 440 that outputs a signal for switching between constant current control and constant voltage control in accordance with the output from the circuit 420 and the output from the storage battery charging current detection circuit 450.

  The power detection circuit 200, the reference voltage adjustment circuit 360, the voltage error detection circuit 350, and the drive signal generation circuit 330 described above constitute a voltage control circuit that realizes MPPT. The current error detection circuit 340 and the drive signal generation circuit 330 constitute a constant current control circuit.

  Next, the operation of the power detection circuit 200 shown in FIG. 6 will be described. The solar cell voltage detection circuit 201 detects the output voltage Vpv from the solar cell 100 and outputs it to the power calculation circuit 203. The solar cell current detection circuit 202 detects the output current Ipv from the solar cell 100 and outputs it to the power calculation circuit 203. The power calculation circuit 203 calculates power Po = voltage Vpv × current Ipv, stores it in the memory circuit 204, and outputs it to the power change amount calculation circuit 205. The power calculation circuit 203 includes an A / D conversion circuit and calculates the power Po as a digital value. The power change amount calculation circuit 205 calculates a difference ΔP = Po−P1 between the power Po calculated this time and the power P1 one unit time before stored in the memory circuit 204, and uses the ΔP as the reference voltage adjustment circuit 360. Output to.

  Next, the operation of the power conversion device 3000 will be described. The reference voltage adjustment circuit 360 of the power conversion device 3000 calculates a reference voltage based on ΔP received from the power change amount calculation circuit 205 and outputs the reference voltage to the voltage error detection circuit 350.

  More specifically, if ΔP> 0, the reference voltage adjustment circuit 360 calculates the reference voltage value V_Vref = V_Vref + f (| ΔP |) × fixed voltage change amount ΔVref, and uses the reference voltage V_Vref as the voltage error detection circuit 350. Output to. Note that f (| ΔP |) is, for example, a function as shown in FIG. In the example of FIG. 7, the function f is, for example, a function proportional to | ΔP | or a quadratic function of | ΔP |. Other functions may be adopted. Here, the next reference voltage value V_Vref is calculated by adding f (| ΔP |) as a gain and adding the product of the gain and the fixed voltage change amount ΔVref to the immediately preceding reference voltage value V_Vref. The reference voltage adjustment circuit 360 includes a D / A conversion circuit, generates a signal of the reference voltage V_Vref from the D / A conversion circuit, and outputs the signal to the voltage error detection circuit 350. Note that the reference voltage adjustment circuit 360 is configured to initially output V_Vref = initial reference voltage Vref_0. Further, it is assumed that the maximum value of the reference voltage V_Vref is the initial reference voltage Vref_0.

  If ΔP = 0, the reference voltage adjustment circuit 360 maintains and outputs the current reference voltage value V_Vref.

  Further, if ΔP <0, the reference voltage adjustment circuit 360 calculates the reference voltage value V_Vref = V_Vref−f (| ΔP |) × fixed voltage change amount ΔVref, and supplies the reference voltage V_Vref to the voltage error detection circuit 350. Output.

  The voltage error detection circuit 350 generates a signal corresponding to the difference between the voltage of the signal from the output voltage detection circuit 320 and the reference voltage V_Vref from the reference voltage adjustment circuit 360 and outputs the signal to the switching circuit 370. In this way, when the output of the voltage error detection circuit 350 is selected by the switching circuit 370, the reference voltage V_Vref can be generated so as to track the maximum power point.

  As described above, the current error detection circuit 340 generates a signal of a voltage corresponding to the difference between the voltage corresponding to the storage battery charging current from the storage battery charging / discharging control circuit 400 and the reference current value, and supplies the signal to the switching circuit 370. Output. That is, when the output of the current error detection circuit 340 is selected by the switching circuit 370, control is performed so that the current flowing through the load storage battery 300 is constant.

  The drive signal generation circuit 330 generates a drive signal for the D / D converter circuit 310 according to the output signal from the current error detection circuit 340 or the voltage error detection circuit 350 output from the switching circuit 370, and the D / D converter circuit. It outputs to 310.

  Next, the operation of the storage battery charge / discharge control circuit 400 will be described. The storage battery voltage detection circuit 410 detects a supply voltage to the load storage battery 300 and outputs a voltage signal corresponding to the supply voltage to the full charge protection circuit 420 and the overdischarge protection circuit 430. When the full charge protection circuit 420 receives a signal from the storage battery voltage detection circuit 410 and detects that the voltage of the signal has reached the voltage at the time of full charge, the full charge protection circuit 420 cuts off the power supply to the load storage battery 300 and the control switching circuit. A switching signal is output to 440. This switching signal is a switching instruction from constant current control to constant voltage control, as shown in FIG. If the power supply from solar cell 100 is sufficient, the charging current is equal to or greater than a predetermined value, so control switching is not performed in control switching circuit 440. If the power supply is not sufficient, the charging current is less than a predetermined value even when fully charged and the charging voltage does not increase, so that the full charge protection circuit 420 does not output a switching signal.

  Conversely, when full charge is no longer full charge, full charge protection circuit 420 starts supplying power to load storage battery 300 and outputs a switching signal to control switching circuit 440. This switching signal is a switching signal for switching from constant voltage control to constant current control. Similarly, the control switching circuit 440 outputs a switching signal for switching from constant voltage control to constant current control to the switching circuit 370.

  Further, when the overdischarge protection circuit 430 receives a signal from the storage battery voltage detection circuit 410 and detects that the voltage of the signal has reached a voltage at which discharge may be started, the overdischarge protection circuit 430 starts discharging to the load A or the like. . On the other hand, when the voltage at which discharge may be started has not been reached, the overdischarge protection circuit 430 stops the discharge.

  Furthermore, storage battery charging current detection circuit 450 detects the charging current output from D / D converter circuit 310 and flows to load storage battery 300, and outputs a voltage signal corresponding to the detected charging current to control switching circuit 440. . Control switching circuit 440 outputs a switching signal to switching circuit 370 when detecting that the voltage corresponding to the charging current is lower than the voltage for detecting the shortage of supply power. This switching signal serves as a switching instruction from constant current control to constant voltage control while the load storage battery 300 is being charged. During charging, the voltage detected by the storage battery voltage detection circuit 410 remains low, and the full charge protection circuit 420 does not output a switching signal.

  Conversely, when control switching circuit 440 detects that the voltage corresponding to the charging current exceeds the voltage indicating that the supplied power has become sufficiently large, control switching circuit 440 outputs a switching signal to switching circuit 370. This switching signal serves as a switching instruction from constant voltage control to constant current control while the load storage battery 300 is being charged.

  At the time of full charge, as described above, the full charge protection circuit 420 operates and the power supply to the load storage battery 300 is stopped. Therefore, the current value output from the storage battery charge current detection circuit 450 remains low. Yes, even if the power supply from the solar cell 100 changes, the constant voltage control is maintained.

  In this way, control as shown in FIG. 4 is realized, and power storage is performed efficiently. In addition, the full charge protection circuit 420 and the overdischarge protection circuit 430 operate appropriately, and power storage and discharge are performed safely.

  The control switching circuit 440 detects a low current detection circuit that detects a shortage of supply power, a detection signal that indicates a shortage of supply power from the low current detection circuit, and a full charge from the full charge protection circuit 420. In some cases, an OR circuit that calculates a logical sum with a signal indicating the above may be included. In this way, when shortage of supply power is detected or when full charge is detected, a switching signal for switching from constant current control to constant voltage control is output to the switching circuit 370. On the other hand, if the supplied power is sufficient and charging is in progress, a switching signal for switching from constant voltage control to constant current control is output to switching circuit 370.

[Embodiment 3]
FIG. 8 shows a functional block diagram of a system according to the third embodiment. The system shown in FIG. 8 is a solar cell system, which includes a solar cell 100, a power conversion device 500 that performs power conversion on the output from the solar cell 100, and an output from the power conversion device 500 for the load storage battery 300. A storage battery charge / discharge control circuit 600 that outputs signals necessary for the charge / discharge control and power converter 500, a load storage battery 300 connected to the output of the storage battery charge / discharge control circuit 600, and various loads A to C, etc. Have The solar cell 100 and the load storage battery 300 are the same as the conventional one. Also, the loads A to C are the same as those in the first embodiment.

  The power conversion device 500 includes (A) a D / D converter circuit 510 having a switch and DC / DC converting the output voltage from the solar cell 100, and (B) depending on the output voltage of the D / D converter circuit 510. An output voltage detection circuit 520 that outputs a voltage output signal; (C) a voltage error detection circuit 550 that generates a signal A2_Out corresponding to the difference between the voltage Vo_fb of the output signal of the output voltage detection circuit 520 and the reference voltage V_Vref; A current error detection circuit 540 that generates a voltage signal corresponding to the difference between the voltage Vbi_fb corresponding to the storage battery charge current from the storage battery charge / discharge control circuit 600 and the voltage corresponding to the reference current value; and (D) storage battery charge / discharge control. A switching circuit 580 for switching the output of the current error detection circuit 540 or the voltage error detection circuit 550 in response to the control switching signal Pul_CV from the circuit 600, and (E) the current error detection circuit 5 0 or a drive signal generation circuit 530 that generates a switching pulse for the switch of the D / D converter circuit 510 according to the output from the voltage error detection circuit 550 and outputs the switching pulse to the D / D converter circuit 510; and (F) drive signal generation A DutyMax detection circuit 560 that receives a signal Duty according to the duty ratio of the switching pulse from the circuit 530 and detects that the duty ratio has reached a predetermined maximum value, and (G) according to a detection signal from the DutyMax detection circuit 560 A reference voltage adjustment circuit 570 that adjusts the initial reference voltage Vref_1 and outputs the adjusted reference voltage V_Vref to the voltage error detection circuit 550.

  The storage battery charge / discharge control circuit 600 performs (A) a storage battery voltage detection circuit 610 that detects a supply voltage to the storage battery, and (B) a full charge protection operation for the load storage battery 300 according to the output from the storage battery voltage detection circuit 610. A full charge protection circuit 620, (C) an overdischarge protection circuit 630 that performs an overdischarge protection operation on the load storage battery 300 according to the output from the storage battery voltage detection circuit 610, and (D) a current Vbi_fb flowing through the load storage battery 300. In order to switch between constant current control and constant voltage control with MPPT according to the storage battery charging current detection circuit 650 to be detected and (E) the output Pul_FC from the full charge protection circuit 620 and the output Vbi_fb from the storage battery charging current detection circuit 650 And a control switching circuit 640 for outputting the signal Pul_CV.

  The output voltage detection circuit 520, voltage error detection circuit 550, drive signal generation circuit 530, DutyMax detection circuit 560, and reference voltage adjustment circuit 570 described above constitute a constant voltage control circuit that realizes MPPT. The current error detection circuit 540 and the drive signal generation circuit 530 constitute a constant current control circuit.

  Next, the operation of the storage battery charge / discharge control circuit 600 shown in FIG. 8 will be described. The operation of storage battery charge / discharge control circuit 600 is the same as that described in the second embodiment in that it is implemented in the form according to FIG.

  The storage battery voltage detection circuit 610 detects the supply voltage to the load storage battery 300 and outputs a voltage signal Vbv_fb corresponding to the supply voltage to the full charge protection circuit 620 and the overdischarge protection circuit 630. When the full charge protection circuit 620 receives the signal Vbv_fb from the storage battery voltage detection circuit 610 and detects that the voltage of the signal Vbv_fb has reached the full charge voltage, the full charge protection circuit 620 cuts off the power supply to the load storage battery 300 and performs control. A switching signal Pul_FC is output to the switching circuit 640. This switching signal Pul_FC is an instruction to switch from constant current control to constant voltage control with MPPT as shown in FIG. 4 when there is sufficient power supply from solar cell 100. In response to the switching signal Pul_FC, the control switching circuit 640 outputs a switching signal Pul_CV for switching from constant current control to constant voltage control with MPPT to the switching circuit 580. If the power supply from solar cell 100 is sufficient, the charging current is equal to or greater than a predetermined value, so control switching is not performed in control switching circuit 640. If the power supply is not sufficient, the charging current is less than a predetermined value even when fully charged and the charging voltage does not increase, so that the full charge protection circuit 620 does not output the switching signal Pul_FC.

  On the other hand, when full charge is no longer full charge, full charge protection circuit 620 starts supplying power to load storage battery 300 and outputs switch signal Pul_FC to control switch circuit 640. This switching signal Pul_FC is a switching signal for switching from constant voltage control with MPPT to constant current control. Similarly, the control switching circuit 640 uses a switching signal Pul_CV for switching from constant voltage control with MPPT to constant current control. Output to the switching circuit 580.

  Further, when the overdischarge protection circuit 630 receives a signal from the storage battery voltage detection circuit 610 and detects that the voltage of the signal has reached a voltage at which discharge may be started, the overdischarge protection circuit 630 starts discharging to the load A or the like. . On the other hand, when the voltage at which discharge can be started has not been reached, the overdischarge protection circuit 630 stops the discharge.

  Further, the storage battery charging current detection circuit 650 detects the charging current output from the D / D converter circuit 510 and flows to the load storage battery 300, and outputs a signal of the voltage Vbi_fb corresponding to the detected charging current to the control switching circuit 640. To do. When the control switching circuit 640 detects that the voltage Vbi_fb corresponding to the charging current is lower than the voltage for detecting the shortage of supply power (for example, Pul_LC is output internally), the control switching circuit 640 generates the switching signal Pul_CV. Output to 580. This switching signal Pul_CV is an instruction to switch from constant current control to constant voltage control with MPPT while the load storage battery 300 is being charged. During charging, the voltage detected by the storage battery voltage detection circuit 610 remains low and the full charge protection circuit 620 does not output the switching signal Pul_FC.

  Conversely, when the control switching circuit 640 detects that the voltage Vbi_fb corresponding to the charging current exceeds the voltage indicating that the supplied power has become sufficiently large, the control switching circuit 640 outputs the switching signal Pul_CV to the switching circuit 580. This switching signal Pul_CV serves as a switching instruction from constant voltage control with MPPT to constant current control while the load storage battery 300 is being charged.

  At the time of full charge, as described above, the full charge protection circuit 620 operates and power supply to the load storage battery 300 is stopped. Along with this, the current value output from the storage battery charging current detection circuit 650 remains low, and even if the power supply from the solar battery 100 changes, constant voltage control with MPPT is maintained.

  In this way, control as shown in FIG. 4 is realized, and power storage is performed efficiently. In addition, the full charge protection circuit 620 and the overdischarge protection circuit 630 operate appropriately, and power storage and discharge are performed safely.

  The control switching circuit 640 includes a low current detection circuit that detects a shortage of power supply, and a detection signal that indicates a shortage of power supply from the low current detection circuit, for example, Pul_LC and a full charge protection circuit described above. It may have an OR circuit that calculates a logical sum with a signal Pul_FC indicating that full charge from 620 has been detected. In this way, when the supply power shortage is detected or when full charge is detected, the switching signal Pul_CV for switching from constant current control to constant voltage control is output to the switching circuit 580. On the other hand, if supply power is sufficient and charging is in progress, switching signal Pul_CV for switching from constant voltage control with MPPT to constant current control is output to switching circuit 580.

  Further, the current error detection circuit 540 generates a signal A1_Out of a voltage corresponding to the difference between the voltage Vbi_fc corresponding to the storage battery charging current from the storage battery charge / discharge control circuit 600 and the voltage corresponding to the reference current value, and the switching circuit Output to 580. That is, when the output of current error detection circuit 540 is selected by switching circuit 580, drive signal generation circuit 530 switches D / D converter circuit 510 so that the current flowing through load storage battery 300 is constant. A switching pulse Pul that turns on is generated.

  Next, with reference to FIGS. 9 and 10, constant voltage control performed with the power conversion apparatus 500 illustrated in FIG. 8 and accompanied by MPPT will be described. The output power from the solar cell 100 is Ppv, the output voltage of the power converter 500 is Vo, the output power is Pout, the output from the drive signal generation circuit 530 to the DutyMax detection circuit 560 is Duty, the initial reference voltage is Vref_1, the reference The output voltage from the voltage adjustment circuit 570 to the voltage error detection circuit 550 is represented as V_Vref.

  FIG. 9A is basically the same as FIG. 1B and shows the relationship between the output current I and the output power P of the solar cell 100. To explain again, when the output current I is increased up to the current Ipv_max, the output power P itself increases, and at the current Ipv_max, the output power P becomes the maximum power point Ppv_max, and when the output power P becomes equal to or greater than the current Ipv_max, the output power P suddenly increases. Decrease. That is, when the current Ipv_max is exceeded, the sudden decrease in the output power P indicates that the output voltage V is also decreasing.

  Here, a power point corresponding to a current value significantly lower than the current Ipv_max is A, a power point corresponding to a current value near the current Ipv_max is C, and a power point corresponding to a current value near the current Ipv_max Is B. Note that power points that do not completely coincide with the power point B but have substantially the same current value are represented as B1 and B2. Further, power points that do not completely coincide with the power point C but have substantially the same current value are represented as C1, C2, and so on. Further, the maximum power point Ppv_max is simply expressed as M. Note that FIG. 9B is exactly the same as FIG.

  FIGS. 10A to 10D show constant voltage control with MPPT in power conversion device 500 according to the present embodiment. In the waveform diagrams for explaining the operation below, the horizontal axis represents time, and the vertical axis mainly represents voltage [V]. However, in the case of electric power, it represents W, and in the case of a duty ratio, it represents%. FIG. 10A shows temporal changes in the output power Ppv from the solar cell 100 and the output voltage Pout of the power conversion device 500. Since there is a loss due to power conversion device 500, the relationship Ppv> Pout always holds. For comparison, the maximum power point Ppv_max is also shown. FIG. 10B shows a change over time in the output voltage Vo of the power conversion device 500. FIG. 10C shows a change over time of the reference voltage V_Vref from the reference voltage adjustment circuit 570. An initial reference voltage Vref_1 is also shown for comparison. FIG. 10D shows the change over time of the output duty of the drive signal generation circuit 530. Note that a maximum value DutyMax predetermined for the output duty is also shown for comparison.

  First, the D / D converter circuit 510, the output voltage detection circuit 520, and the voltage error detection are performed until the output power from the solar battery 100 reaches the power point M from the power smaller than the power point A to the power point A. The circuit 550 and the drive signal generation circuit 530 operate normally. That is, the reference voltage adjustment circuit 570 outputs the initial reference voltage Vref_1 as it is without doing anything (FIG. 10 (c)), and V_Vref = Vref_1, and the voltage error detection circuit 550 includes the reference voltage V_Vref and the output voltage detection circuit. A signal A2_Out corresponding to the difference from the output Vo_fb of 520 is output to the drive signal generation circuit 530 via the switching circuit 580. The drive signal generation circuit 530 generates a switching pulse Pul according to the signal A2_Out, and performs switching so that the switch of the D / D converter circuit 510 is turned on.

  Specifically, if power is drawn from the solar cell 100 beyond the power point A, the output Vo_fb of the output voltage detection circuit 520 is lowered simply by driving the D / D converter circuit 510 as before. . Then, the voltage error detection circuit 550 and the drive signal generation circuit 530 operate so as to gradually increase the duty ratio of the switching pulse and the duty voltage for the switch of the D / D converter circuit 510 as shown in FIG. To do. In this way, as shown in FIG. 10B, the output voltage Vo of the power conversion device 500 is kept constant.

  Thereafter, when the power drawn from the solar cell 100 reaches the power point M, the output power Ppv from the solar cell 100 decreases as shown in FIG. 10A, and accordingly, the output power Pout of the power converter 500 is reduced. Also decreases. Further, as can be seen from FIG. 9B, the output voltage Vo also decreases. Then, the voltage error detection circuit 550 detects that the difference between Vo_fb and V_Vref has increased, and outputs a signal A2_Out corresponding to the difference to the drive signal generation circuit 530. The drive signal generation circuit 530 increases the duty ratio of the switching pulse to the switch of the D / D converter circuit 510 and the voltage of the signal Duty to DutyMax in response to the signal A2_Out.

  When such a situation occurs, the DutyMax detection circuit 560 detects that the voltage of the signal Duty has reached DutyMax, and outputs a detection signal to the reference voltage adjustment circuit 570. The reference voltage adjustment circuit 570 adjusts the initial reference voltage Vref_1 to be lowered according to the detection signal from the DutyMax detection circuit 560, and outputs the adjusted voltage V_Vref to the voltage error detection circuit 550. This state is shown in FIG. The reduction width of the reference voltage V_Vref is determined according to the frequency or the rate at which the detection signal is output from the DutyMax detection circuit 560 within a predetermined period.

  As shown in FIG. 10A, when the voltage error detection circuit 550 and the drive signal generation circuit 530 drive the D / D converter circuit 510 too much, the power drawn from the solar cell 100 also decreases, and the power The actual output power Ppv of the solar cell 100 is balanced at the power point B. As a result, the output voltage Vo and the output power Pout of the power conversion device 500 stop decreasing.

  Also, as shown in FIG. 10D, the voltage error detection circuit 550 detects that the difference between Vo_fb and V_Vref is small, and outputs a signal A2_Out corresponding to the difference to the drive signal generation circuit 530. The drive signal generation circuit 530 reduces the duty ratio of the switching pulse with respect to the switch of the D / D converter circuit 510 and the voltage of the signal Duty. Then, the current drawn from the solar cell 100 is reduced by driving the D / D converter circuit 510 by the voltage error detection circuit 550 and the drive signal generation circuit 530. However, since the decrease width of the current drawn from the solar cell 100 is usually a little larger, it passes through the maximum power point M and returns to the power point C as shown in FIG. Then, as shown in FIG. 10A, during this time, the output power Ppv of the solar cell 100 once increases but decreases again. The output voltage Vo of the power conversion device 500 gradually increases at the drive level of the D / D converter circuit 510 during this period.

  As shown in FIG. 10C, the adjustment of the reference voltage V_Vref by the reference voltage adjustment circuit 570 is delayed, and even if the DutyMax detection circuit 560 decreases the voltage of the signal Duty from the DutyMax, the adjustment is finished immediately. In addition, since there is a time constant for returning to the initial reference voltage Vref_1, the reference voltage V_Vref gradually increases.

  Thereafter, as shown in FIG. 10 (d), the voltage error detection circuit 550 and the drive signal generation circuit 530 drive the D / D converter circuit 510 according to the difference between Vo_fb and the reference voltage V_Vref to thereby form the solar cell 100. The duty ratio of the switching pulse to the switch of the D / D converter circuit 510 and the voltage of the signal Duty are increased so as to draw more power from

  Then, as shown in FIG. 10A, the output power Ppv of the solar cell 100 rises and reaches the power point M again. The subsequent operation is almost the same as that after the power point M is first reached. However, as shown in FIG. 10C, the reference voltage V_Vref has not returned to the initial reference voltage Vref_1, and the output voltage Vo of the power converter 500 has not reached the target value. The reduction width of the voltage V_Vref is slightly different. Since the operations are not completely the same as described above, the on-curve operation in FIG. 9A is switched at C1 and C2 instead of the power point C and at B1 and B2 instead of the power point B.

  After all, the power point B or its vicinity and the power point C or its vicinity are moved back and forth across the maximum power point. That is, maximum power point tracking is possible. The operation described above is based on the assumption that the generated power of the solar cell 100 is constant. However, since the generated power is generally not constant, the maximum power point itself varies, but the operation is the same.

  The difference between power point B and power point C is determined according to the output power and output voltage, but can be adjusted by gain adjustment of a control system including D / D converter circuit 510 and the like. That is, it can be operated near the maximum power point.

[Example of Embodiment 3]
11 and 12 show specific circuit examples according to the third embodiment.

  FIG. 11 shows a specific circuit example of the solar battery 100, a specific circuit example of the D / D converter circuit 510, a specific circuit example of the output voltage detection circuit 520, a specific circuit example of the load storage battery 300, and a storage battery. Specific circuit example of voltage detection circuit 610, specific circuit example of full charge protection circuit 620, specific circuit example of overdischarge protection circuit 630, specific circuit example of control switching circuit 640, and storage battery charging current detection A specific circuit example of the circuit 650 is shown.

  Solar cell 100 includes a current source Icc, a diode D1, and resistors R1 and R2. The anode of the diode D1 and one end of the resistor R1 and one end of R2 are connected to the positive terminal of the current source Icc, and the negative terminal of the current source Icc is grounded together with the cathode of the diode D1 and the other end of the resistor R2. It is connected to the. The other end of the resistor R1 is connected to the D / D converter circuit 510.

  Although the D / D converter circuit 510 in FIG. 11 is shown as a step-up chopper circuit, a half-bridge circuit method, a full-bridge circuit method, a push-pull circuit method, a forward circuit method, a flyback method, a step-down chopper circuit, a SEPIC, With a buck-boost circuit such as a Cuk converter or a Zeta converter, an insulating type or a non-insulating type can be selected according to the application.

  The D / D converter circuit 510 includes back-flow preventing diodes D2 and D3, an electrolytic capacitor C1, a capacitor C2, a coil L1, an n-type FET (S1) switched by the drive signal generation circuit 530, a resistance R3. The anode of the diode D2 is connected to the resistor R1 of the solar cell 100, and the cathode of the diode D2 is connected to the + terminal of the electrolytic capacitor C1 and one end of the coil L1. The negative terminal of the electrolytic capacitor C1 is grounded. The other end of the coil L1 is connected to the drain terminal of the FET (S1) and the anode of the diode D3. The source terminal of the FET (S1) is grounded, and the gate terminal of the FET (S1) is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the output of the drive signal generation circuit 530 via the connection terminal A. The cathode of the diode D3 is connected to one end of the capacitor C2 and the output voltage detection circuit 520. The other end of the capacitor C2 is grounded.

  Output voltage detection circuit 520 includes resistors R4 and R5 for detecting a feedback voltage by resistance division. One end of the resistor R4 is connected to the D / D converter circuit 510 and the load storage battery 300. The other end of the resistor R4 is connected to the voltage error detection circuit 550 via one end of the resistor R5 and the connection terminal B. The other end of the resistor R5 is grounded.

  The output voltage detection circuit 520 is further connected to a full charge protection circuit 620, a storage battery voltage detection circuit 610, and a load such as a DC / AC inverter circuit.

  The load storage battery 300, the DC / AC inverter circuit corresponding to the loads A to C, the D / D converter circuit, and other loads are the same as those in the related art, and the description thereof is omitted.

  The storage battery charging current detection circuit 650 includes a resistor R602. One end of the resistor R602 is connected to the negative terminal of the load storage battery 300, the negative input terminal of the comparator 641 of the control switching circuit 640, and the current error detection circuit 540, and the other end of the resistor R602 is grounded.

  The storage battery voltage detection circuit 610 includes resistors R603 and R604 for detecting a charging voltage by resistance division. One end of the resistor R603 is connected to the positive terminal of the load storage battery 300, and the other end of the resistor R603 is connected to one end of the resistor R604 and inputs of the full charge protection circuit 620 and the overdischarge protection circuit 630. The other end of the resistor R604 is grounded.

  The full charge protection circuit 620 includes resistors R606 to R608 that are shared by the p-type FET (S61), the resistor R601, the comparator 621, and the overdischarge protection circuit 630 and generate a reference voltage by resistance division. And have. One end of the resistor R601 is connected to the output voltage detection circuit 520 and the drain terminal of the FET (S61), and the other end of the resistor R601 is connected to the gate terminal of the FET (S61) and the output of the comparator 621. Yes. The positive input terminal of the comparator 621 is connected to the storage battery voltage detection circuit 610, and the negative input terminal of the comparator 621 is connected to one end of the resistor R606 and one end of the resistor R607. The other end of the resistor R606 is connected to the power source, and the other end of the resistor R607 is connected to one end of the resistor R608 and the positive input terminal of the comparator 631 of the overdischarge protection circuit 630. The other end of the resistor R608 is grounded. The output terminal of the comparator 621 is connected to the control switching circuit 640.

  When the voltage detected by the storage battery voltage detection circuit 610 increases and reaches the voltage at the time of full charge generated by the resistance division constituted by the resistors R606 to R608, the output of the comparator 621 becomes high, and the FET (S61 ) Is turned off, so that power storage in the load storage battery 300 is stopped. The output terminal of the comparator 621 is connected to the control switching circuit 640, and instructs the control switching circuit 640 to switch to constant voltage control with MPPT.

  The overdischarge protection circuit 630 is shared by the comparator 631, the p-type FET (S62), the resistor R605, and the full-charge protection circuit 620, and resistors R606 to R608 for generating a reference voltage by resistance division. And have. The negative input terminal of the comparator 631 is connected to the connection point of the resistors R603 and R604, and the positive input terminal of the comparator 631 is connected to the connection point of the resistors R607 and R608. The output terminal of the comparator 631 is connected to the gate terminal of the FET (S62) and one end of the resistor R605. The other end of the resistor R605 is connected to the positive terminal of the storage battery 300, one end of the resistor R603, and the drain terminal of the FET (S62). The source terminal of the FET (S62) is connected to the load side. In addition, the load side and the output voltage detection circuit 520 side are connected by bypass.

  When the voltage detected by the storage battery voltage detection circuit 610 decreases and reaches the voltage for determining discharge stop generated by the resistance division constituted by the resistors R606 to R608, the output of the comparator 631 becomes high, and the FET Since (S62) is turned off, discharging from the load storage battery 300 to a load such as a DC / AC inverter circuit is stopped.

  The control switching circuit 640 includes a low current detection circuit and an OR circuit 642. The low current detection circuit includes resistors R609 and R610 for generating a reference voltage for detecting a decrease in supply power by resistance division, and a comparator 641. One end of the resistor R609 is connected to the power source, and the other end of the resistor R609 is connected to the positive input terminal of the comparator 641 and one end of the resistor R610. The other end of the resistor R610 is grounded. The negative input terminal of the comparator 641 is connected to the storage battery charging current detection circuit 650. The output terminal of the comparator 641 is connected to the first input terminal of the OR circuit 642. The second input terminal of the OR circuit 642 is connected to the output terminal of the comparator 621 of the full charge protection circuit 620. The output terminal of the OR circuit 642 is connected to the switching circuit 580 via the connection terminal D.

  The output of the comparator 641 becomes high when the supply power shortage is detected, and the output of the comparator 621 becomes high when full charge is detected. Therefore, the output of the OR circuit 642 becomes high when a shortage of supply power is detected or when a full charge is detected. When the output of the OR circuit 642 is high, the constant voltage control with MPPT is instructed, and when the output is low, the constant current control is instructed.

  Next, specific circuit examples of the current error detection circuit 540, the voltage error detection circuit 550, the DutyMax detection circuit 560, the reference voltage adjustment circuit 570, the switching circuit 580, and the drive signal generation circuit 530 will be described with reference to FIG.

  The voltage error detection circuit 550 is connected to the output voltage detection circuit 520 via the connection terminal B, and includes resistors R11 to R14, capacitors C11 and C12, and an operational amplifier 551. The output of the output voltage detection circuit 520 is connected to one end of the resistors R11 and R12, the other end of the resistor R11 is connected to one end of the capacitor C11, and the other end of the capacitor C11 and the other end of the resistor R12 are the negative electrode of the operational amplifier 551. Is connected to the side input terminal. The negative input terminal of the operational amplifier 551 is connected to one end of the capacitor C12 and one end of the resistor R13, the other end of the capacitor C12 is connected to one end of the resistor R14, and the other end of the resistor R14 and the other end of the resistor R13. The end is connected to the output terminal of the operational amplifier 551. Further, the output of the reference voltage adjustment circuit 570 is connected to the positive input terminal of the operational amplifier 551.

  The current error detection circuit 540 is connected to the storage battery charging current detection circuit 650 via the connection terminal C, and outputs resistors R541 to R544, capacitors C541 and C542, an operational amplifier 541, and a voltage corresponding to the reference current value. DC power supply I_Vref is provided. The output of the storage battery charging current detection circuit 650 is connected to one ends of resistors R541 and R542, the other end of the resistor R542 is connected to one end of the capacitor C541, and the other end of the capacitor C541 and the other end of the resistor R541 are connected to the operational amplifier 541. Connected to the negative input terminal. Further, the negative input terminal of the operational amplifier 541 is connected to one end of the capacitor C542 and one end of the resistor R543, and the other end of the capacitor C542 is connected to one end of the resistor R544. The other end of the resistor R544 and the other end of the resistor R543 are connected to the output terminal of the operational amplifier 541. Furthermore, the positive input terminal of the operational amplifier 541 is connected to the positive terminal of the DC power supply I_Vref that outputs a voltage corresponding to the reference current value. The negative terminal of the DC power supply I_Vref is grounded.

  Switching circuit 580 includes analog switches 582 and 583 and a NOT circuit 581. The output of the OR circuit 642 of the control switching circuit 640 is connected to the input terminal of the NOT circuit 581 and the control terminal of the analog switch 583 via the terminal D. The output terminal of the NOT circuit 581 is connected to the control terminal of the analog switch 582. The output of the current error detection circuit 540 is connected to the input side terminal of the analog switch 582, and the output side terminal of the analog switch 582 is connected to the drive signal generation circuit 530. The output of the voltage error detection circuit 550 is connected to the input side terminal of the analog switch 583, and the output side terminal of the analog switch 583 is connected to the drive signal generation circuit 530.

  When the output of the OR circuit 642 of the control switching circuit 640 becomes high, the output of the NOT circuit 581 becomes low, so that the analog switch 582 remains off, but the analog switch 583 turns on. As a result, the output from the voltage error detection circuit 550 is output to the drive signal generation circuit 530. Conversely, when the output of the OR circuit 642 of the control switching circuit 640 becomes low, the output of the NOT circuit 581 becomes high, so that the analog switch 582 is turned on. As a result, the output of the current error detection circuit 540 is output to the drive signal generation circuit 530, but the analog switch 583 is turned off.

  Drive signal generation circuit 530 includes a comparator 531 and a triangular wave generator 532. The output of the switching circuit 580 is connected to the positive input terminal of the comparator 531, and the triangular wave generator 532 is connected to the negative input terminal of the comparator 531. The output terminal of the comparator 531 is connected to the gate terminal of the FET (S1) of the D / D converter circuit 510 via the connection terminal A.

  The DutyMax detection circuit 560 includes a comparator 561, resistors R15 and R16, a capacitor C13, and a DC power supply Vref_2 that outputs a voltage Vref_2. The positive input terminal of the comparator 561 is connected to the output of the switching circuit 580, and the negative input terminal of the comparator 561 is connected to the positive terminal of the DC power source Vref_2. The negative terminal of the DC power supply Vref_2 is grounded. The output of the comparator 561 is connected to one end of the resistor R15, and the other end of the resistor R15 is connected to one end of the resistor R16, one end of the capacitor C13, and the input of the reference voltage adjustment circuit 570. The other end of the resistor R16 and the other end of the capacitor C13 are grounded.

  The DutyMax detection circuit 560 operates effectively while the constant voltage control with MPPT is enabled and the output of the voltage error detection circuit 550 is output to the drive signal generation circuit 530. More specifically, the comparator 561 includes an input signal to the drive signal generation circuit 530, that is, an output signal A2_Out (here, “= A_Out”) of the voltage error detection circuit 550 and a switching pulse that is an output of the drive signal generation circuit 530. Compared with the output voltage Vref_2 of the DC power supply Vref_2 that outputs substantially the same voltage as the voltage of the input signal input to the drive signal generation circuit 530 when the duty ratio of the signal becomes the maximum. When the voltage of the input signal A_Out becomes higher than the voltage Vref_2, the comparator 561 outputs the pulse wave DMC_O1 during that time. However, a low-pass filter is connected to the output of the comparator 561, and the output pulse wave is output to the reference voltage adjustment circuit 570 as a smooth signal DMC_O2.

  The reference voltage adjustment circuit 570 includes a comparator 571, a triangular wave generator 572, resistors R17 to R21, an n-type FET (S11), a DC power supply Vref_1 that outputs an initial reference voltage Vref_1, and capacitors C14 and C15. Have. The output of the DutyMax detection circuit 560 is connected to the positive input terminal of the comparator 571, and the triangular wave generator 572 is connected to the negative input terminal of the comparator 571. One end of the resistor R17 is connected to the output of the comparator 571, and the other end of the resistor R17 is connected to one end of the resistor R18, one end of the capacitor C14, and the gate terminal of the FET (S11). The other end of the resistor R18, the other end of the capacitor C14, and the source terminal of the FET (S11) are grounded. The positive terminal of the DC power supply Vref_1 is connected to one end of the resistor R19, and the negative terminal is grounded. The other end of the resistor R19 is connected to one end of the resistor R20 and one end of the resistor R21, and the other end of the resistor R20 is connected to the drain of the FET (S11). The other end of the resistor R21 is connected to one end of the capacitor C15 and the positive terminal of the operational amplifier 551 of the voltage error detection circuit 550. The other end of the capacitor C15 is grounded.

  The DC power supply Vref_1 of the reference voltage adjusting circuit 570 charges the capacitor C15 while the FET (S11) is off. When the charging is completed, the initial reference voltage Vref_1 is directly used as the output reference voltage V_Vref = Vref_1. On the other hand, when the FET (S11) is turned on, the capacitor C15 discharges the stored charge, so that the voltage that changes depending on the amount of charge held in the capacitor C15 becomes the output V_Vref.

  The comparator 571 of the reference voltage adjustment circuit 570 compares the output DMC_O2 of the DutyMax detection circuit 560 with the triangular wave VTW_2, and outputs a pulse wave DMC2_O when the voltage of the output signal DMC_O2 becomes larger than the voltage of the triangular wave VTW_2. However, since a low-pass filter is formed on the output side of the comparator 571, the signal VQG obtained by smoothing the pulse wave DMC2_O is input to the gate terminal of the FET (S11). As described above, the ON / OFF state of the FET (S11) is determined by the signal VQG, and the discharging period of the capacitor C15 is also determined. Further, the output reference voltage V_Vref is also determined.

  Next, operations of the storage battery charge / discharge control circuit 600 and the power conversion device 500 will be described with reference to FIGS. 13 to 17. First, the control switching shown in FIG. 4 will be described with reference to FIGS. 13 and 14.

  FIGS. 13A to 13G are diagrams showing an operation in a state where the power supply from the solar cell 100 is sufficient and the load storage battery 300 is being charged, that is, when constant current control is performed.

  FIG. 13A shows a switching pulse Pul that is an output of the drive signal generation circuit 530. During this time, the duty ratio is substantially constant. The output voltage Vo of the D / D converter circuit 510 shown in FIG. 13 (b) and the output signal Vo_fb of the output voltage detection circuit 520 shown in FIG. 13 (c) are shown exaggeratedly in the drawing. . However, the average value Vo_ave of the voltage of the output signal Vo of the D / D converter circuit 510 is substantially constant with only a fluctuation that causes a slight ripple according to switching. In the states of FIGS. 13A to 13G, the voltage error detection circuit 550, the DutyMax detection circuit 560, and the reference voltage adjustment circuit 570 are not validated, and thus description thereof is omitted.

  On the other hand, as shown in FIG. 13D, the output Vbi_fb from the storage battery charging current detection circuit 650 varies somewhat like the output voltage of the D / D converter circuit 510, but is generated by resistance division of the resistors R609 and R610. The reference voltage V_LC is not lower than the reference voltage V_LC. Similarly, the output Vbv_fb of the storage battery voltage detection circuit 610 varies somewhat similarly to the output voltage of the D / D converter circuit 510, but is in a state less than the reference voltage V_FC generated by resistance division of the resistors R606 to R608. Yes.

  Accordingly, as shown in FIG. 13E, the output Pul_FC of the comparator 621 of the full charge protection circuit 620 and the output Pul_LC of the comparator 641 of the low current detection circuit remain low. Accordingly, as shown in FIG. 13 (f), the output Pul_CV of the OR circuit 642 of the control switching circuit 640 remains low, and the output Pul_CC of the NOT circuit 581 of the switching circuit 580 remains high. As a result, the output A1_Out of the current error detection circuit 540 is output to the drive signal generation circuit 530. The input A_Out to the drive signal generation circuit 530 becomes the output A1_Out of the current error detection circuit 540, and the comparator 531 compares the triangular wave VTW_1 with the triangular wave VTW_1 or more, as shown in FIGS. 13A and 13G. Coincides with the high part of the switching pulse.

  Next, with reference to FIGS. 14A to 14H, description will be given of the operation when a full charge is detected and a transition from constant current control to constant voltage control is performed in a state where the power supply from the solar cell 100 is sufficient. . FIG. 14A shows an initial state of the switching pulse Pul that is the output of the drive signal generation circuit 530. FIG. 14B shows that the voltage detected by the storage battery voltage detection circuit 610 increases as it approaches full charge. As shown in FIG. 14C, the output Vo_fb of the output voltage detection circuit 520 also increases.

  Further, the voltage Vbv_fb detected by the storage battery voltage detection circuit 610 also rises and becomes equal to or higher than the reference voltage V_FC generated by resistance division of the resistors R606 to R608. As shown in FIG. 14D, the output voltage Vbi_fb of the storage battery charging current detection circuit 650 decreases as indicated by a dotted line when the constant voltage control does not shift to the constant voltage control, but the constant voltage control As shown in FIG.

  In this way, as shown in FIG. 14E, when the voltage Vbv_fb detected by the storage battery voltage detection circuit 610 becomes equal to or higher than the reference voltage V_FC, the output Pul_FC of the comparator 621 of the full charge protection circuit 620 changes to high. The output Vbi_fb from the storage battery charging current detection circuit 650 remains in a state equal to or higher than the reference voltage V_LC.

  When the signal Pul_FC becomes high in this way, the output Pul_CV of the OR circuit 642 of the control switching circuit 640 changes to high as shown in FIG. Conversely, the output Pul_CC of the NOT circuit 581 of the switching circuit 580 changes to low.

  Then, as shown in FIG. 14G, the signal that is compared with the triangular wave VTW_1 by the comparator 531 of the drive signal generation circuit 530 is changed from the output A1_Out of the current error detection circuit 540 to the output A2_Out of the voltage error detection circuit 550. Is done. The output A2_Out of the voltage error detection circuit 550 is lower than the voltage of the output A1_Out as shown in FIG. For this reason, the number of portions that are equal to or greater than the triangular wave VTW_1 is reduced, and as a result, as shown in FIG. 14 (h), when shifting to constant voltage control, the switching pulse is suppressed so as to suppress the drive of the D / D converter circuit 510 The duty ratio of Pul will be lowered.

  In this way, the constant current control is shifted to the constant voltage control. At this time, since the FET (S61) of the full charge protection circuit 620 is also turned off, charging of the load storage battery 300 is stopped.

  Next, an operation when the power supply from the solar cell 100 is reduced during charging will be described with reference to FIGS.

  When the power supply from the solar cell 100 decreases during charging, the current error detection circuit 540 decreases the charging current. Therefore, the duty ratio of the switching pulse with respect to the FET (S1) of the D / D converter circuit 510 is increased to try to draw more current from the solar cell 100. Then, as shown in FIG. 15A, the duty ratio of the switching pulse Pul is increased. On the other hand, as shown in FIG. 15 (b), the output voltage Vo of the D / D converter circuit 510 also decreases due to insufficient power supply from the solar cell 100, and as shown in FIG. 15 (c), the output voltage detection circuit. The output Vo_fb at 520 also decreases.

  Then, as shown in FIG. 15D, the output voltage Vbi_fb of the storage battery charging current detection circuit 650 also decreases, and becomes lower than the reference voltage V_LC generated by resistance division of the resistors R609 and R610. Note that the voltage Vbv_fb detected by the storage battery voltage detection circuit 610 also decreases. However, the decrease in the voltage Vbv_fb affects the operation as long as it does not fall below the lower reference voltage generated by resistance division by the resistors R606 to R608. There is no. If the voltage falls below the lower reference voltage, the comparator 631 goes high, so the FET (S62) is turned off and overdischarge protection is performed.

  Thus, when the voltage Vbi_fb becomes less than the reference voltage V_LC, the output Pul_LC of the comparator 641 of the control switching circuit 640 becomes high as shown in FIG. The output Pul_FC of the comparator 621 of the full charge protection circuit 620 remains low. As a result, as shown in FIG. 15 (f), the output Pul_CV of the OR circuit 642 of the control switching circuit 640 becomes high, and the output Pul_CC of the NOT circuit 581 of the switching circuit 580 becomes low.

  Then, as shown in FIG. 15G, the signal compared with the triangular wave VTW_1 by the comparator 531 of the drive signal generation circuit 530 is changed from the output A1_Out of the current error detection circuit 540 to the output A2_Out of the voltage error detection circuit 550. become. Since the output A2_Out of the voltage error detection circuit 550 is lower than the voltage of the output A1_Out as shown in FIG. 15 (g), the portion that is equal to or higher than the triangular wave VTW_1 is reduced. As a result, as shown in FIG. 15 (h), when shifting to constant voltage control with MPPT, the duty ratio of the switching pulse Pu is lowered so as to suppress the drive of the D / D converter circuit 510.

  In this way, the constant current control is shifted to the constant voltage control with MPPT. Although a detailed description is omitted, if a signal change opposite to that described above occurs, a transition from constant voltage control with MPPT to constant current control is performed.

  In the constant current control, the current error detection circuit 540 generates the output signal A1_Out so that the difference between the voltage corresponding to the reference current value I_Vref and the output voltage Vbi_fb of the storage battery charging current detection circuit 650 becomes small. Then, the drive signal generation circuit 530 generates the switching pulse Pul.

  Next, constant voltage control with MPPT will be described with reference to FIGS. 16 and 17. Since the basic operation has been described with reference to FIGS. 10A to 10D, only the point portion will be described.

  First, the operation in a state where power can be sufficiently supplied from the solar cell 100 at the power point A in FIG. 9A will be described with reference to FIGS. FIGS. 16A to 16G show an operation for a short time, and are diagrams for explaining the basic operation of the circuits shown in FIGS.

  FIG. 16A shows a switching pulse Pul that is an output of the drive signal generation circuit 530. During this time, the duty ratio is substantially constant. The output voltage Vo of the D / D converter circuit 510 shown in FIG. 16B and the output signal Vo_fb of the output voltage detection circuit 520 shown in FIG. 16C are exaggerated in the figure. . However, the average value Vo_ave of the voltage of the output signal Vo of the D / D converter circuit 510 is substantially constant with only a fluctuation that causes a slight ripple according to switching. 16A to 16G, the DutyMax detection circuit 560 and the reference voltage adjustment circuit 570 are not operating effectively, and the initial reference voltage Vref_1 is equal to the output voltage V_Vref of the reference voltage adjustment circuit 570. It has become.

  As shown in FIG. 16C, the voltage error detection circuit 550 compares Vo_fb and V_Vref, and as shown in FIG. 16D, the voltage output signal A2_Out is obtained by inverting the difference between Vo_fb and V_Vref. Is output. In the states of FIGS. 16A to 16G, the voltage of the output signal A2_Out is lower than the voltage Vref_2 used as a reference in the DutyMax detection circuit 560 and corresponding to the maximum duty ratio. As described above, the DutyMax detection circuit 560 and the reference voltage adjustment circuit 570 do not operate. FIGS. 16E to 16G show a state in which the device does not operate. That is, since the voltage of the output signal A2_Out is always lower than Vref_2, the output side signals DMC_O1 and DMC_O2 of the comparator 561 of the DutyMax detection circuit 560 remain zero. Further, even if the comparator 571 of the reference voltage adjustment circuit 570 compares the triangular wave VTW_2 and DMC_O2, the signal DMC2_O and VQG on the output side of the comparator 571 remain zero because DMC_O2 remains zero. Then, since the FET (S11) of the reference voltage adjusting circuit 570 remains off, as shown in FIG. 16 (g), the output voltage V_Vref of the capacitor C15 changes with the initial reference voltage Vref_1 of the DC power supply Vref_1 being changed. do not do.

  Next, the operation when the output Vo of the D / D converter circuit 510 starts to decrease will be described with reference to FIGS. Note that FIGS. 17A to 17I are drawn so as to emphasize the features of the present embodiment, and therefore there are some differences from the actual ones.

  As described above and shown in FIGS. 17 (a) and 17 (b), if the power supply from the solar cell 100 decreases or exceeds the maximum power point, the D / D converter circuit 510 attempts to draw power. The duty ratio of the switching pulse Pul to the gate terminal of the FET (S1) of the / D converter circuit 510 is maximized. On the other hand, the output Vo of the D / D converter circuit 510 is lowered. As shown in FIG. 17C, when the output Vo decreases, the output Vo_fb of the output voltage detection circuit 520 also decreases.

  On the other hand, since the voltage error detection circuit 550 inverts the difference between the output Vo_fb and the current V_Vref, if the voltage Vo_fb of the output voltage detection circuit 520 decreases, the output A2_Out of the voltage error detection circuit 550 increases on the contrary. become. Then, as shown in FIG. 17 (d), the voltage of the output A2_Out of the voltage error detection circuit 550 gradually corresponds to the maximum value of the duty ratio of the switching pulse in the switching period for the FET (S1). The period exceeding Vref_2 becomes longer. As shown in FIG. 17E, the period during which the output DMC_O1 of the comparator 561 of the DutyMax detection circuit 560 is turned on gradually increases. Further, as shown in FIG. 17E, the output DMC_O2 of the DutyMax detection circuit 560 is a signal after the DMC_O1 is smoothed by the low-pass filter. However, since the DMC_O1 is turned on longer, the voltage gradually increases. To rise. Then, during a period in which the voltage of DMC_O1 is higher than the voltage of the triangular wave signal VTW_2 in the reference voltage adjustment circuit 570, the output DMC2_O of the comparator 571 of the reference voltage adjustment circuit 570 is turned on as shown in FIG. When this signal DMC2_O is also smoothed by a low-pass filter, a signal VQG as shown in FIG. 17 (f) is generated. This signal VQG turns on / off the FET (S11) of the reference voltage adjusting circuit 570. When the FET (S11) is turned on, the capacitor C15 is discharged. Therefore, the reference voltage V_Vref decreases as the discharge time increases and the discharge frequency increases. As shown in FIG. 17 (f), when the frequency (or rate) at which the duty ratio of the switching pulse is maximized in the past predetermined period, a period in which the signal VQG is not 0 frequently occurs and becomes longer. Accordingly, as shown in FIG. 17 (g), the reference voltage V_Vref gradually decreases.

  Then, the voltage of the output Vo_fb of the output voltage detection circuit 520 also decreases and the reference voltage V_Vref also decreases, so that the potential difference between the two signals input to the voltage error detection circuit 550 is narrowed. Then, as shown in FIG. 17 (h), after the reference voltage V_Vref is lowered, the difference between the voltage Vo_fb of the output voltage detection circuit 520 and the reference voltage V_Vref becomes small, so that the operational amplifier of the voltage error detection circuit 550 The output A2_Out of 551 (here A2_Out after correction) also gradually decreases. Then, as shown in FIG. 17 (h), the period during which the voltage falls below the voltage of the triangular wave VTW_1 input to the negative side of the comparator 531 of the drive signal generation circuit 530 becomes longer. Then, as shown in FIG. 17I, the ON width of the switching pulse (represented as corrected Pul) is shortened. That is, from the voltage error detection circuit 550, the duty ratio is increased, the ON period of the FET (S1) of the D / D converter circuit 510 is lengthened, and operation is performed to draw more power from the solar cell 100. To do. As a result, it seems as if this operation was effective. Therefore, since the difference between the voltage Vo_fb of the output voltage detection circuit 520 and the reference voltage V_Vref is reduced, the duty ratio is reduced.

  As a result, the power drawn from the solar cell 100 is reduced as described above, and the output Vo of the D / D converter circuit 510 is increased. Thereafter, if the D / D converter circuit 510 operates so as to draw power from the solar battery 100, the voltage Vo decreases as shown in FIG. 17B, so that the operation described above is repeated. become. That is, the maximum power point is tracked.

  In this way, the maximum power point tracking can be performed with only an inexpensive element without using an expensive processor or the like.

[Other Examples of Embodiment 3]
As the voltage error detection circuit 550, a conventional voltage error detection circuit can be used. Also, the DutyMax detection circuit 560 can be replaced with a DutyMax detection circuit 565 as shown in FIG.

  The DutyMax detection circuit 565 includes resistors R31 to R34, capacitors C21 and C22, an operational amplifier 5651, and a DC power supply Vref_2. The DC power supply Vref_2 outputs a voltage that is substantially the same as the voltage of the input signal A2_Out that is input to the drive signal generation circuit 530 when the duty ratio of the switching pulse that is the output of the drive signal generation circuit 530 is maximized.

  The output A2_Out (here, “= A_Out”) of the voltage error detection circuit 550 is connected to one end of the resistor R32 and one end of the resistor R31, and the other end of the resistor R31 is connected to one end of the capacitor C21. The other end of C21 is connected to the other end of the resistor R32 and the positive input terminal of the operational amplifier 5651. The positive input terminal of the operational amplifier 5651 is further connected to one end of the resistor R33 and one end of the resistor R34. The other end of the resistor R34 is connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to the other end of the resistor R33 and the output of the operational amplifier 5651. The negative input terminal of the operational amplifier 5651 is connected to the positive terminal of the DC power supply Vref_2, and the negative terminal of the DC power supply Vref_2 is grounded.

  Such a DutyMax detection circuit 565 outputs a signal DMC_O2 having a voltage corresponding to the difference between the voltage of the output A2_Out (here, “= A_Out”) and the voltage Vref_2. That is, as shown in FIG. 17 (d), when the output A_Out exceeds the voltage Vref_2, DMC_O2 increases correspondingly, so that the change is similar to DMC_O2 shown in FIG. 17 (e).

[Embodiment 4]
FIG. 19 shows a functional block diagram of a system according to the fourth embodiment. The system shown in FIG. 19 is a solar cell system, and includes a solar cell 100, a power conversion device 700 that performs power conversion on the output from the solar cell 100, and an output from the power conversion device 700 for the load storage battery 300. A storage battery charge / discharge control circuit 600 that outputs signals necessary for the charge / discharge control and power conversion device 700, a load storage battery 300 connected to the output of the storage battery charge / discharge control circuit 600, and various loads A to C, etc. Have The solar cell 100 and the load storage battery 300 are the same as the conventional one. Also, the loads A to C are the same as those in the first embodiment.

  The power conversion device 700 includes (A) a D / D converter circuit 510 having a switch and DC / DC converting the output voltage from the solar cell 100, and (B) depending on the output voltage of the D / D converter circuit 510. An output voltage detection circuit 520 that outputs an output signal of the voltage Vo_fb, and (C) according to the difference between the voltage Vof3 of the signal obtained by adjusting the voltage Vo_fb of the output signal of the output voltage detection circuit 520 and the fixed reference voltage V_Vref. A voltage error detection circuit 770 that generates a signal, and (D) a voltage signal corresponding to the difference between the voltage Vbi_fb corresponding to the storage battery charging current from the storage battery charge / discharge control circuit 600 and the voltage corresponding to the reference current value. Current error detection circuit 540 to be output and (E) output of current error detection circuit 540 or voltage error detection circuit 770 in accordance with control switching signal Pul_CV from storage battery charge / discharge control circuit 600 A switching circuit 580 for switching the switching circuit, and (F) a switching pulse for the switch of the D / D converter circuit 510 according to the output from the current error detection circuit 540 or the voltage error detection circuit 770 and output to the D / D converter circuit 510 (G) a duty signal detection circuit 760 that receives a signal corresponding to the duty ratio of the switching pulse from the drive signal generation circuit 530 and detects that the duty ratio has reached a predetermined maximum value; H) A voltage detection signal adjustment circuit 780 that adjusts the output voltage Vo_fb from the output voltage detection circuit 520 according to the detection signal from the DutyMax detection circuit 760 and outputs the adjusted output voltage Vof3 to the voltage error detection circuit 770. Have.

  The storage battery charge / discharge control circuit 600 detects a supply voltage to the storage battery, and a full charge protection circuit 620 that performs a full charge protection operation for the load storage battery 300 according to the output Vbv_fb from the storage battery voltage detection circuit 610. An overdischarge protection circuit 630 that performs an overdischarge protection operation on the load storage battery 300 according to an output from the storage battery voltage detection circuit 610, a storage battery charge current detection circuit 650 that detects a current flowing through the load storage battery 300, and a full charge A control switching circuit 640 for outputting a signal Pul_CV for switching between constant current control and constant voltage control with MPPT in accordance with the output Pul_FC from the protection circuit 620 and the output Vbi_fb from the storage battery charging current detection circuit 650.

  The output voltage detection circuit 520, the voltage error detection circuit 770, the drive signal generation circuit 530, the DutyMax detection circuit 760, and the voltage detection signal adjustment circuit 780 described above constitute a constant voltage control circuit that realizes MPPT. The current error detection circuit 540 and the drive signal generation circuit 530 constitute a constant current control circuit.

  Since the operation of the storage battery charge / discharge control circuit 600 shown in FIG. 19 is the same as that of the second embodiment, description thereof is omitted in this embodiment. By introducing the storage battery charge / discharge control circuit 600, the control as shown in FIG. 4 is realized, and the battery is efficiently stored. In addition, the full charge protection circuit 620 and the overdischarge protection circuit 630 operate appropriately, and power storage and discharge are performed safely.

  The control switching circuit 640 includes a low current detection circuit that detects an insufficient supply power based on the output Vbi_fb of the storage battery charging current detection circuit 650, and a detection signal that indicates that an insufficient supply power from the low current detection circuit is detected. For example, there may be an OR circuit that calculates the logical sum of Pul_LC and a signal Pul_FC indicating that full charge from the full charge protection circuit 620 has been detected. In this way, when shortage of supply power is detected or when full charge is detected, the switching signal Pul_CV for switching from constant current control to constant voltage control with MPPT is output to the switching circuit 580. On the other hand, if the supplied power is sufficient and charging is in progress, switching signal Pul_CV for switching from constant voltage control to constant current control is output to switching circuit 580.

  The current error detection circuit 540 generates a voltage signal corresponding to the difference between the voltage Vbi_fb corresponding to the storage battery charging current from the storage battery charge / discharge control circuit 600 and the voltage corresponding to the reference current value, and the switching circuit 580. Output to. That is, when the output of the current error detection circuit 540 is selected by the switching circuit 580, the drive signal generation circuit 530 performs switching with respect to the switch of the D / D converter circuit 510 so that the current flowing through the load storage battery 300 becomes constant. A pulse Pul is generated.

  The operation of the power conversion device 700 shown in FIG. 19 is almost the same as that of the power conversion device 500 of the third embodiment. However, in this embodiment, the reference voltage V_Vref is not adjusted, but the reference voltage V_Vref is fixed, and the voltage of the detection signal of the output voltage detection circuit 520 is the object of adjustment. The degree of adjustment is the same as in the second embodiment, and is determined according to the frequency (or ratio) at which the state in which the duty ratio of the switching pulse is a predetermined maximum value is detected within a predetermined period.

  More specifically, when the D / D converter circuit 510 draws too much current from the solar cell 100 and the output voltage Vo decreases, the voltage error detection circuit 770 and the drive signal generation circuit 530 cause the duty of the switching pulse. The ratio is set to a predetermined maximum value to increase the voltage. On the other hand, when the DutyMax detection circuit 760 detects a state where the duty ratio of the switching pulse is a predetermined maximum value, the DutyMax detection circuit 760 outputs a detection signal to the voltage detection signal adjustment circuit 780. The voltage detection signal adjustment circuit 780 increases the voltage of the detection signal of the output voltage detection circuit 520 in accordance with the frequency (or rate) of detecting the state in which the duty ratio of the switching pulse is a predetermined maximum value within a predetermined period. Thus, the difference from the reference voltage V_Vref is narrowed.

  Note that the power drawn from the solar cell 100 is also reduced by driving the D / D converter circuit 510 by the voltage error detection circuit 770 and the drive signal generation circuit 530. And the said electric power and the output electric power of the solar cell 100 will balance at the electric power point B of Fig.9 (a). Then, the output voltage Vo and the output power Pout of the power conversion device 700 stop decreasing.

  When the difference between the reference voltage V_Vref and the voltage Vof3 of the adjusted detection signal becomes narrower, the voltage error detection circuit 770 and the drive signal generation circuit 530 lower the switching pulse duty ratio from a predetermined maximum value. Further, the adjustment amount of the detection signal after adjustment has a time constant, and does not immediately become 0, so it gradually decreases.

  The parts other than such operation are almost the same as those of the third embodiment. Therefore, similarly to the third embodiment, the maximum power point can be traced by an inexpensive circuit element.

[Example of Embodiment 4]
FIG. 20 shows a specific circuit example in the fourth embodiment. Note that the solar cell 100, the D / D converter circuit 510, the output voltage detection circuit 520, the storage battery charge / discharge control circuit 600, the loads A to C, and the like are the same as those in the third embodiment, and are not shown. Further, the operation of the charge / discharge control circuit 600 also realizes the control switching shown in FIG.

  The current error detection circuit 540 is connected to the storage battery charging current detection circuit 650 via the connection terminal C, and outputs resistors R541 to R544, capacitors C541 and C542, an operational amplifier 541, and a voltage corresponding to the reference current value. DC power supply I_Vref is provided. The output Vbi_fb of the storage battery charging current detection circuit 650 is connected to one ends of the resistors R541 and R542, the other end of the resistor R542 is connected to one end of the capacitor C541, and the other end of the capacitor C541 and the other end of the resistor R541 are connected to the operational amplifier 541. Connected to the negative side input terminal. The negative input terminal of the operational amplifier 541 is connected to one end of the capacitor C542 and one end of the resistor R543, the other end of the capacitor C542 is connected to one end of the resistor R544, and the other end of the resistor R544 and the resistor R543. The other end is connected to the output terminal of the operational amplifier 541. Furthermore, the positive input terminal of the operational amplifier 541 is connected to the positive terminal of the DC power supply I_Vref that outputs a voltage corresponding to the reference current value. The negative terminal of the DC power supply I_Vref is grounded.

  Switching circuit 580 includes analog switches 582 and 583 and a NOT circuit 581. The output of the OR circuit 642 of the control switching circuit 640 shown in FIG. 11 is connected to the input side terminal of the NOT circuit 581 and the control terminal of the analog switch 583 via Pul_CV, terminal D. The output terminal of the NOT circuit 581 is connected to the control terminal of the analog switch 582. The output terminal A1_Out of the current error detection circuit 540 is connected to the input terminal of the analog switch 582, and the output side terminal of the analog switch 582 is connected to the drive signal generation circuit 530. The output A2_Out of the voltage error detection circuit 770 is connected to the input side terminal of the analog switch 583, and the output side terminal of the analog switch 583 is connected to the drive signal generation circuit 530.

  When the output Pul_CV of the control switching circuit 640 becomes high, the output Pul_CC of the NOT circuit 581 becomes low, so that the analog switch 582 is turned off, but the analog switch 583 is turned on, so that the output from the voltage error detection circuit 770 Is output to the drive signal generation circuit 530. Conversely, when the output Pul_CV of the control switching circuit 640 goes low, the output Pul_CC of the NOT circuit 581 goes high, so the analog switch 582 is turned on and the output of the current error detection circuit 540 is sent to the drive signal generation circuit 530. However, the analog switch 583 is turned off.

  Drive signal generation circuit 530 includes a comparator 531 and a triangular wave generator 532. The output of the switching circuit 580 is connected to the positive input terminal of the comparator 531, and the triangular wave generator 532 is connected to the negative input terminal of the comparator 531. The output terminal of the comparator 531 is connected to the gate terminal of the FET (S1) of the D / D converter circuit 510 via the connection terminal A.

  The DutyMax detection circuit 760 includes a comparator 761, resistors R45 and R46, a capacitor C43, and a DC power supply Vref_2 that outputs a voltage Vref_2. The positive input terminal of the comparator 761 is connected to the output of the switching circuit 580, and the negative input terminal of the comparator 761 is connected to the positive terminal of the DC power supply Vref_2. The negative terminal of the DC power supply Vref_2 is grounded. The output of the comparator 761 is connected to one end of the resistor R45, and the other end of the resistor R45 is connected to one end of the resistor R46, one end of the capacitor C43, and the input of the voltage detection signal adjustment circuit 780. The other end of the resistor R46 and the other end of the capacitor C43 are grounded.

  The comparator 761 of the DutyMax detection circuit 760 includes a drive signal generation circuit when the duty ratio of the signal A2_Out (that is, A_Out) output from the voltage error detection circuit 770 and the switching pulse output from the drive signal generation circuit 530 is maximized. The output voltage Vref_2 of the DC power supply Vref_2 that outputs substantially the same voltage as the voltage of the input signal A2_Out (here, “= A_Out”) input to 530 is compared. When the voltage of the input signal A2_Out (here, “= A_Out”) becomes higher than the voltage Vref_2, the comparator 761 outputs the pulse wave DMC_O1 during that time. However, a low-pass filter is connected to the output of the comparator 761, and the output pulse wave is output to the voltage detection signal adjustment circuit 780 as a smooth signal wave DMC_O2.

  The voltage detection signal adjustment circuit 780 includes a comparator 534, a triangular wave generator 535, operational amplifiers 531 and 532, resistors R51 to R62, n-type FET (S51), transistor T1, capacitors C51 and C52, voltage Two DC power sources V_Vref that output V_Vref and DC power sources Vref_3 that output a predetermined voltage Vref_3 are included.

  The triangular wave generator 535 is connected to the positive input terminal of the comparator 534, and the output of the DutyMax detection circuit 760 is connected to the negative input terminal of the comparator 534. One end of the resistor R56 is connected to the output terminal of the comparator 534, and one end of the resistor R57, one end of the capacitor C51, and the gate terminal of the FET (S51) are connected to the other end of the resistor R56. The other end of the resistor R57 and the other end of the capacitor C51 are grounded. The source terminal of the FET (S51) is grounded, and the drain terminal is connected to one end of the resistor R61. The other end of the resistor R61 is connected to one end of the resistor R58 and one end of the resistor R59. The other end of the resistor R58 is connected to the positive terminal of the DC power supply Vref_3, and the negative terminal of the DC power supply Vref_3 is grounded. Further, the other end of the resistor R59 is connected to one end of the resistor R60 and one end of the capacitor C52. The other end of the capacitor C52 is grounded. The other end of the resistor R60 is connected to one end of the resistor R62 and the base terminal of the transistor T1. Further, the other end of the resistor R62 is grounded. The emitter of the transistor T1 is grounded, and the collector terminal is connected to one end of the resistor R55.

  Furthermore, one end of the resistor R51 is connected to the output of the output voltage detection circuit 520 via the connection terminal B, and the other end of the resistor R51 is connected to one end of the resistor R52 and the negative input terminal of the operational amplifier 531. Yes. The positive input terminal of the operational amplifier 531 is connected to the positive terminal of the DC power supply V_Vref, and the negative terminal of the DC power supply V_Vref is grounded. The other end of the resistor R52 is connected to the output terminal of the operational amplifier 531, the other end of the resistor R55, and one end of the resistor R53.

  The other end of the resistor R53 is connected to one end of the resistor R54 and the negative input terminal of the operational amplifier 532. The positive input terminal of the operational amplifier 532 is connected to the positive terminal of the DC power supply V_Vref, and the negative terminal of the DC power supply V_Vref is grounded. The other end of the resistor R54 is connected to the output terminal of the operational amplifier 532 and the input of the voltage error detection circuit 770.

  The comparator 534 compares the output VTW_3 of the triangular wave generator 535 with the output DMC_O2 of the DutyMax detection circuit 760. However, as long as the duty ratio of the switching pulse does not become the maximum value, the voltage of the output VTW_3 is higher than the voltage of the output DMC_O2 of the DutyMax detection circuit 760, so that a high output DMC2_O is always output. On the other hand, when the duty ratio of the switching pulse reaches the maximum value, the voltage of the output DMC_O2 of the DutyMax detection circuit 760 increases, so the period during which the output DMC2_O is turned off gradually increases. Since a low pass filter is provided on the output side of the comparator 534, the FET (S51) is turned on / off by the signal VQG smoothed by the low pass filter. However, the FET (S51) is normally on, and no charge is stored in the capacitor C52. As the off period becomes longer, electric charges are gradually stored in the capacitor C52 and the voltage becomes higher. On the other hand, when the voltage VQB of the capacitor C52 increases, the voltage VQB applied to the base terminal of the transistor T1 also increases and the transistor T1 is also turned on. In that case, the output voltage of the operational amplifier 531 is lowered.

  The operational amplifier 531 inverts the output Vo_fb of the output voltage detection circuit 520, and acts to lower the voltage Vof2 of the output of the operational amplifier 531 when the transistor T1 is turned on. Then, the operational amplifier 532 inverts the output Vof2 again and outputs the voltage Vof3 to the voltage error detection circuit 770 as the output of the voltage detection signal adjustment circuit 780. More specifically, when Vof2 is lowered, Vof3 is raised, and acts on the voltage error detection circuit 770 as if the output Vo_fb of the output voltage detection circuit 520 is increased.

  Next, main parts of the operation of the circuit shown in FIG. 20 will be described with reference to FIGS.

  First, an operation in a state where power can be sufficiently supplied from the solar cell 100 at the power point A in FIG. 9A will be described with reference to FIGS. 21A to 21G. FIGS. 21A to 21G show an operation for a short time, and are diagrams for explaining the basic operation of the circuit shown in FIG.

  FIG. 21A shows a switching pulse Pul that is an output of the drive signal generation circuit 530. During this time, the duty ratio is substantially constant. The output voltage Vo of the D / D converter circuit 510 shown in FIG. 21B and the output signal Vo_fb of the output voltage detection circuit 520 shown in FIG. 21C are shown exaggeratedly in the drawing. . However, the average value Vo_ave of the voltage of the output signal Vo of the D / D converter circuit 510 is substantially constant with only a fluctuation that causes a slight ripple according to switching. 21A to 21G, the DutyMax detection circuit 760 and the voltage detection signal adjustment circuit 780 do not operate, and the output Vo_fb of the output voltage detection circuit 520 and the voltage detection signal adjustment circuit 780 The output Vof3 is almost the same.

  As shown in FIG. 21 (g), the voltage error detection circuit 770 compares Vof3 and V_Vref, and as shown in FIG. 21 (d), a voltage output signal A2_Out obtained by inverting the difference between Vof3 and V_Vref. Is output. In the states of FIGS. 21A to 21G, the voltage of the output signal A2_Out is lower than the voltage Vref_2 used as a reference in the DutyMax detection circuit 760 and corresponding to the maximum duty ratio. As described above, the DutyMax detection circuit 760 and the voltage detection signal adjustment circuit 780 do not operate. The non-operating state is shown in FIGS. That is, since the voltage of the output signal A2_Out is always lower than Vref_2, the output side signals DMC_O1 and DMC_O2 of the comparator 761 of the DutyMax detection circuit 760 remain zero. Further, even if the comparator 534 of the voltage detection signal adjustment circuit 780 compares the triangular wave VTW_3 and DMC_O2, the signal DMC2_O and VQG on the output side of the comparator 534 remain high because DMC_O2 remains zero. Then, since the FET (S51) of the voltage detection signal adjustment circuit 780 remains on, as shown in FIG. 21 (f), the voltage VQB of the capacitor C52 applied to the base terminal of the transistor T1 changes the transistor T1. It will not be a voltage to turn on and will remain low.

  Next, the operation when the output Vo of the D / D converter circuit 510 starts to decrease will be described with reference to FIGS. Note that FIGS. 22A to 22I are drawn so as to emphasize the features of the present embodiment, and therefore, there are some differences from actual ones.

  As described above and shown in FIGS. 22 (a) and 22 (b), the power supply from the solar cell 100 decreases or exceeds the maximum power point, and the D / D converter circuit 510 attempts to draw current. As a result, the duty ratio of the switching pulse Pul to the gate terminal of the FET (S1) of the D / D converter circuit 510 is maximized, while the output Vo of the D / D converter circuit 510 is lowered. As shown in FIG. 22C, when the output Vo decreases, the output Vo_fb of the output voltage detection circuit 520 also decreases.

  On the other hand, when the output Vo_fb of the output voltage detection circuit 520 decreases and adjustment of Vof2 is not performed, the difference between Vof3 corresponding to Vo_fb and the fixed reference voltage V_Vref becomes large, and the output A2_Out of the voltage error detection circuit 770 Will rise on the contrary. Then, as shown in FIG. 22 (d), the voltage of the output A2_Out of the voltage error detection circuit 770 gradually corresponds to the maximum value of the duty ratio of the switching pulse during the switching period for the FET (S1). The period exceeding Vref_2 becomes longer. As shown in FIG. 22 (e), the period during which the output DMC_O1 of the comparator 761 of the DutyMax detection circuit 760 is turned on gradually increases. Further, as shown in FIG. 22 (e), the output DMC_O2 of the DutyMax detection circuit 760 is a signal after the DMC_O1 is smoothed by the low-pass filter. However, since the DMC_O1 is turned on for a long time, the voltage gradually increases. To rise. Up to this point, the operation is almost the same as that described for the specific circuit example of the third embodiment.

  Then, during the period when the voltage of DMC_O2 is lower than the voltage of the triangular wave signal VTW_3 in the voltage detection signal adjustment circuit 780, the output DMC2_O of the comparator 534 of the voltage detection signal adjustment circuit 780 is turned on as shown in FIG. Further, a signal VQG (not shown) obtained by smoothing the signal DMC2_O with a low-pass filter is generated. This signal VQG turns on / off the FET (S51) of the voltage detection signal adjustment circuit 780. Unlike the specific circuit example of the second embodiment, in this example, the FET (S51) is off and the capacitor A state where the battery is discharged from C52 is normal. However, when the duty ratio of the switching pulse is maximized, the period during which the FET (S51) is turned off becomes longer and frequently turned off, and as shown in FIG. The applied voltage VQB increases. That is, when the frequency (or rate) at which the duty ratio of the switching pulse is maximized in the past predetermined period, the frequency and period when the transistor T1 is turned on becomes longer, and the voltage as shown by the solid line in FIG. The output voltage Vof2 of the operational amplifier 531 of the detection signal adjustment circuit 780 is lowered. The dotted line represents the curve when no adjustment is made. As a result, the output Vof3 of the voltage detection signal adjustment circuit 780 rises in the opposite direction.

  On the other hand, since the reference voltage V_Vref is fixed, the potential difference between the two signals input to the voltage error detection circuit 770 is narrowed. Then, as shown in FIG. 22 (h), after the output Vof3 of the voltage detection signal adjustment circuit 780 is raised, the difference between the voltage of the output Vof3 and the reference voltage V_Vref becomes small, so that the operational amplifier of the voltage error detection circuit 770 The output A2_Out 771 (A2_Out after correction) of 771 gradually decreases. Further, as shown in FIG. 22 (h), the period during which the voltage falls below the voltage of the triangular wave VTW_1 at the negative input terminal of the comparator 531 of the drive signal generation circuit 530 becomes longer. Then, as shown in FIG. 22 (i), the ON width of the switching pulse (represented as corrected Pul) is shortened. That is, from the voltage error detection circuit 770, the duty ratio is increased, the ON period of the FET (S1) of the D / D converter circuit 510 is lengthened, and an operation is performed to draw more power from the solar cell 100. As a result, it works as if it were effective in this operation. Therefore, the difference between the voltage of the output Vof3 of the voltage detection signal adjustment circuit 780 and the reference voltage V_Vref is reduced, and the duty ratio is reduced.

  As a result, the power drawn from the solar cell 100 is reduced as described above, and the output Vo of the D / D converter circuit 510 is increased. Thereafter, if the D / D converter circuit 510 operates so as to draw power from the solar cell 100, the voltage Vo decreases as shown in FIG. 22B. Therefore, the operation described above is repeated. become. That is, the maximum power point is tracked.

  In this way, the maximum power point tracking can be performed with only an inexpensive element without using an expensive processor or the like.

[Embodiment 5]
FIG. 23 shows a functional block diagram of a system according to the fifth embodiment. The system shown in FIG. 23 is a solar cell system, and includes a solar cell 100, a power conversion device 800 that performs power conversion on the output from the solar cell 100, and an output from the power conversion device 800 for the load storage battery 300. A storage battery charge / discharge control circuit 600 that outputs signals necessary for the charge / discharge control and power conversion device 800, a load storage battery 300 connected to the output of the storage battery charge / discharge control circuit 600, and various loads A to C, etc. Have The solar cell 100 and the load storage battery 300 are the same as the conventional one. Also, the loads A to C are the same as those in the first embodiment.

  The power conversion device 800 includes (A) a D / D converter circuit 510 having a switch and DC / DC converting the output voltage from the solar cell 100, and (B) depending on the output voltage of the D / D converter circuit 510. An output voltage detection circuit 520 that outputs a voltage output signal Vo_fb; (C) a voltage error detection circuit 550b that generates a signal A2_Out corresponding to the difference between the voltage of the output signal of the output voltage detection circuit 520 and a reference voltage; D) a current error detection circuit 540 that generates a voltage signal A1_Out corresponding to the difference between the voltage Vbi_fb corresponding to the storage battery charging current from the storage battery charge / discharge control circuit 600 and the voltage corresponding to the reference current value; and (E) the storage battery. A switching circuit 580 for switching to the output of the current error detection circuit 540 or the voltage error detection circuit 550b in response to a control switching signal Pul_CV from the charge / discharge control circuit 600, and (F) a current error A drive signal generation circuit 530b that generates a switching pulse for the switch of the D / D converter circuit 510 according to the output from the output circuit 540 or the voltage error detection circuit 550b and outputs the switching pulse to the D / D converter circuit 510; and (G) drive A DutyMax detection circuit 560b that receives a signal Duty corresponding to the duty ratio of the switching pulse from the signal generation circuit 530b and detects that the duty ratio has reached a predetermined maximum value; and (H) a detection signal from the DutyMax detection circuit 560b. Accordingly, the reference voltage adjusting circuit 570b that adjusts the initial reference voltage Vref_1 and outputs the adjusted output voltage V_Vref to the voltage error detecting circuit 550b, and (I) the drive signal generating circuit according to the detection signal from the DutyMax detecting circuit 560b. Duty of switching pulse generated by 530b When the constant voltage control is enabled in conjunction with the power limiting circuit 860 that forcibly reduces the power ratio and the (J) switching circuit 580, that is, the output of the voltage error detection circuit 550b is input to the drive signal generation circuit 530b. The second switching circuit 870 that transmits the output of the DutyMax detection circuit 560b to the power limiting circuit 860.

  The storage battery charge / discharge control circuit 600 includes a storage battery voltage detection circuit 610 that detects a supply voltage to the load storage battery 300, and a full charge protection circuit that performs a full charge protection operation for the load storage battery 300 according to the output from the storage battery voltage detection circuit 610. 620, an overdischarge protection circuit 630 that performs an overdischarge protection operation on the load storage battery 300 in accordance with an output from the storage battery voltage detection circuit 610, a storage battery charge current detection circuit 650 that detects a current flowing through the load storage battery 300, And a control switching circuit 640 for outputting a signal Pul_CV for switching between constant current control and constant voltage control according to the output from the full charge protection circuit 620 and the output from the storage battery charging current detection circuit 650.

  The output voltage detection circuit 520, voltage error detection circuit 550b, drive signal generation circuit 530b, DutyMax detection circuit 560b, reference voltage adjustment circuit 570b, and power limiting circuit 860 described above constitute a constant voltage control circuit that realizes MPPT. Is done. The current error detection circuit 540 and the drive signal generation circuit 530b constitute a constant current control circuit.

  Since the operation of the storage battery charge / discharge control circuit 600 shown in FIG. 23 is the same as that of the second embodiment, description thereof is omitted in this embodiment. By introducing the storage battery charge / discharge control circuit 600, the control as shown in FIG. 4 is realized, and the battery is efficiently stored. In addition, the full charge protection circuit 620 and the overdischarge protection circuit 630 operate appropriately, and power storage and discharge are performed safely.

  The second switching circuit 870 generates an output of the power limiting circuit 860 in synchronization with the switching of the switching circuit 580 so as to output the signal from the voltage error detection circuit 550b to the driving signal generation circuit 530b. Operate to communicate to circuit 530b.

  Further, the control switching circuit 640 includes a low current detection circuit that detects a shortage of supply power, a detection signal from the low current detection circuit that indicates a shortage of supply power, and a full charge from the full charge protection circuit 620. And an OR circuit that calculates a logical sum with the signal Pul_FC indicating that the signal is detected. In this way, when shortage of supply power is detected or when full charge is detected, the switching signal Pul_CV for switching from constant current control to constant voltage control with MPPT is output to the switching circuit 580. On the other hand, if supply power is sufficient and charging is in progress, switching signal Pul_CV for switching from constant voltage control with MPPT to constant current control is output to switching circuit 580.

  The current error detection circuit 540 generates a signal A1_Out having a voltage corresponding to the difference between the voltage corresponding to the storage battery charging current from the storage battery charge / discharge control circuit 600 and the voltage corresponding to the reference current value, and the switching circuit 580. Output to. That is, when the output of the current error detection circuit 540 is selected by the switching circuit 580, the drive signal generation circuit 530b performs switching with respect to the switch of the D / D converter circuit 510 so that the current flowing through the load storage battery 300 becomes constant. Generate a pulse.

  Next, the operation of the power conversion apparatus 800 shown in FIG. 23 will be described with reference to FIG. As in the third embodiment, the output power from the solar cell 100 is Ppv, the output voltage of the power converter 800 is Vo, the output power is Pout, and the drive signal generation circuit 530b to the DutyMax detection circuit 560b. Assume that the output is Duty, the initial reference voltage is Vref_1, and the output voltage from the reference voltage adjustment circuit 570b to the voltage error detection circuit 550b is V_Vref.

  Also in the present embodiment, the operation of the power conversion apparatus 800 will be described with reference to FIGS. 24A to 24E based on FIGS.

  FIG. 24A shows temporal changes in the output power Ppv from the solar cell 100 and the output voltage Pout of the power conversion device 800. Since there is a loss due to power conversion device 800, the relationship Ppv> Pout always holds. For comparison, the maximum power point Ppv_max is also shown. FIG. 24B shows the change over time of the output voltage Vo of the power conversion device 800. FIG. 24C shows a time change of the reference voltage V_Vref from the reference voltage adjustment circuit 570b. An initial reference voltage Vref_1 is also shown for comparison. FIG. 24D shows the time change of the output duty of the drive signal generation circuit 530b. Note that a maximum value DutyMax predetermined for the output duty is also shown for comparison. FIG. 24E shows the duty ratio of the switching pulse output from the drive signal generation circuit 530b to the D / D converter circuit 510.

  First, the D / D converter circuit 510, the output voltage detection circuit 520, and the voltage error detection are performed until the output power from the solar battery 100 reaches the power point M from the power smaller than the power point A to the power point A. The circuit 550b and the drive signal generation circuit 530b operate as usual. That is, the reference voltage adjustment circuit 570b outputs the initial reference voltage Vref_1 as it is without doing anything (FIG. 24 (c)), and V_Vref = Vref_1, and the voltage according to the difference from the output Vo_fb of the output voltage detection circuit 520. The error detection circuit 550b and the drive signal generation circuit 530b cause the switch of the D / D converter circuit 510 to perform switching.

  Specifically, if power is drawn from the solar cell 100 beyond the power point A, the output Vo_fb of the output voltage detection circuit 520 is lowered simply by driving the D / D converter circuit 510 as before. . Therefore, the voltage error detection circuit 550b and the drive signal generation circuit 530b operate so as to gradually increase the duty ratio of the switching pulse and the duty voltage for the switch of the D / D converter circuit 510, as shown in FIG. To do. If it does in this way, as shown in Drawing 24 (b), output voltage Vo of power converter 800 will be maintained constant.

  Thereafter, when the power drawn from the solar cell 100 reaches the power point M, as shown in FIG. 24A, the output power Ppv from the solar cell 100 decreases, and accordingly, the output power Pout of the power conversion device 800 is decreased. Also decreases. Further, as can be seen from FIG. 9B, the output voltage Vo also decreases. Then, the voltage error detection circuit 550b and the drive signal generation circuit 530b detect that the difference between Vo_fb and V_Vref has increased, and the duty ratio of the switching pulse to the switch of the D / D converter circuit 510 and the voltage of the signal Duty Is raised to DutyMax.

  When such a situation occurs, the DutyMax detection circuit 560b detects that the voltage of the signal Duty has reached DutyMax, and outputs a detection signal to the reference voltage adjustment circuit 570b and the power limiting circuit 860. The reference voltage adjustment circuit 570b adjusts the initial reference voltage Vref_1 to be lowered according to the detection signal from the DutyMax detection circuit 560b, and outputs the adjusted voltage V_Vref to the voltage error detection circuit 550b. This situation is shown in FIG. The reduction width of the reference voltage depends on the frequency or rate at which the detection signal is output from the DutyMax detection circuit 560b within a predetermined period.

  Furthermore, the power limiting circuit 860 lowers the power extraction level from the solar cell 100 by the D / D converter circuit 510 at an early stage. Therefore, in accordance with the detection signal from the DutyMax detection circuit 560b, a signal for controlling switching of the switch of the D / D converter circuit 510, for example, the switching pulse itself or a signal used for generating the switching pulse is lowered. It acts on the drive signal generation circuit 530b. As a result, as indicated by a dotted line in FIG. 24E, the duty ratio of the switching pulse is temporarily reduced.

  As shown in FIG. 24A, when the voltage error detection circuit 550b and the drive signal generation circuit 530b drive the D / D converter circuit 510 too much, the power drawn from the solar cell 100 also decreases. Then, the power and the actual output power Ppv of the solar cell 100 are balanced at the power point B. Then, as shown in FIGS. 24A and 24B, the output voltage Vo and the output power Pout of the power conversion device 800 stop decreasing.

  Also, as shown in FIG. 24D, the voltage error detection circuit 550b detects that the difference between Vo_fb and V_Vref is small, and the duty ratio of the switching pulse to the switch of the D / D converter circuit 510 and The voltage of the signal Duty is lowered. Then, the current drawn from solar cell 100 is reduced by driving D / D converter circuit 510 by voltage error detection circuit 550b and drive signal generation circuit 530b. However, since the decrease width of the current drawn from the solar cell 100 is usually a little larger, it passes through the maximum power point M and returns to the power point C as shown in FIG. As shown in FIG. 24A, during this time, the output power Ppv of the solar cell 100 once increases but decreases again. The output voltage Vo of the power conversion device 800 gradually increases according to the drive level of the D / D converter circuit 510 during this period as shown in FIG.

  Note that, as shown in FIG. 24C, there is a delay in the adjustment of the reference voltage V_Vref by the reference voltage adjustment circuit 570b, and even if the voltage of the signal Duty falls from DutyMax, the adjustment does not end immediately. Furthermore, since there is a time constant for returning to the initial reference voltage Vref_1, the reference voltage V_Vref gradually increases.

  Thereafter, as shown in FIG. 24 (d), the voltage error detection circuit 550b and the drive signal generation circuit 530b drive the D / D converter circuit 510 according to the difference between Vo_fb and the reference voltage V_Vref to thereby form the solar cell 100. The duty ratio of the switching pulse to the switch of the D / D converter circuit 510 and the voltage of the signal Duty are increased so as to draw more power from

  Then, as shown in FIG. 24A, the output power Ppv of the solar cell 100 increases and reaches the power point M again. The subsequent operation is almost the same as that after the power point M is first reached. However, as shown in FIG. 24C, the reference voltage V_Vref has not returned to the initial reference voltage Vref_1 even at the power point M, and the output voltage Vo of the power converter 800 has not reached the target value. However, the reduction width of the reference voltage V_Vref is slightly different. Since the operations are not completely the same as described above, the on-curve operation in FIG. 9A is switched at C1 and C2 instead of the power point C and at B1 and B2 instead of the power point B.

  After all, the power point B or its vicinity and the power point C or its vicinity are moved back and forth across the maximum power point. That is, maximum power point tracking is possible. The operation described above is based on the assumption that the generated power of the solar cell 100 is constant. However, since the generated power is generally not constant, the maximum power point itself varies, but the operation is the same.

  The difference between power point B and power point C is determined according to the output power and output voltage, but can be adjusted by gain adjustment of a control system including D / D converter circuit 510 and the like. That is, it can be operated near the maximum power point.

[Example 1 of Embodiment 5]
Next, referring to FIG. 25, a current error detection circuit 540, a voltage error detection circuit 550b, a DutyMax detection circuit 560b, a reference voltage adjustment circuit 570b, a switching circuit 580, a drive signal generation circuit 530b, a power limiting circuit 860, and a second switching circuit. A specific circuit example with 870 will be described. In addition, about the structure and operation | movement of the storage battery charging / discharging control circuit 600, since it is the same as the Example of 3rd Embodiment, description is abbreviate | omitted.

  The voltage error detection circuit 550b is connected to the output voltage detection circuit 520 via the connection terminal B, and includes resistors R11 to R14, capacitors C11 and C12, and an operational amplifier 551. The output Vo_fb of the output voltage detection circuit 520 is connected to one ends of the resistors R11 and R12, the other end of the resistor R11 is connected to one end of the capacitor C11, and the other end of the capacitor C11 and the other end of the resistor R12 are connected to the operational amplifier 551. Connected to the negative input terminal. The negative input terminal of the operational amplifier 551 is connected to one end of the capacitor C12 and one end of the resistor R13, the other end of the capacitor C12 is connected to one end of the resistor R14, and the other end of the resistor R14 and the resistor R13. The other end is connected to the output terminal of the operational amplifier 551. Further, the output of the reference voltage adjustment circuit 570b is connected to the positive input terminal of the operational amplifier 551.

  The current error detection circuit 540 is connected to the storage battery current detection circuit 650 via the connection terminal C, and outputs resistors R541 to R544, capacitors C541 and C542, an operational amplifier 541, and a voltage corresponding to the reference current value. DC power supply I_Vref. The output Vbi_fb of the storage battery current detection circuit 650 is connected to one ends of the resistors R541 and R542, the other end of the resistor R542 is connected to one end of the capacitor C541, and the other end of the capacitor C541 and the other end of the resistor R541 are Connected to the negative input terminal. The negative input terminal of the operational amplifier 541 is connected to one end of the capacitor C542 and one end of the resistor R543, the other end of the capacitor C542 is connected to one end of the resistor R544, and the other end of the resistor R544 and the resistor R543. The other end is connected to the output terminal of the operational amplifier 541. Furthermore, the positive input terminal of the operational amplifier 541 is connected to the positive terminal of the DC power supply I_Vref that outputs a voltage corresponding to the reference current value. The negative terminal of the DC power supply I_Vref is grounded.

  Switching circuit 580 includes analog switches 582 and 583 and a NOT circuit 581. The output of the OR circuit 642 of the control switching circuit 640 described in FIG. 11 is connected to the input side terminal of the NOT circuit 581 and the control terminal of the analog switch 583 via the terminal D. The output terminal of the NOT circuit 581 is connected to the control terminal of the analog switch 582. The output A1_Out of the current error detection circuit 540 is connected to the input side terminal of the analog switch 582, and the output side terminal of the analog switch 582 is connected to the drive signal generation circuit 530b. The output terminal A2_Out of the voltage error detection circuit 550b is connected to the input side terminal of the analog switch 583, and the output terminal of the analog switch 583 is connected to the drive signal generation circuit 530b.

  When the output of the OR circuit 642 of the control switching circuit 640 becomes high, the output of the NOT circuit 581 becomes low via the terminal D, so the analog switch 582 remains off, but the analog switch 583 turns on. The output A2_Out from the voltage error detection circuit 550b is output to the drive signal generation circuit 530b. Conversely, when the output of the OR circuit 642 of the control switching circuit 640 goes low, the output of the NOT circuit 581 goes high via the terminal D, so the analog switch 582 is turned on and the output of the current error detection circuit 540 is turned on. Although A1_Out is output to the drive signal generation circuit 530b, the analog switch 583 is turned off.

  Drive signal generation circuit 530b includes a comparator 531, a triangular wave generator 532, and a resistor R76. The output of the switching circuit 580 is connected to the positive input terminal of the comparator 531, and the triangular wave generator 532 is connected to the negative input terminal of the comparator 531. The output terminal of the comparator 531 is connected to the gate terminal of the FET (S1) of the D / D converter circuit 510 described in FIG. 11 via the resistor R76 and the connection terminal A. The terminal A side terminal of the resistor R76 is also connected to the power limiting circuit 860.

  The DutyMax detection circuit 560b includes a comparator 562 and a DC power supply Vref_2 that outputs a voltage Vref_2. The positive input terminal of the comparator 562 is connected to the output of the switching circuit 580, and the negative input terminal of the comparator 562 is connected to the positive terminal of the DC power supply Vref_2. The negative terminal of the DC power supply Vref_2 is grounded. The output DMC_O of the comparator 562 is connected to the second switching circuit 870 and the reference voltage adjustment circuit 570b.

  The DutyMax detection circuit 560b operates effectively while constant voltage control with MPPT is enabled by the switching circuit 580 and the second switching circuit 870 and the output of the voltage error detection circuit 550b is output to the drive signal generation circuit 530b. To do. More specifically, the comparator 562 has the maximum duty ratio of the input signal to the drive signal generation circuit 530b (the output signal A2_Out of the voltage error detection circuit 550b) and the switching pulse that is the output of the drive signal generation circuit 530b. In this case, the output voltage Vref_2 of the DC power supply Vref_2 that outputs the voltage Vref_2 substantially the same as the voltage of the input signal input to the drive signal generation circuit 530b is compared. When the voltage of the input signal A2_Out becomes higher than the voltage Vref_2, the comparator 562 outputs the pulse wave DMC_O to the second switching circuit 870 and the reference voltage adjustment circuit 570b.

  The reference voltage adjustment circuit 570b includes resistors R71 to R74, a capacitor C61, and an n-type FET (S62). One end of the resistor R71 is connected to the output of the DutyMax detection circuit 560b, and the other end of the resistor R71 is connected to the gate terminal of the FET (S62). The source terminal of the FET (S62) is grounded, and the drain terminal of the FET (S62) is connected to one end of the resistor R72, one end of the R73, and one end of the resistor R74. The other end of the resistor R72 is connected to a power source Vcc (an output voltage is also referred to as Vcc) of the power converter 800, and the other end of the resistor R73 is grounded. The other end of the resistor R74 is connected to one end of the capacitor C61 and the positive input terminal of the operational amplifier 551 of the voltage error detection circuit 550b. The initial voltage of the output V_Vref of the reference voltage adjusting circuit 570b, that is, the initial reference voltage is calculated by a calculation formula of Vcc × (R73 / (R73 + R72)). Note that R72 is the resistance value of the resistor R72, and R73 is the resistance value of the resistor R73. If the output from the DutyMax detection circuit 560b is low, the capacitor C61 is charged with the initial reference voltage. On the other hand, when the output from the DutyMax detection circuit 560b becomes high, charges are discharged from the capacitor C61, and the voltage of the capacitor C61 is output as V_Vref.

  The power limiting circuit 860 includes a resistor R75 and an n-type FET (S63). One end of the resistor R75 is connected to the output of the second switching circuit 870, and the other end of the resistor R75 is connected to the gate terminal of the FET (S63). The source terminal of the FET (S63) is grounded, and the drain terminal of the FET (S63) is connected to one end of the resistor R76 of the drive signal generation circuit 530b. Therefore, when the output of the DutyMax detection circuit 560b transmitted from the second switching circuit 870 becomes high, the FET (S63) is turned on, and as a result, the output of the drive signal generation circuit 530b is pulled low.

  Second switching circuit 870 includes analog switch 871. The output Pul_CV of the OR circuit 642 of the control switching circuit 640 described in FIG. 11 is connected to the control terminal of the analog switch 871 via the terminal D. The output of the comparator 562 of the DutyMax detection circuit 560b is connected to the input side terminal of the analog switch 871, and the output side terminal of the analog switch 871 is connected to the power limiting circuit 860. In this way, while the output of the voltage error detection circuit 550b is transmitted to the drive signal generation circuit 530b, the output of the DutyMax detection circuit 560b is transmitted to the power limiting circuit 860.

  Next, operation | movement of the power converter device 800 which concerns on a present Example is demonstrated using FIG.26 and FIG.27. As described above, the configuration and operation of the storage battery charge / discharge control circuit 600 are the same as those of the specific circuit example according to the third embodiment, and thus the description thereof is omitted.

  First, an operation in a state where power can be sufficiently supplied from the solar cell 100 at the power point A in FIG. 9A will be described with reference to FIGS. 26A to 26G. FIGS. 26A to 26G show an operation for a short time, and are diagrams for explaining the basic operation of the circuit shown in FIG.

  FIG. 26A shows a switching pulse Pul that is an output of the drive signal generation circuit 530b. During this time, the duty ratio is substantially constant. The output voltage Vo of the D / D converter circuit 510 shown in FIG. 26B and the output signal Vo_fb of the output voltage detection circuit 520 shown in FIG. 26C are shown exaggeratedly in the drawing. . However, the average value Vo_ave of the voltage of the output signal Vo of the D / D converter circuit 510 is substantially constant with only a fluctuation that causes a slight ripple according to switching. In the states of FIGS. 26A to 26G, the DutyMax detection circuit 560b, the reference voltage adjustment circuit 570b, and the power limiting circuit 860 are not operating effectively, and the power supply voltage Vcc is set to R73 / (R73 + R72). The voltage obtained by dividing resistance by the calculation formula is the output voltage V_Vref of the reference voltage adjustment circuit 570b.

  As shown in FIG. 26C, the voltage error detection circuit 550b compares Vo_fb and V_Vref, and as shown in FIG. 26D, the voltage output signal A2_Out is obtained by inverting the difference between Vo_fb and V_Vref. Is output. In the states of FIGS. 26A to 26G, the voltage of the output signal A2_Out is lower than the voltage Vref_2 used as a reference in the DutyMax detection circuit 560b and corresponding to the maximum duty ratio. Accordingly, as described above, the DutyMax detection circuit 560b and the reference voltage adjustment circuit 570b do not operate effectively. The state of not operating is shown in FIGS. That is, since the voltage of the output signal A2_Out is always lower than Vref_2, the output side signal DMC_O of the comparator 562 of the DutyMax detection circuit 560b remains off. Further, the FET (S62) of the reference voltage adjustment circuit 570b also remains off. Then, as shown in FIG. 26 (f), the output voltage V_Vref of the capacitor C61 becomes a value resulting from the resistance division of the voltage Vcc of the power source Vcc by the resistors R72 and R73 as described above.

  Further, as shown in FIG. 26 (g), since the output DMC_O of the DutyMax detection circuit 560b remains off, the FET (S63) of the power limiting circuit 860 also remains off, and the output Pul of the drive signal generation circuit 530b. There is no change.

  Next, the operation when the output Vo of the D / D converter circuit 510 starts to decrease will be described with reference to FIGS. 26 (a) to (i) are drawn so as to emphasize the features of the present embodiment, there are some differences from the actual ones.

  As described above and shown in FIGS. 27 (a) and (b), if the power supply from the solar cell 100 decreases or exceeds the maximum power point, the D / D converter circuit 510 attempts to draw power. While the duty ratio of the switching pulse Pul to the gate terminal of the FET (S1) of the / D converter circuit 510 is maximized, the output Vo of the D / D converter circuit 510 is lowered. As shown in FIG. 27C, when the output Vo decreases, the output Vo_fb of the output voltage detection circuit 520 also decreases.

  On the other hand, since the voltage error detection circuit 550b reverses the difference from the current V_Vref, when the output Vo_fb of the output voltage detection circuit 520 decreases, the output A2_Out of the voltage error detection circuit 550b increases on the contrary. Become. Then, as shown in FIG. 27 (d), the voltage of the output A2_Out of the voltage error detection circuit 550b gradually corresponds to the maximum value of the duty ratio of the switching pulse in the switching period for the FET (S1). The period exceeding Vref_2 becomes longer. As shown in FIG. 27 (e), the period during which the output DMC_O of the comparator 562 of the DutyMax detection circuit 560b is turned on gradually increases. On the other hand, since the FET (S63) of the power limiting circuit 860 is also turned on when DMC_O is turned on, as shown in FIG. 27 (f), the output V_pw of the power limiting circuit 860 is the same as that of the FET (S63). It becomes zero during the period.

  Further, since the FET (S62) of the reference voltage adjustment circuit 570b is also turned on in response to the output DMC_O of the DutyMax detection circuit 560b, the capacitor C61 is discharged. Therefore, the reference voltage V_Vref decreases as the discharge time increases and the discharge frequency increases. As shown in FIG. 27 (g), when the frequency (or ratio) at which the duty ratio of the switching pulse is maximized in the past predetermined period, the capacitor C61 is frequently discharged for a long period. As a result, V_Vref gradually decreases.

  Then, the voltage Vo_fb of the output voltage detection circuit 520 described with reference to FIG. 11 also decreases and the reference voltage V_Vref also decreases, so that the potential difference between the two signals input to the voltage error detection circuit 550b is narrowed. . Also, as shown in FIG. 27 (h), after the reference voltage V_Vref is lowered, the difference between the voltage Vo_fb of the output voltage detection circuit 520 and the reference voltage V_Vref becomes small, so that the operational amplifier of the voltage error detection circuit 550b The output A2_Out of 551 (here A2_Out after correction) also gradually decreases. Then, as shown in FIG. 27 (h), the period during which the voltage falls below the voltage of the triangular wave VTW_1 of the negative side input of the comparator 531 of the drive signal generation circuit 530b becomes longer. Then, as shown by the dotted line in the time axis direction in FIG. 27 (i), the ON width of the switching pulse (represented as corrected Pul) is shortened.

  As described above, the voltage error detection circuit 550b increases the duty ratio, extends the ON period of the FET (S1) of the D / D converter circuit 510, and tries to extract more power from the solar cell 100. Operate. As a result, it seems as if this operation was effective. Therefore, since the difference between the voltage Vo_fb of the output voltage detection circuit 520 and the reference voltage V_Vref is reduced, the duty ratio is reduced.

  However, as indicated by the solid line in FIG. 27 (i), the period during which DMC_O is turned on is forcibly set to zero by the power limiting circuit 860, so that it is not as compared with the case of the third embodiment. The switching width of the switching pulse (Pul after correction) is shortened early. That is, the drive level of the D / D converter circuit 510 is lowered early. As a result, the maximum power point can be tracked at high speed.

  As a result, the power drawn from the solar cell 100 is reduced as described above, and the output Vo of the D / D converter circuit 510 is increased. After that, if the D / D converter circuit 510 operates so as to draw power from the solar cell 100, the voltage Vo decreases as shown in FIG. 27B, so the operation described above is repeated. That is, the maximum power point is tracked.

  In this way, the maximum power point tracking can be performed with only an inexpensive element without using an expensive processor or the like.

[Other Specific Circuit Examples in Embodiment 5]
Instead of the DutyMax detection circuit 560b and the reference voltage adjustment circuit 570b shown in FIG. 25, a DutyMax detection circuit 560c and a reference voltage adjustment circuit 570c as shown in FIG. 28 may be adopted.

  The DutyMax detection circuit 560c includes open collector type comparators 564 and 565, a DC power supply Vref_2 that outputs a voltage Vref_2, and a resistor R81.

  The output A2_Out of the voltage error detection circuit 550b is input to the negative input terminal of the comparator 564 and the positive input terminal of the comparator 565 via the analog switch 583. The positive input terminal of the DC power supply Vref_2 is connected to the positive input terminal of the comparator 564, and the positive terminal of the DC power supply Vref_2 is connected to the negative input terminal of the comparator 565. The negative terminal of the DC power supply Vref_2 is grounded. The output terminal of the comparator 565 is connected to the power supply Vcc via the resistor R81 and is also connected to the input side terminal of the second switching circuit 870.

  The reference voltage adjustment circuit 570c includes resistors R83 to R85 and a capacitor C62. The output terminal of the comparator 564 is connected to one end of the resistor R83, one end of the resistor R84, and one end of the resistor R85, and the other end of the resistor R83 is connected to the power source Vcc. The other end of the resistor R84 is grounded, and the other end of the resistor R85 is connected to one end of the capacitor C62 and the positive input terminal of the operational amplifier 551 of the voltage error detection circuit 550b. The other end of the capacitor C62 is grounded. By using the open collector type comparator 564 in this way, the FET of the reference voltage adjustment circuit 570b is reduced by one. Since the FET of the reference voltage adjustment circuit 570b is removed, the input of the comparator 564 is reversed from that in FIG. That is, the output of the comparator 564 is high until the voltage of the signal A2_Out reaches a voltage corresponding to the maximum value of the duty ratio of the switching pulse. However, since it is an open collector type comparator 564, the voltage value calculated by the formula Vcc × [R84 / (R84 + R83)] as the initial reference voltage obtained by dividing the resistance of the capacitor C62 with the resistors R83 and R84. Is applied and charges are charged. On the other hand, when the voltage of the signal A2_Out reaches the voltage corresponding to the maximum value of the duty ratio of the switching pulse, the output of the comparator 564 becomes low, and the charge is discharged from the capacitor C62 because the comparator 564 is an open collector type. It becomes like this.

  The second switching circuit 870 and the power limiting circuit 860 are the same as those in FIG.

[Embodiment 6]
FIG. 29 shows a functional block diagram of a system according to the sixth embodiment. Note that this embodiment is a modification of the third embodiment. The system shown in FIG. 29 is a solar cell system, and includes a solar cell 100, a power conversion device 900 that performs power conversion on the output from the solar cell 100, and an output from the power conversion device 900 for the load storage battery 300. A storage battery charge / discharge control circuit 600 that outputs signals necessary for the charge / discharge control and power conversion apparatus 900, a load storage battery 300 connected to the output of the storage battery charge / discharge control circuit 600, and various loads A to C, etc. Have The solar cell 100 and the load storage battery 300 are the same as the conventional one. Also, the loads A to C are the same as those in the first embodiment.

  The configuration and operation of the storage battery charge / discharge control circuit 600 according to the present embodiment is the same as that of the above-described embodiment, and the control switching according to FIG. 4, that is, constant voltage control with constant current control and MPPT. Is switched in the same manner as in the embodiment described above. Therefore, the description is omitted.

  The power conversion device 900 includes (A) a D / D converter circuit 510 having a switch and DC / DC converting the output voltage from the solar cell 100, and (B) depending on the output voltage of the D / D converter circuit 510. An output voltage detection circuit 520 that outputs a voltage output signal; (C) a voltage error detection circuit 550c that generates a signal corresponding to the difference between the voltage of the output signal of the output voltage detection circuit 520 and a reference voltage; and (D). A current error detection circuit 540 that generates a voltage signal corresponding to the difference between the voltage corresponding to the storage battery charge current from the storage battery charge / discharge control circuit 600 and the voltage corresponding to the reference current value; and (E) the storage battery charge / discharge control circuit. A switching circuit 580 for switching the output of the error signal synthesis circuit 910 connected to the current error detection circuit 540 or the voltage error detection circuit 550c in response to a control switching signal from 600; ) In response to the output from the error signal synthesis circuit 910 connected to the current error detection circuit 540 or the voltage error detection circuit 550c, a switching pulse for the switch of the D / D converter circuit 510 is generated to the D / D converter circuit 510. A drive signal generation circuit 530 to output, and (G) a DutyMax detection circuit 560c that receives a signal corresponding to the duty ratio of the switching pulse from the voltage error detection circuit 550c and detects that the duty ratio has reached a predetermined maximum value; (H) a reference voltage adjustment circuit 570c that adjusts an initial reference voltage according to a detection signal from the DutyMax detection circuit 560c and outputs the adjusted reference voltage to the voltage error detection circuit 550c; and (I) a DutyMax detection circuit 560c. Check that the duty ratio has reached the predetermined maximum value. A power limiting circuit 860b that acts to lower the duty ratio when output, and (J) an error signal synthesis circuit 910 that adjusts the output signal from the voltage error detection circuit 550c according to the output from the power limiting circuit 860b. Have.

  The MPPT is realized by the output voltage detection circuit 520, the voltage error detection circuit 550c, the drive signal generation circuit 530, the DutyMax detection circuit 560c, the reference voltage adjustment circuit 570c, the power limiting circuit 860b, and the error signal synthesis circuit 910 described above. A constant voltage control circuit is configured. The current error detection circuit 540 and the drive signal generation circuit 530 constitute a constant current control circuit.

  The operation of the constant current control circuit configured by the current error detection circuit 540 and the drive signal generation circuit 530 is the same as that described in the third embodiment, and the description thereof is omitted here.

  Next, an output voltage detection circuit 520, a voltage error detection circuit 550c, a drive signal generation circuit 530, a DutyMax detection circuit 560c, a reference voltage adjustment circuit 570c, a power limiting circuit 860b, and an error signal synthesis circuit 910 are configured to realize MPPT. The operation of the constant voltage control circuit will be briefly described.

  Until the DutyMax detection circuit 560c detects that the duty ratio of the switching pulse reaches a predetermined maximum value, an output signal corresponding to the difference between the output voltage Vo_fb of the output voltage detection circuit 520 and the initial reference voltage Vref_0 is generated. The The output signal of the voltage error detection circuit 550c is output to the drive signal generation circuit 530 via the switching circuit 580 without being adjusted by the error signal synthesis circuit 910 (no adjustment other than a slight level shift).

  On the other hand, when detecting that the duty ratio of the switching pulse has reached a predetermined maximum value, the DutyMax detection circuit 560c outputs a detection signal to the reference voltage adjustment circuit 570c and the power limiting circuit 860b. Then, the reference voltage adjustment circuit 570c generates the reference voltage V_Vref by adjusting the initial reference voltage Vref_0 to be lowered, and outputs the reference voltage V_Vref to the error signal synthesis circuit 910. The reduction width of the initial reference voltage Vref_0 is determined according to the frequency or rate at which the detection signal is output from the DutyMax detection circuit 560c within a predetermined period, for example.

  Further, when receiving the detection signal, the power limiting circuit 860b forcibly lowers the voltage of the output signal of the voltage error detection circuit 550c, for example, for a period in which the detection signal from the DutyMax detection circuit 560c continues to be high (that is, a switching pulse). The instruction signal is output to the error signal synthesis circuit 910 so that the duty ratio is forcibly reduced. Then, error signal synthesis circuit 910 adjusts the signal from voltage error detection circuit 550c to reduce the duty ratio of the switching pulse in accordance with the instruction signal from power limiting circuit 860b, and outputs the adjusted signal to switching circuit 580. To do.

  In this way, the duty ratio of the switching pulse can be reduced earlier than in the third embodiment, and the drive level of the D / D converter circuit 510 can be lowered early. That is, it is possible to correct the state where power is excessively extracted from the solar cell 100 at an early stage, and power maximum point tracking is performed at high speed.

  Although the power limiting circuit is introduced as in the fifth embodiment, if the sixth embodiment is adopted, the second switching circuit becomes unnecessary. Further, since the power limiting circuit 860 according to the fifth embodiment adjusts the switching pulse itself, there is a possibility that the power limiting circuit 860 may operate regardless of the pulse period of the switching pulse. On the other hand, if the sixth embodiment is adopted, the error signal synthesis circuit 910 adjusts the output signal of the voltage error detection circuit 550c, so that the duty ratio of the switching pulse is reduced without disturbing the pulse period of the switching pulse. Can do.

[Example of Embodiment 6]
FIG. 30 shows a specific circuit example in the sixth embodiment. The solar battery 100, the D / D converter circuit 510, the output voltage detection circuit 520, the load storage battery 300, the loads A to C, and the storage battery charge / discharge control circuit 600 are the same as those in the third embodiment. Omitted. That is, FIG. 30 shows a voltage error detection circuit 550c, a switching circuit 580, a drive signal generation circuit 530, a DutyMax detection circuit 560c, a reference voltage adjustment circuit 570c, a current error detection circuit 540, a power limit circuit 860b, and a new one. A specific circuit example of the error signal synthesis circuit 910 added to FIG.

  However, since the current error detection circuit 540, the drive signal generation circuit 530, and the switching circuit 580 are the same as those already described, description thereof is omitted.

  Similarly, the DutyMax detection circuit 560c, the reference voltage adjustment circuit 570c, and the voltage error detection circuit 550c are the same as the circuits described in the example of the fifth embodiment, and thus description thereof is omitted.

  The error signal synthesis circuit 910 includes an operational amplifier 6121, resistors R91 to R95, and a capacitor C71. The output A2_Out of the voltage error detection circuit 550c is connected to the positive input terminal of the operational amplifier 6121, and one end of the resistor R91 and one end of the resistor R95 are connected to the negative input terminal of the operational amplifier 6121. The other end of the resistor R91 is grounded, and the other end of the resistor R95 is connected to the output terminal of the operational amplifier 6121. The output terminal of the operational amplifier 6121 is connected to one end of the resistor R92, and the other end of the resistor R92 is connected to one end of the resistor R93 and the output V_pw of the power limiting circuit 860b. The other end of the resistor R93 is connected to one end of the capacitor C71, one end of the resistor R94, and the input side terminal of the switching circuit 580. The other end of the capacitor C71 and the other end of the resistor R94 are grounded.

  The operational amplifier 6121 of the error signal synthesis circuit 910 functions as a non-inverting buffer, and generates a signal obtained by multiplying the input A2_Out by (1 + R95 / R91) from the resistance values R95 and R91 of the resistors R95 and R91. The voltage of this signal is temporarily lowered by the output when the power limiting circuit 860b operates, but is smoothed by the low-pass filter of the resistors R93 and R94 and the capacitor C71. Then, a signal A3_Out is generated and output to the analog switch 583 of the switching circuit 580.

  The power limiting circuit 860b includes an n-type FET (S301) and a resistor R75. The drain terminal of the FET (S301) is connected to the connection point of the resistors R92 and R93, the gate terminal is connected to one end of the resistor R75, and the source terminal is grounded. The other end of the resistor R75 is connected to the output of the DutyMax detection circuit 560c. When the DutyMax detection circuit 560c informs that the duty ratio of the switching pulse has reached a predetermined maximum value, the FET (S301) is turned on, and the output of the operational amplifier 6121 of the error signal synthesis circuit 910 is output. , Act to forcibly pull down.

  Next, processing when performing constant voltage control with MPPT will be described with reference to FIGS. 31 and 32. As described above, the constant current control is as described above, and the switching of the control is the same as that described above, so the description thereof is omitted here.

  First, the operation in a state where power can be sufficiently supplied from the solar cell 100 at the power point A in FIG. 9A will be described with reference to FIGS. 31A to 31G. FIGS. 31A to 31G show an operation for a short time, and are diagrams for explaining the basic operation of the circuit shown in FIG.

  FIG. 31A shows a switching pulse Pul that is an output of the drive signal generation circuit 530. During this time, the duty ratio is substantially constant. The output voltage Vo of the D / D converter circuit 510 shown in FIG. 31 (b) and the output signal Vo_fb of the output voltage detection circuit 520 shown in FIG. 31 (c) are shown exaggeratedly in the drawing. . However, the average value Vo_ave of the voltage of the output signal Vo of the D / D converter circuit 510 is also constant with only a fluctuation that causes some ripples according to switching. In the states of FIGS. 31A to 31G, the DutyMax detection circuit 560c, the reference voltage adjustment circuit 570c, and the power limiting circuit 860b are not operating. A voltage obtained by dividing the power supply voltage Vcc by resistance as indicated by the calculation formula of R73 / (R73 + R72) is the output voltage V_Vref of the reference voltage adjusting circuit 570c.

  As shown in FIG. 31 (c), the voltage error detection circuit 550c compares Vo_fb and V_Vref, and as shown in FIG. 31 (d), an output signal of a voltage obtained by inverting the difference between Vo_fb and V_Vref. A2_Out is output. Further, as shown in FIG. 31 (d), the non-inverting buffer of the error signal synthesis circuit 910 generates a signal A3_Out having a voltage slightly higher than the output signal A2_Out. Since the difference is highlighted in FIG. 31D, such a difference is not actually produced.

  As shown in FIG. 31 (d), the voltage of the output signal A2_Out is lower than the voltage Vref_2 when the duty ratio of the switching pulse for the D / D converter circuit 510 is maximized, so the DutyMax detection circuit 560c, the reference voltage The adjustment circuit 570c and the power limiting circuit 860b do not operate. That is, as shown in FIGS. 31E to 31G, the output DMC_O of the DutyMax detection circuit 560c remains low and does not change, and as a result, the output V_Vref of the reference voltage adjustment circuit 570c does not change. Further, since the FET (S301) of the power limiting circuit 860b is not turned on, the output V_pw of the power limiting circuit 860b is constant as shown by the dotted line in the time axis direction in FIG.

  Next, the operation when the output Vo of the D / D converter circuit 510 starts to decrease will be described with reference to FIGS. Note that FIGS. 32A to 32I are drawn so as to emphasize the features of the present embodiment, and therefore, there are some differences from actual ones.

  As described above and shown in FIGS. 32 (a) and (b), if the power supply from the solar cell 100 decreases or exceeds the maximum power point, the D / D converter circuit 510 attempts to draw current. The duty ratio of the switching pulse Pul to the gate terminal of the FET (S1) of the / D converter circuit 510 is maximized. On the other hand, the output Vo of the D / D converter circuit 510 is lowered. As shown in FIGS. 32B and 32C, when the output Vo decreases, the output Vo_fb of the output voltage detection circuit 520 also decreases.

  On the other hand, since the voltage error detection circuit 550c inverts the difference between the output Vo_fb and the current V_Vref, if the Vo_fb of the output voltage detection circuit 520 decreases, the output A2_Out of the voltage error detection circuit 550c increases on the contrary. become. Then, as shown in FIG. 32 (d), the voltage of the output A2_Out of the voltage error detection circuit 550c gradually corresponds to the maximum value of the duty ratio of the switching pulse in the switching period for the FET (S1). The period exceeding Vref_2 becomes longer. Further, as shown in FIG. 32 (e), the period during which the output DMC_O of the comparator 562 of the DutyMax detection circuit 560c is turned on gradually increases. On the other hand, the FET (S301) of the power limiting circuit 860b is also turned on when the DMC_O is turned on. Therefore, as shown in FIG. 32 (f), the output V_pw of the power limiting circuit 860b is the same as that of the FET (S301). It becomes zero during the period.

  Further, the FET (S302) of the reference voltage adjustment circuit 570c is also turned on in accordance with the output DMC_O of the DutyMax detection circuit 560c, so that the capacitor C61 is discharged. Therefore, the reference voltage V_Vref decreases as the discharge time increases and the discharge frequency increases. As shown in FIG. 32 (g), when the frequency (or ratio) at which the duty ratio of the switching pulse is maximized in the past predetermined period, the capacitor C61 is discharged frequently and for a long period. As a result, V_Vref gradually decreases.

  Then, the voltage of the output Vo_fb of the output voltage detection circuit 520 also decreases and the reference voltage V_Vref also decreases, so that the potential difference between the two signals input to the voltage error detection circuit 550c is narrowed. Then, as shown in FIG. 32 (h), after the reference voltage V_Vref is lowered, the difference between the output voltage Vo_fb of the output voltage detection circuit 520 and the reference voltage V_Vref becomes small, so that the operational amplifier of the voltage error detection circuit 550c The output A2_Out of 551 (here A2_Out after correction) also gradually decreases.

  Further, a signal generated from the output A2_Out by the operational amplifier 6121 has the same waveform as the output A2_Out of FIG. 32D as shown by a dotted line in FIG. 32H if the power limiting circuit 860b does not exist. . For this reason, the output of the operational amplifier 6121 is forcibly lowered by the output V_pw of the power limiting circuit 860b shown in FIG. However, the voltage is lowered only during the period when the voltage is zero in FIG. Since a low-pass filter is provided at the subsequent stage of the operational amplifier 6121, as shown in FIG. 32 (h), the voltage of the output signal A3_Out decreases during the period when the voltage is zero in FIG. 32 (f). When the operation ends and the voltage of the output A2_Out increases, the voltage of the signal A3_Out also increases accordingly. That is, corrected A2_Out and corrected A3_Out are generated.

  Then, as shown in FIG. 32 (h), the period during which the voltage is lower than the voltage of the triangular wave VTW_1 at the negative input of the comparator 531 of the drive signal generation circuit 530 becomes longer. Therefore, when generating a switching pulse based on the output A3_Out (represented as corrected Pul) as compared to the case where the switching pulse is generated based on the corrected A2_Out as indicated by the dotted line in FIG. The width of the on is shorter.

  As described above, from the voltage error detection circuit 550c, the duty ratio is increased, the ON period of the FET (S1) of the D / D converter circuit 510 is lengthened, and more power is drawn from the solar cell 100. As a result, it seems as if this operation was effective. Accordingly, since the difference between the voltage of the output Vo_fb of the output voltage detection circuit 520 and the reference voltage V_Vref is reduced, the duty ratio is lowered. In this embodiment, the drive level of the D / D converter circuit 510 is lowered early by forcibly reducing the duty ratio of the switching pulse, but in accordance with the cycle of the switching pulse. That is, the maximum power point can be tracked at high speed without increasing the power consumption.

  As a result, the power drawn from the solar cell 100 is lowered, and the output Vo of the D / D converter circuit 510 is increased. After that, if the D / D converter circuit 510 operates so as to draw power from the solar battery 100, the voltage Vo decreases as shown in FIG. 32B, so that the operation as described above is repeated. become. That is, the maximum power point is tracked.

  In this way, the maximum power point tracking can be performed with only an inexpensive element without using an expensive processor or the like.

[Embodiment 7]
FIG. 33 shows a functional block diagram of a system according to the seventh embodiment. Note that this embodiment is a modification of the fourth embodiment. The system shown in FIG. 33 is a solar cell system, and includes a solar cell 100, a power conversion device 1100 that performs power conversion on the output from the solar cell 100, and an output from the power conversion device 1100 for the load storage battery 300. A storage battery charge / discharge control circuit 600 that outputs a signal required by the charge / discharge control and power converter 1100, a load storage battery 300 connected to the output of the storage battery charge / discharge control circuit 600, and various loads A to C, etc. Have The solar cell 100 and the load storage battery 300 are the same as the conventional one. Also, the loads A to C are the same as those in the first embodiment. Furthermore, since the configuration and operation of the storage battery charge / discharge control circuit 600 are the same as those in the fourth embodiment, the description thereof is omitted.

  The power conversion apparatus 1100 includes (A) a D / D converter circuit 510 having a switch and DC / DC converting the output voltage from the solar cell 100, and (B) depending on the output voltage of the D / D converter circuit 510. An output voltage detection circuit 520 that outputs a voltage output signal Vo_fb, and (C) a voltage obtained by adjusting the output signal Vo_fb from the output voltage detection circuit 520 (output of a voltage detection signal adjustment circuit 780b described below) and a fixed reference A voltage error detection circuit 770b that generates a signal A2_Out corresponding to the difference from the voltage, and (D) a difference between a voltage corresponding to the storage battery charging current from the storage battery charge / discharge control circuit 600 and a voltage corresponding to the reference current value. A current error detection circuit 540 that generates a signal A1_Out of the detected voltage, and (E) a current error detection circuit 540 or a control signal Pul_CV from the storage battery charge / discharge control circuit 600. A switching circuit 580 for switching to the output from the voltage error detection circuit 770b, and (F) generating a switching pulse for the switch of the D / D converter circuit 510 in accordance with the output from the current error detection circuit 540 or the voltage error detection circuit 770b. A drive signal generation circuit 530b that outputs to the D / D converter circuit 510, and (G) a signal corresponding to the duty ratio of the switching pulse is received from the drive signal generation circuit 530b, and it is detected that the duty ratio has reached a predetermined maximum value. DutyMax detection circuit 760b that performs adjustment, and (H) the output voltage Vo_fb from output voltage detection circuit 520 is adjusted in accordance with the detection signal from DutyMax detection circuit 760b, and the signal of adjusted output voltage Vof3 is supplied to voltage error detection circuit 770b. A voltage detection signal adjustment circuit 780b to output, and (I) MPP A power limiting circuit 860c that acts to forcibly lower the duty ratio of the switching pulse when the duty ratio of the switching pulse reaches a predetermined maximum value while performing constant voltage control including When constant voltage control involving MPPT is performed in conjunction with the switching circuit 580, that is, when the output of the voltage error detection circuit 770b is input to the drive signal generation circuit 530b, the output of the DutyMax detection circuit 760b is transmitted to the power limiting circuit 860c. 2 switching circuit 870.

  The output voltage detection circuit 520, voltage error detection circuit 770b, drive signal generation circuit 530b, DutyMax detection circuit 760b, voltage detection signal adjustment circuit 780b, and power limiting circuit 860c described above constitute a voltage control circuit that realizes MPPT. Is done. The current error detection circuit 540 and the drive signal generation circuit 530b constitute a constant current control circuit.

  The constant current control circuit configured by the current error detection circuit 540 and the drive signal generation circuit 530b is the same as that in the fourth embodiment, and thus further description thereof is omitted.

  Voltage control that realizes MPPT, which includes the output voltage detection circuit 520, the voltage error detection circuit 770b, the drive signal generation circuit 530b, the DutyMax detection circuit 760b, the voltage detection signal adjustment circuit 780b, and the power limiting circuit 860c described above. The operation of the circuit is the same as that of the fourth embodiment except for the operations of the second switching circuit 870 and the power limiting circuit 860c.

  That is, in a state where the D / D converter circuit 510 draws too much current from the solar battery 100 and the output voltage decreases, the voltage error detection circuit 770b and the drive signal generation circuit 530b set the duty ratio of the switching pulse to a predetermined maximum. Try to raise the voltage to the value. On the other hand, when detecting the state in which the duty ratio of the switching pulse is a predetermined maximum value, the DutyMax detection circuit 760b outputs a detection signal to the voltage detection signal adjustment circuit 780b. The voltage detection signal adjustment circuit 780b increases the voltage of the detection signal of the output voltage detection circuit 520 according to the frequency (or rate) of detecting the state where the duty ratio of the switching pulse is a predetermined maximum value within a predetermined period. Thus, the difference from the reference voltage V_Vref is narrowed.

  Note that the power drawn from the solar cell 100 by driving the D / D converter circuit 510 by the voltage error detection circuit 770b and the drive signal generation circuit 530b also decreases, and the power and the output power of the solar cell 100 are shown in FIG. The power point B of a) is balanced. Then, the output voltage Vo and the output power Pout of the power conversion device 1100 stop decreasing.

  In the present embodiment, during constant voltage control involving MPPT, the second switching circuit 870 performs switching so as to output the detection signal from the DutyMax detection circuit 760b to the power limiting circuit 860c. In response to the detection signal from the DutyMax detection circuit 760b, the power limiting circuit 860c acts to forcibly reduce the duty ratio of the switching pulse generated and output by the drive signal generation circuit 530b.

  Thereafter, when the difference between the reference voltage Vref_1 and the voltage Vof3 of the adjusted detection signal becomes narrower, the voltage error detection circuit 770b and the drive signal generation circuit 530b lower the duty ratio of the switching pulse from a predetermined maximum value. The adjustment amount for the post-adjustment detection signal has a time constant, and does not immediately become 0, so it gradually decreases.

  Portions other than such operations are almost the same as in the fourth embodiment. Therefore, as in the fourth embodiment, the maximum power point can be tracked at high speed with an inexpensive circuit element.

[Example of Embodiment 7]
FIG. 34 shows a specific circuit example in the seventh embodiment. Note that the solar cell 100, the D / D converter circuit 510, the output voltage detection circuit 520, the storage battery charge / discharge control circuit 600, the loads A to C, and the like are the same as those in the third embodiment, and are not shown. Further, the operation of the storage battery charge / discharge control circuit 600 also realizes the control switching shown in FIG.

  In addition, the configurations and operations of the current error detection circuit 540 and the switching circuit 580 are the same as those in the fourth embodiment, and thus description thereof is omitted.

  The DutyMax detection circuit 760b includes a comparator 5511 and a DC power supply Vref_2 that outputs a voltage Vref_2. The positive input terminal of the comparator 5511 is connected to the output terminal of the switching circuit 580, and the negative input terminal of the comparator 5511 is connected to the positive terminal of the DC power supply Vref_2. The negative terminal of the DC power supply Vref_2 is grounded. The output of the comparator 5511 is connected to the voltage detection signal adjustment circuit 780b.

  The comparator 5511 of the DutyMax detection circuit 760b is input to the drive signal generation circuit 530b when the duty ratio between the input signal A_Out to the drive signal generation circuit 530b and the switching pulse Pu that is the output of the drive signal generation circuit 530b is maximized. The output voltage Vref_2 of the DC power supply Vref_2 that outputs substantially the same voltage as the signal A_Out is compared. When the voltage of the signal A_Out becomes higher than the voltage Vref_2, the comparator 5511 outputs the pulse wave DMC_O to the voltage detection signal adjustment circuit 780b and the power limiting circuit 870 during that time.

  The voltage detection signal adjustment circuit 780b includes operational amplifiers 5311 and 5312, resistors R102 to R109, a transistor T2, a capacitor C101, and two DC power sources V_Vref that output a voltage V_Vref.

  One end of the resistor R108 is connected to the output of the DutyMax detection circuit 760b, and the other end of the resistor R108 is connected to one end of the resistor R109, one end of the resistor R107, and one end of the capacitor C101. The other end of the resistor R109 and the other end of the capacitor C101 are grounded. The other end of the resistor R107 is connected to the base terminal of the transistor T2. The emitter terminal of the transistor T2 is grounded, and the collector terminal is connected to one end of the resistor R106.

  Further, one end of the resistor R102 is connected to the output Vo_fb of the output voltage detection circuit 520, and the other end of the resistor R102 is connected to one end of the resistor R103 and the negative input terminal of the operational amplifier 5311. The positive input terminal of the operational amplifier 5311 is connected to the positive terminal of the DC power supply V_Vref, and the negative terminal of the DC power supply V_Vref is grounded. The other end of the resistor R103 is connected to the output terminal of the operational amplifier 5311, the other end of the resistor R106, and one end of the resistor R104.

  The other end of the resistor R104 is connected to one end of the resistor R105 and the negative input terminal of the operational amplifier 5312. The positive input terminal of the operational amplifier 5312 is connected to the positive terminal of the DC power supply V_Vref, and the negative terminal of the DC power supply V_Vref is grounded. The other end of the resistor R105 is connected to the output terminal of the operational amplifier 5312 and the input of the voltage error detection circuit 770b.

  When the output DMC_O of the DutyMax detection circuit 760b is turned on, charges are stored in the capacitor C101. When the frequency and period when DMC_O is turned on become longer, charges are accumulated in the capacitor C101, and the voltage VGB applied to the base terminal of the transistor T2 also rises. Then, the transistor T2 is turned on, so that the output voltage of the operational amplifier 5311 is lowered.

  Note that the operational amplifier 5311 inverts the output Vo_fb of the output voltage detection circuit 520, and acts to lower the output voltage Vof2 of the operational amplifier 5311 when the transistor T2 is turned on. Then, the operational amplifier 5312 inverts the output Vof2 again and outputs the output Vof3 to the voltage error detection circuit 770b as the output of the voltage detection signal adjustment circuit 780b. More specifically, when Vof2 is lowered, Vof3 is raised, and acts on the voltage error detection circuit 770b as if the output Vo_fb of the output voltage detection circuit 520 is increased.

  Second switching circuit 870 includes analog switch 871. The control terminal of the analog switch 871 is connected to the output Pul_CV of the control switching circuit 640 via the terminal D, and the input side terminal of the analog switch 871 is connected to the output of the DutyMax detection circuit 760b. The output side terminal is connected to the input of the power limiting circuit 860c. Thus, the analog switch 871 transmits the output of the DutyMax detection circuit 760b to the power limiting circuit 860c when the control switching circuit 640 outputs high, and when the control switching circuit 640 outputs low, the DutyMax detection circuit 760b. The output of is shut off.

  The power limiting circuit 860c includes an n-type FET (S81) and a resistor R81. One end of the resistor R81 is connected to the output of the second switching circuit 870, and the other end of the resistor R81 is connected to the gate terminal of the FET (S81). The source terminal of the FET (S81) is grounded, and the drain terminal of the FET (S1) of the D / D converter circuit 510 is connected to one end of the resistor R76 connected to the output of the drive signal generation circuit 530b and the terminal A. Connected to the gate terminal. Therefore, when the signal DMC_O output from the DutyMax detection circuit 760b via the second switching circuit 870 becomes high, the FET (S81) is turned on, and the output of the drive signal generation circuit 530b is forcibly lowered to low. By doing so, the duty ratio of the switching pulse Pul can be lowered, so that the drive level of the D / D converter circuit 510 can be lowered early and the maximum power point can be tracked at high speed.

  Next, the main part of the operation of the circuit shown in FIG. 34 will be described with reference to FIG. The description of the constant current control is omitted, and the operation when the comparator 5511 of the DutyMax detection circuit 760b is not turned on is the same as the operation in the fourth embodiment, so the description is omitted.

  The operation when the output Vo of the D / D converter circuit 510 starts to decrease will be described with reference to FIGS. 35 (a) to (i). 35A to 35I are drawn so as to emphasize the features of the present embodiment, there are some differences from the actual ones.

  As described above and shown in FIGS. 35 (a) and (b), if the power supply from the solar cell 100 decreases or exceeds the maximum power point, the D / D converter circuit 510 attempts to draw power. The duty ratio of the switching pulse Pul to the gate terminal of the FET (S1) of the / D converter circuit 510 is maximized. On the other hand, the output Vo of the D / D converter circuit 510 is lowered. As shown in FIGS. 35B and 35C, when the output Vo decreases, the output Vo_fb of the output voltage detection circuit 520 also decreases.

  On the other hand, since the voltage error detection circuit 770b inverts the difference between the output Vo_fb and the fixed reference voltage V_Vref, the voltage error is detected when the output Vo_fb of the output voltage detection circuit 520 decreases and no adjustment is made to Vof2. On the contrary, the output A2_Out of the detection circuit 770b rises. Then, as shown in FIG. 35 (d), the voltage of the output A2_Out of the voltage error detection circuit 770b gradually corresponds to the maximum value of the duty ratio of the switching pulse in the switching period for the FET (S1). The period exceeding Vref_2 becomes longer. Further, as shown in FIG. 35 (e), the period during which the output DMC_O of the comparator 5511 of the DutyMax detection circuit 760b is turned on gradually becomes longer. That is, when the frequency (or ratio) at which the duty ratio of the switching pulse is maximized within a predetermined period in the past, the frequency and period during which the transistor T2 is turned on becomes longer, as shown by a thin solid line in FIG. The output voltage Vof2 of the operational amplifier 5311 of the voltage detection signal adjustment circuit 780b is lowered. The dotted line represents the curve when no adjustment is made. Then, the output Vof3 of the voltage detection signal adjustment circuit 780b increases on the contrary.

  On the other hand, since the reference voltage V_Vref is fixed, the potential difference between the two signals input to the voltage error detection circuit 770b is narrowed. Then, as shown in FIG. 35 (h), after the output Vof3 of the voltage detection signal adjustment circuit 780b is raised, the difference between the voltage of the output Vof3 and the reference voltage V_Vref becomes small, so that the operational amplifier of the voltage error detection circuit 770b. The output A2_Out 771 (A2_Out after correction) of 771 gradually decreases.

  Then, as shown in FIG. 35 (h), the period during which the voltage falls below the voltage of the triangular wave VTW_1 at the negative input terminal of the comparator 531 of the drive signal generation circuit 530b becomes longer. Then, as indicated by a solid line in FIG. 35 (i), the ON width of the Pul after switching pulse correction is shortened. That is, from the voltage error detection circuit 770b, the duty ratio is increased, the ON period of the FET (S1) of the D / D converter circuit 510 is lengthened, and an operation is performed to draw more power from the solar cell 100. . As a result, it acts as if this operation had an effect. Therefore, since the difference between the voltage of the output Vof3 of the voltage detection signal adjustment circuit 780b and the reference voltage V_Vref is reduced, the duty ratio is reduced.

  Further, in this embodiment, as shown in FIG. 35 (g), when the output DMC_O of the DutyMax detection circuit 760b is turned on, the output of the power limiting circuit 860c becomes zero. That is, since the switching pulse for the switch of the D / D converter circuit 510 is forcibly turned off, the pulse width is further narrowed as shown by a solid line in FIG. Thus, the maximum power point can be tracked at high speed by lowering the drive level by the D / D converter circuit 510 at an early stage.

  As a result, the power drawn from the solar cell 100 is reduced as described above, and the output Vo of the D / D converter circuit 510 is increased. After that, if the D / D converter circuit 510 operates so as to draw power from the solar battery 100, the voltage Vo will decrease as shown in FIG. 35B, so that the operation described above is repeated. become. That is, the maximum power point is tracked.

  In this way, the maximum power point tracking can be performed with only an inexpensive element without using an expensive processor or the like.

[Embodiment 8]
FIG. 36 shows a functional block diagram of a system according to the eighth embodiment. Note that this embodiment is a modification of the sixth and seventh embodiments. The system shown in FIG. 36 is a solar cell system, and includes a solar cell 100, a power conversion device 1200 that performs power conversion on the output from the solar cell 100, and an output from the power conversion device 1200 for the load storage battery 300. A storage battery charge / discharge control circuit 600 that outputs a signal required by the charge / discharge control and power converter 1200, a load storage battery 300 connected to the output of the storage battery charge / discharge control circuit 600, and various loads A to C, etc. Have The solar cell 100 and the load storage battery 300 are the same as the conventional one. Also, the loads A to C are the same as those in the first embodiment. Furthermore, since the configuration and operation of the storage battery charge / discharge control circuit 600 are the same as those in the fourth embodiment, the description thereof is omitted.

  The power converter 1200 includes (A) a D / D converter circuit 510 that includes a switch and DC / DC converts the output voltage from the solar cell 100, and (B) corresponds to the output voltage of the D / D converter circuit 510. An output voltage detection circuit 520 that outputs a voltage output signal; and (C) a signal obtained by adjusting an output signal from the output voltage detection circuit 520 (output voltage of a voltage detection signal adjustment circuit 780c described below) and a fixed reference voltage A voltage error detection circuit 770c that generates a signal corresponding to the difference; and (D) a current that generates a signal A1_Out of a voltage corresponding to the difference between the output of the storage battery charging current from the storage battery charge / discharge control circuit 600 and the reference current value. The error detection circuit 540 and (E) the current error detection circuit 540 or the voltage error detection circuit according to the control switching signal Pul_CV from the storage battery charge / discharge control circuit 600 The switching circuit 580 for switching to the output A3_Out of the error signal synthesis circuit 930 connected to 770c, and (F) the output A3_Out from the error signal synthesis circuit 930 connected to the current error detection circuit 540 or the voltage error detection circuit 770c. In response to this, a drive signal generation circuit 530c that generates a switching pulse for the switch of the D / D converter circuit 510 and outputs it to the D / D converter circuit 510, and (G) a voltage error detection circuit 770c according to the duty ratio of the switching pulse The DutyMax detection circuit 760c that receives the signal and detects that the duty ratio has reached a predetermined maximum value, and (H) adjusts the output voltage Vo_fb from the output voltage detection circuit 520 according to the detection signal from the DutyMax detection circuit 760c Adjusted output voltage Vof3 signal The voltage detection signal adjustment circuit 780c output to the voltage error detection circuit 770c and (I) the duty of the switching pulse when the duty ratio of the switching pulse becomes a predetermined maximum value while performing constant voltage control with MPPT A power limiting circuit 860d that acts to forcibly reduce the ratio; and (J) a switching circuit that adjusts the output signal from the voltage error detection circuit 770c to decrease the duty ratio in accordance with the output from the power limiting circuit 860d. And an error signal synthesis circuit 930 for outputting to 580.

  The voltage control circuit for realizing the MPPT includes the output voltage detection circuit 520, the voltage error detection circuit 770c, the drive signal generation circuit 530c, the DutyMax detection circuit 760c, the voltage detection signal adjustment circuit 780c, the power limit circuit 860d, and the error signal. And a synthesis circuit 930. The constant current control circuit includes a current error detection circuit 540 and a drive signal generation circuit 530c.

  The constant current control circuit configured by the current error detection circuit 540 and the drive signal generation circuit 530c is the same as that in the fourth embodiment, and thus description thereof is omitted.

  The output voltage detection circuit 520, the voltage error detection circuit 770c, the drive signal generation circuit 530c, the DutyMax detection circuit 760c, the voltage detection signal adjustment circuit 780c, the power limiting circuit 860d, and the error signal synthesis circuit 930 described above are included, and MPPT The operation of the constant voltage control circuit realizing the above is as follows.

  That is, in a state where the D / D converter circuit 510 draws too much current from the solar cell 100 and the output voltage decreases, the voltage error detection circuit 770c and the drive signal generation circuit 530c set the duty ratio of the switching pulse to a predetermined maximum. Try to raise the voltage to the value. On the other hand, when detecting the state where the duty ratio of the switching pulse is a predetermined maximum value, the DutyMax detection circuit 760c outputs a detection signal to the voltage detection signal adjustment circuit 780c. The voltage detection signal adjustment circuit 780c increases the voltage of the detection signal of the output voltage detection circuit 520 according to the frequency (or ratio) of detecting the state where the duty ratio of the switching pulse is a predetermined maximum value within a predetermined period. Thus, the difference from the reference voltage V_Vref is narrowed.

  Note that the power drawn from the solar cell 100 by driving the D / D converter circuit 510 by the voltage error detection circuit 770c and the drive signal generation circuit 530c also decreases, and the power and the output power of the solar cell 100 are shown in FIG. The power point B of a) is balanced. As a result, the output voltage Vo and the output power Pout of the power conversion device 1200 stop decreasing.

  In the present embodiment, the power limiting circuit 860d causes the duty ratio of the switching pulse to the switch of the D / D converter circuit 510 to decrease with respect to the error signal synthesis circuit 930 in response to the detection signal from the DutyMax detection circuit 760c. The output signal from the voltage error detection circuit 770c is adjusted. In response to an instruction from the power limiting circuit 860d, the error signal synthesis circuit 930 adjusts the output signal from the voltage error detection circuit 770c so that the duty ratio of the switching pulse decreases, and outputs the adjusted signal. The signal is output to the drive signal generation circuit 530c via the switching circuit 580. As a result, the drive level of the D / D converter circuit 510 can be lowered earlier.

  Thereafter, when the difference between the reference voltage V_Vref and the voltage Vof3 of the adjusted detection signal becomes narrower, the voltage error detection circuit 770c and the drive signal generation circuit 530c lower the duty ratio of the switching pulse from a predetermined maximum value. Further, since the adjustment amount of the detection signal after adjustment has a time constant, it does not immediately become 0 but gradually decreases. However, since there is also an adjustment by the power limiting circuit 860d, the effect is easily obtained as compared with the case where the power limiting circuit 860d is not used. Further, since the switching pulse is not directly adjusted, the adjustment is performed according to the cycle of the switching pulse, so that the on / off of the pulse does not frequently occur, and the problem that the power consumption increases can be avoided.

  Portions other than such operations are almost the same as in the fourth embodiment. Therefore, as in the fourth embodiment, the maximum power point can be traced by an inexpensive circuit element.

[Example of Embodiment 8]
FIG. 37 shows a specific circuit example according to the eighth embodiment. The solar cell 100, the D / D converter circuit 510, the output voltage detection circuit 520, the loads A to C, and the like are the same as those in the third embodiment, and thus are not shown. Further, the operation of the storage battery charge / discharge control circuit 600 also realizes the control switching shown in FIG.

  In addition, the configurations and operations of the current error detection circuit 540 and the switching circuit 580 are the same as those in the fourth embodiment, and thus description thereof is omitted.

  The DutyMax detection circuit 760c includes a comparator 5511 and a DC power supply Vref_2 that outputs a voltage Vref_2. The positive input terminal of the comparator 5511 is connected to the output terminal of the voltage error detection circuit 770c, and the negative input terminal of the comparator 5511 is connected to the positive terminal of the DC power supply Vref_2. The negative terminal of the DC power supply Vref_2 is grounded. The output DMC_O of the comparator 5511 is connected to the voltage detection signal adjustment circuit 780c.

  The comparator 5511 of the DutyMax detection circuit 760c outputs from the voltage error detection circuit 770c when the duty ratio between the output signal A2_Out from the voltage error detection circuit 770c and the switching pulse output from the drive signal generation circuit 530c is maximized. The output voltage Vref_2 of the DC power supply Vref_2 that outputs a voltage substantially the same as the voltage of the signal A2_Out is compared. When the voltage of the signal A2_Out becomes higher than the voltage Vref_2, the comparator 5511 outputs an output DMC_O that is a pulse wave during that time to the voltage detection signal adjustment circuit 780c and the power limiting circuit 860d.

  The voltage detection signal adjustment circuit 780c includes operational amplifiers 5311 and 5312, resistors R102 to R109, a transistor T2, a capacitor C101, and a DC power supply V_Vref that outputs a voltage V_Vref.

  One end of the resistor R108 is connected to the output DMC_O of the DutyMax detection circuit 760c, and the other end of the resistor R108 is connected to one end of the resistor R109, one end of the resistor R107, and one end of the capacitor C101. The other end of the resistor R109 and the other end of the capacitor C101 are grounded. The other end of the resistor R107 is connected to the base terminal of the transistor T2. The emitter terminal of the transistor T2 is grounded, and the collector terminal is connected to one end of the resistor R106.

  Further, one end of the resistor R102 is connected to the output Vo_fb of the output voltage detection circuit 520, and the other end of the resistor R102 is connected to one end of the resistor R103 and the negative input terminal of the operational amplifier 5311. The positive input terminal of the operational amplifier 5311 is connected to the positive terminal of the DC power supply V_Vref, and the negative terminal of the DC power supply V_Vref is grounded. The other end of the resistor R103 is connected to the output terminal of the operational amplifier 5311, the other end of the resistor R106, and one end of the resistor R104.

  The other end of the resistor R104 is connected to one end of the resistor R105 and the negative input terminal of the operational amplifier 5312. The positive input terminal of the operational amplifier 5312 is connected to the positive terminal of the DC power supply V_Vref, and the negative terminal of the DC power supply V_Vref is grounded. The other end of the resistor R105 is connected to the output terminal of the operational amplifier 5312 and the input of the voltage error detection circuit 770c.

  When the output DMC_O of the DutyMax detection circuit 760c is turned on, charge is stored in the capacitor C101. When the frequency and period when DMC_O is turned on become longer, charges are accumulated in the capacitor C101, and the voltage VGB applied to the base terminal of the transistor T2 also rises. Then, the transistor T2 is turned on, so that the output voltage of the operational amplifier 5311 is lowered.

  Note that the operational amplifier 5311 inverts the output Vo_fb of the output voltage detection circuit 520. When the transistor T2 is turned on, the operational amplifier 5311 further acts to lower the voltage of the output Vof2 of the operational amplifier 5311. Then, the operational amplifier 5312 inverts the output Vof2 again and outputs the output Vof3 to the voltage error detection circuit 770c as the output of the voltage detection signal adjustment circuit 780c. More specifically, when Vof2 is lowered, Vof3 is raised, and it appears to the voltage error detection circuit 770c as if the output Vo_fb of the output voltage detection circuit 520 has increased.

  The voltage error detection circuit 770c is connected to the output of the voltage detection signal adjustment circuit 780c, and includes resistors R41 to R44, capacitors C41 and C42, an operational amplifier 4311, and a DC power supply V_Vref that outputs a fixed reference voltage V_Vref. . The output of the voltage detection signal adjustment circuit 780c is connected to one ends of the resistors R41 and R42, the other end of the resistor R42 is connected to one end of the capacitor C41, and the other end of the capacitor C41 and the other end of the resistor R41 are connected to the operational amplifier 4311. Connected to the negative input terminal. The negative input terminal of the operational amplifier 4311 is connected to one end of the capacitor C42 and one end of the resistor R43, the other end of the capacitor C42 is connected to one end of the resistor R44, and the other end of the resistor R44 and the resistor R43. Is connected to the output terminal of the operational amplifier 4311. Further, the positive input terminal of the operational amplifier 4311 is connected to the positive input terminal of the DC power supply V_Vref. The negative terminal of the DC power supply V_Vref is grounded.

  The error signal synthesis circuit 930 includes an operational amplifier 6121, resistors R91 to R95, and a capacitor C71. The output A2_Out of the voltage error detection circuit 770c is connected to the positive input terminal of the operational amplifier 6121, and one end of the resistor R91 and one end of the resistor R95 are connected to the negative input terminal of the operational amplifier 6121. The other end of the resistor R91 is grounded, and the other end of the resistor R95 is connected to the output terminal of the operational amplifier 6121. The output terminal of the operational amplifier 6121 is connected to one end of the resistor R92, and the other end of the resistor R92 is connected to one end of the resistor R93 and the output of the power limiting circuit 860d. The other end of the resistor R93 is connected to one end of the capacitor C71, one end of the resistor R94, and the input side terminal of the analog switch 583 in the switching circuit 580. The other end of the capacitor C71 and the other end of the resistor R94 are grounded.

  The operational amplifier 6121 of the error signal synthesis circuit 930 functions as a non-inverting buffer, and generates a signal obtained by multiplying the input A2_Out by (1 + R95 / R91) from the resistance values R95 and R91 of the resistors R95 and R91. This signal is temporarily pulled down by the output when the power limiting circuit 860d operates, but is smoothed by the low-pass filter of the resistors R93 and R94 and the capacitor C71. Then, a signal A3_Out is generated and output to the analog switch 583 of the switching circuit 580.

  The power limiting circuit 860d includes an n-type FET (S61) and a resistor R75. One end of the resistor R75 is connected to the output DMC_O of the DutyMax detection circuit 760c, and the other end of the resistor R75 is connected to the gate terminal of the FET (S61). The source terminal of the FET (S61) is grounded, and the drain terminal is connected to the connection portion of the resistor R92 and the resistor R93 of the error signal synthesis circuit 930.

  When the signal DMC_O output from the DutyMax detection circuit 760c becomes high, the FET (S61) is turned on, and the output voltage of the operational amplifier 6121 of the error signal synthesis circuit 930 is forcibly lowered. As a result, since the duty ratio of the switching pulse to the switch of the D / D converter circuit 510 can be lowered, the drive level of the D / D converter circuit 510 can be lowered early and the maximum power point can be tracked at high speed. Can do. Further, since the switching pulse itself is not adjusted, switching does not occur regardless of the period of the switching pulse, so that the forced adjustment of the switching pulse is performed without increasing the power consumption.

  As described above, by increasing the output voltage Vo_fb of the output voltage detection circuit 520 and reducing the difference from the reference voltage V_Vref, the duty ratio of the switching pulse is decreased, and the output of the voltage error detection circuit 770c is also adjusted. Further, the duty ratio of the switching pulse is lowered, and maximum power point tracking is performed at high speed.

  Note that the circuit example shown above is only an example, and other circuit examples that realize the same function may be employed.

  Moreover, a power converter device and a storage battery charge / discharge control circuit may be collectively referred to as a power converter device.

Claims (10)

A D / D converter circuit for DC / DC converting an output voltage from a direct current power source having a maximum power point and outputting the same to a storage battery;
A storage battery charging current detection circuit for detecting a current value of a current flowing in a storage battery storing power output from the D / D converter circuit;
A voltage control circuit for controlling the D / D converter circuit so as to track the maximum power point according to an output voltage of the D / D converter circuit;
A constant current control circuit that controls the D / D converter circuit so that the current value becomes constant according to the current value detected by the storage battery charging current detection circuit;
If the storage battery is charging and the current value detected by the storage battery charging current detection circuit is less than a predetermined value, the control of the voltage control circuit is validated, and the storage battery is charging and the storage battery charging current detection circuit A control switching circuit for enabling the control of the constant current control circuit if the current value detected by is equal to or greater than the predetermined value;
A power conversion device. A storage battery voltage detection circuit for detecting an output voltage of the storage battery;
The control switching circuit is
If the current value detected by the storage battery charging current detection circuit is not less than the predetermined value and the output voltage detected by the storage battery voltage detection circuit is not less than a second predetermined value, the voltage control circuit is controlled. The constant current if the current value detected by the storage battery charging current detection circuit is greater than or equal to the predetermined value and the output voltage detected by the storage battery voltage detection circuit is less than the second predetermined value. The power conversion device according to claim 1, wherein control of the control circuit is validated. A storage battery voltage detection circuit for detecting an output voltage of the storage battery;
The power conversion device according to claim 1, wherein the storage battery is being charged by specifying that the output voltage detected by the storage battery voltage detection circuit is less than a second predetermined value. An output voltage detection circuit that outputs an output signal of a voltage corresponding to the output voltage of the D / D converter circuit;
The voltage control circuit is
A constant voltage control circuit that controls the D / D converter circuit according to a difference between a voltage of an output signal of the output voltage detection circuit and a reference comparison voltage;
When the voltage of the output signal of the output voltage detection circuit decreases despite the control by the constant voltage control circuit, the potential difference between the voltage of the output signal of the output voltage detection circuit and the reference comparison voltage is forcibly narrowed. An adjustment circuit;
The power conversion device according to claim 1. The adjustment circuit is
A duty ratio maximum detection circuit for detecting a state in which a duty ratio of a signal for controlling switching of a switch included in the D / D converter circuit becomes a predetermined maximum value in response to a voltage drop of an output signal of the output voltage detection circuit; ,
A voltage adjustment circuit that changes the voltage of the output signal of the output voltage detection circuit or the reference comparison voltage according to the frequency or rate at which the detection signal is output within a predetermined period from the duty ratio maximum detection circuit;
The power converter according to claim 4 which has. The voltage regulator circuit is
The power conversion device according to claim 5, further comprising: a circuit that switches to discharge from the discharge circuit for a period according to a frequency or a rate at which a detection signal is output from the maximum duty ratio detection circuit within a predetermined period. The voltage regulator circuit is
A first inversion circuit for inverting the polarity of the output signal of the output voltage detection circuit;
An inversion signal adjustment circuit that lowers the voltage of the output signal of the first inversion circuit according to the frequency or rate at which the detection signal is output from the maximum duty ratio detection circuit within a predetermined period;
A second inverting circuit for inverting the polarity of the output signal of the first inverting circuit whose voltage has been lowered by the inverting signal adjustment circuit;
The power converter according to claim 5 which has. The adjustment circuit is
6. The limiting circuit according to claim 5, further comprising: a limiting circuit that controls switching of a switch included in the D / D converter circuit to limit output of power when a detection signal is output from the duty ratio maximum detection circuit. Power conversion device. The constant voltage control circuit is
The error voltage corresponding to the difference between the voltage of the output signal of the output voltage detection circuit and a reference comparison voltage is compared with a predetermined triangular wave signal, the period when the error voltage exceeds the voltage of the triangular wave signal, A circuit for generating a signal for turning on a switch included in the D / D converter circuit,
The adjustment circuit is
The power converter according to claim 5, further comprising: a limiting circuit that reduces the error voltage according to a frequency or a rate at which a detection signal is output from the maximum duty ratio detection circuit within a predetermined period. The adjustment circuit is
The power conversion device according to claim 4, wherein the amount of change is gradually reduced after forcibly changing the voltage of the output signal of the output voltage detection circuit or the reference comparison voltage.

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