JP5445500B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a BIST (built in self test) function, and more particularly to a semiconductor memory device having a programmable BIST function capable of programming and using a test pattern.

  In the inspection of a flash memory which is one of semiconductor memory devices, memory defects are detected by performing operations such as program (write) and read (read) on the bits of the entire area of the memory. In the flash memory device having the BIST function, it is possible to inspect the memory and determine the result by itself. When executing the program inspection, the conventional configuration executes the control of the flowchart shown in FIG. The same data is sequentially written for every sector in all sectors.

  First, in step S10 of FIG. 8, initialization for program inspection of the memory cell array of the flash memory is performed. In step S20, a data pattern (write data, expected value) for one unit data to be programmed in the memory cell array of the flash memory is generated in the buffer (write buffer). Subsequently, the process proceeds to step S30, and a process of programming a data pattern for one unit data in the memory cell array, that is, a write operation and a verify operation are executed. Then, the process proceeds to step S40, where it is determined whether or not the program (write) has been normally performed. If there is an abnormality, the process proceeds to “NO” and ends abnormally (fail).

  If the program is normally executed in step S40, the process proceeds to “YES”, and the process proceeds to step S50 to determine whether or not it is the last unit data in the sector of the memory cell array. If it is not the last unit data, the process proceeds to “NO” in step S50, moves to the next unit data (step S60), returns to step S20, and returns to the next unit data (write data, expected value). ) In the buffer. Thereafter, the above steps S10 to S60 are repeated until all the unit data in the sector are programmed.

  When the programming of all the unit data in the sector is completed, the process proceeds to “YES” in step S50 and proceeds to step S70 to determine whether or not it is the last sector in the memory cell array. If it is not the last sector, the process proceeds to “NO” in step S70, moves to the next sector (step S80), returns to step S10, and stores the data pattern (expected value) of the first unit data in the sector. To generate. Thereafter, steps S10 to S80 described above are repeated until all the unit data in the last sector are programmed. As a result, data of the same pattern can be programmed in all sectors.

  Similarly, in the case where the read inspection is executed, the read inspection is performed on all the sectors based on the flow shown in FIG. 9 as Example 1 or FIG. 10 as Example 2. In Example 1, after performing the read operation for each read unit in the sector, as disclosed in Patent Document 1, it is determined whether or not the data matches the expected data by the data determination circuit ahead of the sense amplifier. In Example 2, after performing the read operation for each read unit, the data is temporarily stored in a RAM or the like, and it is determined whether or not the data matches the expected data by the CPU accessing the data and performing an operation or the like. In either example, the reading operation is sequentially performed one sector at a time from the first sector to the last sector, thereby completing the read inspection of all sectors.

JP 2007-207319 A

  In the case of the program inspection with the above-described conventional configuration, it is necessary to execute a process of generating a data pattern for one unit data to be programmed in the buffer in a step S20 by calculation by the CPU or the like. In the program inspection of the conventional configuration, since all the unit data in the memory cell array must execute the process of step S20 in addition to the process of step S30 which is the write operation inspection, before the program inspection ends, In addition to the time required for the original write operation, there is a problem that it takes a long time and the efficiency is not good.

  Further, in the case of the above-described conventional lead inspection, since the dedicated pattern determination circuit is used for determining the read data in Example 1, the determination can be made only with the data pattern assumed at the time of circuit design. If the pattern to be used for inspection is changed at the start of mass production, etc., it is necessary to change the circuit. On the other hand, in Example 2, the read data is temporarily stored in a RAM or the like, and the CPU accesses the data and performs an operation to determine whether the data matches the expected data, so that the time required for the inspection becomes longer.

  Therefore, an object of the present invention is to enable inspection using any data pattern without changing a circuit in a configuration having a BIST function, and to minimize unnecessary repetition by devising an inspection sequence. An object of the present invention is to provide a semiconductor memory device that can shorten the time required for inspection of a memory cell array. Since this method can be realized by a simple logic circuit change in addition to a circuit (such as a RAM) already existing in the memory chip, there is an advantage that the impact on the chip area is small.

According to the first aspect of the present invention, in the semiconductor memory device having a BIST function for program-inspecting a memory cell array, the memory cell array is composed of a first set number of sectors, and the sector is a second set number unit. The unit data is data of a unit to be programmed, is composed of a third set number of bits of data, and stores a program check data of one unit data; and the sector in a state that the data for program inspection of the first unit data stored in the buffer in the, in the first unit data in the first sector using the data for this program checking for the last sector first the program test to unit data sequentially performed for each first unit data, then the second unit data in said sector of The data for program inspection in a state stored in the buffer, the program test from the second unit data in the first sector using the data for the program verify until the second unit data in the last sector Are sequentially executed for each second unit data , and in the same manner, program inspection means for executing program inspection for all sectors by sequentially executing program inspection of the third and subsequent unit data. Since it is provided, an arbitrary data pattern can be used in the program inspection of the memory cell array, and the time required for the inspection can be shortened.

According to the invention of claim 2, the storage means for storing the expected value of the read unit data, the comparison circuit for comparing the read data and the expected value of the read data in the storage means by circuit operation, Finally the expected value of the read data when the read first data unit in said sectors in a state stored in the storage means, from the first unit data in the first sector using the expected value The read inspection is sequentially executed for each first unit data until the first unit data in the sector, and then the expected value of the read data when the second unit data in the sector is read while holding the storage means, the first second from the unit data in the last sector of the second unit data each second unit data read test until in the sector with the expectation Sequentially executed every, and so on, by sequentially executing the read test of the unit data of third and subsequent, since a lead inspection means for performing a read test of all the sectors of the memory cell array Any data pattern can be used in the lead inspection, and the time required for the inspection can be shortened.

  According to the invention of claim 3, when there is an overlap in the program unit data in the sector and the buffer for storing the data for program inspection of one unit data, the program order of the unit data is appropriately changed to be the same In order to reduce the number of times data patterns are stored in the buffer by continuously executing the programs for the program units for programming the data and holding the program data of the unit data in the buffer in the meantime. The program inspection means for controlling the inspection is provided, so that the time required for the inspection can be further reduced.

  According to the invention of claim 4, the storage means for storing the expected value of the read unit data, the comparison circuit for comparing the read data and the expected value of the read data in the storage means by circuit operation, When there is an overlap in the read unit data in the sector, the read order of the unit data is appropriately changed so that the read operation for the same read unit with the expected data is continuously performed, while the expected read data of the unit data is By holding the state stored in the buffer as it is, the lead inspection means for controlling to reduce the number of times the data pattern is stored in the buffer is provided, so that the time required for the inspection can be further shortened.

1 is a block diagram of a flash memory device showing a first embodiment of the present invention. FIG. 6 illustrates a structure of a memory cell array The figure which shows an example of the data pattern at the time of a memory test | inspection The flowchart which shows the control of the program inspection of this invention Flowchart showing control of lead inspection of the present invention FIG. 1 equivalent view showing a second embodiment of the present invention FIG. 3 equivalent view showing a third embodiment of the present invention. FIG. 4 equivalent diagram showing the conventional configuration FIG. 5 equivalent diagram showing a conventional configuration (Example 1) FIG. 5 equivalent diagram showing a conventional configuration (example 2)

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. First, FIG. 1 is a diagram showing an electrical configuration of a flash memory device (semiconductor memory device) 1 of the present embodiment. The flash memory device 1 includes a memory cell array 2, a column decoder 3, a sense amplifier 4, a row decoder 5, a sector decoder 6, a booster circuit 7, a control circuit 8, and an input / output buffer 9.

  The memory cell array 2 is an array of flash memory cells and is composed of a plurality of sectors. A sector is a unit of memory cells that are erased at a time, and the size of one sector is usually about several tens of Kbits to several Mbits, for example. A specific structure of the sector (memory cell array 2) will be described later.

  The column decoder 3 connects the bit line of the memory cell array 2 selected by the address information to the sense amplifier 4 during a read (read) operation. In addition, the column decoder 3 disconnects the sense amplifier 4 from the memory cell array 2 and supplies a necessary voltage to the memory cell array 2 during a program (write) operation or an erase (erase) operation. The sense amplifier 4 detects the current flowing through the selected memory cell, and determines whether the data is “1” or “0” based on the result.

  The row decoder 5 selects a word line (memory cell gate) of the memory cell array 2 from the address information. A voltage required for reading, programming or erasing is applied to the gate of the selected memory cell through this block.

  The sector decoder 6 selects and enables a sector that performs a read, program, or erase operation from the address information. The booster circuit 7 generates a high voltage or a negative voltage for performing a read, program, or erase operation.

  The control circuit 8 includes a CPU 10, a ROM 11, and a RAM 12, and is configured to input / output address information, commands (control), and data via the input / output buffer 9. The control circuit 8 interprets a command received from the outside to execute an operation such as a program or erase, and disables and enables the booster circuit 7 and controls the program and erase pulse. Further, the control circuit 8 has a function of controlling output enable / disable when data is output to the outside by a read operation, a function of temporarily storing the result of program verification in the RAM 12, a state of the chip and a memory cell. A function of controlling the operation of the device.

  In particular, the control circuit 8 of the present embodiment also includes a logic circuit and a CPU (CPU 10) for realizing a BIST (built in self test) operation. In this case, the control circuit 8 constitutes program inspection means and lead inspection means. Note that BIST is a function of performing an inspection using read, program, erase, etc. on the memory cell array 2 in the chip and determining the result. The control circuit 8 of the present embodiment has a function of realizing the BIST operation by software BIST, that is, software stored in the ROM 11 or RAM 12 on the semiconductor chip. Therefore, the control circuit 8 includes a CPU 10 and a logic circuit that can be controlled by software for realizing the software BIST operation. The control circuit 8 may be configured to incorporate a dedicated circuit (hardware) for realizing various operations such as BIST instead of the CPU.

  Next, the program inspection in the operation of the above configuration and the BIST operation will be described with reference to FIGS. First, the structure of the memory cell array 2 of this embodiment will be described with reference to FIGS. As shown in FIG. 2, the memory cell array 2 is composed of N sectors 13 (N = 16 is shown in FIG. 2) as the first set number. As shown in FIG. 3, one sector 13 includes n (n rows) word lines 14 as the second set number. One (one row) word line 14 is composed of M-bit data as the third set number, and here, it is assumed that it matches the unit of program (write). In general, the unit data of the program is not limited to data of the size of one word line 14.

  When the program inspection of the memory cell array 2 is executed, the data “0111... 1” (M bits) as a diagonal pattern as shown in FIG. (In this case, expressed in binary), the data “1011... 1” as the second word line 14, the data “1101... 1” as the third word line 14,. A test for writing data “1111... 10” as the nth word line 14 is executed. The diagonal pattern shown in FIG. 3 is an example, and other various patterns may be used. The diagonal pattern data of each word line 14 shown in FIG. 3 is generated by calculation based on the address information by the CPU 10 in the control circuit 8 in the chip. Note that, for example, the data of the diagonal pattern may be transmitted (written) to the control circuit 8 from a tester outside the semiconductor chip.

  Next, program inspection control will be described with reference to the flowchart of FIG. First, in step S110, initialization for program inspection is performed, and "1" is set to each of the two variables s and i. The variable s is a numerical value indicating the order of the sectors 13, and the variable i is a numerical value indicating the order of the word lines 14. In step S120, the data of the word line 14 to be written for the program check, in this case, the data “0111... 1” of the first word line 14 is buffered (provided in the RAM 12 of the control circuit 8). Stored).

  In step S130, the i-th word line 14 of the s-th sector 13 of the memory cell array 2 (in this case, the first word line 14 of the first sector 13 of the memory cell array 2) is stored in the buffer. The data is programmed (written), specifically, a write operation and a verify operation are performed.

  Thereafter, the process proceeds to step S140, where it is determined whether or not the writing has been executed normally. If it is determined that there is a writing abnormality, the process proceeds to “NO” and the program inspection is terminated as “program abnormality present”. Fail.

  If it is determined in step S140 that the writing has been normally executed, the program check of the i-th (in this case, the first) word line 14 of the next (second in this case) sector 13 is performed. Therefore, the process proceeds to “YES” and proceeds to step S150. In this step S150, whether or not the sector 13 subjected to the program check is the last (in this case, the 16th (Nth in the case of generalization)) sector, that is, whether s = 16 (N). Judge whether or not. In this case, since the sector 13 subjected to the program inspection is not the last sector 13, the process proceeds to “NO”, proceeds to step S160, and moves to the next sector 13, that is, counts up the variable s indicating the order of the sectors 13 The process of (s = s + 1 = 1 + 1 = 2) is executed.

  Thereafter, the process returns to step S130, and the data in the buffer is programmed (written) to the i-th (first in this case) word line 14 of the next (second in this case) sector 13. That is, a write operation and a verify operation are performed. Thereafter, the processes in steps S130 to S160 are repeatedly executed until the program inspection of the i-th (first in this case) word line 14 of the last sector 13 is completed.

  When the program check of the i-th (in this case, the first) word line 14 (unit data) of the last sector 13 is completed, the next word line 14 of all the sectors 13 (in this case, the second word line 14). In order to perform the program inspection of the word line 14), the process proceeds to “YES” in step S150, and then proceeds to step S170. In this step S170, whether or not the i-th word line 14 (in this case, the first word line 14) subjected to the program check is the last word line 14 (n-th word line 14) in the sector 13 or not. That is, it is determined whether i = n. In this case, since the word line 14 subjected to the program check is not the last word line 14, the process proceeds to “NO”, proceeds to step S180, and moves to the next word line 14 (unit data), that is, the word line 14 A process of counting up the variable i indicating the order (i = i + 1 = 1 + 1 = 2) and initializing the variable s indicating the order of the sector 13 (s = 1) is executed.

  Thereafter, the process returns to step S120, and the data of the i-th word line 14 to be written for the program check, in this case, the data “1011... 1” of the second word line 14 is buffered (of the control circuit 8). Stored in the RAM 12). Subsequently, the process proceeds to step S130, and the data in the buffer is programmed (written) to the i-th (in this case, the second) word line 14 of the s-th (in this case, the first) sector 13. An operation, that is, a write operation and a verify operation are performed. Thereafter, the processing of steps S130 to S160 is repeatedly executed until the program inspection of the i-th (second in this case) word line 14 of the last sector 13 is completed.

  When the program inspection of the i-th (second in this case) word line 14 of the last sector 13 is completed, the next word line 14 of all the sectors 13 (in this case, the third word line 14). In step S150, the process proceeds to “YES”, and the process proceeds to step S170. In this step S170, it is determined whether or not the word line 14 (the second word line 14 in this case) subjected to the program inspection is the last word line 14 (nth word line 14) in the sector 13, that is, It is determined whether i = n. In this case, since the word line 14 subjected to the program check is not the last word line 14, the process proceeds to “NO”, proceeds to step S180, and moves to the next word line 14 (unit data), that is, the word line 14 After counting up the variable i indicating the order (i = i + 1 = 21 + 1 = 3) and initializing the variable s indicating the order of the sector 13 (s = 1), the process returns to step S120. Thereafter, the processes of steps S120 to S180 are repeatedly executed until the program inspection of the last word line 14 (nth word line 14) of all the sectors 13 is completed.

  When the program check of the last word line 14 of all the sectors 13 (in this case, the nth word line 14) is completed, the process proceeds to “YES” in step S170 to complete the program check of the memory cell array 2. To do.

  Next, read inspection control of the memory cell array 2 will be described with reference to FIGS. 5 to 6 as a second embodiment. FIG. 5 shows a flowchart of lead inspection, and FIG. 6 shows a second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the second embodiment, the data read by the comparison circuit 15 (hardware circuit) provided in the control circuit 8 is determined. Specifically, the data of the word line 14 in the sector 13 in the memory cell array 2, that is, the sense amplifier output and the data in RAM (expected value data) are compared with the circuit of the comparison circuit 15 in the control circuit 8. It was set as the structure collated (comparison) by operation | movement. Here, one (one row) word line 14 is assumed to coincide with the unit of reading (reading), and is composed of M-bit data as the third set number. In general, the unit data for reading is not limited to the data of the size of one word line 14, and the unit of data used for programming and the unit of data used for reading may not be the same. Absent.

  First, in step S210 in FIG. 5, initialization for lead inspection is performed, and “1” is set in each of the two variables s and i. Subsequently, the process proceeds to step S220, where the expected value of the read data, in this case, the data “0111... 1” of the first word line 14 of each sector 13 is provided in the SRAM (RAM 12 of the control circuit 8). Stored).

  In step S230, the data of the i-th word line 14 in the s-th sector 13 of the memory cell array 2 (in this case, the first word line 14 in the first sector 13 of the memory cell array 2) is read. (Read). In step S240, the read data and the data in the RAM (expected value data) are collated (compared) by a circuit operation. Next, the process proceeds to step S250, and it is determined whether or not the read has been normally executed, that is, whether or not the read data matches the expected value data. Here, if it is determined that there is a reading abnormality, the process proceeds to “NO” in step S250, and the lead inspection is terminated when there is an abnormality (fail).

  If it is determined in step S250 that the reading has been normally executed, the read check of the i-th (first in this case) word line 14 of the next (second in this case) sector 13 is performed. Therefore, the process proceeds to “YES” and proceeds to step S260. In this step S260, whether or not the sector 13 subjected to the read check is the last (in this case, the 16th (Nth in the general case)) sector, that is, whether s = 16 (N). Judge whether or not. In this case, since the sector 13 subjected to the program check is not the last sector 13, the process proceeds to “NO”, and the process proceeds to step S270. In step S270, a process of moving to the next sector 13, that is, a process of counting up the variable s indicating the order of the sectors 13 (s = s + 1 = 1 + 1 = 2) is executed.

  Thereafter, the process returns to step S230, and the data of the i-th (first in this case) word line 14 of the next s-th (second in this case) sector 13 is read. Thereafter, the processing of steps S230 to S270 is repeatedly executed until the data read inspection of the i-th (in this case, the first) word line 14 of the last sector 13 is completed.

  When the data read inspection of the i-th (in this case, the first) word line 14 of the last sector 13 is completed, the next word line 14 of all the sectors 13 (in this case, the second word line) 14) In order to perform the program inspection of step 14), the process proceeds to “YES” in step S260, and then proceeds to step S280. In step S280, the word line 14 (the first word line 14 in this case) as the i-th unit data subjected to the read check is the last word line 14 (n-th word line 14) in the sector 13. It is determined whether or not i.e., i = n. In this case, since the read-inspected word line 14 (unit data) is not the last word line 14, the process proceeds to “NO”, proceeds to step S290, and moves to the next word line 14 (unit data). The variable i indicating the order of the word lines 14 is counted up (i = i + 1 = 1 + 1 = 2), and the variable s indicating the order of the sectors 13 is initialized (s = 1).

  Thereafter, the process returns to step S220, and the expected value of the data of the i-th word line 14 read for the read inspection, in this case, the data “1011. Stored in the RAM 12 of the circuit 8. Subsequently, the process proceeds to step S230, and the data of the i-th (second in this case) word line 14 of the s-th (first in this case) sector 13 is read. Thereafter, the processing of steps S230 to S270 is repeatedly executed until the program inspection of the i-th (second in this case) word line 14 of the last sector 13 is completed.

  When the data read inspection of the i-th (in this case, second) word line 14 of the last sector 13 is completed, the next word line 14 of all the sectors 13 (in this case, the third word line) In step S260, the process advances to “YES” and the process advances to step S280 to perform the data lead inspection of 14). In this step S280, whether or not the i-th word line 14 (in this case, the second word line 14) subjected to the read check is the last word line 14 (n-th word line 14) in the sector 13 or not. That is, it is determined whether i = n. In this case, since the word line 14 subjected to the read check is not the last word line 14, the process proceeds to “NO”, proceeds to step S290, and moves to the next word line 14 (unit data), that is, the word line 14 After counting up the variable i indicating the order (i = i + 1 = 2 + 1 = 3) and initializing the variable s indicating the order of the sector 13 (s = 1), the process returns to step S220. Thereafter, the processes of steps S220 to S290 are repeatedly executed until the data read inspection of the last word line 14 (nth word line 14) in all the sectors 13 is completed.

  When the data read inspection of the last word line 14 (in this case, the nth word line 14) of all the sectors 13 is completed, the process proceeds to “YES” in step S280, and the read inspection of the memory cell array 2 is performed. To complete.

  In the first embodiment, when the program inspection of the memory cell array 2 is performed with the BIST function, the number of times the data of the word line 14 to be written for the program inspection is stored in the buffer is n times (that is, the number of the word lines 14). The number of times). For this reason, according to the present embodiment, the number of times the data of the word line 14 is stored in the buffer is significantly reduced (in the case of the conventional configuration shown in FIG. 8, this is (n * 16 (N)) times. 1/16 (N)). Since it usually takes time to execute the process of storing the data of the word line 14 in the buffer, the inspection time required for the program inspection can be greatly shortened by reducing the number of repetitions. Further, according to the above-described embodiment, the data pattern written in all the sectors 13 of the memory cell array 2 at the time of program inspection can be freely changed only by changing the software incorporated in the control circuit 8. In the case of a change, it is not necessary to change the hardware and can be easily handled.

  In the second embodiment, the determination whether the data read in the lead inspection matches the expected data is not performed by a pattern determination circuit prepared in advance, but by calculation using a CPU or the like. Instead of using software, the decision was made by a circuit that collates the sense amplifier output with the expected value data generated on the RAM (RAM 12 of the control circuit 8). As a result, the data pattern for the lead inspection (expected value data) stored in the RAM during the lead inspection can be freely changed only by changing the software incorporated in the control circuit 8. When a pattern is changed, it can be easily handled without changing the circuit, and the time required for verification can be shortened as compared with the configuration in which the pattern match is determined by the calculation of the CPU 10 of the control circuit 8. Can do. Similarly to the case of the program check in the first embodiment, the expected number of data of the word line 14 read for the read check is stored in the RAM n times (that is, the number of word lines 14). It comprised so that it might become. For this reason, according to the present embodiment, the number of times the expected value of the data of the word line 14 is stored in the RAM is significantly reduced (in the conventional configuration, (n * 16 (N)) times. 1/16 (N)), the inspection time required for lead inspection can be greatly shortened. In particular, since it takes a long time to execute the process of storing the expected value of the data of the word line 14 in the RAM, the inspection time required for the read inspection can be substantially reduced. As described above, it is possible to achieve both inspection with an arbitrary data pattern and reduction in inspection time.

  FIG. 7 shows a third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same structure as 1st Embodiment. In the first embodiment, when the program inspection is executed, the diagonal pattern as shown in FIG. 3 is written. Instead, in the third embodiment, the checkerboard pattern shown in FIG. 7 is used. Configured to write.

  As shown in FIG. 7, in the checkerboard pattern, the data patterns of the odd-numbered word lines 14 are all the same, and the data patterns of the even-numbered word lines 14 are all the same. That is, there are only two types of data patterns for the word line 14 (unit data). For this reason, in the third embodiment, the number of times the data of the word line 14 to be written for the program check is stored in the buffer can be set to two.

  For example, first, in a state where the data pattern of the odd-numbered word lines 14 is stored in the buffer, the program check of the odd-numbered word lines 14 is executed for all the sectors 13 (the first word for all the sectors 13). The line is programmed, then the third word line is programmed for all sectors 13, and then the fifth and subsequent odd word lines are similarly programmed), and then the data pattern of the even-numbered word lines 14 is buffered. , The program check of the even-numbered word lines 14 is executed for all sectors 13 (the second word line is programmed for all sectors 13 and then the fourth word for all sectors 13 is written. Program the line and then the sixth and subsequent even numbered word lines) It may be controlled to so that.

  The configuration of the third embodiment other than that described above is the same as that of the first embodiment. Therefore, in the third embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, according to the third embodiment, since the number of times the data of the word line 14 to be written for the program inspection is stored in the buffer can be reduced to two times, the inspection time required for the program inspection can be further increased. It can be greatly shortened.

  In the third embodiment, a data pattern in which there are only two types of data patterns of the word line 14 (unit data) has been described as a data pattern to be written to the sector 13 when executing the program inspection. If the data pattern of the word line 14 (unit data) in the sector is not duplicated, the number of times the data of the word line 14 to be written for program inspection is stored in the buffer is minimized. The program check of the word lines 14 for all the sectors 13 (that is, the program check of the word lines 14 of the same type of data pattern for all the sectors 13) (Control to be executed collectively) may be appropriately configured.

In the third embodiment and the modification, the unit data of the program is one word line 14, but the present invention is not limited to this.
As in the fourth embodiment, similarly to the third embodiment, in the case of performing the lead inspection with the checkerboard pattern, the data pattern of the odd-numbered word lines 14 is first stored in the buffer, and all the sectors 13 are The read inspection of the odd-numbered word lines 14 is executed, and then the read inspection of the even-numbered word lines 14 is executed for all the sectors 13 with the data pattern of the even-numbered word lines 14 stored in the buffer. By controlling in this way, the number of times the data of the word line 14 to be written for the read test can be stored in the buffer can be reduced to a minimum of 2, and the time can be further reduced.

  In the above embodiment, when the program check of the memory cell array 2 is performed and there is a write abnormality, it is determined that the sector having the abnormality is defective and processing such as replacement with a redundant sector is performed. It may be configured. In the above embodiment, when the read inspection of the memory cell array 2 is performed and there is a reading abnormality, the sector having the abnormality is determined to be defective, and processing such as replacement with a redundant sector is performed. It may be configured.

  In the drawings, 1 is a flash memory device, 2 is a memory cell array, 8 is a control circuit, 10 is a CPU, 11 is a ROM, 12 is a RAM, 13 is a sector, 14 is a word line, and 15 is a comparison circuit.

Claims (4)

In a semiconductor memory device having a BIST function for program-inspecting a memory cell array,
The memory cell array is composed of a first set number of sectors,
The sector is composed of a second set number of unit data,
The unit data is data of a unit to be programmed, and is composed of a third set number of bits of data,
A buffer for storing data for program inspection of one unit data;
While storing the data for program inspection of the first unit data in the sector in the buffer, first for the last sector from the first unit data in the sector using the data for the program verification The program check is sequentially executed for each first unit data until the first unit data in the data, and then the program check data of the second unit data in the sector is stored in the buffer. sequentially executes the program test until the second unit data in the last sector from the second unit data in the first sector using the data for the program test for each second unit data, In the same manner, the program check for executing the program check for all sectors is performed by sequentially executing the program check for the third and subsequent unit data. The semiconductor memory device characterized by comprising a means. In a semiconductor memory device having a BIST function for performing a lead inspection on a memory cell array,
The memory cell array is composed of a first set number of sectors,
The sector is composed of a second set number of unit data,
The unit data is data of a unit to be read, and is composed of a third set number of bits of data,
A storage means for storing the expected value of the read unit data, a comparison circuit for comparing the read data with the expected value of the read data in the storage means,
Finally the expected value of the read data when the read first data unit in said sectors in a state stored in the storage means, from the first unit data in the first sector using the expected value The read inspection is sequentially executed for each first unit data until the first unit data in the sector, and then the expected value of the read data when the second unit data in the sector is read while stored in the storage unit, the lead inspection until the second unit data in the last sector from the second unit data in the first sector using the expected value for each second unit data sequentially executes, in the same manner, by sequentially executing the read test of the unit data of third and subsequent, characterized by comprising a lead inspection means for performing a read test of all the sectors Conductor memory device.   When there is an overlap in program unit data in the sector, the program order of the unit data is appropriately changed, and the write operation to the program unit for programming the same data is continuously executed, while the program data of the unit data is 2. The semiconductor memory device according to claim 1, further comprising program checking means for controlling to reduce the number of times the data pattern is stored in the buffer by holding the buffer in the state stored in the buffer.   If there is an overlap in the read unit data in the sector, the read order of the unit data is appropriately changed so that the read operation for the read unit with the same expected data is continuously executed, and the expected read data for the unit data is 3. The semiconductor memory according to claim 2, further comprising: a read inspection unit that controls to reduce the number of times an expected data pattern is stored in the buffer by holding the buffer in the state stored in the buffer. apparatus.

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