JP5443956B2 - In-circuit emulator adapter and in-circuit emulator - Google Patents

Description

  The present invention relates to an adapter for an in-circuit emulator that emulates the function of an additional circuit for a gaming machine microcomputer, and the function of a CPU (Central Processing Unit) core of the in-circuit emulator adapter and the gaming machine control microcomputer. The present invention relates to an in-circuit emulator including an in-circuit emulator for a CPU core that emulates the above.

  The gaming machine control microcomputer must be configured to be inspected by an external verification machine in order to detect fraudulent acts such as program tampering. For this reason, the CPU core that is conventionally mounted on the gaming machine control microcomputer must be used.

  On the other hand, in order to cope with higher functionality and higher performance of gaming machines, the gaming machine control microcomputer is equipped with additional circuits for gaming machines such as a watchdog timer, a random number circuit, and a FIFO (First In First Out) circuit. It came to be.

Here, when developing a game machine program or game machine hardware, an in-circuit emulator (hereinafter referred to as ICE) that emulates the function of the game machine control microcomputer is used.
However, if an ICE is developed for each gaming machine control microcomputer equipped with various additional circuits, the cost of the ICE increases. Therefore, the ICE that emulates the function of the gaming machine control microcomputer is composed of a CPU core ICE and an ICE adapter that emulates the function of the additional circuit for the gaming machine (see, for example, Patent Document 1).

JP 2009-43209 A

When the ICE for the microcomputer for gaming machine control is stopped (breaks), the data from the predetermined memory or register in the CPU core is saved while the internal state of the circuit in the CPU core is preserved. You can read it out.
However, some of the additional circuits for gaming machines mounted on the adapter change the internal state of the circuit when data is read during a break.
For example, when the receiving FIFO circuit reads data during a break, the pointer value of the read pointer changes. The ICE disclosed in Patent Document 1 does not change the pointer value of the read pointer during a break, and only the first input data among a plurality of data stored in the reception FIFO circuit is a reception FIFO circuit. Can be read from. However, this ICE cannot read out the second and subsequent input data from the reception FIFO circuit during the break.

  The present invention has been made in view of the above circumstances, and during a break, data is stored from a predetermined memory or register in the additional circuit while preserving the internal state of the additional circuit for the gaming machine mounted on the adapter. It is an object of the present invention to provide an in-circuit emulator adapter for a microcomputer for gaming machine control capable of reading out and an in-circuit emulator using the same.

In order to achieve the above object, an adapter for an in-circuit emulator according to the present invention is:
An adapter for an in-circuit emulator that emulates the function of the additional circuit for the gaming machine of the microcomputer for gaming machine control constituted by the CPU core and the additional circuit for the gaming machine,
Stop detection means for detecting that the in-circuit emulator for CPU core emulating the function of the CPU core stops execution of the game machine control program;
In response to the execution stop of the game machine control program being detected by the stop detection means, the predetermined memory and register included in the additional circuit for the gaming machine are stored while the internal state of the additional circuit for the gaming machine is preserved. Read control means for enabling the data stored in the CPU core in-circuit emulator to be read; and
It is characterized by providing.

  Preferably, the stop detection unit detects a stop of execution of the game machine control program when a break signal output from the in-circuit emulator for CPU core when the execution of the game machine control program is stopped is input. To do.

Preferably, the additional circuit for a gaming machine has received a random number circuit that sets the generated random value in a random value register, a watchdog timer that generates a time-out signal when the counter value of the counter matches a predetermined value, and Including a storage unit for storing a plurality of data and a read pointer for designating data output from the storage unit, and a reception FIFO circuit for outputting the data from the storage unit in the order of reception. ,
The read control means stops the state transition of the random number circuit and the watchdog timer in response to detecting that the execution stop of the game machine control program is detected, and the random number circuit is executed by the CPU core in-circuit emulator. The random number value and the counter value can be read from the random value register included in the watchdog timer and the counter included in the watchdog timer, respectively, and the pointer value of the read pointer is stored by the in-circuit emulator for the CPU core. Thus, each data stored in the storage unit included in the reception FIFO circuit can be read out.

Preferably, the reading control means includes
A data bus connected to the CPU core in-circuit emulator;
An address bus connected to the CPU core in-circuit emulator;
Have
Based on an address transmitted through the address bus, a random value stored in a random value register included in the random number circuit, a counter value stored in a counter included in the watchdog timer, or the FIFO circuit for reception Each data stored in the storage unit included in is output to the data bus.

The in-circuit emulator according to the present invention is
An in-circuit emulator comprising an in-circuit emulator for CPU core that emulates the function of a CPU core and an adapter for in-circuit emulator that emulates the function of an additional circuit for gaming machines,
The in-circuit emulator for the CPU core includes break signal output means for outputting a break signal while the execution of the game machine control program is stopped.
The in-circuit emulator adapter is
In response to the break signal being output by the break signal output means of the in-circuit emulator for CPU core, the internal state of the additional circuit for the gaming machine is stored and the predetermined circuit included in the additional circuit for the gaming machine is stored. Read control means for enabling the data stored in the memory and register of the CPU to be read by the in-circuit emulator for CPU core,
Is provided.

  According to the present invention, the microcomputer ICE for controlling the gaming machine controls the data from the predetermined memory or register in the additional circuit while the internal state of the additional circuit for the gaming machine mounted on the adapter is preserved during the break. Can be read out.

It is a figure which shows an example of a structure of the in-circuit emulator for the microcomputer for game machine control which concerns on embodiment of this invention. It is a figure which shows an example of a structure of the random number circuit which concerns on embodiment of this invention. It is a figure which shows an example of a structure of the watchdog timer which concerns on embodiment of this invention. It is a figure which shows the 1st example of a structure of the FIFO circuit for reception concerning embodiment of this invention. It is a figure which shows the 2nd example of a structure of the FIFO circuit for reception concerning embodiment of this invention. It is a figure which shows the 3rd example of a structure of the FIFO circuit for reception concerning embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

As shown in FIG. 1, an in-circuit emulator 1 for a gaming machine control microcomputer according to an embodiment of the present invention includes an ICE adapter 10 and a CPU core ICE 20. Note that the target board 30 is a board on which a circuit constituting the gaming machine is mounted.
The CPU core ICE 20 is connected to a computer or the like (not shown). The in-circuit emulator 1 is controlled by this computer or the like.

The CPU core ICE 20 emulates, for example, the functions of a CPU core compatible with Z80 instructions and a CPU core compatible with M6800 / M6801 instructions.
The ICE adapter 10 is necessary for a gaming machine such as a random number circuit 11 or a watch dog timer 12 dedicated circuit, a reception FIFO circuit 13, a transmission FIFO circuit (not shown), a timer circuit (not shown), or the like. General purpose circuitry and CPU socket 14.

The CPU core ICE 20 has all input / output terminals and break signal output terminals (Break) of the CPU core.
All input / output terminals of the CPU core are connected to the ICE adapter 10 via the CPU socket 14. These input / output terminals are classified into an address output terminal (Address), a data input / output terminal (Data), and a control signal terminal (Control).
For example, in the case of a Z80 instruction compatible CPU core, the control signal terminal includes a read strobe output terminal and a write strobe output terminal. Hereinafter, a signal output from the read strobe output terminal is referred to as an RD signal, and a signal output from the write strobe output terminal is referred to as a WR signal.
Hereinafter, a Z80 instruction compatible CPU core will be described as an example.

The break signal output from the break signal output terminal indicates that the CPU core ICE 20 is broken, that is, the execution of the program is stopped.
When the user inputs an instruction to break the in-circuit emulator 1 from the computer that controls the in-circuit emulator 1, the CPU core ICE 20 stops the execution of the game machine control program. The CPU core ICE 20 outputs a break signal while the execution of the game machine control program is stopped.

The target board 30 is mounted with a socket for a gaming machine control microcomputer. In the completed gaming machine, a gaming machine control microcomputer is attached to this socket. During development of hardware and software of the gaming machine, the input / output terminal of the ICE adapter 10 is connected to the target board 30 through this socket.
The break signal is a signal between the CPU core ICE 20 and the ICE adapter 10, and is not a signal output from the gaming machine control microcomputer. For this reason, the break signal output terminal is not connected to the target board 30.

  The circuits mounted on the random number circuit 11, the watchdog timer 12, the reception FIFO circuit 13, and other ICE adapters 10 include an address bus (Address), a data bus (Data), and an RD signal line as necessary. It is connected to a control signal line (Control) including a WR signal line and a break signal line (Break).

The random number circuit 11 generates a pseudo-random number for the purpose of controlling the timing of winning such as a jackpot.
As shown in FIG. 2, the random number circuit 11 includes a counter 111, a random number generation circuit 112, a random number value register 113, a random number generation stop circuit 114, an address decoding circuit 115, and a tristate buffer 116. Yes.

The counter 111 and the random number generation circuit 112 are state transition circuits in which the state of the circuit changes every clock.
The counter 111 is used when the random number is periodically updated. When the counter value of the counter 111 reaches a preset value, the random number value of the random number generation circuit 112 is updated.
The random number generation circuit 112 generates a random value for each clock and sets the generated random value in the random value register 113.
The random number generation stop circuit 114 operates the counter 111 and the random number generation circuit 112 when the CPU core ICE 20 is executing a game machine control program. On the other hand, the random number generation stop circuit 114 stops the state transition of the counter 111 and the random number generation circuit 112 when a break signal is output from the CPU core ICE 20.

  The address decoding circuit 115 opens the tri-state buffer 116 when the address output to the address bus matches the address assigned to the random value register 113 and the RD signal is output to the RD signal line. The random value set in the random value register 113 is output to the data bus.

Therefore, the CPU core ICE 20 outputs the address of the random value register 113 and the RD signal to the address bus and the RD signal line, respectively, and executes the random number value output to the data bus while executing the game machine control program. By reading, the random value can be read from the random value register 113.
Further, while the CPU core ICE 20 is broken (when the execution of the game machine control program is stopped), the CPU core ICE 20 stops the state transition of the random number circuit 11 (the counter 111 and the random number generation circuit 112). A random value can be read from the numerical register 113.
It should be noted that by inputting a break signal to the address decoding circuit 115 and decoding the address and the break signal together, different addresses between the execution of the game machine control program and the break are assigned to the random value register 113. Can also be assigned.

The gaming machine control microcomputer is reset every predetermined time so that the gaming machine does not run away even under the influence of noise such as static electricity, and the execution of the program is resumed from a predetermined address in the memory (for example, address 0). .
For this purpose, a watchdog timer 12 is provided. The watchdog timer 12 generates a timeout signal every predetermined time. When the time-out signal is generated, the gaming machine control microcomputer is reset.
As shown in FIG. 3, the watchdog timer 12 includes a counter 121, an output control circuit 122, a watchdog timer stop circuit 123, an address decode circuit 124, and a tristate buffer 125.

The counter 121 is a state transition circuit in which the circuit state transitions for each clock. The counter 121 counts the number of clocks corresponding to the predetermined time described above.
The output control circuit 122 outputs a timeout signal when the counter value of the counter 121 reaches the number of clocks corresponding to a predetermined time.
The watchdog timer stop circuit 123 operates the counter 121 while no break signal is output from the CPU core ICE 20. On the other hand, the watchdog timer stop circuit 123 stops the counter 121 while the break signal is output from the CPU core ICE 20.

  When the address output to the address bus coincides with the address assigned to the counter 121, the RD signal is output to the RD signal line, and the break signal is output, the address decode circuit 124 outputs the tristate buffer 125. And the counter value of the counter 121 is output to the data bus.

  Therefore, the CPU core ICE 20 stops the watchdog timer 12 (counter 121) while the break is occurring (the execution of the game machine control program is stopped), and the counter is applied to the address bus and the RD signal line, respectively. The counter value can be read from the counter 121 by outputting the address 121 and the RD signal and reading the counter value output to the data bus.

The reception FIFO 13 outputs the received data in the order of reception (old order).
FIG. 4 shows a first example of the configuration of the reception FIFO circuit according to the embodiment of the present invention.
The FIFO circuit 13A includes a storage unit 131, a read pointer (RDP) 132, a read pointer (RDP) 133, a read pointer (RDP) switching circuit 134, a selector 135, a selector 136, an address decoding circuit 137, It has a tristate buffer 138 and a write pointer (not shown).

  The storage unit 131 can store 4 words from address 0 to address 3. Data input to the input port is written to the address pointed to by the write pointer in the storage unit 131. The write pointer is incremented by 1 each time data is written to the storage unit 131 and returns to 0 when 3 is exceeded.

  The read pointer switching circuit 134 operates the read pointer 132 while the CPU core ICE 20 is executing the game machine control program. On the other hand, when a break signal is output from the CPU core ICE 20, the read pointer switching circuit 134 stops the read pointer 132, copies the pointer value of the read pointer 132 to the read pointer 133, and operates the read pointer 133.

The selector 135 selects the read pointer 132 when the CPU core ICE 20 is executing the game machine control program, and sends the address stored in the read pointer 132 to the selector 136. At this time, the selector 136 selects the data in the storage unit 131 stored at the address indicated by the read pointer 132.
The read pointer 132 is incremented by 1 each time data is read from the storage unit 131, and returns to 0 when 3 is exceeded. The address indicated by the read pointer 132 is controlled by a circuit (not shown) so as not to exceed the address indicated by the write pointer.

On the other hand, when a break signal is output from the CPU core ICE 20, the selector 135 selects the read pointer 133 and sends the address stored in the read pointer 133 to the selector 136. At this time, the selector 136 selects the data in the storage unit 131 stored at the address indicated by the read pointer 133.
The read pointer 133 is incremented by 1 each time data is read from the storage unit 131, and returns to 0 when 3 is exceeded. The address indicated by the read pointer 133 is controlled by a circuit (not shown) so as not to exceed the address indicated by the write pointer.

  The address decoding circuit 137 opens the tri-state buffer 138 when the address output to the address bus matches the address assigned to the FIFO circuit 13A and the RD signal is output to the RD signal line. As a result, the data at the address indicated by the read pointer 132 or the read pointer 133 in the storage unit 131 is output to the data bus.

As described above, the FIFO circuit 13A uses the read pointer 132 when the CPU core ICE 20 is executing the game machine control program, and uses the read pointer 133 when the CPU core ICE 20 is broken. The pointer 132 is stopped. For this reason, even if data is read from the FIFO circuit 13A during the break, the contents of the read pointer 132 are not changed and saved.
The read pointer switching circuit 134 stops the read pointer 133 and operates the read pointer 132 again when returning to the execution of the game machine control program from the state where the CPU core ICE 20 is broken.

  Note that the storage unit 131 can be configured by a register separately from the selector 136, or the storage unit 131 and the selector 136 can be integrated and configured by a memory.

FIG. 5 shows a second example of the configuration of the reception FIFO circuit according to the embodiment of the present invention.
A second example of the reception FIFO circuit is constituted by a FIFO circuit 13B, a FIFO circuit 13C, and a FIFO switching circuit 139.
The FIFO circuit 13B includes a storage unit 131, a read pointer 132, a selector 136, an address decoding circuit 137B, a tristate buffer 138, and a write pointer (not shown).
The FIFO circuit 13C includes a storage unit 131, a read pointer 133, a selector 136, an address decoding circuit 137C, a tristate buffer 138, and a write pointer (not shown).
The same components in FIGS. 4 and 5 are denoted by the same reference numerals, and description thereof is omitted.

  Data input from the input port is written to the same address in the storage unit 131 of the FIFO circuit 13B and the storage unit 131 of the FIFO circuit 13C. Therefore, the storage unit 131 of the FIFO circuit 13B and the storage unit 131 of the FIFO circuit 13C hold the same data.

The FIFO switching circuit 139 outputs data from the FIFO circuit 13B while the CPU core ICE 20 executes the game machine control program, and outputs data from the FIFO circuit 13C while the break signal is output from the CPU core ICE 20. Is output.
That is, the address decoding circuit 137B opens the tristate buffer 138 of the FIFO circuit 13B while the CPU core ICE 20 executes the game machine control program, and the data at the address pointed to by the read pointer 132 is transferred from the storage unit 131 to the data. Output to the bus. On the other hand, the address decoding circuit 137C opens the tristate buffer 138 of the FIFO circuit 13C while the break signal is output from the CPU core ICE 20, and the data at the address indicated by the read pointer 133 is transferred from the storage unit 131 to the data bus. Output.

When the CPU core ICE 20 is broken, the FIFO circuit 13B does not operate. For this reason, the contents of the read pointer 132 are not changed and are stored.
The FIFO switching circuit 139 stops the FIFO circuit 13C and operates the FIFO circuit 13B again when returning to the execution of the game machine control program from the state where the CPU core ICE 20 is broken.

FIG. 6 shows a third example of the configuration of the reception FIFO circuit according to the embodiment of the present invention.
The FIFO circuit 13D includes a storage unit 131, a read pointer 132, a selector 136, an address decode circuit 137, a tristate buffer 138, an address decode circuit 140, a tristate buffer 141, a tristate buffer 142, a tristate buffer, It has a state buffer 143, a tristate buffer 144, and a write pointer (not shown).
The same components in FIGS. 4 and 6 are denoted by the same reference numerals, and description thereof is omitted.

The tri-state buffers 141 to 144 are provided for outputting data stored in addresses 0 to 3 of the storage unit 131 to the address bus, respectively. Different addresses are assigned to the tristate buffers 141 to 144.
The address decode circuit 140, for example, matches the address output to the address bus and the address assigned to the tristate buffer 141, outputs the RD signal to the RD signal line, and outputs the break signal to the break signal line. If so, the tri-state buffer 131 is opened. As a result, the data at address 0 in the storage unit 131 is output to the data bus. The address decoding circuit 140 operates the tristate buffers 142 to 144 in the same manner.

  When the CPU core ICE 20 is broken, the data stored in the storage unit 131 is read via the tristate buffers 141 to 144. For this reason, the contents of the read pointer 132 are not changed and are stored.

  In the first to third examples of the reception FIFO circuit shown in FIGS. 4 to 6, the case where the storage unit 131 can store four words of data is shown. However, the number of data that the storage unit 131 can store is shown. Is not limited to 4 words, but may be 8 words, 16 words, or the like. Other word numbers may also be used.

  In the above embodiment, the Z80 instruction compatible CPU core has been described as an example. However, it goes without saying that the present invention can be applied to an M6800 / M6801 compatible CPU core and other CPU cores.

As described above, according to the present invention, in a circuit including a state transition circuit such as a random number circuit or a watchdog timer, the state transition of the state transition circuit is stopped when the CPU core ICE is broken. For this reason, during the break, when the CPU core ICE reads the contents of the registers and memories included in the circuit, the internal state of the circuit is not changed and is saved.
Also, in a circuit in which the internal state changes when the CPU core ICE reads the contents of the register or memory, such as the read pointer of the reception FIFO circuit, the contents of the register or memory can be read while the internal state is preserved. Add a circuit.
Therefore, the microcomputer ICE for controlling a gaming machine according to the present invention stores data from a predetermined memory or register in the additional circuit while the internal state of the additional circuit for the gaming machine mounted on the adapter is preserved during the break. Can be read out.

  Although the embodiments of the present invention have been described above, various modifications and combinations necessary for design reasons and other factors are described in the inventions described in the claims and the specific embodiments described in the embodiments of the invention. It should be understood that it falls within the scope of the invention corresponding to the examples.

DESCRIPTION OF SYMBOLS 1 ... In-circuit emulator, 10 ... Adapter for in-circuit emulator, 11 ... Random number circuit, 12 ... Watchdog timer, 13 ... FIFO circuit for reception, 14 ... CPU socket, 20 ... In-circuit emulator for CPU core, 30 ... Target board 111 ... Counter 112 ... Random number generation circuit 113 ... Random number value register 114 ... Random number generation stop circuit 115 ... Address decoding circuit 116 ... Tri-state buffer 121 ... Counter 122 ... Output control circuit 123 ... Watch dog Timer stop circuit 124... Address decode circuit 125. Tristate buffer 13 A, 13 B, 13 C, 13 D FIFO circuit 131 131 storage unit 132 read pointer 133 read pointer 134 read pointer switching Road, 135 ... selector, 136 ... selector, 137,137B, 137C ... address decoding circuit, 138 ... tristate buffer, 139 ... FIFO switching circuit, 140 ... address decoding circuit, 141, 142, 143, 144 ... tristate buffer

Claims (5)

An adapter for an in-circuit emulator that emulates the function of the additional circuit for the gaming machine of the microcomputer for gaming machine control constituted by the CPU core and the additional circuit for the gaming machine,
Stop detection means for detecting that the in-circuit emulator for CPU core emulating the function of the CPU core stops execution of the game machine control program;
In response to the execution stop of the game machine control program being detected by the stop detection means, the predetermined memory and register included in the additional circuit for the gaming machine are stored while the internal state of the additional circuit for the gaming machine is preserved. Read control means for enabling the data stored in the CPU core in-circuit emulator to be read; and
An in-circuit emulator adapter characterized by comprising:   The stop detection means detects the stop of execution of the game machine control program by receiving a break signal output from the CPU core in-circuit emulator when the execution of the game machine control program is stopped. The adapter for an in-circuit emulator according to claim 1, wherein the adapter is an in-circuit emulator. The additional circuit for gaming machines includes a random number circuit that sets a generated random value in a random value register, a watchdog timer that generates a timeout signal when the counter value of the counter matches a predetermined value, and a plurality of received data Including a storage unit that stores data and a read pointer that specifies data output from the storage unit, and a reception FIFO circuit that outputs the data from the storage unit in the order received.
The read control means stops the state transition of the random number circuit and the watchdog timer in response to detecting that the execution stop of the game machine control program is detected, and the random number circuit by the CPU core in-circuit emulator The random number value and the counter value can be read from the random value register included in the watchdog timer and the counter included in the watchdog timer, respectively, and the pointer value of the read pointer is stored by the in-circuit emulator for the CPU core. Enabling each data stored in the storage unit included in the reception FIFO circuit to be read.
The adapter for an in-circuit emulator according to claim 1 or 2. The read control means includes
A data bus connected to the CPU core in-circuit emulator;
An address bus connected to the CPU core in-circuit emulator;
Have
Based on an address transmitted through the address bus, a random value stored in a random value register included in the random number circuit, a counter value stored in a counter included in the watchdog timer, or the FIFO circuit for reception Outputting each data stored in the storage unit included in the data bus,
The in-circuit emulator according to claim 3. An in-circuit emulator comprising an in-circuit emulator for CPU core that emulates the function of a CPU core and an adapter for in-circuit emulator that emulates the function of an additional circuit for gaming machines,
The in-circuit emulator for the CPU core includes break signal output means for outputting a break signal while the execution of the game machine control program is stopped.
The in-circuit emulator adapter is
In response to the break signal being output by the break signal output means of the in-circuit emulator for CPU core, the internal state of the additional circuit for the gaming machine is stored and the predetermined circuit included in the additional circuit for the gaming machine is stored. Read control means for enabling the data stored in the memory and register of the CPU to be read by the in-circuit emulator for CPU core,
An in-circuit emulator comprising:

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