JP5440109B2 - Method for producing compound semiconductor - Google Patents

Description

  The present invention relates to a compound semiconductor manufacturing method, a compound semiconductor, and a compound semiconductor element using a metal organic chemical vapor deposition method.

  In recent years, various semiconductor elements such as LEDs (Light Emitting Diodes), FETs (Field Effect Transistors), and HEMTs (High Electron Mobility Transistors) using compound semiconductors have been widely used.

  As one method for growing such a compound semiconductor crystal, a metal organic chemical vapor deposition method (hereinafter referred to as MOCVD method) is known. In the MOCVD method, for example, a group III organometallic source gas and a group V source gas are supplied into a reaction chamber as a mixed gas with a high-purity hydrogen carrier gas, and the source is pyrolyzed in the vicinity of a substrate heated in the reaction chamber, A compound semiconductor wafer is obtained by epitaxially growing a compound semiconductor crystal on a substrate.

  As a conventional technique described in the publication, in an MOCVD apparatus using the MOCVD method, a plurality of growth wafers to be grown with compound semiconductor crystals are placed inside an epitaxial growth furnace to which a raw material gas is supplied, and the crystal growth surface is on the upper side. There exists what is arranged in such a way (see Patent Document 1).

  As another prior art described in other publications, in a MOCVD apparatus using the MOCVD method, a plurality of substrates are held inside a reaction chamber to which a source gas is supplied so that the growth surface of the compound semiconductor crystal faces upward. A substrate holder that rotates while rotating and a cover plate that is provided above the substrate holder so as to face the substrate holder are provided, and a source gas is supplied from the center of the cover plate toward each substrate held by the substrate holder There exists a thing (refer patent document 2).

JP 2002-234793 A Special table 2003-518199 gazette

By the way, in the above-described MOCVD method, a reaction product (for example, a compound semiconductor) generated in the reaction chamber by the reaction of the source gas adheres to and accumulates on the inner wall of the reaction chamber.
The reaction product adhered and deposited in this way is removed by performing cleaning after forming a compound semiconductor film on the substrate by MOCVD.

  However, a part of the reaction product adhered and deposited on the inner wall of the reaction chamber may be peeled off from the inner wall of the reaction chamber or the like during the film formation operation of the compound semiconductor. When the reaction product lump thus peeled falls on the growth surface on the substrate, the reaction product lump is included in the compound semiconductor layer formed on the substrate.

As a result, the site where the reaction product lump is attached cannot be made into a final product, that is, a semiconductor element, so that the yield in manufacturing of a semiconductor element using a substrate on which a compound semiconductor layer is formed is reduced. Was invited.
In addition, if the number or amount of reaction products adhering to the substrate is remarkably large, the substrate itself on which the compound semiconductor layer is formed must be discarded, resulting in a decrease in yield in manufacturing the substrate on which the compound semiconductor layer is formed. I was invited.

  It is an object of the present invention to suppress a decrease in yield due to a peeled reaction product adhering to a substrate or a compound semiconductor layer on a substrate in the manufacture of a compound semiconductor using a metal organic chemical vapor deposition method. And

The method for producing a compound semiconductor to which the present invention is applied includes particles having a Knoop hardness higher than that of a solid member on the surface of the solid member having a front surface and a back surface and first irregularities formed in advance on the surface. The first step of roughening the surface by forming the second unevenness finer than the first unevenness with respect to the first unevenness , and the formed body and the formed body within the reaction chamber A second member that contains a solid member disposed so that its surface faces the body to be formed and supplies a source gas and forms a compound semiconductor layer on the body using metal organic vapor phase epitaxy Process.

Such a method for producing a compound semiconductor can be characterized in that the first unevenness in the solid member is formed by a groove formed of a continuous recess.
Moreover, the 1st unevenness | corrugation whose depth will be 0.2 mm or more and 0.8 mm or less is previously formed in the surface of a solid member, and the 2nd unevenness | corrugation whose depth becomes 10 micrometers or more in a 1st process is formed. It can be characterized by forming.
Furthermore, the surface of the solid member is formed with first irregularities having a depth of 0.2 mm or more and 0.8 mm or less, and in the first step, the particle size is set to 250 μm or more and 600 μm or less. It can be characterized by injecting.
Further, in the first step, the reaction product adhering to the surface of the solid member with the formation of the compound semiconductor layer performed before the first step is removed by jetting particles and the surface is roughened. Can be characterized.
Furthermore, the solid member can be made of quartz and the particles can be made of alumina.

  According to the present invention, in the manufacture of a compound semiconductor using metal organic vapor phase epitaxy, it is possible to suppress a decrease in yield due to the peeled reaction product adhering to the substrate or the compound semiconductor layer on the substrate. Can do.

It is an example of the schematic diagram which shows the cross-sectional structure of the MOCVD (Metal Organic Chemical Vapor Deposition) apparatus with which this Embodiment is applied. It is II-II sectional drawing of the MOCVD apparatus shown in FIG. (A) is the figure which looked at an example of the protection member from the lower side, (b) is the figure which looked at the protection member shown to (a) from the upper side, (c) is a cross section of the protection member shown to (a) FIG. It is an example of sectional drawing of the laminated semiconductor wafer manufactured using a MOCVD apparatus. It is an example of sectional drawing of the light emitting element chip | tip obtained by further processing a laminated semiconductor wafer. It is a flowchart for demonstrating the manufacturing method of the laminated semiconductor wafer which uses a compound semiconductor substrate as a starting material. It is a figure for demonstrating an example of a structure of the blast processing apparatus used for reproduction | regeneration of a protection member. (A)-(e) is a figure for demonstrating the other structural example of a protection member.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 1 is a diagram showing a cross-sectional configuration of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus 1 as an example of a compound semiconductor manufacturing apparatus to which the present embodiment is applied. FIG. 2 is a cross-sectional view of the MOCVD apparatus 1 shown in FIG.
The MOCVD apparatus 1 includes a substrate 110 (see FIG. 4 to be described later) for epitaxially growing a compound semiconductor crystal, and a compound semiconductor substrate in which at least one compound semiconductor layer having an arbitrary composition is formed on the substrate 110 (an example). The compound semiconductor substrate 40 can also be cited as an example. In the present specification, these are also referred to as objects to be formed). For example, when the compound semiconductor substrate 40 is used, the crystal growth surface faces upward. It has a so-called vertical configuration in which a source gas, which is disposed and is used for epitaxial growth, is supplied from above the compound semiconductor substrate 40.

The MOCVD apparatus 1 includes a reaction vessel 10 in which a reaction chamber is formed, and a support 20 disposed in the reaction chamber of the reaction vessel 10.
Among these, the reaction vessel 10 has a cylindrical shape with an opening facing upward, and a receiving portion 11 for receiving the support 20 therein, and a disc-like shape. 11 and a lid 12 attached to the upper part of 11.

  Here, the accommodating part 11 and the cover part 12 are comprised with metals, such as stainless steel. The lid portion 12 is attached to the housing portion 11 so that it can be opened and closed. A sealing material such as an O-ring (not shown) is attached to a portion where the housing portion 11 and the lid portion 12 face each other.

Further, a through-hole for supplying a source gas into the reaction chamber from a gas supply mechanism (not shown) provided outside is formed in the central portion of the lid portion 12. A supply pipe 13 is connected to the through hole. Furthermore, a through-hole for observing the inside of the reaction chamber from the outside is also formed at a position deviated from the center of the lid 12.
On the other hand, a plurality of exhaust pipes for exhausting the source gas supplied into the reaction chamber to the outside of the reaction chamber are formed through the bottom surface of the accommodating portion 11. Furthermore, a through-hole for passing a shaft 21 described later is also formed in the center of the bottom surface of the accommodating portion 11.

Here, the source gas used in the MOCVD apparatus 1 will be described.
In the present embodiment, a group III nitride semiconductor layer is further formed on the compound semiconductor substrate 40 in which a compound semiconductor layer having an arbitrary composition is formed on the substrate 110 in advance using the MOCVD apparatus 1. For this reason, an organic metal containing a group III element and ammonia NH ₃ containing nitrogen are used as raw materials. However, since organic metal is mainly a liquid raw material, an organic material obtained by bubbling liquid organic metal with nitrogen N ₂ and hydrogen H ₂ and mixing the obtained nitrogen N _2, hydrogen H _2, and organic metal. A metal gas MO is supplied as a raw material gas. In the present embodiment, the organometallic gas MO and ammonia NH ₃ are supplied from the supply pipe 13.

Examples of the organic metal include trimethylgallium (TMG) or triethylgallium (TEG) containing group III Ga, for example, trimethylaluminum (TMA) or triethylaluminum (TEA) containing group III Al, for example, group III In And trimethylindium (TMI) or triethylindium (TEI). Examples of n-type dopants include monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ) Si raw materials, germane gas (GeH ₄ ), tetramethyl germanium ((CH ₃ ) ₄ Ge), and tetraethyl germanium (( C ₂ H ₅ ) ₄ Ge) may be used as the Ge raw material. On the other hand, as a p-type dopant, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) or bisethylcyclopentadienyl magnesium (EtCp ₂ Mg) may be used as the Mg raw material. Further, hydrazine (N ₂ H ₄ ) can be used instead of ammonia. In addition to the organic metal MO described above, other group III elements can be included, and if necessary, dopants such as Ge, Si, Mg, Ca, Zn, and Be can be included. it can. Furthermore, it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.

Further, the support 20 has a disk shape, and is disposed in the accommodating portion 11 so that one surface, that is, the front surface faces upward, and the other surface, that is, the rear surface faces downward. . And the support body 20 is comprised by what coated the coating by SiC on the outer side of the base material formed with carbon (C). Here, six concave portions each having a circular shape are formed at equal intervals in the circumferential direction on the surface side of the support 20. On the other hand, a metal shaft 21 extending downward from the central portion is attached to the back surface side of the support body 20, and this shaft 21 is inserted through a through hole provided in the central portion of the bottom surface of the housing portion 11. It protrudes outside the reaction vessel 10. The support 20 rotates in the direction of arrow A shown in FIG. 2 by applying a driving force to the shaft 21 from the outside of the reaction vessel 10.
A through hole (not shown) for supplying nitrogen N ₂ toward the bottom surfaces of the six recesses provided in the support 20 is formed inside the support 20. Note that the method for supplying nitrogen N _{2 to} the bottom surfaces of the six recesses provided on the support 20 may be appropriately changed.

  In addition, a circular substrate holder 30 is attached to each of the six recesses provided on the surface of the support 20. Each of these substrate holders 30 has a circular recess formed on the surface facing upward, and a compound semiconductor substrate 40 is attached to each recess. The substrate holder 30 is also configured by applying a coating with SiC to the outside of the base material formed of carbon. A gap is formed between the concave portion provided in the support 20 and the substrate holder 30, and these six substrate holders 30 are detachable from the support 20.

Here, the compound semiconductor substrate 40 as an example of the body to be formed is held in the recess of the substrate holder 30 such that the crystal growth surface, that is, the surface on which the crystal is formed is exposed to the outside. The compound semiconductor substrate 40 is detachable from the substrate holder 30.
Each substrate holder 30 rotates in the direction of arrow B shown in FIG. 2 by the flow of nitrogen N ₂ supplied through the above-described through hole (not shown) while holding the compound semiconductor substrate 40. It is like that.

  Further, a heating unit 50 for heating the compound semiconductor substrate 40 via the support 20 and the substrate holder 30 is provided between the back side of the support 20 of the MOCVD apparatus 1 and the bottom surface of the housing 11. Yes. The heating unit 50 has a ring shape in which a hole penetrating the shaft 21 is formed, and a coil is accommodated therein. In addition, the heating part 50 electromagnetically heats the carbon which comprises the support body 20 by supplying an electric current to a coil.

  Further, a product generated by the reaction of the source gas supplied into the reaction chamber adheres to and accumulates on the inner wall of the lid 12 below the lid 12 of the MOCVD apparatus 1 and above the support 20. A protective member 60 is provided for protecting the lid 12 by preventing the above. Here, the protective member 60 as an example of the solid member has a circular shape, and penetrates as an example of a raw material supply port that supplies the raw material gas to the inside of the reaction chamber from the outside to the center, similarly to the lid portion 12. A hole is formed. The protective member 60 is also provided with a through-hole for observing the inside of the reaction chamber from the outside, like the lid portion 12.

  And the protection member 60 is attached to the cover part 12 with the attachment member which is not shown in figure. The attachment member is detachable from the lid 12, and accordingly, the protection member 60 can be attached to and detached from the lid 12. Further, the protection member 60 is fixed by being attached to the lid portion 12 by an attachment member.

  As shown by a broken line in FIG. 2, the protection member 60 is disposed so as to cover the entire surface of the support 20 when viewed from above with the lid portion 12 closed with respect to the housing portion 11. Accordingly, the six compound semiconductor substrates 40 held on the support 20 via the substrate holders 30 are positioned below the protective member 60.

  Further, between the support 20 and the protective member 60 of the MOCVD apparatus 1, the source gas or the like that is supplied into the reaction chamber and used for the epitaxial growth of the crystal is provided on the side of the discharge pipe provided on the bottom surface of the container 11. An exhaust member 80 is attached to guide the gas. The exhaust member 80 has a ring shape. Further, the inner wall of the exhaust member 80 is located outside the six recesses provided in the support 20. A plurality of through holes (not shown) are formed on the inner wall of the exhaust member 80 to discharge the used raw material gas and the like to the outside. The exhaust member 80 is configured so as not to hinder the rotation of the support 20 at a portion facing the edge side of the outer peripheral portion of the support 20. In FIG. 2, the exhaust member 80 is not shown.

And the monitoring apparatus 90 is attached to the upper part of the through-hole provided in the cover part 12 of this MOCVD apparatus 1. FIG. The monitoring device 90 is held by the support 20 via the through holes provided in the lid portion 12 and the protection member 60, and more specifically, the state inside the reaction chamber, more specifically, the substrate holder 30. The state of crystals epitaxially grown on the compound semiconductor substrate 40, the state of warpage of the compound semiconductor substrate 40, and the like are monitored. In order to prevent the raw material gas and the like from flowing into the monitoring device 90 through these through holes, a purge gas such as nitrogen N ₂ is supplied from the monitoring device 90 to the reaction chamber.

  FIG. 3 is a diagram for explaining an example of the configuration of the protective member 60 used in the MOCVD apparatus 1 described above. Here, FIG. 3A is a view of the protection member 60 shown in FIG. 1 as viewed from the support 20 side, that is, the lower side, and FIG. 3B is a view of the protection member 60 as viewed from the lid portion 12 side, that is, from the upper side. FIG. 3C is a view showing a cross section of the protection member 60. In the following description, the surface shown in FIG. 3A is called the front surface of the protection member 60, and the surface shown in FIG. 3B is called the back surface of the protection member 60.

  The protection member 60 is made of quartz glass, and a first through hole 61 for supplying a raw material gas is formed in the center thereof, and monitoring by the monitoring device 90 is performed at one site on the right side in the drawing. For this purpose, a second through hole 62 is formed.

In addition, 360 grooves 63 are formed radially on the surface side of the protective member 60, that is, on the surface facing the compound semiconductor substrate 40 in the MOCVD apparatus 1. On the surface side of the protective member 60, 360 grooves 63 as an example of deep recesses are formed at equal intervals every other degree, and each has a V-shaped cross-sectional shape. Here, the width W of each groove 63 may be, for example, in the range of 0.4 mm to 2.0 mm, and may have a structure in which the width W is arbitrarily changed in the circumferential direction. Moreover, it is preferable that the depth D of each groove | channel 63 shall be 0.2 mm or more and 0.8 mm or less, for example. That is, unevenness is formed by a plurality of grooves 63 on the surface of the protective member 60 used in the present embodiment.
In the present invention, the groove 63 of the protection member 60 may have a U-shaped cross-sectional shape in addition to the V-shaped cross-sectional shape. In this case, the width W of each groove 63 is, for example, 0. The range of 4 mm or more and 2.0 mm or less is good, and the width W may be arbitrarily changed in the middle in the circumferential direction. The depth D of each groove 63 is, for example, 0.2 mm or more and 0 It is preferable that the thickness is 8 mm or less.

  Here, in the present embodiment, the surface side of the protection member 60 is subjected to blasting, and the surface of the protection member 60 is formed with a plurality of grooves 63 and also concave portions that are finer than the plurality of grooves 63. Yes. Further, after the protective member 60 is used for the film forming operation by the MOCVD apparatus 1, the surface side is cleaned and repeatedly used, but this blasting process is also used for cleaning the surface side of the protective member 60. The Details of the blast process will be described later.

  Further, the starting point of each groove 63 on the first through hole 61 side, that is, the central portion side, is located at a radius of 100 mm from the center of the circular protective member 60, and is on the outer peripheral edge side of each groove 63. The end point is a position having a radius of 220 mm from the center of the protective member 60. In FIG. 3A, the movement trajectory (inner end portion and outer end portion) of the compound semiconductor substrate 40 due to the rotation of the support 20 (see FIG. 2) is indicated by broken lines. Here, the position of the start point of each groove 63 is closer to the center than the movement trajectory of the inner ends of the six compound semiconductor substrates 40 held by the opposing support 20, and the end point of each groove 63 is The position is outside the movement trajectory of the outer end portions of the six compound semiconductor substrates 40 held by the opposing support 20. That is, the groove 63 provided on the surface of the protective member 60 always faces the upper side of the six compound semiconductor substrates 40 held and rotated by the support 20.

  Moreover, the position of the end point of each groove | channel 63 is a center part side rather than the position of the inner side edge part of the exhaust member 80 shown with a dotted line in Fig.3 (a). Therefore, a flat portion existing on the outer peripheral edge side of the surface of the protective member 60 is opposed to the outer peripheral edge of the exhaust member 80, and the protective member 60 and the exhaust member 80 are connected to each other via the groove 63. The raw material gas is prevented from leaking from the opposite portion.

  FIG. 4 shows a cross-sectional view of an example of a laminated semiconductor wafer SW as an example of a compound semiconductor manufactured using the MOCVD apparatus 1 described above. The compound semiconductor constituting the laminated semiconductor wafer SW is not particularly limited, and examples include III-V group compound semiconductors, II-VI group compound semiconductors, and IV-IV group compound semiconductors. In the present embodiment, a III-V group compound semiconductor is preferable, and among these, a group III nitride compound semiconductor is preferable. In the following description, the laminated semiconductor wafer SW having a group III nitride compound semiconductor will be described as an example. Note that the laminated semiconductor wafer SW shown in FIG. 4 is a starting material for manufacturing, for example, a blue light emitting chip that outputs blue light, and a light emitting device using the blue light emitting chip.

  The laminated semiconductor wafer SW includes a substrate 110, an intermediate layer 120 formed on the substrate 110, an underlayer 130, an n-type semiconductor layer 140, a light emitting layer 150, and a p-type semiconductor that are sequentially laminated on the intermediate layer 120. Layer 160.

  Here, the n-type semiconductor layer 140 includes an n-type contact layer 140a provided on the base layer 130 side and an n-type cladding layer 140b provided on the light emitting layer 150 side. The light emitting layer 150 has a structure in which barrier layers 150a and well layers 150b are alternately stacked, and one well layer 150b is sandwiched between the two barrier layers 150a. Further, the p-type semiconductor layer 160 includes a p-type cladding layer 160a provided on the light emitting layer 150 side and a p-type contact layer 160b provided on the uppermost layer. In the following description, the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160 are collectively referred to as the compound semiconductor layer 100.

(Substrate 110)
The substrate 110 is made of a material different from the group III nitride compound semiconductor, and a group III nitride semiconductor crystal is epitaxially grown on the substrate 110. Examples of the material constituting the substrate 110 include sapphire, silicon carbide (silicon carbide: SiC), silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, zirconium boride, and oxidation. Examples include gallium, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten, and molybdenum. Among these, sapphire and silicon carbide (silicon carbide: SiC) are preferable.

(Intermediate layer 120)
As described above, the substrate 110 is made of a material different from the group III nitride compound semiconductor. For this reason, it is preferable to provide the intermediate layer 120 exhibiting a buffer function on the substrate 110 before forming the compound semiconductor layer 100 using the MOCVD apparatus 1 shown in FIG. In particular, the intermediate layer 120 preferably has a single crystal structure from the viewpoint of the buffer function. When the intermediate layer 120 having a single crystal structure is formed on the substrate 110, the buffer function of the intermediate layer 120 effectively acts, and the base layer 130 and the compound semiconductor layer 100 formed on the intermediate layer 120 are: A crystal film with good crystallinity is obtained.
The intermediate layer 120 preferably contains Al, and particularly preferably contains AlN which is a group III nitride.

(Underlayer 130)
As a material used for the underlayer 130, a group III nitride (GaN-based compound semiconductor) containing Ga is used, and in particular, AlGaN or GaN can be preferably used. The film thickness of the underlayer 130 is 0.1 μm or more, preferably 0.5 μm or more, and more preferably 1 μm or more. In this specification, AlGaN and GaInN may be described in a form in which the composition ratio of each element is omitted.

(N-type semiconductor layer 140)
The n-type semiconductor layer 140 includes an n-type contact layer 140a and an n-type cladding layer 140b.
Here, as the n-type contact layer 140a, a GaN-based compound semiconductor is used in the same manner as the base layer 130. In addition, the gallium nitride compound semiconductor constituting the base layer 130 and the n-type contact layer 140a preferably has the same composition, and the total film thickness thereof is 0.1 μm to 20 μm, preferably 0.5 μm to 15 μm, Preferably, it is set in the range of 1 to 12 μm.

  On the other hand, the n-type cladding layer 140b can be formed of AlGaN, GaN, GaInN, or the like. Further, a heterojunction of these structures or a superlattice structure in which a plurality of layers are laminated may be employed. When GaInN is adopted as the n-type cladding layer 140b, it is desirable to make the band gap larger than the GaInN band gap of the light emitting layer 150. The film thickness of the n-type cladding layer 140b is preferably in the range of 5 nm to 500 nm, more preferably 5 nm to 100 nm.

(Light emitting layer 150)
The light emitting layer 150 includes a barrier layer 150a made of a gallium nitride-based compound semiconductor and a well layer 150b made of a gallium nitride-based compound semiconductor containing indium, which are alternately stacked, and the n-type semiconductor layer 140 side and the p-type layer. The barrier layers 150a are stacked in the order in which the barrier layers 150a are disposed on the side of the type semiconductor layer 160, respectively. In the present embodiment, the light emitting layer 150 includes six barrier layers 150a and five well layers 150b that are alternately and repeatedly stacked, and the barrier layer 150a is disposed on the uppermost layer and the lowermost layer of the light emitting layer 150. A well layer 150b is arranged between the barrier layers 150a.

As the barrier layer 150a, for example, a gallium nitride-based material such as Al _c Ga _1-c N (0 ≦ c ≦ 0.3) having a larger band gap energy than the well layer 150b made of a gallium nitride-based compound semiconductor containing indium. A compound semiconductor can be suitably used.
Further, for the well layer 150b, for example, gallium indium nitride such as Ga _1-s In _s N (0 <s <0.4) can be used as the gallium nitride compound semiconductor containing indium.
The film thickness of the entire light-emitting layer 150 is not particularly limited, but is preferably a film thickness that provides a quantum effect, that is, a critical film thickness region. For example, the thickness of the light emitting layer 150 is preferably in the range of 1 nm to 500 nm, and more preferably about 100 nm. Further, the thickness of the well layer 150b is not particularly limited, but it is preferably a thickness enough to obtain a quantum effect.

(P-type semiconductor layer 160)
The p-type semiconductor layer 160 includes a p-type cladding layer 160a and a p-type contact layer 160b. As the p-type cladding layer 160a, preferably, Al _d Ga _1-d N (0 <d ≦ 0.4) is cited. The film thickness of the p-type cladding layer 160a is preferably 1 nm to 400 nm, more preferably 5 nm to 100 nm.
On the other hand, as the p-type contact layer 160b, a gallium nitride-based compound semiconductor layer containing Al _e Ga _1-e N (0 ≦ e <0.5) can be given. The thickness of the p-type contact layer 160b is not particularly limited, but is preferably 10 nm to 500 nm, and more preferably 50 nm to 200 nm.

FIG. 5 shows a cross-sectional view of a light emitting element chip LC as an example of a compound semiconductor element obtained by further processing the above-described laminated semiconductor wafer SW.
In the light emitting element chip LC, the transparent positive electrode 170 is laminated on the p-type contact layer 160b of the p-type semiconductor layer 160, and the positive electrode bonding pad 180 is formed thereon, and the n-type contact of the n-type semiconductor layer 140 is formed. A negative electrode bonding pad 190 is laminated on the exposed region 140c formed in the layer 140a.

(Transparent positive electrode 170)
Examples of the material constituting the transparent positive electrode 170 include ITO (In ₂ O ₃ —SnO ₂ ), AZO (ZnO—Al ₂ O ₃ ), IZO (In ₂ O ₃ —ZnO), and GZO (ZnO—Ga ₂ O). Conventionally known materials such as ₃ ) are listed. Moreover, the structure of the transparent positive electrode 170 is not specifically limited, A conventionally well-known structure is employable. The transparent positive electrode 170 may be formed so as to cover almost the entire surface of the p-type semiconductor layer 160, or may be formed in a lattice shape or a tree shape.

(Positive electrode bonding pad 180)
The positive electrode bonding pad 180 as an electrode formed on the transparent positive electrode 170 is, for example, a conventionally known Au, Al, Ti, V, Cr, Mn, Co, Zn, Ge, Zr, Nb, Mo, Ru, Ta, It consists of materials, such as Ni and Cu. The structure of the positive electrode bonding pad 180 is not particularly limited, and a conventionally known structure can be adopted.
The thickness of the positive electrode bonding pad 180 is, for example, in the range of 100 nm to 2000 nm, and preferably in the range of 300 nm to 1000 nm.

(Negative electrode bonding pad 190)
The negative electrode bonding pad 190 is a compound semiconductor layer 100 (n-type semiconductor layer 140, light emitting layer 150, and p-type semiconductor layer 160) further formed on the intermediate layer 120 and the base layer 130 formed on the substrate 110. The n-type semiconductor layer 140 is formed so as to be in contact with the n-type contact layer 140a. Therefore, when forming the negative electrode bonding pad 190, the p-type semiconductor layer 160, the light emitting layer 150, and the n-type semiconductor layer 140 are partially removed to form an exposed region 140c of the n-type contact layer 140a. A negative electrode bonding pad 190 is formed on the substrate.
The material of the negative electrode bonding pad 190 may have the same composition and structure as the positive electrode bonding pad 180, and negative electrodes having various compositions and structures are well known, and these known negative electrodes can be used without any limitation. It can be provided by known conventional means.

  Next, a manufacturing method of the above-described laminated semiconductor wafer SW will be described. Before that, a manufacturing method of the compound semiconductor substrate 40 used for manufacturing the laminated semiconductor wafer SW will be described.

(Method for Manufacturing Compound Semiconductor Substrate 40)
First, a sapphire substrate 110 having a predetermined diameter and thickness is set in a sputtering apparatus (not shown). Then, an intermediate layer 120 made of a group III nitride is formed on the substrate 110 by activating and reacting a gas containing a group V element and a metal material with plasma in a sputtering apparatus.
Subsequently, the substrate 110 on which the intermediate layer 120 is formed is set in the MOCVD apparatus 1 shown in FIG. Specifically, each substrate 110 is set on each substrate holder 30 so that the intermediate layer 120 faces outward, and each substrate holder 30 on which each substrate 110 is set is provided on the support 20. It arrange | positions so that the intermediate | middle layer 120 may face upwards in each recessed part. Then, the foundation layer 130 is formed on the intermediate layer 120 using the MOCVD apparatus 1 to obtain the compound semiconductor substrate 40.

(Manufacturing method of laminated semiconductor wafer SW)
FIG. 6 is a flowchart for explaining a manufacturing method of the laminated semiconductor wafer SW using the compound semiconductor substrate 40 as a starting material.
First, the compound semiconductor substrate 40 obtained by the above-described process is set in the MOCVD apparatus 1 shown in FIG. 1 (step 201). Specifically, each substrate 110 is set on each substrate holder 30 so that the base layer 130 faces outward, and each substrate holder 30 on which each substrate 110 is set is provided on the support 20. It arrange | positions so that the intermediate | middle layer 120 may face upwards in each recessed part. Then, the n-type contact layer 140a is formed on the base layer 130 using the MOCVD apparatus 1 (step 202), the n-type cladding layer 140b is formed on the n-type contact layer 140a (step 203), and the n-type contact layer 140a is formed. The light emitting layers 150, that is, the barrier layers 150a and the well layers 150b are alternately formed on the cladding layer 140b (step 204), and the p-type cladding layer 160a is formed on the light-emitting layer 150 (step 205). A p-type contact layer 160b is formed on the layer 160a (step 206) to obtain a laminated semiconductor wafer SW.

  The n-type semiconductor layer 140 (n-type contact layer 140a and n-type cladding layer 140b), the light emitting layer 150 (barrier layer 150a and well layer 150b), and the p-type semiconductor layer 160 (p-type cladding layer 160a and p-type contact layer). The formation of 160b) is performed continuously. That is, by changing the composition of the organometallic gas MO supplied into the reaction vessel 10 in the course of forming the compound semiconductor layer 100, the composition is different without opening the lid 12 of the reaction vessel 10 halfway. A plurality of films can be continuously formed and stacked.

  The configuration of the compound semiconductor substrate 40 is not limited to this. For example, the compound semiconductor substrate 40 may be configured by forming the n-type contact layer 140a on the base layer 130 and including the substrate 110, the intermediate layer 120, the base layer 130, and the n-type contact layer 140a. In this case, step 202 may be omitted in manufacturing the laminated semiconductor wafer SW. However, also in this case, the n-type contact layer 140a is preferably formed using the MOCVD apparatus 1.

(Method for manufacturing light-emitting element chip LC)
A transparent positive electrode 170 is laminated on the p-type semiconductor layer 160 of the laminated semiconductor wafer SW obtained by the process shown in FIG. 6, and a positive electrode bonding pad 180 is formed thereon. Further, an exposed region 140c is formed in the n-type contact layer 140a using etching or the like, and a negative electrode bonding pad 190 is provided in the exposed region 140c.
Thereafter, the surface of the substrate 110 opposite to the surface on which the intermediate layer 120 is formed is ground and polished until a predetermined thickness is reached.
Then, the light-emitting element chip LC is obtained by cutting the wafer with the adjusted thickness of the substrate 110 into, for example, a 350 μm square.

  Now, the operation of the MOCVD apparatus 1 in the method for manufacturing the laminated semiconductor wafer SW described above, that is, the second step will be described.

(Operation of MOCVD apparatus 1)
First, one compound semiconductor substrate 40 is set in each of the recesses of the six substrate holders 30. At this time, the base layer 130 of the compound semiconductor substrate 40 is exposed to the outside. Subsequently, the lid 12 of the reaction vessel 10 is opened, and the six substrate holders 30 each having the compound semiconductor substrate 40 set therein are set in the six recesses provided in the support 20 of the MOCVD apparatus 1. . At this time, the base layer 130 of the compound semiconductor substrate 40 is set to face upward.

Moreover, the protective member 60 is arrange | positioned inside the cover part 12, and the protective member 60 is attached to the cover part 12 using an attachment member. At this time, the monitoring through hole provided in the lid portion 12 and the second through hole 62 provided in the protection member 60 are made to coincide with each other.
Thereafter, the lid portion 12 to which the protection member 60 is attached is closed to bring the housing portion 11 and the lid portion 12 into close contact.

Subsequently, in the MOCVD apparatus 1, supply of nitrogen N ₂ is started toward the bottom of each concave portion of the support 20 through a through hole (not shown), and rotation of the shaft 21 is started. Accordingly, the support 20 rotates in the direction of arrow A, and the six substrate holders 30 attached to the support 20 rotate in the direction of arrow B. As a result, the compound semiconductor substrate 40 attached to each substrate holder 30 revolves in the arrow A direction while rotating in the arrow B direction.

  In the MOCVD apparatus 1, power supply to the coil of the heating unit 50 is started, and the support 20 is electromagnetically heated by the current flowing through the heating unit 50. Further, when the support 20 is heated by electromagnetic induction, the six substrate holders 30 held by the support 20 and the compound semiconductor substrate 40 held by each substrate holder 30 are heated to a target temperature. The Furthermore, supply of purge gas from the monitoring device 90 toward the reaction chamber is started.

The MOCVD apparatus 1 supplies the organometallic gas MO and ammonia NH ₃ for the n-type contact layer 140a from the supply pipe 13 to the reaction chamber by a gas supply mechanism (not shown). Accordingly, in the reaction chamber, the organic metal and ammonia NH ₃ react in the vicinity of the heated compound semiconductor substrate 40, and as a result, a group III nitride compound for the n-type contact layer 140a is generated. Then, most of the generated group III nitride compound for the n-type contact layer 140 a falls to the support 20 side located below the supply pipe 13 and is held by the support 20 via the substrate holder 30. It adheres to the compound semiconductor substrate 40. At this time, since the compound semiconductor substrate 40 is heated to a target temperature, a group III nitride compound crystal for the n-type contact layer 140a grows epitaxially on the underlying layer 130 of the compound semiconductor substrate 40. .

  Note that as the source gas is supplied to the reaction chamber, a part of the gas already existing in the reaction chamber is discharged to the outside of the reaction chamber through a through hole provided in the exhaust member 80, and further the reaction vessel 10 is discharged to the outside of the reaction vessel 10 through a through hole provided in the bottom surface of the accommodating portion 11.

When the formation of the n-type contact layer 140a is completed, the MOCVD apparatus 1 uses an unillustrated gas supply mechanism to change the n-type cladding layer from the supply pipe 13 to the reaction chamber, instead of the metal-organic gas MO for the n-type contact layer 140a. An organometallic gas MO for 140b is supplied. At this time, the MOCVD apparatus 1 continues to supply ammonia NH ₃ . Accordingly, in the reaction chamber, the organic metal and ammonia NH ₃ react in the vicinity of the compound semiconductor substrate 40 to be heated, and as a result, a group III nitride compound for the n-type cladding layer 140b is generated. Then, most of the generated group III nitride compound for the n-type cladding layer 140 b falls to the support 20 side located below the supply pipe 13 and is held by the support 20 via the substrate holder 30. It adheres to the compound semiconductor substrate 40. At this time, since the compound semiconductor substrate 40 is heated to a predetermined temperature, a group III nitride compound crystal for the n-type cladding layer 140b is epitaxially grown on the n-type contact layer 140a of the compound semiconductor substrate 40. To do.

  Thereafter, by sequentially changing the organometallic gas MO supplied to the reaction chamber, the n-type cladding layer 140b formed on the compound semiconductor substrate 40 includes a light emitting layer having a plurality of barrier layers 150a and a plurality of well layers 150b. 150, and a p-type semiconductor layer 160 having a p-type cladding layer 160a and a p-type contact layer 160b are sequentially formed. Through such a procedure, the laminated semiconductor wafer SW can be obtained.

  In the above-described manufacturing process of the compound semiconductor substrate 40, the base layer 130 is formed on the substrate 110 / intermediate layer 120 in advance using the MOCVD apparatus 1, and this is also the same procedure as described above. The underlayer 130 can be formed using

  By the way, in the film forming process using the MOCVD apparatus 1 described above, a part of the group III nitride compound (reaction product) generated in the reaction chamber is not only the compound semiconductor substrate 40 but also the surface of the protective member 60, for example. Also adhere to. At this time, like the compound semiconductor layer 100 formed on the compound semiconductor substrate 40, a plurality of films having different compositions are stacked on the surface of the protective member 60.

  Here, the surface of the protective member 60 faces the compound semiconductor substrate 40 held on the support 20 via the substrate holder 30 as described above, and above the crystal growth surface of the compound semiconductor substrate 40. The surface of the protective member 60 is located at the top. The protection member 60 is made of a material different from quartz glass, that is, a group III nitride compound semiconductor constituting the compound semiconductor layer 100.

  For this reason, when the protective member 60 expands / shrinks due to a temperature change in the reaction chamber during the film forming process, the film of the group III nitride compound semiconductor attached and deposited on the surface of the protective member 60 may be peeled off from the protective member 60. is there. In addition, when the group III nitride compound semiconductor is peeled off from the protective member 60, there is a possibility that foreign matters generated by the peeling may fall on the compound semiconductor substrate 40 located below the protective member 60. When the foreign matter peeled off from the protective member 60 adheres to the compound semiconductor substrate 40, each layer constituting the compound semiconductor layer 100 is further formed at the foreign matter attachment site. As a result, in the obtained laminated semiconductor wafer SW, a portion to which foreign matter is attached cannot be used as the light emitting element chip LC, and the yield of the light emitting element chip LC is reduced accordingly. Further, if the number or amount of foreign matters adhering to the compound semiconductor substrate 40 is remarkably large, the laminated semiconductor wafer SW has to be discarded, and the yield of the laminated semiconductor wafer SW is reduced accordingly.

  Therefore, in the present embodiment, as shown in FIG. 3, the surface area of the protective member 60 is increased by forming a plurality of grooves 63 radially on the surface of the protective member 60, so that the surface of the protective member 60 is Peeling of the attached group III nitride compound semiconductor is suppressed. In the present embodiment, the surface of the protective member 60 in which the plurality of grooves 63 are formed is subjected to a blasting process using alumina particles, thereby forming fine irregularities in addition to the irregularities formed by the plurality of grooves 63. Thus, the surface area of the surface of the protective member 60 is further increased, and the peeling of the group III nitride compound semiconductor attached to the surface of the protective member 60 is further suppressed. As a result, in the course of the film forming process using the MOCVD apparatus 1, the adhesion and deposition of foreign matters on the compound semiconductor substrate 40 is suppressed.

  Therefore, in the present embodiment, the yield of the laminated semiconductor wafer SW can be improved, and the yield of the light emitting element chips LC manufactured using the laminated semiconductor wafer SW as a starting material can also be improved.

In the present embodiment, the plurality of grooves 63 are formed radially on the surface of the protective member 60, so that the organometallic gas MO and ammonia NH ₃ introduced into the reaction vessel 10 are supported radially. It can supply toward 20 side.

  By the way, in the MOCVD apparatus 1 of the present embodiment, as described above, the protective member 60 performs the removal of the reaction product adhering to the surface and the re-formation of fine irregularities after being used for the film forming operation. And reused.

Next, a method for regenerating the protection member 60 as an example of the first step will be described.
FIG. 7 is a diagram illustrating an example of the configuration of the blast processing apparatus 200 used for the regeneration of the protection member 60.
The blast processing apparatus 200 includes an air supply unit 201 that supplies compressed air, a particle supply unit 202 that supplies blasting particles, an air supplied from the air supply unit 201, and a blast supply supplied from the particle supply unit 202. The mixed output unit 203 that mixes and outputs the particles and the mixed output unit 203 via a pipe or a hose and the like, and compressed air containing alumina particles supplied from the mixed output unit 203 (in the following description, a mixed gas) And an injection nozzle 204 that injects the protective member 60 toward the protective member 60 that is the object to be processed. In the present embodiment, the mixed gas is sprayed by the spray nozzle 204 onto the surface side of the protective member 60 after use, that is, the surface to which the reaction product is attached. As described above, in the present embodiment, the blasting process is performed using the so-called pneumatic blasting apparatus 200.

In the present embodiment, alumina having Knoop hardness higher than quartz constituting the protective member 60 is used as the blast particles. In addition, the Knoop hardness of quartz is about 820 (kg / cm ² ), and the Knoop hardness of alumina is about 2250 (kg / cm ² ). However, it is not limited to alumina, and for example, SiC, c-BN, diamond or the like may be used. For example, in the case where the protective member 60 is made of a material having a Knoop hardness lower than that of quartz, quartz may be used as blast particles.
In the present invention, the Knoop hardness can be adopted as a quantitative measure representing the hardness of the industrial material, but is not limited thereto. In addition to the Knoop hardness scale, for example, a scale such as Vickers hardness, Mohs hardness, Brinell hardness, Rockwell hardness, shear hardness, or the like may be used. For example, on the scale of Mohs hardness, values of alumina (9), GaN-based compound semiconductor (9), iron (8-8.5), quartz (7), glass (5-6), etc. are known.

  In the present embodiment, the pressure of the mixed gas injected from the injection nozzle 204 (hereinafter referred to as blast pressure) is set to 0.3 MPa, and the injection time of the mixed gas with respect to one protective member 60 is 1 minute to About 10 minutes. However, the blast pressure and the injection time may be changed as appropriate.

  In the present embodiment, the arithmetic average roughness Ra on the surface side of the protective member 60 after the blast treatment is set to 10 μm or more, more preferably 20 μm or more, so that the protective member 60 can be used in a film forming operation during reuse. The reaction product attached to the surface side is further prevented from peeling off. In addition, as a method for setting the arithmetic average roughness Ra on the surface side of the protective member 60 to 20 μm or more, for example, the average particle diameter of blast particles (alumina) used for blasting may be selected from a range of 250 μm to 600 μm. Can be mentioned.

In the present embodiment, a plurality of radial grooves 63 are formed in advance on the surface of the protective member 60, and fine irregularities are formed by blasting using alumina particles. The following structure may be adopted.
FIG. 8 shows another configuration example of the surface of the protection member 60.
First, as shown in FIG. 8A, a large number of concave portions having regularity or irregularity may be formed on the surface of the protective member 60, for example.
Further, as shown in FIG. 8B, a plurality of grooves 63 extending in one direction may be formed on the surface of the protection member 60.
Further, as shown in FIG. 8C, a plurality of grooves 63 directed in one direction and a plurality of other grooves 63 directed in a direction orthogonal to the one direction are formed on the surface of the protective member 60. Also good.
Furthermore, as shown in FIG. 8D, a plurality of grooves 63 may be formed concentrically on the surface of the protective member 60.
And as shown in FIG.8 (e), you may make it form the groove | channel 63 on the surface of the protection member 60 not in concentric form but in the shape of a spiral. 8E shows an example in which one groove 63 is formed in a spiral shape, a plurality of grooves 63 may be formed in a spiral shape.
However, in any case, the depth of the recess formed on the surface of the protective member 60 may be set larger than the depth of the recess formed by blasting in advance.

  On the other hand, the groove 63 may not be formed on the surface of the protective member 60, and only the concave portion by blasting using alumina particles may be formed. This will be described in detail in the embodiments described later.

  Further, in the present embodiment, the source gas is supplied from the first through hole 61 of the protective member 60 provided above the support 20, but the present invention is not limited to this. That is, the source gas may be supplied from the side of the support 20 in the horizontal direction.

Next, examples of the present invention will be described, but the present invention is not limited to the examples.
The inventor forms the compound semiconductor layer 100 on the compound semiconductor substrate 40 using the MOCVD apparatus 1 shown in FIG. 1, and the protection member 60 used at that time and the protection member 60 have been previously formed. The relationship between the blasting conditions and the number of foreign substances existing in the compound semiconductor layer 100 formed on the compound semiconductor substrate 40 was examined. However, here, the MOCVD apparatus 1 capable of mounting eight substrate holders 30, that is, eight compound semiconductor substrates 40 on the support 20 was used.

  Table 1 shows the configuration of the protective member 60, the contents of the blasting process, and the evaluation results in each of Examples 1 to 4 and Comparative Examples 1 and 2.

  In Examples 1 and 2, as the protective member 60, a member in which a radial groove 63 was previously formed on the surface as shown in FIG. 3 and then blasted with alumina particles was used. Here, in Example 1, the average particle diameter of the alumina particles used for the blasting treatment was 600 μm, and in Example 2, the average particle diameter of the alumina particles used for the blasting treatment was 250 μm. Further, in Examples 3 and 4, the protective member 60 used was blasted with alumina particles in a state where the grooves 63 were not formed on the surface in advance. Here, in Example 3, the average particle diameter of the alumina particles used for the blast treatment was 600 μm, and in Example 4, the average particle diameter of the alumina particles used for the blast treatment was 250 μm.

On the other hand, in Comparative Example 1, as the protective member 60, the radial groove 63 formed in advance as shown in FIG. 3 and then blasted with borosilicate glass particles was used. Here, in Comparative Example 1, the average particle size of the glass particles used for the blasting treatment was 180 μm. Moreover, in the comparative example 2, what used the blast process by the glass particle in the state which did not form the groove | channel 63 previously on the surface as the protective member 60 was used. Here, in Comparative Example 2, the average particle size of the glass particles used for the blast treatment was 180 μm. The Knoop hardness of the borosilicate glass used in Comparative Example 1 and Comparative Example 2 is about 480 (kg / cm ² ).

  Then, the MOCVD apparatus 1 was used to perform the film forming operation 56 times under each condition, and the compound semiconductor layer 100 of the 448 (8 × 56) stacked semiconductor wafers SW obtained in each condition was visually observed. . At this time, “A” means that the number of foreign substances existing in the compound semiconductor layer 100 is 10 or less, and “B” means that more than 10 and 20 or less. “C” was used, “D” was over 50 and less than 50, and “E” was over 51. Of these, evaluations “A”, “B”, and “C” are acceptable products, and “D” and “E” are unacceptable products.

Next, the evaluation result will be described.
When the film forming operation was performed using the protective member 60 that was blasted using alumina particles, as shown in Table 1, “A” in Example 1, “B” in Examples 2 and 3, In Example 4, an evaluation result of “C” was obtained. On the other hand, as shown in Table 1, when blasting was performed using glass particles, as shown in Table 1, evaluation results of “D” in Comparative Example 1 and “E” in Comparative Example 2 were obtained. It was.

  Here, Table 1 also shows the arithmetic average roughness Ra of the surface of the protective member 60 after the blasting process (before the film forming operation) in each example and each comparative example. In this case, the gravity average sandblasting device (MY-40) manufactured by Shinto Kogyo Co., Ltd. is used as the blasting device, and the Violet Laser Color 3D Profile Microscope Vk-9510 device of KEYENCE is used. Ra was evaluated. In Examples 1 to 3 in which the evaluation results are “A” and “B”, it can be seen that the arithmetic average roughness Ra after the blasting process is 20 μm or more. Further, in Example 4 in which the evaluation result is “C”, it can be seen that the arithmetic average roughness Ra after the blasting process is 10 μm or more. On the other hand, in Comparative Examples 1 and 2 in which the evaluation results are “D” and “E”, it can be seen that the arithmetic average roughness Ra after blasting is less than 10 μm.

From the above results, the following can be said.
First, by performing blasting using alumina particles that are harder than quartz constituting the protective member 60, the protective member 60 was adhered to the protective member 60 in the subsequent film forming operation, compared to when blasting was performed using glass particles. The reaction product is less likely to be peeled off and can be prevented from falling to the compound semiconductor layer 100 side.
In addition, by forming a plurality of grooves 63 on the surface of the protective member 60 in advance, and further performing blasting using alumina particles, the alumina particles are formed in a state where the grooves 63 are not formed on the surface of the protective member 60 in advance. The reaction product attached to the protective member 60 is less likely to be peeled off in the subsequent film forming operation than when the blast treatment is performed, and the fall to the compound semiconductor layer 100 side can be suppressed.
Further, when the surface of the protective member 60 is subjected to blasting using alumina particles, the average particle size is increased regardless of the presence or absence of the grooves 63, so that the protective member 60 can be used in subsequent film forming operations. The attached reaction product does not easily peel off, and can be prevented from falling to the compound semiconductor layer 100 side.

This is considered to be due to the following reasons.
First, when the surface of the protection member 60 made of quartz is blasted with alumina particles, the amount of local scraping of the protection member 60 is likely to be larger than when blasting with glass particles. The surface area of the surface increases.
Further, when the plurality of grooves 63 are formed in advance on the surface side of the protection member 60 made of quartz, the surface area of the surface of the protection member 60 is increased as compared with the case where the plurality of grooves 63 are not formed.
Further, when the average particle size of the alumina particles used in the blasting process is increased, the local scraping amount of the protective member 60 is likely to be larger than when the average particle size of the alumina particles is small. 60 The surface area of the surface is increased.
When the surface area of the surface of the protective member 60 increases in this way, the contact area between the protective member 60 and the reaction product can be increased, and as a result, peeling of the reaction product attached to the protective member 60 can be suppressed. I think.

DESCRIPTION OF SYMBOLS 1 ... MOCVD apparatus, 10 ... Reaction container, 11 ... Storage part, 12 ... Cover part, 20 ... Support body, 30 ... Substrate holding body, 40 ... Compound semiconductor substrate, 50 ... Heating part, 60 ... Protection member, 63 ... Groove , 100 ... Compound semiconductor layer, 110 ... Substrate, 120 ... Intermediate layer, 130 ... Underlayer, 140 ... n-type semiconductor layer, 140a ... n-type contact layer, 140b ... n-type cladding layer, 150 ... Light emitting layer, 150a ... Barrier Layer, 150b ... well layer, 160 ... p-type semiconductor layer, 160a ... p-type cladding layer, 160b ... p-type contact layer, 170 ... transparent positive electrode, 180 ... positive electrode bonding pad, 190 ... negative electrode bonding pad, 200 ... blast treatment apparatus SW ... Laminated semiconductor wafer LC ... Light emitting device chip

Claims (6)

Particles made of a material having Knoop hardness higher than that of the solid member are jetted onto the surface of the solid member having a front surface and a back surface and first unevenness is formed on the surface in advance , On the other hand, a first step of roughening the surface by forming second irregularities finer than the first irregularities ;
An organic metal vapor phase is supplied in the reaction chamber by containing a material to be formed and the solid member disposed so that the surface is opposed to the material to be formed above the material to be formed. And a second step of forming a compound semiconductor layer on the object to be formed using a growth method. The method for producing a compound semiconductor according to claim 1, wherein the first unevenness in the solid member is formed by a groove including a recess having continuity. The first unevenness having a depth of 0.2 mm or more and 0.8 mm or less is formed in advance on the surface of the solid member,
Forming the second unevenness having a depth of 10 μm or more in the first step;
A method for producing a compound semiconductor according to claim 1 or 2. The first unevenness having a depth of 0.2 mm or more and 0.8 mm or less is formed on the surface of the solid member,
In the first step, spraying the particles having a particle size set to 250 μm or more and 600 μm or less
The method for producing a compound semiconductor according to claim 1, wherein: In the first step, the reaction product adhering to the surface of the solid member with the formation of the compound semiconductor layer performed before the first step is removed by jetting the particles. The method of manufacturing a compound semiconductor according to claim 1 , wherein the surface is roughened. 6. The method for producing a compound semiconductor according to claim 1, wherein the solid member is made of quartz and the particles are made of alumina.

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