JP5438667B2 - Microprocessor intermittent error detection method - Google Patents

Description

  The present invention relates to a method for detecting an intermittent abnormality caused by an instantaneous drop in the power supply voltage of a microprocessor in a control device.

  Conventionally, in a control device using a microprocessor, an abnormality of the microprocessor is monitored using a watch dog timer circuit. That is, when the microprocessor enters an illegal state and the reset signal is not transmitted regularly (timeout), an abnormality detection signal is generated and a prescribed procedure is executed. The prescribed measures include a system reset, a forced system stop by power-off, or a power-on after power-off.

  For example, in Patent Document 1, as a processor abnormality monitoring method using a watchdog timer, the watchdog timer counter starts counting from an initial value every time the processor generates a reset signal, and the count value is set to the first setting. A first timeout signal is generated when the value is reached, an interrupt signal is generated by the first timeout signal, counting is started at the timing of the interrupt signal, and an alarm signal is generated from the second timeout signal when the second set value is reached. The way it occurs is presented.

  According to this method, it is not necessary to set the first set value depending on the task having the longest processing time, and for example, the setting time can be set in consideration of the processing time of the task with the highest execution frequency. It is possible to detect a processor abnormality promptly without depending on.

  By the way, in the microprocessor, when the processing becomes a heavy load, the power consumption increases, and the power supply voltage may drop instantaneously. In the control device, the power supply voltage drop is monitored. However, the instantaneous power supply voltage drop caused by the load state of the microprocessor as described above is not recognized as an abnormality and is not detected.

Japanese Patent Laid-Open No. 11-327959

  As described above, in the conventional abnormality detection method, when the power supply voltage instantaneously drops due to the load state of the microprocessor, the microprocessor can operate intermittently because it is not a complete voltage drop, and the watchdog timer works. There was no case. As a result, for example, there is a possibility that even if the microprocessor falls into an intermittent abnormality state where task A is normally executed but task B is not normally executed, it cannot be detected.

  The present invention has been made to solve the above-described problems, and can easily monitor that the microprocessor is executing all tasks normally, and can easily detect intermittent abnormalities in the microprocessor. An object of the present invention is to provide a method for detecting intermittent abnormality of a microprocessor.

A method for detecting an intermittent abnormality of a microprocessor according to the present invention includes a first counter, n tasks (n ≧ 2) including task 1 having the highest priority of execution and task n having the lowest priority, and a watchdog timer reset A microprocessor that executes a task and a watchdog timer circuit having a second counter, and resets the second counter each time the microprocessor generates a reset signal, and the count value of the second counter reaches a set value In the control device provided with the abnormality detection circuit for executing the prescribed action, a method for detecting an intermittent abnormality of the microprocessor for detecting that any of the n tasks has not been normally executed, comprising: The initial value of the count value is given to task 1, n tasks are executed in order of priority, and the count value is The first step is sequentially sent to the task, and the count value is incremented in task n and given to task 1 in the next calculation cycle. Thereafter, the same process is repeated, and the first counter in the first step is counted. This includes a second step of monitoring the value and determining that an intermittent abnormality has occurred in the microprocessor when there is no change in the count value of the first counter in the current calculation cycle and the previous calculation cycle.

  According to the intermittent abnormality detection method for a microprocessor according to the present invention, n tasks are executed in descending order of priority, and the count value of the first counter is sequentially sent to the subsequent task. The microprocessor normalizes all tasks in a simple way by comparing the count value of the first counter of the previous calculation cycle and the previous calculation cycle while repeating the process of counting up and giving to task 1 of the next calculation cycle It is possible to easily monitor whether or not the microprocessor is running and to easily detect an intermittent abnormality of the microprocessor.

It is the schematic which shows the structure of the control apparatus using the microprocessor in Embodiment 1 of this invention. It is a figure which shows the intermittent abnormality detection method of the microprocessor in Embodiment 1 of this invention. It is a figure which shows the abnormality detection method of the microprocessor using the conventional watchdog timer circuit which is a comparative example of Embodiment 1 of this invention. It is a figure which shows the intermittent abnormality detection method of the microprocessor in Embodiment 2 of this invention. It is a figure which shows the intermittent abnormality detection method of the microprocessor in Embodiment 3 of this invention. It is a figure which shows the intermittent abnormality detection method of the microprocessor in Embodiment 4 of this invention. It is a figure which shows the intermittent abnormality detection method of the microprocessor in Embodiment 5 of this invention. It is a figure which shows the intermittent abnormality detection method of the microprocessor in Embodiment 6 of this invention. It is a figure which shows the intermittent abnormality detection method of the microprocessor in Embodiment 7 of this invention.

Embodiment 1 FIG.
Hereinafter, an intermittent abnormality detection method for a microprocessor according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram illustrating a configuration of a control device using a microprocessor according to the first embodiment, and FIG. 2 is a flowchart illustrating a method for detecting an intermittent abnormality of the microprocessor according to the first embodiment. In the drawing, the same and corresponding parts are denoted by the same reference numerals.

As shown in FIG. 1, the control device (hereinafter abbreviated as “this device”) in the first embodiment includes a microprocessor 1 and an abnormality detection circuit 2. The microprocessor 1 of this apparatus has an operation counter (not shown) as a first counter, and includes n tasks (n ≧ 2) including the task 1 having the highest execution priority and the task n having the lowest priority. The watchdog timer reset task is executed.

  Further, the abnormality detection circuit 2 includes a watchdog timer circuit 21 having a second counter (hereinafter abbreviated as a counter), and whenever the microprocessor 1 generates a watchdog timer reset signal (hereinafter abbreviated as a reset signal), The counter of the watchdog timer circuit 21 is reset. The abnormality detection circuit 2 executes a prescribed measure when the reset signal is not regularly transmitted from the microprocessor 1 to the watchdog timer circuit 21 and the count value of the counter reaches the set value. The prescribed process is a process for generating, for example, a microprocessor stop signal and a failure alarm signal and outputting them.

  The microprocessor 1 that has received the microprocessor stop signal output from the abnormality detection circuit 2 performs a forced stop process. The other device 3 that has received the failure alarm signal output from the alarm output circuit 22 of the abnormality detection circuit 2 recognizes an abnormality in the microprocessor 1 of this device. The other device 3 is another control device or a computer. When this device is a turbine control device of a power plant, for example, the other device 3 is a boiler control device, a sequence control device, a plant control computer, or the like. To do. When this apparatus is a server of an information communication system, for example, the other apparatus 3 corresponds to a client personal computer. Alternatively, the present apparatus and the other apparatus 3 may be reversed.

  The method for detecting an intermittent abnormality of a microprocessor according to the first embodiment includes a first process and a second process described below, and n is performed by instantaneous reduction of the power supply voltage caused by the load state of the microprocessor 1. It is an easy method to detect that one of the tasks is not executed normally.

  First, in the first step, the initial value of the count value of the operation counter is given to task 1, n tasks are executed in descending order of priority, and the count values are sequentially sent to subsequent tasks. At n, the count value is counted up (+1). This counted up count value is given to task 1 of the next calculation cycle, and thereafter the same processing is repeated. The count value of the operation counter is transmitted to the subsequent task as an operation counter signal.

  Subsequently, in the second step, the count value of the operation counter in the first step is monitored, and if there is no change in the count value of the operation counter in the current calculation cycle and the previous calculation cycle, the microprocessor 1 is intermittently abnormal. Is determined to have occurred. In the first embodiment, the second step is executed in the watchdog timer reset task, and the watchdog timer reset task is executed when the count value of the operation counter in the current calculation cycle and the previous calculation cycle is changed. Then, a reset signal is transmitted to the watchdog timer circuit 21 of the abnormality detection circuit 2.

  The method for detecting an intermittent abnormality of the microprocessor according to the first embodiment will be described in detail with reference to the flowchart of FIG. The microprocessor 1 executes the initialization process of step 11 (S11) following the start process of step 10 (S10). In this initialization process, “zero” is substituted into the operation counter signal “LA0” as the initial value of the count value of the operation counter.

Next, in step 12 (S12), a watchdog timer reset task is executed. At the time of initial activation, in step S12, step 121 (S121) is not executed, and the operation counter signal “LA0” serving as the initial value of the operation counter is transmitted to task 1 in step 13 (S13).

  In S13, task 1 with the highest priority is executed, and the operation counter signal “LA0” transmitted from S12 is assigned to “LA1”, and this “LA1” is transferred to task 2 in the next step 14 (S14). Send. Subsequently, in S14, the task 2 having the second highest priority is executed, and the operation counter signal “LA1” transmitted from the task 1 in S13 is assigned to “LA2” and transmitted to the subsequent task (not shown). . Similarly, all tasks are executed in descending order of priority, and operation counter signals are transmitted.

  Further, in task n in step 15 (S15), task n having the lowest priority is executed, and operation counter signal “LA (n−1)” transmitted from task (n−1), which is the preceding task, is executed. +1 count up with respect to the count value. This counted up count value is transmitted to the watchdog timer reset task in S12 as an updated operation counter signal “LAn”.

  In the watchdog timer reset task in S12, the count value of the operation counter in the current calculation cycle and the previous calculation cycle is compared in S121. The operation counter signal “LAn” of the current calculation cycle and the previous calculation cycle are compared, and when those values are changed (YES), it is determined that all tasks are executed normally, and the abnormality detection circuit 2 A reset signal is transmitted to the watchdog timer circuit 21. The watchdog timer reset task in S12 assigns the updated operation counter signal “LAn” to “LA0” and gives it to task 1 (S13) of the next calculation cycle.

  On the other hand, the abnormality detection circuit 2 counts up (+1) the counter of the watchdog timer circuit 21 in step 21 (S21) after the start process in step 20 (S20). Further, when a reset signal is transmitted from the microprocessor 1 in step 22 (S22) (YES), the counter of the watchdog timer circuit 21 is reset (cleared to 0) in step 23 (S23), and step 24 (S24). Proceed to

  If the reset signal is not transmitted from the microprocessor 1 for a predetermined period in S22 (NO), it is confirmed in S24 whether the counter of the watchdog timer circuit 21 is overflowed. In case of overflow (YES), step 25 (S25) and step 26 (S26) are executed. In S25, a microprocessor stop signal is generated and output. In S26, a failure alarm signal is generated, and a failure alarm is digitally output (DO1) to the other device 3. When the microprocessor stop signal is output in S25, the microprocessor 1 is forcibly stopped in step 16 (S16).

  Next, an operation when an intermittent abnormality occurs in the microprocessor 1 will be described. For example, when task 1 in S13 is executed and the power supply voltage of the microprocessor 1 is instantaneously reduced and task 1 is not executed normally, the value of the operation counter signal “LA1” transmitted to task 2 in S14 in task 1 Can not be updated. Therefore, the same operation counter signal “LA1” as the previous calculation cycle is transmitted to the next task 2. Task 2 substitutes operation counter signal “LA1”, which has not been updated since the previous calculation cycle, in “LA2”, and transmits it to the subsequent task.

Thus, the operation counter signal “LA (n−1)” transmitted to the task n in S15 is not updated from the previous calculation cycle. The count value incremented by 1 to this value is equal to the previous calculation cycle. Therefore, in S121 of the watchdog timer reset task in S12, when the current calculation cycle and the previous calculation cycle “LAn” are compared, there is no change in the values (NO), so a reset signal is sent to the abnormality detection circuit 2. Do not send.

  When such a state continues for a predetermined period, the abnormality detection circuit 2 continues to receive no reset signal in S22, and the counter of the watchdog timer circuit 21 overflows in S24. As a result, a microprocessor stop signal is output in S25, and a failure alarm is output in S26. As a result, the other device 3 recognizes that an abnormality has occurred in the microprocessor 1, and the microprocessor 1 is stopped in the abnormal state by the forced stop processing in S16.

  FIG. 3 shows a microprocessor abnormality detection method using a conventional watchdog timer, which is a comparative example of the first embodiment. In FIG. 3, the processes S10 to S16 executed by the microprocessor 1 and the processes S20 to S26 executed by the abnormality detection circuit 2 are basically intermittent microprocessor abnormalities in the first embodiment shown in FIG. This is the same process as the detection method.

  However, in the conventional abnormality detection method, the watchdog timer reset task in S12 outputs a reset signal at a fixed period, and does not determine whether normal processing has been executed in other tasks. The reset signal is not output from the watchdog timer reset task (S12) of the microprocessor 1, and as a result, the counter of the watchdog timer in the abnormality detection circuit 2 overflows (S24), and an abnormality occurs in the microprocessor 1. Judge that

  In the conventional abnormality detection method, an instantaneous drop in the power supply voltage occurs in the microprocessor 1. For example, even if the task 2 in S14 is not normally executed, the power supply voltage is recovered immediately thereafter, and the subsequent tasks are sequentially executed. When the task n of S15 is finally executed, the watchdog timer reset task of S12 transmits a reset signal to the abnormality detection circuit 2. For this reason, the watchdog timer does not work and the intermittent abnormality of the microprocessor 1 is not detected.

  As described above, according to the intermittent abnormality detection method for a microprocessor according to the first embodiment, the initial value of the count value of the operation counter is given to task 1 and n tasks are executed in descending order of priority. , Sequentially sending the count value to the subsequent task, counting up the count value in task n, giving it to task 1 in the next calculation cycle, and thereafter repeating the same processing, A second step of monitoring the count value of the operation counter in step (2) and determining that an intermittent abnormality has occurred in the microprocessor 1 when there is no change in the count value of the operation counter in the current calculation cycle and the previous calculation cycle. Therefore, it is possible to easily monitor that the microprocessor 1 is executing all the tasks normally, and to detect an intermittent abnormality of the microprocessor 1 easily. Kill.

Embodiment 2. FIG.
FIG. 4 is a flowchart showing a method for detecting an intermittent abnormality of a microprocessor according to the second embodiment of the present invention. In FIG. 4, the same reference numerals are assigned to the same and corresponding parts as in FIG. In the first embodiment, the count value of the operation counter is monitored (second step) in the watchdog timer reset task (S12). However, in the second embodiment, the operation counter monitoring task in the subsequent stage of task n is performed. Is to be executed. Since other configurations and operations are the same as those in the first embodiment, description thereof is omitted.

  In the second embodiment, as shown in FIG. 4, the count value of the operation counter is monitored in the operation counter monitoring task in step 17 (S17) subsequent to task n. Note that the watchdog timer reset task in S12 outputs a reset signal at a constant cycle to the abnormality detection circuit 2 as in the conventional method (see FIG. 3).

  Task 1 in S13 starts processing using the count value “LA1” of the operation counter initialized in the initialization processing in S11. In the operation counter monitoring task in S17, step 171 (S171) is not executed in the first calculation cycle, and in the second and subsequent calculation cycles, the count values of the current calculation cycle and the previous calculation cycle are compared in S171.

  That is, the operation counter signal “LAn” of the current calculation cycle and the previous calculation cycle are compared, and when those values change (YES), it is assumed that all tasks are executed normally, and the operation counter monitoring task is A reset signal is transmitted to the watchdog timer circuit 21 of the abnormality detection circuit 2. In S171, if there is no change between “LAn” of the current calculation cycle and the previous calculation cycle (NO), no reset signal is transmitted to the abnormality detection circuit 2.

  According to the second embodiment, the intermittent abnormality of the microprocessor 1 is self-diagnosed by the operation counter monitoring task (S17) in addition to the conventional watchdog timer reset task (S12). There is an effect to increase.

Embodiment 3 FIG.
FIG. 5 is a flowchart showing a method for detecting an intermittent abnormality of a microprocessor according to the third embodiment of the present invention. In FIG. 5, the same reference numerals are assigned to the same and corresponding parts as in FIG. 4. In the third embodiment, as in the second embodiment, monitoring of the count value of the operation counter (second step) is executed in the operation counter monitoring task in S17. Further, a self-diagnosis circuit for forcibly stopping the microprocessor 1 when it is determined in the operation counter monitoring task of S17 that an intermittent abnormality has occurred in the microprocessor 1 is provided. Since other configurations and operations are the same as those in the first embodiment, description thereof is omitted.

  In the third embodiment, as shown in FIG. 5, the count value of the operation counter is monitored in the operation counter monitoring task of S17, and in the second and subsequent calculation cycles, the count value of the current calculation cycle and the previous calculation cycle in S171. Compare If these values have changed (YES), it is assumed that all tasks have been executed normally, and a reset signal is transmitted to the watchdog timer circuit 21 of the abnormality detection circuit 2. If there is no change in these values (NO), it is determined that an intermittent abnormality has occurred in the microprocessor 1, and the microprocessor 1 is forcibly stopped by the self-diagnosis circuit (S16).

  According to the third embodiment, when an intermittent abnormality of the microprocessor 1 is self-diagnosed by the operation counter monitoring task (S17) in addition to the conventional watchdog timer reset task (S12), and it is determined that the intermittent abnormality has occurred. By providing a self-diagnosis circuit for forcibly stopping the microprocessor 1, the microprocessor 1 can be quickly and reliably stopped when an abnormality occurs.

Embodiment 4 FIG.
FIG. 6 is a flowchart showing a method for detecting an intermittent abnormality of a microprocessor according to the fourth embodiment of the present invention. In FIG. 6, the same reference numerals are assigned to the same and corresponding parts as in FIG. In the fourth embodiment, the count value of the operation counter is output as an analog signal to the other device 3, and the count value of the operation counter is monitored (second step) in the other device 3. Since other configurations and operations are the same as those in the first embodiment, description thereof is omitted.

  In the fourth embodiment, as shown in FIG. 6, the count value of the operation counter in task n in S15 is output as an analog signal (AO1 in the figure) to the other device 3. The other device 3 monitors the count value of the operation counter and determines that an intermittent abnormality has occurred in the microprocessor 1 of this device when there is no change in the count value of the current calculation cycle and the previous calculation cycle.

  According to the fourth embodiment, in addition to the conventional watchdog timer reset task (S12), the count value of the operation counter is monitored by the other device 3, so that the intermittent abnormality of the microprocessor 1 of this device can be monitored. It can be detected by the device 3.

Embodiment 5 FIG.
FIG. 7 is a flowchart showing a method for detecting an intermittent abnormality of a microprocessor according to the fifth embodiment of the present invention. In FIG. 7, the same reference numerals are assigned to the same and corresponding parts as in FIG. The fifth embodiment is a combination of the third embodiment (FIG. 5) and the fourth embodiment (FIG. 6), and the count value of the operation counter (second step) is monitored by the operation of S17. The counter monitoring task is executed in the other device 3. Since other configurations and operations are the same as those in the first embodiment, description thereof is omitted.

  In the fifth embodiment, as shown in FIG. 7, when it is determined in the operation counter monitoring task in S17 that an intermittent abnormality has occurred in the microprocessor 1, the self-diagnostic circuit performs the same as in the third embodiment. The microprocessor 1 is forcibly stopped. Similarly to the fourth embodiment, the other device 3 monitors the count value of the operation counter, and if there is no change in the count value of the current calculation cycle and the previous calculation cycle, the microprocessor 1 of the present device It is determined that an intermittent abnormality has occurred.

  According to the fifth embodiment, since the count value of the operation counter is monitored by the other device 3 in addition to the conventional watchdog timer reset task (S12), the intermittent abnormality of the microprocessor 1 of this device can be monitored. It can be detected by the device 3. Furthermore, by providing a self-diagnosis circuit that forcibly stops the microprocessor 1 when it is determined that an intermittent abnormality has occurred, the microprocessor 1 can be stopped quickly and reliably when an abnormality occurs.

Embodiment 6 FIG.
FIG. 8 is a flowchart showing a method for detecting an intermittent abnormality of a microprocessor according to the sixth embodiment of the present invention. In FIG. 8, the same reference numerals are assigned to the same and corresponding parts as in FIG. In the sixth embodiment, the count value of the operation counter is output as an analog signal to the other device 3 as in the fourth embodiment (FIG. 6). However, in the sixth embodiment, a plurality of other devices are output. 3 is output to the network, and the count value of the operation counter is monitored (second step) in a plurality of other devices 3. Since other configurations and operations are the same as those in the first embodiment, description thereof is omitted.

  In the sixth embodiment, as shown in FIG. 8, the count value of the operation counter in task n in S15 is network-outputted to a plurality of other devices 3 (AO100 in the figure). The plurality of other devices 3 monitor the count values of the operation counters, and determine that an intermittent abnormality has occurred in the microprocessor 1 of this device when there is no change in the count values of the current calculation cycle and the previous calculation cycle.

  According to the sixth embodiment, since the count value of the operation counter is monitored by a plurality of other devices 3 in addition to the conventional watchdog timer reset task (S12), the intermittent abnormality of the microprocessor 1 of the present device Can be detected earlier.

Embodiment 7 FIG.
FIG. 9 is a flowchart showing a method for detecting an intermittent abnormality of a microprocessor according to the seventh embodiment of the present invention. In FIG. 9, the same reference numerals are given to the same parts as those in FIGS. 7 and 8. The seventh embodiment is a combination of the fifth embodiment (FIG. 7) and the sixth embodiment (FIG. 8), and the count value of the operation counter (second step) is monitored by the operation of S17. The counter monitoring task is executed in a plurality of other devices 3. Since other configurations and operations are the same as those in the first embodiment, description thereof is omitted.

  In the seventh embodiment, as shown in FIG. 9, when it is determined that an intermittent abnormality has occurred in the microprocessor 1 in the operation counter monitoring task in S17, the microprocessor 1 is forcibly stopped by the self-diagnosis circuit. In addition, the count values of the operation counters are also monitored in a plurality of other devices 3, and it is determined that an intermittent abnormality has occurred in the microprocessor 1 of this device when there is no change in the count values of the current calculation cycle and the previous calculation cycle. To do.

  According to the seventh embodiment, in addition to the conventional watchdog timer reset task (S12), the count value of the operation counter is monitored by the operation counter monitoring task and a plurality of other devices 3. It is possible to detect the intermittent abnormality of the processor 1 earlier. Furthermore, by providing a self-diagnosis circuit that forcibly stops the microprocessor 1 when it is determined that an intermittent abnormality has occurred, the microprocessor 1 can be stopped quickly and reliably when an abnormality occurs.

  The present invention can be used as an intermittent abnormality detection method for a microprocessor used in a control device.

1 Microprocessor, 2 Anomaly detection circuit, 3 Other devices,
21 Watchdog timer circuit, 22 Alarm output circuit.

Claims (8)

A microprocessor having a first counter, executing n tasks (n ≧ 2) including task 1 having the highest execution priority from task 1 to lowest task n and a watchdog timer reset task, and a second counter An abnormality detection circuit that includes a watchdog timer circuit, resets the second counter each time the microprocessor generates a reset signal, and executes a prescribed action when the count value of the second counter reaches a set value In a control device comprising: a microprocessor intermittent error detection method for detecting that any of the n tasks has not been executed normally;
The initial value of the count value of the first counter is given to the task 1, the n tasks are executed in order of priority, and the count values are sequentially sent to the subsequent task. A first step of counting up the value and giving it to the task 1 of the next calculation cycle, and repeating the same processing;
The count value of the first counter in the first step is monitored, and it is determined that an intermittent abnormality has occurred in the microprocessor when there is no change in the count value of the first counter in the current calculation cycle and the previous calculation cycle. A method for detecting an intermittent abnormality of a microprocessor, comprising: a second step of:   2. The method for detecting an intermittent abnormality of a microprocessor according to claim 1, wherein the second step is executed in the watchdog timer reset task, and the watchdog timer reset task includes a current calculation cycle and a previous calculation cycle. An intermittent abnormality detection method for a microprocessor, comprising: transmitting a reset signal to the abnormality detection circuit when the count value of the first counter is changed.   2. The method according to claim 1, wherein the second step is executed in an operation counter monitoring task subsequent to the task n, and the operation counter monitoring task includes a current calculation cycle and a previous time. An intermittent abnormality detection method for a microprocessor, comprising: transmitting a reset signal to the abnormality detection circuit when a change is made in the count value of the first counter in a calculation cycle.   2. The microprocessor intermittent abnormality detection method according to claim 1, wherein in the second step, when it is determined that an intermittent abnormality has occurred in the microprocessor, the microprocessor performs self-diagnosis using the self-diagnosis circuit. A method for detecting an intermittent abnormality of a microprocessor, wherein the processor is forcibly stopped.   2. The method according to claim 1, wherein the count value of the first counter is output as an analog signal to another device, and the second step is executed in the other device. A method for detecting intermittent abnormality of a microprocessor, which is characterized.   6. The microprocessor intermittent abnormality detection method according to claim 5, wherein the other device is another control device or a computer.   6. The method for detecting intermittent abnormality of a microprocessor according to claim 5, wherein the count value of the first counter is network-outputted to the plurality of other devices, and the second step is executed in the plurality of other devices. An intermittent abnormality detection method for a microprocessor, characterized in that The intermittent abnormality detection method for a microprocessor according to any one of claims 1 to 7, wherein the abnormality detection circuit generates a microprocessor stop signal and a failure alarm signal as the prescribed measures, A method for detecting an intermittent abnormality of a microprocessor, characterized by outputting them.

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