JP5433845B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents
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Description
本発明は、製造過程のばらつきを補正することができる半導体集積回路装置及びその製造方法に関する。 The present invention relates to a semiconductor integrated circuit device capable of correcting variations in manufacturing processes and a manufacturing method thereof.
ナノメートル世代（65ナノメートル以細）の半導体集積回路装置においては、チップ内の同一形状のトランジスタであっても、製造過程のばらつきにより特性が異なってくる。そのため、良品チップの歩留りが低下したり、良品チップでも性能が劣化するといった問題が生じる。 In a semiconductor integrated circuit device of nanometer generation (65 nanometers or smaller), even if transistors of the same shape in a chip have different characteristics due to variations in manufacturing processes. Therefore, there arises a problem that the yield of non-defective chips is reduced, and the performance is deteriorated even with good chips.
またナノメートル世代の半導体集積回路装置においては、ウェハ間、チップ間におけるトランジスタの特性ばらつきのみならず、チップ内のトランジスタの特性ばらつきが顕著となり、ウェハ当たりの良品チップ率である歩留りを低下させ、経済的にもコストを低下させる。また、目標速度や消費電力といった仕様を満たせないチップも多くなる。このため、回路設計においてばらつきマージンを大きく取る必要があり、仕様性能を満たすための設計に大きな負担を負うことになる。 In addition, in the nanometer generation semiconductor integrated circuit device, not only the transistor characteristic variation between wafers and chips, but also the transistor characteristic variation in the chip becomes significant, reducing the yield, which is a good chip rate per wafer, Economically reduce costs. In addition, more chips cannot meet the specifications such as target speed and power consumption. For this reason, it is necessary to provide a large variation margin in the circuit design, and a large burden is imposed on the design for satisfying the specification performance.
現在DFM（Design For Manufacturability:製造容易化設計）によりこの問題を解決しようと試みられている。これは、特性ばらつきを予測し、設計や製造プロセスにフィードバックして歩留りを向上させようとする技術である（図１３参照）。しかしながら、この手法では、設計や製造プロセスに大きな制約がかかり、TAT（ターンアラウンドタイム）を悪化させる等の問題がある。特に大ききな特性ばらつきを考慮するため、設計マージンが大きく、仕様設計の段階で高い性能のチップを目指すことが困難となっている。
本発明が解決しようとする課題は、ナノメートル世代の半導体集積回路装置の製造上で生じるトランジスタの特性ばらつきによる動作不良や性能劣化を製造後に検出し、その部分、又は回路全体の動作を良品レベルに引き上げ、歩留り及び性能を向上させようとするものである。また、DFMによる設計制約や製造プロセス制約を緩和させ、マージンによる仕様設計の性能劣化を改善しつつ、歩留りも向上できるといった設計、製造容易性と歩留りを両立させることである。 The problem to be solved by the present invention is to detect a malfunction or performance degradation due to variations in characteristics of transistors occurring in the fabrication of a nanometer generation semiconductor integrated circuit device after fabrication, and to detect the operation of the part or the entire circuit at a non-defective level. To improve the yield and performance. In addition, the design constraints and manufacturing process constraints due to DFM are alleviated, the performance deterioration of the specification design due to the margin is improved, and the yield can also be improved, and both the ease of design and manufacturability and the yield are compatible.
上記の課題を解決するために本発明は、次のような半導体集積回路装置及びその製造方法を提供するものである。
（１）製造後の各トランジスタの特性のばらつきを補正できる回路素子を接続したトランジスタを含み、上記回路素子は、不揮発性のＴＭＲ素子であることを特徴とする半導体集積回路装置。
（２）上記回路素子は、上記各トランジスタの抵抗特性を補正できるものであることを特徴とする（１）に記載の半導体集積回路装置。
（３）上記回路素子は、異なる絶対値を持つ複数のＴＭＲ素子を直列、並列、又は直並列に接続して構成されたものであることを特徴とする（１）又は（２）に記載の半導体集積回路装置。
（４）上記トランジスタは、差動増幅回路又はＣＭＯＳインバータ回路を構成するトランジスタであることを特徴とする（１）乃至（３）のいずれかに記載の半導体集積回路装置。
（５）上記回路素子は、補正対象のトランジスタに直列に接続されていることを特徴とする（１）乃至（４）のいずれかに記載の半導体集積回路装置。
（６）上記回路素子は、補正対象のトランジスタに並列に接続されていることを特徴とする（１）乃至（４）のいずれかに記載の半導体集積回路装置。
（７）製造後の各トランジスタの特性のばらつきを補正できる回路素子として、不揮発性のＴＭＲ素子を補正対象のトランジスタに接続し、トランジスタの製造後、前記補正対象のトランジスタの特性のばらつきを補正できるようにしたことを特徴とする半導体集積回路装置の製造方法。
（８）上記トランジスタの特性は、トランジスタの抵抗特性であることを特徴とする（７）に記載の半導体集積回路装置の製造方法。
In order to solve the above-described problems, the present invention provides the following semiconductor integrated circuit device and manufacturing method thereof.
(1) saw including a transistor connected to the circuit element variations can be corrected in the characteristics of the transistor after manufacturing, the circuit elements, the semiconductor integrated circuit device which is a TMR element in a nonvolatile.
(2) The semiconductor integrated circuit device according to (1), wherein the circuit element is capable of correcting a resistance characteristic of each transistor.
(3) The circuit element is configured by connecting a plurality of TMR elements having different absolute values in series, parallel, or series-parallel, according to (1) or (2) Semiconductor integrated circuit device.
(4) The semiconductor integrated circuit device according to any one of (1) to (3) , wherein the transistor is a transistor constituting a differential amplifier circuit or a CMOS inverter circuit.
(5) The semiconductor integrated circuit device according to any one of (1) to (4), wherein the circuit element is connected in series to a transistor to be corrected.
(6) The semiconductor integrated circuit device according to any one of (1) to (4), wherein the circuit element is connected in parallel to a transistor to be corrected.
(7) A non-volatile TMR element can be connected to a transistor to be corrected as a circuit element that can correct the variation in characteristics of each transistor after manufacture, and the characteristics variation of the transistor to be corrected can be corrected after the transistor is manufactured. A method of manufacturing a semiconductor integrated circuit device, characterized in that it is configured as described above.
(8) The method for manufacturing a semiconductor integrated circuit device according to (7), wherein the characteristics of the transistor are resistance characteristics of the transistor.
本発明によれば、特性ばらつきを製造後に補正することで歩留り及び性能を改善可能である。さらに製造プロセス制約や設計マージン制約等が緩和され、より高性能な半導体集積回路装置を制約にとらわれずに設計・製造することが可能となる。 According to the present invention, it is possible to improve yield and performance by correcting characteristic variations after manufacturing. Further, manufacturing process restrictions, design margin restrictions, and the like are relaxed, and a higher performance semiconductor integrated circuit device can be designed and manufactured without being restricted by the restrictions.
本発明に係る製造工程を図１２に示す。本発明では、トランジスタの特性を補正できる回路素子をトランジスタに付加し、トランジスタの製造後、トランジスタの特性を補正できるようにしている。以下本発明の半導体集積回路装置及びその製造方法について詳細に説明する。 A manufacturing process according to the present invention is shown in FIG. In the present invention, a circuit element capable of correcting the characteristics of the transistor is added to the transistor so that the characteristics of the transistor can be corrected after the transistor is manufactured. Hereinafter, a semiconductor integrated circuit device and a manufacturing method thereof according to the present invention will be described in detail.
図１にトランジスタの特性を補正できる回路素子として不揮発性メモリ等に使用される不揮発性デバイスを用いた例を示す。これは、トランジスタの特性ばらつきを、製造後に不揮発性デバイスの抵抗値などの特性により改善するものである。図１(a)、(b)に示すようにトランジスタに不揮発性デバイス等の回路素子を直列又は並列に接続することが基本である。 FIG. 1 shows an example in which a nonvolatile device used in a nonvolatile memory or the like is used as a circuit element that can correct the characteristics of a transistor. This is to improve the characteristic variation of the transistor by the characteristic such as the resistance value of the nonvolatile device after the manufacture. As shown in FIGS. 1A and 1B, a circuit element such as a nonvolatile device is basically connected in series or in parallel to a transistor.
図２(a)は、磁気メモリ（MRAM）の記憶セルであるTMR（磁気抵抗効果）素子を上記回路素子として用いた例であり、トランジスタと直接接続して回路を構成する。簡単のためトランジスタの特性を線形抵抗と考え設計時の目標値をRTRとする。このとき製造ばらつきによる抵抗値のずれを−ΔRとする。ここで、TMR素子の抵抗値RTMRをΔRと等しくすることにより、ばらつきによる特性変化を相殺することが可能となる。また、図２(b)のようにTMR素子を並列に接続することでばらつきを補正することもできる。 FIG. 2A shows an example in which a TMR (magnetoresistance effect) element, which is a storage cell of a magnetic memory (MRAM), is used as the circuit element, and a circuit is configured by directly connecting to a transistor. For simplicity, the transistor characteristics are assumed to be linear resistors, and the target value at the time of design is RTR . At this time, the deviation of the resistance value due to manufacturing variation is assumed to be −ΔR. Here, by making the resistance value R TMR of the TMR element equal to ΔR, it is possible to cancel the characteristic change due to variation. Further, the variation can be corrected by connecting TMR elements in parallel as shown in FIG.
図３は、基本的なCMOSインバータ回路である。
図４は、CMOSインバータ回路の直流特性であり、反転する入力電圧値VINをVTとする。通常VTは、電源電圧の1/2となるように設計されるが、PMOS又はNMOSトランジスタの特性がばらつくと、VTが変化してしまい、遅延に変動を起こし、誤動作の原因となる場合がある。
FIG. 3 shows a basic CMOS inverter circuit.
FIG. 4 shows the DC characteristics of the CMOS inverter circuit, and the inverted input voltage value V IN is V T. Normally, V T is designed to be 1/2 of the power supply voltage, but if the characteristics of the PMOS or NMOS transistor vary, V T will change, causing fluctuations in the delay and causing malfunctions. There is.
図５は、各NMOS、PMOSトランジスタにそれぞれTMR素子を直列に接続したCMOSインバータ回路であり、このTMR素子の抵抗値を変化させることで、PMOS又はNMOSトランジスタの特性のばらつきを補正することができる。 FIG. 5 shows a CMOS inverter circuit in which a TMR element is connected in series to each NMOS and PMOS transistor, and variations in the characteristics of the PMOS or NMOS transistor can be corrected by changing the resistance value of the TMR element. .
図６は、アナログ回路の基本となり、ディジタル回路の高速スイッチング基本回路としても活用されている差動増幅回路である。差動増幅回路では、差動入力VIN1‐VIN2により、出力電流I1、I2は図７のような特性を示す。 FIG. 6 shows a differential amplifier circuit that is the basis of an analog circuit and is also used as a high-speed switching basic circuit of a digital circuit. In the differential amplifier circuit, the output currents I 1 and I 2 exhibit characteristics as shown in FIG. 7 due to the differential inputs V IN1 to V IN2 .
しかしながら、差動対の両方又は片方のトランジスタの特性がばらつきにより変化してしまうと、図８のようにクロスポイントがずれてしまい、アナログ回路においてはオフセットとなったり、ディジタル回路においては、論理値に誤りを発生させる場合がある。そのため、図９のように各差動対トランジスタに直列にTMR素子を挿入することで、差動対の両方又は片方のトランジスタの特性のばらつきを吸収し、クロスポイントを補正することが可能となる。 However, if the characteristics of both or one of the transistors in the differential pair change due to variations, the cross point shifts as shown in FIG. 8, resulting in an offset in an analog circuit or a logical value in a digital circuit. May cause errors. Therefore, by inserting a TMR element in series with each differential pair transistor as shown in FIG. 9, it is possible to absorb variations in characteristics of both or one of the transistors in the differential pair and correct the cross point. .
TMR素子は、磁性の方向により２種類の抵抗値しか記憶することができないため、図１０のように異なる絶対値を持つTMR素子を直列、並列又は直並列に接続することで細かな抵抗値を作り出すことが可能となる。 Since the TMR element can only store two types of resistance values depending on the direction of magnetism, a fine resistance value can be obtained by connecting TMR elements having different absolute values in series, parallel, or series-parallel as shown in FIG. It becomes possible to produce.
さらに回路が複雑になった場合、図１１(a)、(b)に示すように、トランジスタとTMR素子を組合わせたブロックを直並列に接続することで、各トランジスタの特性補正が可能となるだけでなく、全体回路のばらつきによる補正も可能となる。 When the circuit becomes more complicated, as shown in FIGS. 11A and 11B, the characteristics of each transistor can be corrected by connecting the combination of the transistor and the TMR element in series and parallel. In addition, correction by variations in the entire circuit is also possible.
また、TMR素子は不揮発性であるため、一度書き込みを行えば、その抵抗値を維持することができるため、書込み動作は、製造後基本的に1回だけで済む。
また、トランジスタの経年変化により特性が変わって動作不良を起こしても、そのトランジスタを再度補正することにより、半導体集積回路装置が再利用可能となる。
In addition, since the TMR element is non-volatile, the resistance value can be maintained once writing is performed. Therefore, the writing operation is basically required only once after the manufacture.
In addition, even if the characteristics change due to the aging of the transistor and malfunction occurs, the semiconductor integrated circuit device can be reused by correcting the transistor again.
TMR素子の書込み方法としては、磁界を使って磁化の方向を変える方法と、TMR素子自体に電流を流し、書き換える方法がある。前者の場合には、非接触でTMR素子の特性を変えることができる利点がある。 As a writing method of the TMR element, there are a method of changing the direction of magnetization using a magnetic field and a method of rewriting by passing a current through the TMR element itself. The former case has an advantage that the characteristics of the TMR element can be changed without contact.
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