JP2014154189A - Resistance change type memory counter basis read-out circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a read-out circuit which prevents a resistance change type memory from malfunctioning due to a low voltage condition and temperature change, requires no reference voltage necessary for logic determination, and avoids lowering in a reading margin.SOLUTION: A resistance change type memory read-out circuit is constituted of: a negative resistance circuit connected in parallel via a read-out node of a resistance change type memory cell; a pressure rise load circuit connected to the negative resistance circuit in parallel and sharing a power source voltage therewith; a variable resistive element configuring the resistance change type memory cell; and a determination circuit for determining a data logic held in the memory cell on the basis of the voltage of the read-out node changed by a current flowing in the negative resistance circuit. The determination circuit is configured by a ring oscillator, and determines the data logic held in the resistance change type memory cell by converting the voltage of the read-out node into a frequency of the ring oscillator and counting the number of oscillations.

Description

  The present invention relates to a read circuit of a resistance change type memory having memory cells that hold data according to a resistance value.

The resistance change type memory is an MRAM (Magneto resistive RAM) or CER (Colossal Electro) composed of memory cells using a magnetic tunnel junction (MTJ) element.
ReRAM (Resistance RAM) using a resistance element.
For example, in the case of an MRAM, data writing and data reading are performed by passing a current through the MTJ element. Data writing to the MRAM memory cell is performed by passing a write current larger than the threshold current value at which magnetization reversal occurs to the MTJ element, while data reading from the MRAM memory cell is smaller than the threshold current value. This is done without causing magnetization reversal by passing a current through the MTJ element.
As a circuit for reading data from the MRAM memory cell, for example, the configuration of the read circuit shown in FIG. 25 is known.

  In general, the electrical characteristics of the resistance change type memory are likely to vary due to variations in manufacturing conditions. For example, in the case where the resistance change type memory is composed of MTJ elements, it is assumed that the threshold current value at which magnetization reversal occurs due to variations in electrical characteristics is reduced to about the value of the read current. In that case, there is a problem that the data held in the memory cell is rewritten during the read operation, and the resistance change type memory malfunctions. In consideration of variations in the magnetization reversal threshold current value, the read current value needs to be set to a sufficiently small value in order to prevent erroneous write operation of the resistance change memory. However, when the value of the read current is set to be small, the amount of charge obtained when reading data from the resistance change type memory cell is reduced, which causes problems such as a decrease in speed and a decrease in read margin.

  In the conventional read circuit using the pMOS load circuit as shown in FIG. 25, since the change in potential (potential difference) accompanying the change in resistance value of the resistance change type memory cell is as small as several tens mV, low voltage operation (for example, Reading with a sense amplifier (0.4 V operation) was difficult. In addition, there is a problem that when the potential difference is increased, the speed is decreased, whereas when the speed is increased, the potential difference is decreased.

In view of the above problems, the present inventors have already proposed a resistance change type memory read circuit that prevents a malfunction under a low voltage and improves a read margin (Japanese Patent Application No. 2011-273934).
As shown in FIG. 26, the resistance change type memory read circuit proposed by the present inventors comprises a negative resistance circuit connected in parallel via a read node of a resistance change type memory cell, and a negative resistance circuit. A substrate terminal for controlling the substrate bias voltage of the pair of pMOS transistors, a boost load circuit connected in parallel with the negative resistance circuit and sharing the power supply voltage, and a variable resistance element constituting the resistance change type memory cell And a determination circuit that determines the data logic held in the resistance change type memory cell based on the voltage of the read node that changes depending on the current flowing through the load resistance circuit.

In the above-described resistance change type memory read circuit, by adding the load line of the negative resistance circuit and the load line of the boost load circuit, the read stability when the variable resistance element of the resistance change type memory is in the low resistance state is added. The potential difference between the potential and the stable reading potential when the variable resistance element is in the high resistance state can be increased, and the malfunction of the resistance change memory under a low voltage is prevented, and the reading margin is improved. That is, by combining the negative resistance circuit and the boost load circuit, a potential difference sufficient for reading of the sense amplifier used in the determination circuit can be obtained as compared with the conventional reading circuit.
Further, the read current is small when the variable resistance element is in the low resistance state, and erroneous writing can be eliminated. On the other hand, the read current is large when the variable resistance element is in the high resistance state, and the read speed is improved.

A load line of the resistance change type memory reading circuit proposed above will be described with reference to FIG.
FIG. 27 shows an example of a load line (TT corner) and shows the current-voltage characteristics of the negative resistance circuit. The horizontal axis represents the voltage of the node (S), and the vertical axis represents the current flowing into the node (S) and the current flowing out from the node (S). The TT corner is a simulation in which the threshold voltage of the transistor is a typical value.
In FIG. 27, the solid line is the proposed readout circuit, of which the dotted line drawn to the right is a boosted nMOS circuit, and the dashed-dotted line is the load line of the negative resistance circuit. It represents the current flowing into S). Further, the plots of the low resistance state and the high resistance state represent the current drawn by the resistance change type memory cell. The plot of the readout circuit under proposal (solid line) is a combination of the plot of the boosting nMOS circuit (dotted line) and the plot of the negative resistance circuit (dotted line curve).

When the read operation of the resistance change memory is started, the voltage of the node (S) rises from zero. In the proposed resistance change memory read circuit, when the memory cell is in the low resistance state, the low resistance state plot and the solid line plot are indicated at the intersection, that is, “L” in the figure. The voltage rise stops at the point (around 0.08V).
On the other hand, when the memory cell is in the high resistance state, when the read operation is similarly started, the voltage of the node (S) rises from 0, but there is no intersection between the high resistance state plot and the solid line plot in the vicinity of 0.08V. The voltage rises as it is, and at the intersection of the high resistance state plot and the solid line plot, the voltage rise stops at the place marked "H" in the figure (near 0.38V). .

  As can be seen from the plot of the negative resistance circuit in FIG. 27 (two-dot chain line), when the read operation is performed only with the negative resistance circuit, the voltage of the node (S) is 0 (V), which is the intersection. The voltage remains zero. From the plot (solid line) of the proposed readout circuit in FIG. 27, it can be seen that it operates as a negative resistance when the potential of the node (S) exceeds 0.28V. In the low resistance state, a plurality of intersections may be provided, and the intersection on the lowest voltage side is the stable point.

  Further, as shown in FIG. 28, in the case of the load line of the proposed resistance change type memory read circuit, as described above, if the memory cell is in a low resistance state, the location indicated as “L” (near 0.08V) ) Stops the voltage rise, and the high voltage resistance stops at the location marked “H” (around 0.38 V) in the high resistance state, so the variable resistance element of the resistance change memory is in the low resistance state. Difference between the read stable potential and the read stable potential when the variable resistive element is in the high resistance state can be increased to about 0.3 V (= 0.38-0.08) (ΔVprop in the figure is reference). This can be made larger than the potential difference ΔVconv (= 0.28−0.1) in the case of the load line of the conventional circuit (pMOS load circuit), and it can be seen that the voltage margin for logic determination is improved.

In the proposed resistance change memory read circuit, the substrate terminal can be used to control the pMOS substrate bias of the negative resistance circuit, so that the load line can be changed and adjusted arbitrarily, thereby adapting to process variations. Yes.
As shown in FIG. 29, the load characteristic is adjusted so that the load line passes through the window between the low resistance state and the high resistance state by changing the pMOS substrate bias of the negative resistance circuit.

  However, in the conventional resistance change type memory read circuit, a sense amplifier is used in the read operation (in the sense amplifier, the voltage in the “0” state or “1” state and the “0” state) The intermediate value Vref in the “1” state is read by comparing the reference voltage), and since the margin is narrow, it is more difficult to generate this Vref, which causes a reduction in the read margin of the sense amplifier.

  On the other hand, in the case of the proposed resistance change type memory read circuit, the read stable potential when the variable resistance element is in the low resistance state is lower, and the read stable potential when the variable resistance element is in the high resistance state. Therefore, even when the reference voltage when the determination circuit is configured by a sense amplifier is set to, for example, about ½ of the power supply voltage (Half VDD), a read margin can be further increased. However, in practice, an intermediate value between the “0” state and the “1” state is ideal as in the conventional read circuit.

  In the case of the proposed resistance change memory read circuit, the load line can be arbitrarily changed / adjusted by the substrate bias of the pair of pMOS transistors constituting the negative resistance circuit, thereby making it possible to cope with process variations. . That is, although the process variation can be dealt with, as shown in FIG. 30, when the temperature changes from room temperature to high temperature (125 ° C.), the present inventors have a problem that reading is difficult without changing the substrate bias condition. Recognized.

JP 2011-159358 A

  In view of the above situation, the present invention prevents a malfunction due to a low voltage and a temperature change of a resistance change type memory having a memory cell that holds data according to a resistance value, improves a read margin, and performs logic determination. It is an object of the present invention to provide a resistance change type memory read circuit that does not require generation of a reference voltage necessary for the above-described and avoids a decrease in read margin caused by inappropriate reference voltage generation.

In order to achieve the above object, the resistance change type memory counter base read circuit of the present invention is connected in parallel via a read node of the resistance change type memory cell, and in parallel with the negative resistance circuit. And held in the resistance change type memory cell based on the voltage of the read load node that changes depending on the current flowing through the load resistance circuit, the variable load element that constitutes the resistance change type memory cell, and the boost load circuit that shares the power supply voltage And a determination circuit for determining the data logic.
The above determination circuit is composed of a ring oscillator, converts the voltage of the read node into the frequency of the ring oscillator, and counts the number of oscillations, thereby obtaining the data logic held in the resistance change type memory cell. judge.
Since the voltage of the read node is converted to the frequency of the ring oscillator, the logic judgment is not performed by comparing the potential with the potential, but the logic judgment is performed by comparing the digital value of the number of oscillations. Is no longer necessary. In addition, since a calculation after reading can be performed using a digital value called the number of oscillations, a reference value can be generated arithmetically.

Here, the boost load circuit is preferably configured to be able to switch the amount of current flowing through the circuit from a small amount of current to a large amount of current in a stepwise manner. The boost load circuit is connected in parallel with the negative resistance circuit and shares the power supply potential VDD. The boosting load circuit is specifically composed of an nMOS transistor, and the gate terminal of the nMOS transistor is turned ON at the start of data reading. By providing the boosting load circuit, it is possible to add the load line due to the boosting load circuit to the load line due to the negative resistance circuit, so that the voltage can be increased from 0 when performing the read operation of the read circuit. By applying a voltage higher than the power supply potential to the gate terminal of the nMOS transistor, the difference between the gate potential and the source potential of the nMOS transistor is increased, and the influence of the threshold voltage fluctuation of the nMOS transistor can be reduced, resulting in process variations. Resistant to fluctuations.
A dynamic load line is realized by adopting a configuration in which the amount of current flowing through the circuit can be switched from a small amount of current to a large amount of current in a stepwise manner.

As one aspect of the boost load circuit, a circuit configuration in which a plurality of nMOS transistors of the same size are connected in parallel and a gate switch of each nMOS transistor is sequentially turned on to change the amount of current flowing in the circuit in stages. Is done.
As another aspect of the boost load circuit, a plurality of nMOS transistors having different sizes are connected in parallel, and the gate switch of each nMOS transistor is controlled to be turned on / off, whereby the amount of current flowing in the circuit is stepwise. The circuit configuration is changed.

Here, it is more preferable that the resistance change type memory counter base readout circuit of the present invention further includes a non-operating bias current suppression switch connected in parallel with the negative resistance circuit.
By providing the non-operating bias current suppression switch, it is possible to eliminate power consumption when the read operation is not performed. The non-operating bias current suppression switch can be constituted by, for example, an inverter (NOT circuit) and an nMOS transistor, and can be realized by connecting the inverter to the gate circuit of the nMOS transistor.

Further, in the resistance change type memory counter base read circuit of the present invention, it is more preferable that a clamp switch circuit is further provided on the wiring connecting the resistance change type memory cell and the negative resistance circuit.
By providing the clamp switch circuit, it is possible to prevent a large current from flowing through the resistance change type memory cell and to prevent erroneous writing. The clamp switch circuit can be realized, for example, by providing an nMOS transistor on a line connecting the resistance change type memory cell and the negative resistance circuit.

  Here, the WL boosted potential is a boosted potential applied to the word line (WL). For example, the WL boost potential is generated from the power supply potential using a charge pump circuit or the like. Note that, in the low power supply voltage operation of the nMOS transistor (access transistor) in the memory cell, as the difference between the gate potential and the source potential is larger, the influence of the threshold voltage variation of the transistor becomes smaller and the tolerance to process variations can be improved. In addition, boosting the gate potential of the access transistor can reduce the transistor size and thus the memory cell area. Therefore, boosting of the word line (WL) is preferable.

Further, in the determination circuit of the resistance change type memory counter base read circuit according to the present invention, the threshold used for determining the data logic is the number of oscillations of the ring oscillator in the low resistance state with respect to the reference memory cell. And the number of oscillations of the ring oscillator in the high resistance state are acquired in advance, and the value is preferably an arithmetic operation result value including an arithmetic average using the acquired both oscillation numbers as parameters.
The number of oscillations of the ring oscillator is a digital value, and an arithmetic operation after reading can be performed with the digital value. Therefore, the threshold value for data logic determination can be generated by arithmetic operation.
Using the readout circuit of the present invention for the reference memory cell, the number of oscillations of the ring oscillator in the low resistance state and the number of oscillations of the ring oscillator in the high resistance state are obtained. Then, for example, arithmetic averaging is performed using both oscillation numbers as parameters, and the resulting count value is set as a threshold value. If each memory cell of the resistance change type memory cell has a count value larger than the set threshold value, the logical determination is “0”, and if the count value is smaller than the threshold value, “1” is logically determined.
An arithmetic operation other than the arithmetic average may be used. It is also possible to set a threshold value in consideration of the distribution statistical information of the count value of the memory cell serving as a reference.

  According to the resistance change type memory counter base read circuit of the present invention, it is possible to prevent malfunction under low voltage of a resistance change type memory having a memory cell that holds data according to a resistance value, and to improve a read margin. Rather than making a logical determination by comparison with a potential as in the past, by making a logical determination by comparing the digital value of the number of oscillations, a sense amplifier is unnecessary, and operations after reading with a digital value are possible. The value of can be generated by arithmetic.

Basic configuration of resistance change type memory counter base readout circuit of the present invention Circuit description 1 of a resistance change type memory counter base read circuit according to the first embodiment Circuit description 2 of the resistance change type memory counter base read circuit according to the first embodiment Configuration example of boost load circuit (1) Configuration example of boost load circuit (2) Configuration example of boost load circuit (3) Dynamic load line when boosting load is switched to 16 steps; (a) TT corner (25 ° C); (b) SS corner (-20 ° C) Graph showing the oscillation state of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment (TT corner: −20 ° C.) Graph showing the oscillation state of the ring oscillator in the readout circuit of the resistance change memory according to the first embodiment (TT corner: 25 ° C.) Graph showing the oscillation state of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment (TT corner: 100 ° C.) The graph which shows the oscillation state of the ring oscillator in the read-out circuit of the resistance change memory of Example 1 (FF corner: -20 degreeC) Graph showing the oscillation state of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment (FF corner: 25 ° C.) Graph showing the oscillation state of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment (FF corner: 100 ° C.) Graph showing the oscillation state of the ring oscillator in the read circuit of the resistance change memory according to the first embodiment (FS corner: −20 ° C.) Graph showing the oscillation state of the ring oscillator in the readout circuit of the resistance change memory according to the first embodiment (FS corner: 25 ° C.) Graph showing the oscillation state of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment (FS corner: 100 ° C.) The graph which shows the oscillation state of the ring oscillator in the read-out circuit of the resistance change type memory of Example 1 (SF corner: -20 degreeC) Graph showing the oscillation state of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment (SF corner: 25 ° C.) Graph showing the oscillation state of the ring oscillator in the readout circuit of the resistance change memory according to the first embodiment (SF corner: 100 ° C.) The graph which shows the oscillation state of the ring oscillator in the read-out circuit of the resistance change type memory of Example 1 (SS corner: -20 degreeC) Graph showing the oscillation state of the ring oscillator in the readout circuit of the resistance change memory according to the first embodiment (SS corner: 25 ° C.) Graph showing the oscillation state of the ring oscillator in the readout circuit of the resistance change memory according to the first embodiment (SS corner: 100 ° C.) Comparison table of oscillation count numbers at each process corner of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment Explanatory drawing of the logic determination in the read circuit of the resistance change type memory according to the first embodiment. Conventional readout circuit (prior art) Proposed readout circuit (prior art) Load line 1 (TT corner) of proposed readout circuit and conventional readout circuit Load line 2 (TT corner) of proposed readout circuit and conventional readout circuit Load line (25 ° C) of proposed readout circuit and conventional readout circuit Load line (125 ° C) of proposed readout circuit and conventional readout circuit Modification 1 of the circuit configuration of the ring oscillator Modification 2 of ring oscillator circuit configuration Modified example 3 of the circuit configuration of the ring oscillator

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The scope of the present invention is not limited to the following examples and illustrated examples, and many changes and modifications can be made.

With reference to FIG. 1, a basic configuration of a resistance change type memory counter base read circuit of the present invention will be described. The voltage of the read node (S) of the resistance change memory is converted into the frequency of the ring oscillator 3 and the oscillation circuit counts the number of oscillations by the counter circuit 12 to determine the data logic held in the resistance change memory cell. To do.
The ring oscillator 3 has a configuration in which one NAND circuit and an even number of inverters are connected in series, and the output of the final stage inverter is fed back to the NAND circuit. Each NAND and inverter has a power source side source terminal connected to the drain terminal of the pMOS transistor, and the source terminal of these transistors becomes the power source potential.

  That is, by connecting the gate terminal of the pMOS above the ring oscillator 3 in which the pMOS transistors are stacked in two stages to the read node S, the ring oscillator oscillates. The ring oscillator 3 is connected to the reference cell in the “0” state and “1” state and the memory cell to be read, and the number of oscillations is counted. Reading is performed by comparing the reference value arithmetically generated from the oscillation number of the reference cell in the “0” state and the “1” state with the oscillation number of the read target cell.

That is, the voltage of the read node is converted to the frequency of the ring oscillator, the number of oscillations is counted, and the arithmetically generated reference value is compared with the number of oscillations of the read target cell to be held in the resistance change type memory cell. Determine the data logic that is present.
Unlike conventional methods, logic is determined by comparing digital values such as the number of oscillations, rather than making logical determinations by comparing potentials. Conventional sense amplifiers are not required, and reference values are generated arithmetically. can do.

Next, with reference to FIG. 2, the configuration of the resistance change type memory counter base readout circuit of this embodiment will be described.
The resistance change type memory counter base readout circuit of the present embodiment includes a negative resistance circuit 1, a boost load circuit 2, a ring oscillator 3, a counter circuit 12, and a clamp transistor 5. Note that the presence or absence of the clamp transistor 5 depends on the reading performance of the resistance element. Therefore, the clamp transistor 5 is not always necessary.
The negative resistance circuit 1 is connected in parallel with the boost load circuit 2 via the read node (S) of the resistance change type memory cell 10.

The boost load circuit 2 is connected in parallel with the negative resistance circuit 1 and shares the power supply potential VDD. The boost load circuit 2 is specifically composed of an nMOS transistor. The gate terminal of the nMOS transistor is “Read
The “Read Enable” signal line is turned ON at the start of reading. By providing the boosting load circuit 2, the load line by the negative resistance circuit 1 is connected to the load line by the boosting load circuit 2 as described above. Since the load lines can be added together, the voltage rises from 0 when the read operation of the read circuit of the resistance change type memory cell 10 is performed.
This “Read”
It is preferable to apply a voltage boosted from the power supply potential VDD to the “Enable” signal line.

Further, as shown in FIG. 3, a non-operating bias current suppression switch 4 may be provided. The non-operating bias current suppression switch 4 is connected in parallel with the negative resistance circuit 1 and functions to eliminate power consumption when the read operation is not performed. Specifically, it is composed of an inverter (NOT circuit) and an nMOS transistor, and the inverter is connected to the gate circuit of the nMOS transistor. “Read
When the “Enable” signal line is turned OFF, the node (S) becomes the ground potential.

  The clamp transistor 5 is provided to prevent a large current from flowing through the resistance change type memory cell 10, and specifically, an nMOS transistor is provided on the bit line (BL) connected to the node (S). There are many cases (not necessarily necessary).

  According to the circuit configurations of FIGS. 2 and 3, when the load line by the negative resistance circuit 1 and the load line by the boost load circuit 2 are added, the variable resistance element of the resistance change memory is in a low resistance state. The potential difference between the stable read potential and the stable read potential when the variable resistance element is in the high resistance state can be increased.

  Further, since the voltage of the read node (S) is converted into the frequency of the ring oscillator and the number of oscillations is counted by the counter circuit 12, the data logic held in the resistance change type memory cell is determined. A conventional sense amplifier is not required. Further, since a post-read operation can be performed with a digital value called the number of oscillations, a reference value can be generated arithmetically.

The configuration of the negative resistance circuit will be described with reference to FIG. The negative resistance circuit includes a pair of pMOS transistors (P1, P2) and an nMOS transistor N1. In the pMOS transistor P1, the source is connected to the power supply potential VDD, and the gate and the drain are connected to each other. The pMOS transistor P2 has a source connected to the power supply potential VDD, a gate connected to the gate of the pMOS transistor P1, and a drain connected to the node (S).
The nMOS transistor N1 has a source grounded, a gate connected to the node (S), and a drain connected to the drain of the pMOS transistor P1.

Next, a configuration example of the boost load circuit will be described with reference to FIGS.
4 to 6 can switch the amount of current flowing through the circuit from a small amount of current to a large amount of current step by step.
In the boosting load circuit shown in FIG. 4, 16 nMOS transistors having the same current drive capability ratio are connected in parallel. By sequentially turning on the gate switches of the 16 nMOS transistors, the amount of current flowing through the circuit can be changed in 16 steps.
Further, in the boost load circuit shown in FIG. 5, four nMOS transistors having different types of drive capability ratios are connected in parallel. The four types of current drive capability ratios are 1, 2, 4, and 8. By controlling on / off of the gate switches of these four nMOS transistors, the amount of current flowing through the circuit becomes 16 and can be changed in 16 steps.
In the boost load circuit shown in FIG. 6, two nMOS transistors having different current drive capability ratios are connected in parallel. The current drive capability ratio of the two nMOS transistors has a large difference such as 1 and 15. By gradually turning on the gate switches of the two nMOS transistors having a large difference in current drive capability ratio, the amount of current flowing in the circuit can be changed in two steps with a gradual change.

FIG. 7 shows a dynamic load line when the boost load is switched to 16 levels. FIG. 7A shows a load line at the TT corner (25 ° C.), and FIG. 7B shows a load line at the SS corner (−20 ° C.).
By switching the boosting load in multiple stages, as shown in FIGS. 7A and 7B, the load characteristic is such that the load line passes dynamically through the window between the low resistance state and the high resistance state. Can be changed over time.
As described in the background art, when the temperature changes to a high temperature (125 ° C.), if the same load line is used, it is difficult to control the load characteristics, but by switching the boosting load in time, Adjustment can be made so that the load line passes through the window between the low resistance state and the high resistance state at any timing.

8 to 22 show the low resistance under the temperature conditions of −20 ° C., 25 ° C., and 100 ° C. for the TT corner, the FF corner, the FS corner, the SF corner, and the SS corner of the read circuit of the resistance change type memory according to the first embodiment. The state of the oscillation of the ring oscillator in the state and the high resistance state is shown.
The TT corner, FF corner, FS corner, SF corner, and SS corner are the following process corners.
The TT corner is a value with a typical threshold voltage of the nMOS transistor and a value with a typical threshold voltage of the pMOS transistor.
The FF corner is a value where the threshold voltage of the nMOS transistor is lower than a typical value and the absolute value of the threshold voltage of the pMOS transistor is also lower than a typical value.
The FS corner means that the threshold voltage of the nMOS transistor is lower than a typical value, and the absolute value of the threshold voltage of the pMOS transistor is higher than a typical value.
The SF corner is a value in which the threshold voltage of the nMOS transistor is higher than a typical value, and the absolute value of the threshold voltage of the pMOS transistor is lower than a typical value.
The SS corner is a value where the threshold voltage of the nMOS transistor is higher than a typical value, and the absolute value of the threshold voltage of the pMOS transistor is also higher than a typical value.

8 to 22, even if the process corner changes, the difference in the count value can be clearly confirmed between the number of oscillations of the ring oscillator in the low resistance state and the number of oscillations of the ring oscillator in the high resistance state.
By dynamically changing the load line at all process corners and temperatures, temporally, a difference is generated between the voltage of the readout node (S) in the low resistance state and the voltage of the readout node (S) in the high resistance state. As a result, a difference is given to the number of oscillations of the output waveform of the ring oscillator.

  FIG. 23 is a comparison table of oscillation count numbers at each process corner of the ring oscillator in the read circuit of the resistance change type memory according to the first embodiment. It can be seen that the high resistance state (7 kΩ) and the low resistance state (3.5 kΩ) can be distinguished under the temperature conditions of −20 ° C., 25 ° C., and 100 ° C. at all process corners.

With reference to FIG. 24, the logic determination in the read circuit of the resistance change type memory according to the present embodiment will be described.
First, the number of oscillations is obtained for a reference memory cell using a read circuit. The number of oscillations of the ring oscillator in the “low resistance state = 0” state (3 KΩ) is 239, and the number of oscillations of the ring oscillator in the “high resistance state = 1” state (7.5 KΩ) is 180. To do. In this case, for example, a count value of arithmetic mean, (239 + 180) /2=209.5 is set as a threshold value, and each memory cell of the resistance change type memory cell (MRAM cell array) has a count value larger than the threshold value. If the count value is smaller than the threshold, the logical determination is “1”.
In the above description, the threshold value is an intermediate value between the number of oscillations of the low-resistance ring oscillator and the number of oscillations of the high-resistance ring oscillator of the reference memory cell. It is also possible to set a threshold in consideration of the distribution statistical information of the count value.

(Other examples)
-The variation (modification example) of a ring oscillator is demonstrated. 31 to 33 show modifications of the circuit configuration of the ring oscillator in the above embodiment. In either case, the number of oscillations differs between the low resistance state and the high resistance state.
The NAND circuit in the ring oscillator of the above embodiment and the ring oscillator having the configuration shown in FIGS. 31 to 33 may be a NOR circuit.

  The present invention is useful for a read circuit of a resistance change type memory such as MRAM or ReRAM.

DESCRIPTION OF SYMBOLS 1 Negative resistance circuit 2 Boost load circuit 3 Ring oscillator 4 Non-operation bias current suppression circuit 5 Clamp transistor 8 Access transistor 9 Variable resistance element 10 Resistance change type memory cell 12 Counter circuit WL Word line VDD Power supply potential MTJ MTJ (Magnetic Tunneling Junction) element OSOUT Ring oscillator output S Read node SA Sense amplifier

Claims (7)

A negative resistance circuit connected in parallel via a read node of the resistance change type memory cell;
A boost load circuit connected in parallel with the negative resistance circuit and sharing a power supply voltage;
Determination of data logic held in the resistance change type memory cell based on a variable resistance element constituting the resistance change type memory cell and a voltage of the read node which is changed by a current flowing in the load resistance circuit In the resistance change type memory reading circuit composed of a circuit,
The determination circuit is composed of a ring oscillator, and the data logic held in the resistance change type memory cell is determined by converting the voltage of the read node into the frequency of the ring oscillator and counting the number of oscillations. A resistance change type memory counter base readout circuit characterized by:   2. The resistance change type memory counter base read circuit according to claim 1, wherein the boost load circuit is configured to be able to switch the amount of current flowing in the circuit from a small amount of current to a large amount of current stepwise. .   The boost load circuit is characterized in that a plurality of nMOS transistors of the same size are connected in parallel, and the amount of current flowing in the circuit is changed stepwise by sequentially turning on the gate switch of each nMOS transistor. The resistance change type memory counter base read circuit according to claim 2.   The boost load circuit includes a plurality of nMOS transistors having different sizes connected in parallel, and the amount of current flowing in the circuit is changed stepwise by controlling on / off of the gate switch of each nMOS transistor. The resistance change type memory counter base read circuit according to claim 2.   5. The resistance change type memory counter base read circuit according to claim 1, further comprising a non-operating bias current suppression switch connected in parallel with the negative resistance circuit. 6.   6. The resistance change type memory counter base read-out according to claim 1, further comprising a clamping switch circuit on a line connecting the resistance change type memory cell and the negative resistance circuit. circuit. In the determination circuit, the threshold value used for determining the data logic is the number of oscillations of the low resistance ring oscillator and the number of oscillations of the ring oscillator in the high resistance state with respect to a reference memory cell. The resistance change type memory counter base read circuit according to claim 1, wherein the resistance change type memory counter base read circuit is a value of an arithmetic operation result including an arithmetic average using the acquired number of oscillations as a parameter.