JP5420887B2 - Distortion compensation device - Google Patents

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JP5420887B2
JP5420887B2 JP2008310388A JP2008310388A JP5420887B2 JP 5420887 B2 JP5420887 B2 JP 5420887B2 JP 2008310388 A JP2008310388 A JP 2008310388A JP 2008310388 A JP2008310388 A JP 2008310388A JP 5420887 B2 JP5420887 B2 JP 5420887B2
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distortion
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拓也 舩山
康英 田中
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Japan Radio Co Ltd
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Description

本発明は、無線送信装置に利用される歪補償装置に係り、特に、増幅回路で発生する歪みを補償するためのDPD(Digital PreDistortion)を利用する歪補償装置に関する。   The present invention relates to a distortion compensator used for a radio transmission apparatus, and more particularly, to a distortion compensator using a DPD (Digital PreDistortion) for compensating distortion generated in an amplifier circuit.

増幅回路からの出力の一部をフィードバックして、増幅回路への入力信号とフィードバック信号とから歪補償値を求め、適応的に動作させるディジタル歪補償装置において、DSP(Digital Signal Processor)を用いたものが提案されている(例えば、特許文献1参照。)。
特開2001−267850号公報
A digital signal processor (DSP) is used in a digital distortion compensation apparatus that feeds back a part of an output from an amplifier circuit, obtains a distortion compensation value from an input signal to the amplifier circuit and a feedback signal, and operates adaptively. The thing is proposed (for example, refer patent document 1).
JP 2001-267850 A

従来の歪補償装置では、歪逆特性を算出する際に除算処理を行っていたので、回路規模が大きくなってしまっていた。そのため、処理に遅延が生じるとともに、コストが増大する可能性があった。   In the conventional distortion compensator, since the division process is performed when calculating the inverse distortion characteristic, the circuit scale has been increased. Therefore, there is a possibility that the processing is delayed and the cost is increased.

そこで、本発明は、歪逆特性を算出する際の除算処理をなくすことで回路規模を縮小した歪補償装置の提供を目的とする。   Accordingly, an object of the present invention is to provide a distortion compensation apparatus that reduces the circuit scale by eliminating the division process when calculating the inverse distortion characteristic.

上記課題を解決するために、本発明に係る歪補償装置は、歪逆特性をLMS(Least Mean Square)アルゴリズムにより算出する歪逆特性算出部を備え、各入力信号電力の歪補償値を、前記歪逆特性算出部の算出する歪みの逆特性に応じて新たな歪補償値に更新することを特徴とする。
LMSアルゴリズムを用いることで、除算処理を行うことなく歪逆特性を算出することができる。
In order to solve the above problem, the distortion compensating apparatus according to the present invention includes a distortion inverse characteristic calculation unit that exits Risan by distortion inverse characteristic in LMS (Least Mean Square) algorithm, distortion compensation value of each input signal power Is updated to a new distortion compensation value according to the inverse characteristic of the distortion calculated by the distortion inverse characteristic calculating unit .
By using the LMS algorithm, the distortion inverse characteristic can be calculated without performing division processing.

本発明によれば、除算処理を行うことなく歪逆特性を算出するので、回路規模を縮小することができる。   According to the present invention, since the inverse distortion characteristic is calculated without performing division processing, the circuit scale can be reduced.

添付の図面を参照して本発明の実施の形態を説明する。以下に説明する実施の形態は本発明の構成の例であり、本発明は、以下の実施の形態に制限されるものではない。   Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment.

(実施形態1)
図1は、本実施形態に係る歪補償装置の構成概略図である。本実施形態に係る歪補償装置は、D/A21と、Q−MOD22と、HYB23と、発振器24と、増幅回路11と、を備え、歪補償出力信号d(t)を直交変調して送信する。さらに、アドレス算出部16と、参照テーブル(LUT)15と、歪補償部12と、を備え、増幅回路11の非線形歪を補償する。さらに、Q−DEM25と、HYB23と、発振器24と、A/D26と、歪逆特性算出部13と、歪補償値更新部14と、アドレス算出部17と、を備え、適応歪補償を行う。
(Embodiment 1)
FIG. 1 is a schematic configuration diagram of a distortion compensation apparatus according to the present embodiment. The distortion compensation apparatus according to this embodiment includes a D / A 21, a Q-MOD 22, a HYB 23, an oscillator 24, and an amplifier circuit 11. The distortion compensation output signal d (t) is orthogonally modulated and transmitted. . Furthermore, an address calculation unit 16, a reference table (LUT) 15, and a distortion compensation unit 12 are provided to compensate for nonlinear distortion of the amplifier circuit 11. Further, the Q-DEM 25, the HYB 23, the oscillator 24, the A / D 26, the distortion inverse characteristic calculation unit 13, the distortion compensation value update unit 14, and the address calculation unit 17 are provided to perform adaptive distortion compensation.

アドレス算出部16は、入力信号x(t)の電力|x(t)|を計算する。これをLUT15のアドレスa’とする。アドレス算出部17は、フィードバック信号y(t)の電力|y(t)|を計算する。これを歪逆特性算出のアドレスaとする。アドレス算出部16とアドレス算出部17は同じ構成とすることができる。 The address calculation unit 16 calculates the power | x (t) | 2 of the input signal x (t). This is the address a ′ of the LUT 15. The address calculation unit 17 calculates the power | y (t) | 2 of the feedback signal y (t). This is an address a for calculating distortion inverse characteristics. The address calculation unit 16 and the address calculation unit 17 can have the same configuration.

LUT15は、歪補償値w(n)が規定された参照テーブルである。またアドレス算出部16で計算されたアドレスa’に対応する歪補償値を読み出す。歪補償部12は、増幅回路11の前段に接続され、入力信号電力|x(t)|に応じたアドレスa’の歪補償値wa’(t)が規定された参照テーブルに基づき、増幅回路11に入力される入力信号x(t)に歪補償値wa’(t)の複素乗算を行う。例えば、LUT15の読み出した歪補償値wa’(t)を、入力信号x(t)に複素乗算して、信号d(t)を出力する。 The LUT 15 is a reference table in which a distortion compensation value w (n) is defined. Further, the distortion compensation value corresponding to the address a ′ calculated by the address calculation unit 16 is read out. The distortion compensation unit 12 is connected to the previous stage of the amplifier circuit 11 and is based on a reference table in which a distortion compensation value w a ′ (t) of an address a ′ corresponding to the input signal power | x (t) | 2 is defined. A complex multiplication of the distortion compensation value w a ′ (t) is performed on the input signal x (t) input to the amplifier circuit 11. For example, the input signal x (t) is complex-multiplied by the distortion compensation value w a ′ (t) read from the LUT 15 to output the signal d (t).

そして、信号d(t)は、D/A21にてアナログ信号に変換され、Q−MOD22、HYB23及び発振器24にて直交変調された後、増幅回路11にて増幅される。これにより、増幅回路11で生じる非線形歪を補償した信号を送信することができる。   The signal d (t) is converted into an analog signal by the D / A 21, orthogonally modulated by the Q-MOD 22, HYB 23 and the oscillator 24, and then amplified by the amplifier circuit 11. As a result, it is possible to transmit a signal in which nonlinear distortion generated in the amplifier circuit 11 is compensated.

増幅回路11からの出力信号の一部は、フィードバック信号として、Q−DEM25、HYB23、及び発振器24にて復調され、A/D26にてディジタル信号に変換された後、歪逆特性算出部13に入力される。   A part of the output signal from the amplifier circuit 11 is demodulated as a feedback signal by the Q-DEM 25, the HYB 23, and the oscillator 24, converted into a digital signal by the A / D 26, and then sent to the distortion inverse characteristic calculation unit 13. Entered.

歪逆特性算出部13は、入力信号x(t)に対する増幅回路11からのフィードバック信号y(t)の歪みの逆特性r(M)を、LMSアルゴリズムを用いて算出する。歪補償値更新部14は、歪補償値w(n)を、歪逆特性算出部13の算出する歪みの逆特性r(M)に応じて新たな歪補償値w(n+1)に更新する。 The distortion inverse characteristic calculation unit 13 calculates the distortion inverse characteristic r b (M b ) of the feedback signal y (t) from the amplifier circuit 11 with respect to the input signal x (t) using the LMS algorithm. The distortion compensation value update unit 14 converts the distortion compensation value w b (n) to a new distortion compensation value w b (n + 1) according to the inverse distortion characteristic r b (M b ) calculated by the distortion inverse characteristic calculation unit 13. Update to

歪逆特性算出においてLMSアルゴリズムを用いることで、歪逆特性算出部13における除算処理及び平均化処理などが必要なくなり、歪逆特性算出部13の回路規模を縮小させることができる。   By using the LMS algorithm in the distortion inverse characteristic calculation, the division process and the averaging process in the distortion inverse characteristic calculation unit 13 become unnecessary, and the circuit scale of the distortion inverse characteristic calculation unit 13 can be reduced.

以下、歪逆特性算出部13、歪補償値更新部14及び歪補償部12の詳細について説明する。
数式1及び数式2は歪逆特性算出部13における歪逆特性算出処理を表す数式である。歪逆特性算出部13は、数式1及び数式2を繰り返し算出することで歪みの逆特性r(K)を算出する。数式1及び数式2はLMSアルゴリズムである。但し、レベル(アドレスa)毎に求める点が違う。フィードバック信号y(t)からアドレスaを算出し、そのアドレスa毎に係数rを計算する。
Hereinafter, details of the distortion inverse characteristic calculation unit 13, the distortion compensation value update unit 14, and the distortion compensation unit 12 will be described.
Equations 1 and 2 are equations representing distortion inverse characteristic calculation processing in the distortion inverse property calculator 13. The inverse distortion characteristic calculation unit 13 calculates the inverse distortion characteristic r a (K a ) by repeatedly calculating Expression 1 and Expression 2. Equations 1 and 2 are LMS algorithms. However, the point to be obtained is different for each level (address a). Calculating the address a from the feedback signal y (t), calculates the coefficient r a for respective address a.

Figure 0005420887
Figure 0005420887
Figure 0005420887
Figure 0005420887

ただし、xは入力信号、yはフィードバック信号、rは係数、eは誤差、μはステップサイズ、aはフィードバック信号y(k)に対応するアドレスで0≦a<Aを満たす整数値、Aはアドレス数、kはアドレスaに対応する係数rの更新回数で0≦k<Kを満たす整数値である。ここで、kの初期値は0である。e、x、y、rは複素数であり、*は複素共役を示す。 However, x is the input signal, y is the feedback signal, r a is a coefficient, e a is the error, mu 1 is the step size, a is an integer satisfying 0 ≦ a <A at the address corresponding to the feedback signal y (k a) numerical, a is the number of addresses, k a is an integer satisfying 0 ≦ k a <K a in the number of updates of the coefficient r a corresponding to the address a. Here, the initial value of k a is 0. e a , x, y, and r a are complex numbers, and * indicates a complex conjugate.

数式3は歪補償値更新部14における歪補償値の更新処理を表す数式である。歪補償値更新部14は、数式3をアドレスbごとに算出することで、参照テーブルにおける歪補償値w(n)を新たな歪補償値w(n+1)に更新する。数式1及び数式2の処理を任意の回数繰り返した後、数式3によりアドレスbの全てに対してwを更新する。

Figure 0005420887
Equation 3 is an equation representing the distortion compensation value update processing in the distortion compensation value update unit 14. The distortion compensation value update unit 14 calculates Equation 3 for each address b, thereby updating the distortion compensation value w b (n) in the reference table to a new distortion compensation value w b (n + 1). After repeating the processing of Equation 1 and Equation 2 any number of times, w b is updated for all addresses b by Equation 3.
Figure 0005420887

ただし、wは歪補償値(LUTの値)、μ はステップサイズ、nはwの更新回数、r(M)は更新時のr(k)の値、bは更新するアドレスで0≦b<Aを満たす整数値である。ここで、Aはアドレス数である。また、w、rは複素数である。 However, w b is the distortion compensation value (the value of the LUT), μ 2 is the step size, n is the number of updates w b, the value of r b (M b) is at the time of update r a (k a), b update Is an integer value satisfying 0 ≦ b <A. Here, A is the number of addresses. In addition, w b, r b is a complex number.

以上の数式1、数式2、数式3で歪補償値の1回の更新処理である。これらの数式を繰り返して歪補償値を算出する。   The above-described Formula 1, Formula 2, and Formula 3 are a single update process of the distortion compensation value. The distortion compensation value is calculated by repeating these mathematical expressions.

数式4は歪補償部12における歪補償の処理を表す数式である。アドレスa’によりLUT15の歪補償値wa’(t)が読み出され、入力信号x(t)と複素乗算して信号d(t)を得る。

Figure 0005420887
Equation 4 is an equation representing distortion compensation processing in the distortion compensator 12. The distortion compensation value w a ′ (t) of the LUT 15 is read out by the address a ′, and the signal d (t) is obtained by complex multiplication with the input signal x (t).
Figure 0005420887

(実施形態2)
図2は、本実施形態に係る歪補償装置の構成概略図である。本実施形態に係る歪補償装置では、歪逆特性算出部13のアドレスaが、入力信号x(t)の電力|x(t)|となっている。この場合、a=a’である。数式1、数式2、数式3の処理を繰り返すことで、歪逆特性は線形となり|x(t)|と|y(t)|の違いはなくなる。また、実施形態1におけるアドレス算出部17を省略することで、回路規模をより小さくすることができる。
(Embodiment 2)
FIG. 2 is a schematic configuration diagram of the distortion compensation apparatus according to the present embodiment. In the distortion compensation apparatus according to the present embodiment, the address a of the distortion inverse characteristic calculation unit 13 is the power | x (t) | 2 of the input signal x (t). In this case, a = a ′. By repeating the processing of Equation 1, Equation 2, and Equation 3, the distortion inverse characteristic becomes linear, and the difference between | x (t) | 2 and | y (t) | 2 is eliminated. Further, by omitting the address calculation unit 17 in the first embodiment, the circuit scale can be further reduced.

図3は、LUTに格納する歪補償値の一例を示す。図3はAM−AM歪補償値やAM−PM歪補償値、または、実数値や虚数値のいずれかに限定されるものではない。フィードバック信号に周波数歪が含まれる場合(PAメモリ効果も含む)、電力の小さいアドレス領域においては歪がない、または、歪が小さいにも関わらず歪補償値の誤差が大きくなる。全アドレスの誤差が大きくなるが、小さいアドレス領域が特に大きくなる。全アドレスが不安定にあるが、小さいアドレス領域が特に不安定である。これは、図3に示すように小さいアドレスは隣接アドレスと同じ値にすることで改善する。小さいアドレス領域は歪(歪補償値)が小さいため、同じ値にしても影響は小さい。   FIG. 3 shows an example of the distortion compensation value stored in the LUT. FIG. 3 is not limited to the AM-AM distortion compensation value, the AM-PM distortion compensation value, or any of a real value and an imaginary value. When frequency distortion is included in the feedback signal (including the PA memory effect), there is no distortion in the address area with low power, or the error of the distortion compensation value increases despite the small distortion. Although the error of all addresses is large, a small address area is particularly large. All addresses are unstable, but a small address area is particularly unstable. This is improved by setting the small address to the same value as the adjacent address as shown in FIG. Since a small address area has a small distortion (distortion compensation value), even if the value is the same, the influence is small.

本発明は、無線送信装置に利用することができる。   The present invention can be used for a wireless transmission device.

実施形態1に係る歪補償装置の構成概略図である。1 is a schematic configuration diagram of a distortion compensation apparatus according to Embodiment 1. FIG. 実施形態2に係る歪補償装置の構成概略図である。FIG. 3 is a schematic configuration diagram of a distortion compensation apparatus according to a second embodiment. LUTに格納する歪補償値の一例を示す。An example of the distortion compensation value stored in the LUT is shown.

符号の説明Explanation of symbols

11 増幅回路
12 歪補償部
13 歪逆特性算出部
14 歪補償値更新部
15 LUT
16 アドレス算出部
17 アドレス算出部
21 D/A
22 Q−MOD
23 HYB
24 発振器
25 Q−DEM
26 A/D
DESCRIPTION OF SYMBOLS 11 Amplifier circuit 12 Distortion compensation part 13 Distortion reverse characteristic calculation part 14 Distortion compensation value update part 15 LUT
16 Address Calculation Unit 17 Address Calculation Unit 21 D / A
22 Q-MOD
23 HYB
24 oscillator 25 Q-DEM
26 A / D

Claims (1)

増幅回路の非線形歪を補償する歪補償装置において、
前記増幅回路の前段に接続され、前記増幅回路に入力される入力信号電力に応じて歪補償値が規定された参照テーブルに基づき、前記入力信号に歪補償値の複素乗算を行う歪補償部と、
前記入力信号に対する前記増幅回路からのフィードバック信号の歪みの逆特性を、LMS(Least Mean Square)アルゴリズムを用いて算出する歪逆特性算出部と、
前記参照テーブルに規定されている各入力信号電力の歪補償値を、前記歪逆特性算出部の算出する歪みの逆特性に応じて新たな歪補償値に更新する歪補償値更新部と、
を備え
前記歪逆特性算出部は、数式1及び数式2から算出される係数r (k +1)を任意の回数更新して得られた前記歪みの逆特性r (M )を算出し、
前記歪補償値更新部は、数式3をアドレスbごとに算出することで、前記参照テーブルにおける歪補償値w (n)を前記新たな歪補償値w (n+1)に更新することを特徴とする歪補償装置。
Figure 0005420887
Figure 0005420887
Figure 0005420887
ただし、xは入力信号、yはフィードバック信号、r は係数、e は誤差、μ 、μ はステップサイズ、aはフィードバック信号y(k )の電力に対応する前記参照テーブルのアドレスで0≦a<Aを満たす整数値、Aは前記参照テーブルのアドレス数、k は係数r の更新回数、w は歪補償値、nはw の更新回数、r (M )は更新時のr (k )の値、bは更新する係数の前記参照テーブルのアドレスで0≦b<Aを満たす整数値である。
In a distortion compensation device that compensates for nonlinear distortion of an amplifier circuit,
A distortion compensation unit that is connected to the previous stage of the amplifier circuit and that performs complex multiplication of the distortion compensation value on the input signal based on a reference table in which a distortion compensation value is defined in accordance with input signal power input to the amplifier circuit; ,
A distortion inverse characteristic calculation unit that calculates an inverse characteristic of distortion of the feedback signal from the amplification circuit with respect to the input signal using an LMS (Least Mean Square) algorithm;
A distortion compensation value updating unit that updates the distortion compensation value of each input signal power defined in the reference table to a new distortion compensation value according to the distortion inverse characteristic calculated by the distortion inverse characteristic calculation unit ;
Equipped with a,
The distortion inverse characteristic calculation unit calculates the distortion inverse characteristic r b (M b ) obtained by updating the coefficient r a (k a +1) calculated from Equations 1 and 2 an arbitrary number of times ,
The distortion compensation value update unit calculates Equation 3 for each address b, thereby updating the distortion compensation value w b (n) in the reference table to the new distortion compensation value w b (n + 1). A distortion compensation device.
Figure 0005420887
Figure 0005420887
Figure 0005420887
However, x is the input signal, y is the feedback signal, r a is a coefficient, e a is the error, μ 1, μ 2 is the step size, a is the address of the reference table corresponding to the power of the feedback signal y (k a) integer satisfying 0 ≦ a <a in, a is the number of addresses of the lookup table, k a is the number of updates of the coefficients r a, w b is distortion compensation values, n represents the number of updates of w b, r b (M b ) Is the value of r a (k a ) at the time of update , and b is an integer value satisfying 0 ≦ b <A with the address of the reference table of the coefficient to be updated.
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